Semiconductor device

Abstract

The present invention provides a semiconductor device comprising a ferroelectric layer made of a two-dimensional material. The semiconductor device comprises a substrate, a gate structure disposed on the substrate and extending in a first direction, and an active pattern spaced apart from the substrate in a second direction and extending in a third direction and penetrating the gate structure, wherein the active pattern comprises a two-dimensional semiconductor material, and the gate structure comprises a gate insulating layer, a lower gate conductive layer, a ferroelectric layer, and an upper gate conductive layer sequentially stacked on the active pattern, wherein the gate insulating layer comprises h-BN (hexagonal boron nitride), and the ferroelectric layer comprises a two-dimensional material formed as a bilayer.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device comprising ferroelectrics. Background Technology

[0002] Ferroelectrics are materials that possess ferroelectricity, maintaining spontaneous polarization through the alignment of internal electric dipole moments even without the application of an external electric field. Furthermore, the polarization of a ferroelectric can be altered by applying an external electric field exceeding the critical coercive field, and this state can be electrically read through changes within adjacent materials such as metals and semiconductors. Consequently, research is continuously being conducted to improve performance by applying these properties of ferroelectrics to semiconductor devices.

[0003] In particular, with the discovery of the ferroelectricity of hafnium-based oxides, ferroelectric field effect transistors (FeFETs) utilizing hafnium-based oxides are being developed. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device comprising a ferroelectric layer made of a two-dimensional material.

[0005] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] One aspect of a semiconductor device of the present invention for solving the above problem comprises a substrate, a gate structure disposed on the substrate and extending in a first direction, and an active pattern spaced apart from the substrate in a second direction and extending in a third direction and penetrating the gate structure, wherein the active pattern comprises a two-dimensional semiconductor material, and the gate structure comprises a gate insulating layer, a lower gate conductive layer, a ferroelectric layer, and an upper gate conductive layer sequentially stacked on the active pattern, wherein the gate insulating layer comprises h-BN (hexagonal boron nitride), and the ferroelectric layer comprises a two-dimensional material formed as a bilayer.

[0007] Another aspect of the semiconductor device of the present invention for solving the above problem comprises, on a substrate, a channel layer comprising a two-dimensional semiconductor material, a gate structure disposed on the channel layer, and source / drain contacts disposed on both sides of the gate structure and connected to the channel layer, wherein the gate structure comprises a gate insulating layer comprising h-BN, a lower gate graphene layer comprising graphene on the gate insulating layer, a ferroelectric layer comprising a two-dimensional material formed of a double layer on the lower gate graphene layer, and an upper gate graphene layer comprising graphene on the ferroelectric layer.

[0008] Another aspect of a semiconductor device of the present invention for solving the above problem comprises a substrate, a gate structure disposed on the substrate and extending in a first direction, a first active pattern spaced apart from the substrate in a second direction and extending in a third direction and penetrating the gate structure, a second active pattern disposed on the first active pattern and spaced apart from the first active pattern in a second direction and extending in the third direction and penetrating the gate structure, wherein the length of the second active pattern in the third direction is smaller than the length of the first active pattern in the third direction, a first source / drain contact connected to the first active pattern and disconnected from the second active pattern, and a second source / drain contact connected to the second active pattern and disconnected from the first active pattern, wherein the first active pattern and the second active pattern comprise a two-dimensional semiconductor material, and the gate structure extends along the periphery of the first active pattern and the periphery of the second active pattern, and comprises a gate insulating layer comprising h-BN, and the gate insulating layer On the upper side, a lower gate graphene layer comprising graphene extending along the perimeter of the first active pattern and the perimeter of the second active pattern; on the lower gate graphene layer, a ferroelectric layer comprising a two-dimensional material formed of a double layer extending along the perimeter of the first active pattern and the perimeter of the second active pattern; on the ferroelectric layer, an upper gate conductive layer extending along the perimeter of the first active pattern and the perimeter of the second active pattern; and a filling gate conductive layer disposed on the upper gate conductive layer.

[0009] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0010] FIG. 1 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. Figures 2 and 3 are cross-sectional views taken along A-A and B-B of Figure 1. Figure 4 is an enlarged view of section P of Figure 2. Figures 5 and 6 are drawings for explaining the layered structure of the gate insulating film of Figure 2. Figures 7 and 8 are drawings for explaining the layered structure of the ferroelectric layer of Figure 2. FIG. 9 is a drawing for illustrating a semiconductor device according to some embodiments. FIG. 10 is a drawing for illustrating a semiconductor device according to some embodiments. FIG. 11 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. Figure 12 is a cross-sectional view taken along C-C of Figure 11. FIG. 13 is a drawing for illustrating a semiconductor device according to some embodiments. FIGS. 14 to 19 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to some embodiments. Specific details for implementing the invention

[0011] In this specification, although terms such as "first," "second," etc. are used to describe various elements or components, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Therefore, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention.

[0012] Hereinafter, a semiconductor device according to several embodiments will be described with reference to FIGS. 1 to 8.

[0013] FIG. 1 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 2 and FIG. 3 are cross-sectional views taken along A-A and B-B of FIG. 1. FIG. 4 is an enlarged view of portion P of FIG. 2. FIG. 5 and FIG. 6 are diagrams for illustrating the layered structure of the gate insulating film of FIG. 2. FIG. 7 and FIG. 8 are diagrams for illustrating the layered structure of the ferroelectric layer of FIG. 2.

[0014] Referring to FIGS. 1 to 8, a semiconductor device according to some embodiments may include a plurality of active patterns (AP1, AP2, AP3), a gate structure (GS), a plurality of source / drain electrodes (160, 260, 360), and a plurality of source / drain contacts (180, 280, 380).

[0015] The substrate (100) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate (100) may be a silicon substrate or may include other materials, such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0016] Active patterns (AP1, AP2, AP3) are placed on a substrate (100). The active patterns (AP1, AP2, AP3) are spaced apart from the substrate (100) in a third direction (D3).

[0017] The first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) can be sequentially disposed on the substrate (100). Each of the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) can be extended in a first direction (D1).

[0018] The first active pattern (AP1) may be placed on the substrate (100). The first active pattern (AP1) may be spaced apart from the substrate (100) in a third direction (D3). The first active pattern (AP1) may be spatially separated from the substrate (100).

[0019] The first active pattern (AP1) may include a channel portion (AP1_G) and a source / drain portion (AP1_S). The source / drain portion (AP1_S) of the first active pattern may protrude in a first direction (D1) from the channel portion (AP1_G) of the first active pattern. The source / drain portion (AP1_S) of the first active pattern may be positioned on both sides of the channel portion (AP1_G) of the first active pattern.

[0020] The second active pattern (AP2) may be placed on the first active pattern (AP1). The second active pattern (AP2) may be spaced apart from the first active pattern (AP1) in a third direction (D3). The second active pattern (AP2) may be spatially separated from the first active pattern (AP1).

[0021] The second active pattern (AP2) may include a channel portion (AP2_G) and a source / drain portion (AP2_S). The source / drain portion (AP2_S) of the second active pattern may protrude in a first direction (D1) from the channel portion (AP2_G) of the second active pattern. The source / drain portion (AP2_S) of the second active pattern may be positioned on both sides of the channel portion (AP2_G) of the second active pattern.

[0022] The third active pattern (AP3) may be placed on the second active pattern (AP2). The third active pattern (AP3) may be spaced apart from the second active pattern (AP2) in a third direction (D3). The third active pattern (AP3) may be spatially separated from the second active pattern (AP2).

[0023] The third active pattern (AP3) may include a channel portion (AP3_G) and a source / drain portion (AP3_S). The source / drain portion (AP3_S) of the third active pattern may protrude in a first direction (D1) from the channel portion (AP3_G) of the third active pattern. The source / drain portion (AP3_S) of the third active pattern may be positioned on both sides of the channel portion (AP3_G) of the third active pattern.

[0024] The length (L1) of the first active pattern (AP1) in the first direction (D1) is greater than the length (L2) of the second active pattern (AP2) in the first direction (D1). The length (L2) of the second active pattern (AP2) in the first direction (D1) is greater than the length (L3) of the third active pattern (AP3) in the first direction (D1). As one moves away from the substrate (100), the lengths of the active patterns (AP1, AP2, AP3) sequentially arranged on the substrate (100) decrease.

[0025] The channel portion (AP2_G) of the second active pattern overlaps with the channel portion (AP1_G) of the first active pattern and the channel portion (AP3_G) of the third active pattern in the third direction (D3). The length of the source / drain portion (AP2_S) of the second active pattern is greater than the length of the source / drain portion (AP3_S) of the third active pattern and smaller than the length of the source / drain portion (AP1_S) of the first active pattern. From a cross-sectional perspective, the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) can be stacked on the substrate (100) in a stepped shape.

[0026] Each of the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) may be a channel pattern used as a channel region of a transistor.

[0027] The first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) may include a two-dimensional semiconductor material. For example, each of the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) may be a channel pattern formed of a two-dimensional semiconductor material.

[0028] The first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) may include, for example, a TMD (Transition Metal Dichalcogenide) material. The first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) may include, for example, at least one of MoS2, MoSe2, MoTe2, WS2, WSe2, and WTe2, but are not limited thereto.

[0029] For example, the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) may contain the same material. For another example, the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) may contain different materials. For yet another example, the material included in some of the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) may be different from the material included in the remainder. In a semiconductor device according to some embodiments, the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) may contain MoS2.

[0030] Although it is illustrated that three active patterns (AP1, AP2, AP3) are disposed on the substrate (100), it is not limited thereto. Unlike what is illustrated, one or two active patterns may be disposed on the substrate (100). Alternatively, four or more active patterns may be disposed on the substrate (100).

[0031] The first channel isolation insulating layer (165) may be disposed between the substrate (100) and the first active pattern (AP1). The first channel isolation insulating layer (165) may overlap the source / drain portion (AP1_S) of the first active pattern in the third direction (D3). The first channel isolation insulating layer (165) may not overlap the channel portion (AP1_G) of the first active pattern in the third direction (D3).

[0032] The first channel separation insulating layer (165) can be in contact with the first active pattern (AP1). The first channel separation insulating layer (165) can be in contact with the source / drain portion (AP1_S) of the first active pattern.

[0033] The second channel separation insulating layer (265) may be placed between the first active pattern (AP1) and the second active pattern (AP2). The second channel separation insulating layer (265) may overlap the source / drain portion (AP2_S) of the second active pattern in the third direction (D3). The second channel separation insulating layer (265) may not overlap the channel portion (AP2_G) of the second active pattern in the third direction (D3).

[0034] The second channel separation insulating layer (265) can be in contact with the second active pattern (AP2). The second channel separation insulating layer (265) can be in contact with the source / drain portion (AP2_S) of the second active pattern.

[0035] The third channel isolation insulating layer (365) may be placed between the second active pattern (AP2) and the third active pattern (AP3). The third channel isolation insulating layer (365) may overlap the source / drain portion (AP3_S) of the third active pattern in the third direction (D3). The third channel isolation insulating layer (365) may not overlap the channel portion (AP3_G) of the third active pattern in the third direction (D3).

[0036] The third channel isolation insulating layer (365) can be in contact with the third active pattern (AP3). The third channel isolation insulating layer (365) can be in contact with the source / drain portion (AP3_S) of the third active pattern.

[0037] The channel separation insulating layer (165, 265, 365) comprises, for example, an insulating material. The channel separation insulating layer (165, 265, 365) may comprise at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0038] A gate structure (GS) is placed on a substrate (100). The gate structure (GS) extends in a second direction (D2).

[0039] Each of the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) intersects the gate structure (GS). Each of the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) penetrates the gate structure (GS).

[0040] The gate structure (GS) overlaps the channel portion (AP1_G) of the first active pattern, the channel portion (AP2_G) of the second active pattern, and the channel portion (AP3_G) of the third active pattern in the third direction (D3). The gate structure (GS) can wrap the channel portion (AP1_G) of the first active pattern, the channel portion (AP2_G) of the second active pattern, and the channel portion (AP3_G) of the third active pattern.

[0041] The source / drain portion (AP1_S) of the first active pattern, the source / drain portion (AP2_S) of the second active pattern, and the source / drain portion (AP3_S) of the third active pattern do not overlap with the gate structure (GS) in the third direction (D3). The source / drain portion (AP1_S) of the first active pattern, the source / drain portion (AP2_S) of the second active pattern, and the source / drain portion (AP3_S) of the third active pattern protrude in the first direction (D1) from the sidewall of the gate structure (GS).

[0042] The gate structure (GS) may include a gate insulating layer (130) sequentially stacked on active patterns (AP1, AP2, AP3), a lower gate conductive layer (120), a ferroelectric layer (135), an upper gate conductive layer (125), and a filling gate conductive layer (127).

[0043] A gate insulating layer (130) is disposed on a first active pattern (AP1), a second active pattern (AP2), and a third active pattern (AP3). The gate insulating layer (130) may extend along the perimeter of the first active pattern (AP1), the perimeter of the second active pattern (AP2), the perimeter of the third active pattern (AP3), and along the upper surface of the substrate (100).

[0044] The gate insulating layer (130) can be in contact with the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3). The gate insulating layer (130) can be in contact with the channel portion (AP1_G) of the first active pattern, the channel portion (AP2_G) of the second active pattern, and the channel portion (AP3_G) of the third active pattern.

[0045] The gate insulating layer (130) may extend along the sidewalls of the first channel isolation insulating layer (165), the second channel isolation insulating layer (265), and the third channel isolation insulating layer (365). The gate insulating layer (130) may come into contact with the first channel isolation insulating layer (165), the second channel isolation insulating layer (265), and the third channel isolation insulating layer (365).

[0046] The gate insulating layer (130) may include, for example, a two-dimensional material. The gate insulating layer (130) may include, for example, h-BN (hexagonal boron nitride). In a semiconductor device according to some embodiments, the gate insulating layer (130) may be an h-BN layer.

[0047] The lower gate conductive layer (120) is disposed on the gate insulating layer (130). The lower gate conductive layer (120) may extend along the perimeter of the first active pattern (AP1), the perimeter of the second active pattern (AP2), the perimeter of the third active pattern (AP3), and the upper surface of the substrate (100).

[0048] The lower gate conductive layer (120) may include, for example, a two-dimensional material. The lower gate conductive layer (120) may include, for example, graphene. In a semiconductor device according to some embodiments, the lower gate conductive layer (120) may be a graphene layer.

[0049] The ferroelectric layer (135) is disposed on the lower gate conductive layer (120). The ferroelectric layer (135) may extend along the perimeter of the first active pattern (AP1), the perimeter of the second active pattern (AP2), the perimeter of the third active pattern (AP3), and the upper surface of the substrate (100).

[0050] The ferroelectric layer (135) may include, for example, a two-dimensional material. The ferroelectric layer (135) may be composed of a bilayer. The ferroelectric layer (135) may include a two-dimensional material composed of a bilayer.

[0051] The ferroelectric layer (135) may include, for example, h-BN. More specifically, the ferroelectric layer (135) may include h-BN formed into a double layer.

[0052] The gate insulating layer (130) and the ferroelectric layer (135) may include h-BN, which is a two-dimensional material. However, the stacked structure of the gate insulating layer (130) is different from the stacked structure of the ferroelectric layer (135). That is, the stacked structure of h-BN included in the gate insulating layer (130) is different from the stacked structure of h-BN included in the ferroelectric layer (135).

[0053] The h-BN included in the gate insulating layer (130) may have a stacked structure as shown in FIG. 5 or FIG. 6. In the gate insulating layer (130), the hexagonal h-BN of the first layer is arranged to be vertically stacked with the hexagonal h-BN of the second layer.

[0054] In FIG. 5, nitrogen atoms contained in the second layer of h-BN are arranged to overlap vertically on nitrogen atoms contained in the first layer of h-BN. Boron atoms contained in the second layer of h-BN are arranged to overlap vertically on boron atoms contained in the first layer of h-BN. For example, the h-BN contained in the gate insulating layer (130) may have an AA stacked structure.

[0055] In FIG. 6, nitrogen atoms contained in the second layer of h-BN are arranged to overlap vertically with boron atoms contained in the first layer of h-BN. Boron atoms contained in the second layer of h-BN are arranged to overlap vertically with nitrogen atoms contained in the first layer of h-BN. For example, the h-BN contained in the gate insulating layer (130) may have an AA' stacked structure.

[0056] The h-BN included in the ferroelectric layer (135) may have a stacked structure as shown in FIG. 7 or FIG. 8. In the ferroelectric layer (135), the hexagonal h-BN of the first layer is not vertically superimposed with the hexagonal h-BN of the second layer.

[0057] In FIG. 7, the nitrogen atoms contained in the second layer of h-BN are arranged to overlap vertically with the boron atoms contained in the first layer of h-BN. The boron atoms contained in the second layer of h-BN are not arranged to overlap vertically with the nitrogen atoms contained in the first layer of h-BN.

[0058] The boron atoms contained in the second layer of h-BN are positioned in the center of the first layer of h-BN having a hexagonal structure. The nitrogen atoms contained in the first layer of h-BN are positioned in the center of the second layer of h-BN having a hexagonal structure. For example, the h-BN contained in the ferroelectric layer (135) may have an AB stacked structure. If the second layer of h-BN in FIG. 5 is moved to the left or right relative to the first layer of h-BN, it may be a stacked structure of the ferroelectric layer (135) shown in FIG. 7.

[0059] In FIG. 8, the boron atoms contained in the second layer of h-BN are arranged to overlap vertically with the boron atoms contained in the first layer of h-BN. The nitrogen atoms contained in the second layer of h-BN are not arranged to overlap vertically with the nitrogen atoms contained in the first layer of h-BN.

[0060] The nitrogen atoms contained in the second layer of h-BN are positioned in the center of the first layer of h-BN having a hexagonal structure. For example, the h-BN contained in the ferroelectric layer (135) may have an AB1' stacked structure. If the second layer of h-BN in FIG. 6 is shifted to the right relative to the first layer of h-BN, it may be the stacked structure of the ferroelectric layer (135) shown in FIG. 8.

[0061] Unlike as shown in FIG. 8, the nitrogen atoms contained in the second layer of h-BN are arranged to overlap vertically on the nitrogen atoms contained in the first layer of h-BN. The boron atoms contained in the second layer of h-BN are not arranged to overlap vertically on the boron atoms contained in the first layer of h-BN.

[0062] The boron atoms contained in the second layer of h-BN are positioned in the center of the first layer of h-BN having a hexagonal structure. For example, the h-BN contained in the ferroelectric layer (135) may have an AB2' stacked structure. In FIG. 6, if the second layer of h-BN is moved to the left relative to the first layer of h-BN, it may be the stacked structure of the ferroelectric layer (135) described above.

[0063] The upper gate conductive layer (125) is disposed on the ferroelectric layer (135). The upper gate conductive layer (125) may extend along the perimeter of the first active pattern (AP1), the perimeter of the second active pattern (AP2), the perimeter of the third active pattern (AP3), and the upper surface of the substrate (100).

[0064] The upper gate conductive layer (125) may include, for example, a two-dimensional material. The upper gate conductive layer (125) may include, for example, graphene. In a semiconductor device according to some embodiments, the upper gate conductive layer (125) may be a graphene layer.

[0065] The upper gate conductive layer (125) may come into contact with the ferroelectric layer (135). For example, graphene contained in the upper gate conductive layer (125) may come into contact with the ferroelectric layer (135).

[0066] The filling gate conductive layer (127) is disposed on the upper gate conductive layer (125). The filling gate conductive layer (127) can fill the space between the substrate (100) and the first active pattern (AP1), the space between the first active pattern (AP1) and the second active pattern (AP2), and the space between the second active pattern (AP2) and the third active pattern (AP3).

[0067] The filling gate conductive layer (127) may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal carbonitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0068] The first source / drain electrode (160) may be placed on the first active pattern (AP1). The first source / drain electrode (160) may be placed between the first active pattern (AP1) and the second channel separation insulating layer (265).

[0069] The first source / drain electrode (160) may overlap the source / drain portion (AP1_S) of the first active pattern in the third direction (D3). The first source / drain electrode (160) does not overlap the channel portion (AP1_G) of the first active pattern in the third direction (D3). The first source / drain electrode (160) contacts the first active pattern (AP1). The first source / drain electrode (160) contacts the source / drain portion (AP1_S) of the first active pattern.

[0070] The second source / drain electrode (260) may be placed on the second active pattern (AP2). The second source / drain electrode (260) may be placed between the second active pattern (AP2) and the third channel separation insulating layer (365).

[0071] The second source / drain electrode (260) may overlap the source / drain portion (AP2_S) of the second active pattern in the third direction (D3). The second source / drain electrode (260) does not overlap the channel portion (AP2_G) of the second active pattern in the third direction (D3). The second source / drain electrode (260) contacts the second active pattern (AP2). The second source / drain electrode (260) contacts the source / drain portion (AP2_S) of the second active pattern.

[0072] The third source / drain electrode (360) may be placed on the third active pattern (AP3). The third source / drain electrode (360) may overlap the source / drain portion (AP3_S) of the third active pattern in the third direction (D3). The third source / drain electrode (360) does not overlap the channel portion (AP3_G) of the third active pattern in the third direction (D3).

[0073] The third source / drain electrode (360) contacts the third active pattern (AP3). The third source / drain electrode (360) contacts the source / drain portion (AP3_S) of the third active pattern.

[0074] For example, the second active pattern (AP2) may include a first surface (AP2_US) and a second surface (AP2_BS) that are opposite in the third direction (D3). The second surface (AP2_BS) of the second active pattern may face the substrate (100).

[0075] The second source / drain electrode (260) may be placed on the first surface (AP2_US) of the second active pattern at the source / drain portion (AP2_S) of the second active pattern. The second source / drain electrode (260) may be in contact with the first surface (AP2_US) of the second active pattern.

[0076] The second channel separation insulating layer (265) may be disposed on the second surface (AP2_BS) of the second active pattern at the source / drain portion (AP2_S) of the second active pattern. The second channel separation insulating layer (265) may be in contact with the second surface (AP2_BS) of the second active pattern.

[0077] The gate insulating layer (130) may extend along the sidewalls of the first source / drain electrode (160), the second source / drain electrode (260), and the third source / drain electrode (360). The gate insulating layer (130) may be in contact with the first source / drain electrode (160), the second source / drain electrode (260), and the third source / drain electrode (360).

[0078] The source / drain electrode (160, 260, 360) may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal carbonitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0079] The first interlayer insulating film (190) is disposed on the substrate (100). The first interlayer insulating film (190) may cover the source / drain electrodes (160, 260, 360). The upper surface of the first interlayer insulating film (190) may be placed in the same plane as the upper surface of the gate structure (GS), but is not limited thereto.

[0080] The first interlayer insulating film (190) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Low dielectric constant materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped Silicon Oxide), OSG (Organo Silicate) Glass), SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, It may include mesoporous silica or a combination thereof, but is not limited thereto.

[0081] The second interlayer insulating film (195) is placed on the first interlayer insulating film (190). The second interlayer insulating film (195) can cover the upper surface of the gate structure (GS).

[0082] The second interlayer insulating film (195) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0083] A first source / drain contact (180) is disposed on a first source / drain electrode (160). The first source / drain contact (180) can be connected to the first source / drain electrode (160) by penetrating the first interlayer insulating film (190) and the second interlayer insulating film (195).

[0084] The first source / drain contact (180) can be connected to the first active pattern (AP1) through the first source / drain electrode (160). The first source / drain contact (180) is not connected to the second active pattern (AP2) and the third active pattern (AP3).

[0085] A second source / drain contact (280) is disposed on a second source / drain electrode (260). The second source / drain contact (280) can be connected to the second source / drain electrode (260) by penetrating the first interlayer insulating film (190) and the second interlayer insulating film (195).

[0086] The second source / drain contact (280) can be connected to the second active pattern (AP2) through the second source / drain electrode (260). The second source / drain contact (280) is not connected to the first active pattern (AP1) and the third active pattern (AP3).

[0087] A third source / drain contact (380) is disposed on a third source / drain electrode (360). The third source / drain contact (380) can be connected to the third source / drain electrode (360) by penetrating the first interlayer insulating film (190) and the second interlayer insulating film (195).

[0088] The third source / drain contact (380) can be connected to the third active pattern (AP3) through the third source / drain electrode (360). The third source / drain contact (380) is not connected to the first active pattern (AP1) and the second active pattern (AP2).

[0089] The source / drain contact (180, 280, 380) may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal carbonitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

[0090] FIG. 9 is a drawing for explaining a semiconductor device according to several embodiments. For convenience of explanation, the explanation focuses on the differences from the explanation using FIG. 1 to 8. For reference, FIG. 9 is an enlarged view of section P of FIG. 2.

[0091] Referring to FIG. 9, in a semiconductor device according to some embodiments, the ferroelectric layer (135) may include MoS2. The ferroelectric layer (135) may include MoS2 formed into a double layer.

[0092] When the active pattern (AP1, AP2, AP3) contains MoS2, the active pattern (AP1, AP2, AP3) and the ferroelectric layer (135) may contain MoS2, which is a two-dimensional material. However, the stacked structure of the active pattern (AP1, AP2, AP3) is different from the stacked structure of the ferroelectric layer (135). That is, the stacked structure of MoS2 contained in the active pattern (AP1, AP2, AP3) is different from the stacked structure of MoS2 contained in the ferroelectric layer (135).

[0093] MoS2 included in the active pattern (AP1, AP2, AP3) may have a 2H-Stacking structure with a hexagonal symmetry structure. For example, MoS2 included in the active pattern (AP1, AP2, AP3) may have one of the point groups D3h and D3d in crystallography.

[0094] The MoS2 contained in the ferroelectric layer (135) may have a 3R-Stacking structure having a rhombic symmetry structure. The MoS2 contained in the ferroelectric layer (135) may have a non-centrosymmetric point group. For example, the MoS2 contained in the ferroelectric layer (135) may have a C3v point group in crystallography.

[0095] The upper gate conductive layer (125) may include a first sub-gate conductive layer (125A) and a second sub-gate conductive layer (125B). The first sub-gate conductive layer (125A) is disposed between the ferroelectric layer (135) and the second sub-gate conductive layer (125B). The first sub-gate conductive layer (125A) may be in contact with the ferroelectric layer (135) and the second sub-gate conductive layer (125B).

[0096] The first sub-gate conductive layer (125A) and the second sub-gate conductive layer (125B) may include, for example, a two-dimensional material.

[0097] The first sub-gate conductive layer (125A) may include, for example, h-BN. More specifically, the first sub-gate conductive layer (125A) may include h-BN formed as a monolayer.

[0098] The second sub-gate conductive layer (125B) may include graphene. For example, the second sub-gate conductive layer (125B) may be a graphene layer.

[0099] FIG. 10 is a drawing for illustrating a semiconductor device according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 to 8.

[0100] Referring to FIG. 10, a semiconductor device according to some embodiments may further include a gate spacer (140) disposed on the sidewall of a gate structure (GS).

[0101] The gate spacer (140) may be placed on the third source / drain electrode (360). A portion of the third source / drain electrode (360) may overlap the gate spacer (140) in the third direction (D3).

[0102] The gate spacer (140) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0103] FIG. 11 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 12 is a cross-sectional view taken along C-C of FIG. 11. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 through 9.

[0104] Referring to FIGS. 11 and 12, a semiconductor device according to some embodiments may include a channel layer (CH_L), a gate structure (GS), and a fourth source / drain contact (480).

[0105] A channel layer (CH_L) is disposed on a substrate (100). The channel layer (CH_L) can be disposed in an active region defined by a device isolation layer (STI).

[0106] The channel layer (CH_L) may include a two-dimensional semiconductor material. The channel layer (CH_L) may include, for example, at least one of MoS2, MoSe2, MoTe2, WS2, WSe2, and WTe2, but is not limited thereto. In a semiconductor device according to some embodiments, the channel layer (CH_L) may include MoS2.

[0107] The device isolation layer (STI) may be disposed, for example, around the channel layer (CH_L). The device isolation layer (STI) may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0108] The gate structure (GS) can be placed on the channel layer (CH_L). The gate structure (GS) can be placed across the channel layer (CH_L) and the device isolation layer (STI).

[0109] The gate structure (GS) may include a gate insulating layer (130) sequentially stacked on a channel layer (CH_L), a lower gate conductive layer (120), a ferroelectric layer (135), and an upper gate conductive layer (125). The gate structure (GS) may further include a filling gate conductive layer (127) disposed on the upper gate conductive layer (125).

[0110] The gate insulating layer (130) is disposed on the channel layer (CH_L). The gate insulating layer (130) can be in contact with the channel layer (CH_L).

[0111] The lower gate conductive layer (120) may be in contact with the gate insulating layer (130). The lower gate conductive layer (120) may include graphene. For example, the lower gate conductive layer (120) may be a lower gate graphene layer.

[0112] The details regarding the material included in the lower gate conductive layer (120) and the filling gate conductive layer (127) may be substantially the same as those described using FIGS. 1 to 9.

[0113] For example, the ferroelectric layer (135) may include h-BN formed as a double layer. The upper gate conductive layer (125) may include graphene disposed on the ferroelectric layer (135). The upper gate conductive layer (125) may include graphene. The upper gate conductive layer (125) may be an upper gate graphene layer. The upper gate conductive layer (125) is in contact with the ferroelectric layer (135).

[0114] As another example, the ferroelectric layer (135) may include MoS2 in a double layer. The stacked structure of MoS2 included in the channel layer (CH_L) is different from the stacked structure of MoS2 included in the ferroelectric layer (135).

[0115] The upper gate conductive layer (125) may include an upper gate graphene layer containing graphene. The upper gate conductive layer (125) may include an insert gate layer disposed between the upper gate graphene layer and the ferroelectric layer. The insert gate layer may include h-BN made of a single layer. The insert gate layer may be in contact with the ferroelectric layer (135).

[0116] The filling gate conductive layer (127) can be placed on the upper gate conductive layer (125).

[0117] A gate hard mask pattern (GS_HM) is disposed on the upper surface of a gate structure (GS). The gate hard mask pattern (GS_HM) is disposed on an upper gate conductive layer (125). The gate hard mask pattern (GS_HM) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), and silicon oxide (SiO2).

[0118] The gate spacer (140) is placed on the channel layer (CH_L). The gate spacer (140) is placed on the sidewall of the gate structure (GS). The gate insulating layer (130) does not extend along the sidewall of the gate spacer (140).

[0119] The first interlayer insulating film (190) is placed on the channel layer (CH_L). The first interlayer insulating film (190) is placed on the gate hard mask pattern (GS_HM).

[0120] The fourth source / drain contact (480) is disposed on the channel layer (CH_L). The fourth source / drain contact (480) may be disposed on both sides of the gate structure (GS). The fourth source / drain contact (480) may penetrate the first interlayer insulating film (190) and be connected to the channel layer (CH_L).

[0121] FIG. 13 is a drawing illustrating a semiconductor device according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 11 and FIG. 12.

[0122] Referring to FIG. 13, in a semiconductor device according to some embodiments, a gate insulating layer (130), a lower gate conductive layer (120), a ferroelectric layer (135), and an upper gate conductive layer (125) may each extend along the upper surface of the channel layer (CH_L) and the side wall of the gate spacer (140).

[0123] The filling gate conductive layer (127) can fill the recess defined by the upper gate conductive layer (125).

[0124] The upper surface of the gate structure (GS) can be placed in the same plane as the upper surface of the first interlayer insulating film (190).

[0125] Although not shown, a gate capping pattern may be placed on the filling gate conductive layer (127). In this case, the upper surface of the gate capping pattern may be placed in the same plane as the upper surface of the first interlayer insulating film (190).

[0126] The second interlayer insulating film (195) is disposed on the first interlayer insulating film (190), the gate structure (GS), and the gate spacer (140).

[0127] The fourth source / drain contact (480) can be connected to the channel layer (CH_L) by penetrating the first interlayer insulating film (190) and the second interlayer insulating film (195).

[0128] FIGS. 14 to 19 are intermediate step drawings for explaining a method for manufacturing a semiconductor device according to some embodiments.

[0129] For reference, FIGS. 14, 16, 18, and 19 may be cross-sectional views taken along A-A of FIG. 1. FIGS. 15 and 17 may be cross-sectional views taken along B-B of FIG. 1.

[0130] Referring to FIGS. 14 and 15, a first active pattern (AP1), a second active pattern (AP2), and a third active pattern (AP3) are formed on a substrate (100).

[0131] More specifically, a mold structure is formed on a substrate (100). The mold structure may include a plurality of mold unit structures. The mold unit structures may include a separation insulating film, an active film, and an electrode film sequentially stacked on the substrate (100).

[0132] In order to make the mold structure have a stepped structure, a photolithography process may be performed. Subsequently, the mold structure having the stepped structure may be patterned using an etching process. Through this, a first active pattern (AP1), a second active pattern (AP2), and a third active pattern (AP3) having a stepped structure may be formed.

[0133] While the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) are being formed, a first channel isolation insulating layer (165) is formed between the substrate (100) and the first active pattern (AP1). A second channel isolation insulating layer (265) is formed between the first active pattern (AP1) and the second active pattern (AP2). A third channel isolation insulating layer (365) is formed between the second active pattern (AP2) and the third active pattern (AP3).

[0134] While the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3) are being formed, a first pre-source / drain electrode (160P) is formed between the first active pattern (AP1) and the second channel separation insulating layer (265). A second pre-source / drain electrode (260P) is formed between the second active pattern (AP2) and the third channel separation insulating layer (365). A third pre-source / drain electrode (360P) is formed on the third active pattern (AP3).

[0135] The first interlayer insulating film (190) can be formed on the first active pattern (AP1), the second active pattern (AP2), and the third active pattern (AP3).

[0136] Referring to FIGS. 16 and 17, a mask pattern (MASK) can be formed on the first interlayer insulating film (190).

[0137] A gate trench (GS_T) can be formed using a mask pattern (MASK). Channel isolation insulating layers (165, 265, 365) exposed by the mask pattern (MASK) can be removed. Additionally, free source / drain electrodes (160P, 260P, 360P) exposed by the mask pattern (MASK) can be removed. While the gate trench (GS_T) is being formed, a portion of the free source / drain electrodes (160P, 260P, 360P) may be removed to form source / drain electrodes (160, 260, 360).

[0138] Referring to FIG. 18, a free gate insulating layer (130P), a free lower gate conductive layer (120P), a free ferroelectric layer (135P), and a free upper gate conductive layer (125P) can be sequentially formed along the perimeter of an active pattern (AP1, AP2, AP3).

[0139] For example, a free gate insulating layer (130P), a free lower gate conductive layer (120P), a free ferroelectric layer (135P), and a free upper gate conductive layer (125P) can be transferred onto an active pattern (AP1, AP2, AP3).

[0140] The free gate insulating layer (130P), the free lower gate conductive layer (120P), the free ferroelectric layer (135P), and the free upper gate conductive layer (125P) may be formed along the sidewalls and bottom surfaces of the gate trench (GS_T). The free gate insulating layer (130P), the free lower gate conductive layer (120P), the free ferroelectric layer (135P), and the free upper gate conductive layer (125P) may be formed along the upper surface of the first interlayer insulating film (190).

[0141] A pre-filling gate conductive layer (127P) is formed on a pre-upper gate conductive layer (125P). The pre-filling gate conductive layer (127P) can fill the gate trench (GS_T). The pre-filling gate conductive layer (127P) can be formed on the upper surface of the first interlayer insulating film (190).

[0142] Referring to FIGS. 18 and 19, the free gate insulating layer (130P), free lower gate conductive layer (120P), free ferroelectric layer (135P), free upper gate conductive layer (125P) and free filling gate conductive layer (127P) on the upper surface of the first interlayer insulating film (190) can be removed.

[0143] Through this, a gate structure (GS) can be formed within the gate trench (GS_T).

[0144] Next, referring to FIG. 2, a second interlayer insulating film (195) may be formed on the first interlayer insulating film (190) and the gate structure (GS). Subsequently, source / drain contacts (180, 280, 380) may be formed.

[0145] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0146] 100: Substrate 120: Lower gate conductive layer 125: Upper gate conductive layer 130: Gate insulating layer 135: Ferroelectric layer 160, 260, 360: Source / drain electrodes AP1, AP2, AP3: Activation pattern CH_L: Channel layer

Claims

Claim 1 A semiconductor device comprising: a substrate; a gate structure disposed on the substrate and extending in a first direction; and an active pattern spaced apart from the substrate in a second direction and extending in a third direction and penetrating the gate structure, wherein the active pattern comprises a two-dimensional semiconductor material, and the gate structure comprises a gate insulating layer, a lower gate conductive layer, a ferroelectric layer, and an upper gate conductive layer sequentially stacked on the active pattern, wherein the gate insulating layer comprises h-BN (hexagonal boron nitride), and the ferroelectric layer comprises a two-dimensional material formed as a bilayer. Claim 2 In claim 1, the semiconductor device wherein the ferroelectric layer comprises h-BN. Claim 3 In claim 2, the stacked structure of the ferroelectric layer is different from the stacked structure of the gate insulating layer in the semiconductor device. Claim 4 In claim 2, the lower gate conductive layer and the upper gate conductive layer each comprise graphene, and the graphene included in the upper gate conductive layer is in contact with the ferroelectric layer. Claim 5 In claim 1, the ferroelectric layer comprises MoS2 in a semiconductor device. Claim 6 A semiconductor device according to claim 5, wherein the upper gate conductive layer comprises a first sub-gate conductive layer and a second sub-gate conductive layer sequentially stacked on the ferroelectric layer, the lower gate conductive layer and the second sub-gate conductive layer each comprise graphene, and the first sub-gate conductive layer comprises h-BN formed as a monolayer. Claim 7 In claim 5, the active pattern comprises MoS2, and the stacked structure of the ferroelectric layer is different from the stacked structure of the active pattern in a semiconductor device. Claim 8 A semiconductor device according to claim 7, wherein the ferroelectric layer has a C3v point group and the active pattern has one of a point group D3h and D3d. Claim 9 A semiconductor device comprising: a channel layer including a two-dimensional semiconductor material on a substrate; a gate structure disposed on the channel layer; and source / drain contacts disposed on both sides of the gate structure and connected to the channel layer, wherein the gate structure comprises a gate insulating layer including h-BN, a lower gate graphene layer including graphene on the gate insulating layer, a ferroelectric layer including a two-dimensional material formed by a double layer on the lower gate graphene layer, and an upper gate graphene layer including graphene on the ferroelectric layer. Claim 10 A substrate; a gate structure disposed on the substrate and extending in a first direction; a first active pattern spaced apart from the substrate in a second direction and extending in a third direction, penetrating the gate structure; a second active pattern disposed on the first active pattern, spaced apart from the first active pattern in a second direction and extending in the third direction, penetrating the gate structure, wherein the length of the second active pattern in the third direction is smaller than the length of the first active pattern in the third direction; a first source / drain contact connected to the first active pattern and unconnected to the second active pattern; A semiconductor device comprising a second source / drain contact connected to the second active pattern and disconnected from the first active pattern, wherein the first active pattern and the second active pattern comprise a two-dimensional semiconductor material, and the gate structure comprises a gate insulating layer comprising h-BN extending along the perimeter of the first active pattern and the perimeter of the second active pattern, a lower gate graphene layer comprising graphene extending along the perimeter of the first active pattern and the perimeter of the second active pattern on the gate insulating layer, a ferroelectric layer comprising a two-dimensional material formed of a double layer extending along the perimeter of the first active pattern and the perimeter of the second active pattern on the lower gate graphene layer, an upper gate conductive layer extending along the perimeter of the first active pattern and the perimeter of the second active pattern on the ferroelectric layer, and a filling gate conductive layer disposed on the upper gate conductive layer.

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