Display panel and display device

Abstract

A display panel and display device according to embodiments of the present disclosure can prevent the first transistor from being exposed to hydrogen or light by including a first active layer, a first source electrode connected to one side of the first active layer, a first drain electrode connected to the other side of the first active layer, and a first gate electrode that overlaps with the first active layer, overlaps with all or part of the first source electrode, and overlaps with all or part of the first drain electrode, thereby preventing the first transistor from being exposed to hydrogen or light.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to display panels and display devices. Background Technology

[0002] Transistors are widely used in the field of electronic devices as switching devices or driving devices.

[0003] In particular, since thin-film transistors can be manufactured on glass or plastic substrates, they are widely used as driving elements (driving transistors) or switching elements (switching transistors) in display devices such as liquid crystal display devices or organic light-emitting display devices. However, if these transistors are exposed to light or hydrogen, their device characteristics change, and the transistors may fail to achieve the desired device performance. The problem to be solved

[0004] Embodiments of the present disclosure may provide a display panel and a display device comprising a transistor having a structure robust to exposure to light or hydrogen.

[0005] The embodiments of the present disclosure can provide a display panel and a display device including a transistor having a structure that is not exposed to light or hydrogen, even if the transistor has a top gate structure that is highly likely to be exposed to light or hydrogen, etc.

[0006] The embodiments of the present disclosure may provide a display panel and a display device having a transistor having a structure that is not exposed to light or hydrogen, etc., in a display panel having an upper light-emitting structure that is highly likely to be exposed to light or hydrogen, etc.

[0007] Embodiments of the present disclosure may provide a display panel and a display device comprising different types of transistors having structures differentiated according to the advantages and disadvantages of changes in device characteristics due to exposure to light or hydrogen, etc. means of solving the problem

[0008] A display panel according to embodiments of the present disclosure may include a data signal line for supplying a data signal, a scan signal line for supplying a scan signal, and a subpixel connected to the data signal line and the scan signal line and including a first transistor.

[0009] The first transistor may include a first active layer, a first source electrode connected to one side of the first active layer, a first drain electrode connected to the other side of the first active layer, and a first gate electrode that overlaps with the first active layer, overlaps with all or part of the first source electrode, and overlaps with all or part of the first drain electrode.

[0010] The subpixel may further include a light-emitting element, a second transistor, and a storage capacitor.

[0011] The light-emitting element may include a first electrode, a light-emitting layer, and a second electrode.

[0012] The second transistor may include a second active layer, a second source electrode connected to one side of the second active layer, a second drain electrode connected to the other side of the second active layer, and a second gate electrode that overlaps with a part of the second active layer and does not overlap with the second source electrode and the second drain electrode.

[0013] The first transistor is a driving transistor, and the second transistor may be a scan transistor, which is a type of switching transistor.

[0014] The first gate electrode of the first transistor may be a top gate electrode located on the first active layer, and the second gate electrode of the second transistor may be a top gate electrode located on the second active layer.

[0015] A display panel according to embodiments of the present disclosure may further include a side shield disposed between a storage capacitor and a first transistor. The side shield may include a trench-shaped contact hole line in which a second capacitor electrode and a first gate electrode are connected.

[0016] A display panel according to embodiments of the present disclosure may further include a substrate, a buffer layer on the substrate, and a lower shield located between the substrate and the buffer layer and overlapping with a first active layer.

[0017] The lower shield can be electrically connected to the first source electrode.

[0018] Alternatively, the lower shield can be electrically connected to the first gate electrode.

[0019] The first gate electrode may include a first lower gate electrode and a first upper gate electrode. The first lower gate electrode is in contact with the second capacitor electrode and may include the same material as the first capacitor electrode.

[0020] In a display panel according to embodiments of the present disclosure, the light-emitting region of a subpixel may be located above a storage capacitor.

[0021] In a display panel according to embodiments of the present disclosure, the first gate electrode is composed of a single layer and may include the same material as the first capacitor electrode.

[0022] In a display panel according to embodiments of the present disclosure, the light-emitting region of a subpixel may overlap with a first transistor and be located above the first transistor.

[0023] In a display panel according to embodiments of the present disclosure, the area where the first source electrode and the first gate electrode overlap may be larger than the area where the first drain electrode and the first gate electrode overlap.

[0024] In a display panel according to embodiments of the present disclosure, an additional storage capacitor may be configured as the first source electrode and the first gate electrode overlap.

[0025] A display device according to embodiments of the present disclosure may include a substrate, and a first transistor and a second transistor on the substrate.

[0026] The first transistor may include a first active layer, a first source electrode connected to one side of the first active layer, a first drain electrode connected to the other side of the first active layer, and a first gate electrode that overlaps all or part of the first active layer.

[0027] The second transistor may include a second active layer, a second source electrode connected to one side of the second active layer, a second drain electrode connected to the other side of the second active layer, and a second gate electrode that overlaps with a part of the second active layer.

[0028] It may further include a gate insulating film disposed between the first active layer and the first gate electrode and between the second active layer and the second gate electrode.

[0029] In the gate insulating film, the hydrogen concentration or light exposure amount in the portion between the first active layer and the first gate electrode may be lower than the hydrogen concentration or light exposure amount in the portion between the second active layer and the second gate electrode. Effects of the invention

[0030] According to embodiments of the present disclosure, a display panel and a display device comprising a transistor having a structure robust to exposure to light or hydrogen can be provided.

[0031] According to embodiments of the present disclosure, a display panel and a display device can be provided that include a transistor having a structure that is not exposed to light or hydrogen, even if the transistor has a top gate structure that is highly likely to be exposed to light or hydrogen.

[0032] According to embodiments of the present disclosure, a display panel and a display device can be provided that include a transistor having a structure not exposed to light or hydrogen, etc., in a display panel having an upper light-emitting structure that is highly likely to be exposed to light or hydrogen, etc.

[0033] According to embodiments of the present disclosure, a display panel and a display device may be provided that include different types of transistors having structures differentiated according to the advantages and disadvantages of changes in device characteristics due to exposure to light or hydrogen. Brief explanation of the drawing

[0034] FIG. 1 is a schematic system configuration diagram of a display device according to embodiments of the present disclosure. FIGS. 2 and FIGS. 3 are equivalent circuits of a subpixel of a display device according to embodiments of the present disclosure. FIG. 4 is an exemplary system configuration diagram of a display device according to embodiments of the present disclosure. FIG. 5 shows a schematic structure of a display panel according to embodiments of the present disclosure. FIG. 6 is a cross-sectional view of a display panel according to embodiments of the present disclosure. Figure 7 is a plan view of the display panel of Figure 6. Figure 8 is a plan view showing only the parts related to the first transistor selected from the plan view of Figure 7. Figure 9 is a plan view showing only the parts related to the storage capacitor selected from the plan view of Figure 7. FIG. 10 shows the differential characteristics regarding the blocking of light and hydrogen of a display panel according to embodiments of the present disclosure. FIG. 11 shows a parasitic capacitor utilization structure of a display panel according to embodiments of the present disclosure. FIG. 12 is another cross-sectional view of a display panel according to embodiments of the present disclosure. FIG. 13 is another cross-sectional view of a display panel according to embodiments of the present disclosure. Fig. 14 is a plan view of the display panel of Fig. 13. FIG. 15 is a plan view showing only the parts related to the first transistor selected from the plan view of FIG. 14. Figure 16 is a plan view showing only the parts related to the storage capacitor selected from the plan view of Figure 14. FIG. 17 illustrates the differential characteristics regarding the blocking of light and hydrogen of a display panel according to embodiments of the present disclosure. FIG. 18 shows a parasitic capacitor utilization structure of a display panel according to embodiments of the present disclosure. FIG. 19 is another cross-sectional view of a display panel according to embodiments of the present disclosure. Specific details for implementing the invention

[0035] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions may obscure the essence of the present disclosure, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless there is a special explicit description otherwise.

[0036] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used to describe the components of the present disclosure. These terms are used merely to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by such terms.

[0037] In describing the positional relationship of components, where it is stated that two or more components are "connected," "combined," or "joined," it should be understood that while the two or more components may be directly "connected," "combined," or "joined," they may also be "connected," "combined," or "joined" with other components "intervened." Here, the other components may be included in one or more of the two or more components that are "connected," "combined," or "joined" with one another.

[0038] In describing the temporal flow relationship regarding components, methods of operation, or methods of production, for example, when the temporal or sequential relationship is described using "after," "following," "next," or "before," it may include cases where the relationship is not continuous unless "immediately" or "directly" is used.

[0039] Meanwhile, where numerical values ​​or corresponding information regarding a component (e.g., levels, etc.) are mentioned, even without separate explicit notation, the numerical values ​​or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0040] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0041] FIG. 1 is a schematic system configuration diagram of a display device (100) according to embodiments of the present disclosure.

[0042] Referring to FIG. 1, a display device (100) according to embodiments of the present disclosure may include a display panel (110) and a driving circuit for driving the display panel (110).

[0043] The driving circuit may include a data driving circuit (120) and a gate driving circuit (130), and may further include a controller (140) that controls the data driving circuit (120) and the gate driving circuit (130).

[0044] A display panel (110) may include a substrate (SUB) and signal wiring such as a plurality of data signal lines (DL) and a plurality of gate signal lines (GL) disposed on the substrate (SUB). The display panel (110) may include a plurality of subpixels (SP) connected to a plurality of data signal lines (DL) and a plurality of gate signal lines (GL).

[0045] The display panel (110) may include a display area (DA) where an image is displayed and a non-display area (NDA) where an image is not displayed. In the display panel (110), a plurality of subpixels (SP) for displaying an image are arranged in the display area (DA), and driving circuits (120, 130, 140) may be electrically connected or driving circuits (120, 130, 140) may be mounted in the non-display area (NDA), and a pad portion to which an integrated circuit or printed circuit is connected may be arranged.

[0046] The data driving circuit (120) is a circuit for driving a plurality of data signal lines (DL) and can supply data signals to a plurality of data signal lines (DL). The gate driving circuit (130) is a circuit for driving a plurality of gate signal lines (GL) and can supply gate signals to a plurality of gate signal lines (GL). The controller (140) can supply a data control signal (DCS) to the data driving circuit (120) to control the operation timing of the data driving circuit (120). The controller (140) can supply a gate control signal (GCS) to the gate driving circuit (130) to control the operation timing of the gate driving circuit (130).

[0047] The controller (140) can start scanning according to the timing implemented in each frame, convert externally input image data to match the data signal format used by the data driving circuit (120), supply the converted image data (Data) to the data driving circuit (120), and control data driving at an appropriate time in accordance with the scan.

[0048] The controller (140) receives various timing signals, including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE: Data Enable), a clock signal (CLK), etc., along with input video data from an external source (e.g., a host system (150)).

[0049] The controller (140) receives timing signals such as a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE), and a clock signal (CLK) to control the data driving circuit (120) and the gate driving circuit (130), generates various control signals (DCS, GCS), and outputs them to the data driving circuit (120) and the gate driving circuit (130).

[0050] For example, the controller (140) outputs various gate control signals (GCS: Gate Control Signal), including a gate start pulse (GSP: Gate Start Pulse), a gate shift clock (GSC: Gate Shift Clock), and a gate output enable signal (GOE: Gate Output Enable), in order to control the gate driving circuit (130).

[0051] Additionally, the controller (140) outputs various data control signals (DCS), including a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE), in order to control the data driving circuit (120).

[0052] The controller (140) may be implemented as a separate component from the data driving circuit (120), or it may be integrated with the data driving circuit (120) to be implemented as an integrated circuit.

[0053] The data driving circuit (120) receives image data (Data) from the controller (140) and drives the multiple data signal lines (DL) by supplying the data signal to the multiple data signal lines (DL). Here, the data driving circuit (120) is also referred to as a source driving circuit.

[0054] This data driving circuit (120) may include one or more source driver integrated circuits (SDIC).

[0055] Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, etc. Each source driver integrated circuit (SDIC) may additionally include an analog-to-digital converter (ADC) depending on the case.

[0056] For example, each source driver integrated circuit (SDIC) may be connected to the display panel (110) by Tape Automated Bonding (TAB), connected to the bonding pad of the display panel (110) by Chip On Glass (COG) or Chip On Panel (COP), or connected to the display panel (110) by Chip On Film (COF).

[0057] The gate driving circuit (130) can output a gate signal of a turn-on level voltage or a gate signal of a turn-off level voltage according to the control of the controller (140). The gate driving circuit (130) can sequentially drive a plurality of gate signal lines (GL) by sequentially supplying a gate signal of a turn-on level voltage to a plurality of gate signal lines (GL).

[0058] The gate driving circuit (130) may be connected to the display panel (110) via tape automatic bonding (TAB), connected to the bonding pad of the display panel (110) via chip-on-glass (COG) or chip-on-panel (COP) methods, or connected to the display panel (110) via chip-on-film (COF) methods. Alternatively, the gate driving circuit (130) may be formed in the non-display area (NDA) of the display panel (110) in the form of a gate-in-panel (GIP) type. The gate driving circuit (130) may be placed on a substrate (SUB) or connected to the substrate (SUB). That is, if the gate driving circuit (130) is of the GIP type, it may be placed in the non-display area (NDA) of the substrate (SUB). If the gate driving circuit (130) is of the chip-on-glass (COG) type, chip-on-film (COF) type, etc., it may be connected to the substrate (SUB).

[0059] Meanwhile, at least one of the data driving circuit (120) and the gate driving circuit (130) may be placed in the display area (DA). For example, at least one of the data driving circuit (120) and the gate driving circuit (130) may be placed so as not to overlap with the subpixels (SP), or may be placed so as to partially or entirely overlap with the subpixels (SP).

[0060] The data driving circuit (120) can convert image data (Data) received from the controller (140) into an analog data signal and supply it to a plurality of data signal lines (DL) when a specific gate signal line (GL) is opened by the gate driving circuit (130).

[0061] The data driving circuit (120) may be connected to one side (e.g., the upper side or the lower side) of the display panel (110). Depending on the driving method, panel design method, etc., the data driving circuit (120) may be connected to both sides (e.g., the upper side and the lower side) of the display panel (110), or to two or more sides of the four sides of the display panel (110).

[0062] The gate driving circuit (130) may be connected to one side (e.g., left or right) of the display panel (110). Depending on the driving method, panel design method, etc., the gate driving circuit (130) may be connected to both sides (e.g., left and right) of the display panel (110), or to two or more of the four sides of the display panel (110).

[0063] The controller (140) may be a timing controller used in conventional display technology, or a control device capable of performing other control functions including a timing controller, or a control device different from a timing controller, or a circuit within a control device. The controller (140) may be implemented as various circuits or electronic components such as an IC (Integrate Circuit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or processor.

[0064] The controller (140) is mounted on a printed circuit board, a flexible printed circuit, etc., and can be electrically connected to a data driving circuit (120) and a gate driving circuit (130) through the printed circuit board, the flexible printed circuit, etc.

[0065] The controller (140) can transmit and receive signals to and from the data driving circuit (120) according to one or more predetermined interfaces. Here, for example, the interface may include an LVDS (Low Voltage Differential Signaling) interface, an EPI interface, an SPI (Serial Peripheral Interface), etc.

[0066] The controller (140) may include one or more memory media, such as registers.

[0067] The display device (100) according to the embodiments of the present invention may be a display including a backlight unit such as a liquid crystal display, or a self-emissive display such as an OLED (Organic Light Emitting Diode) display, a Quantum Dot display, or a Micro LED (Micro Light Emitting Diode) display.

[0068] In the case where the display device (100) according to the present embodiment is an OLED display, each subpixel (SP) may include a self-emitting organic light-emitting diode (OLED) as a light-emitting element. In the case where the display device (100) according to the present embodiment is a quantum dot display, each subpixel (SP) may include a light-emitting element made of a quantum dot, which is a semiconductor crystal that emits light. In the case where the display device (100) according to the present embodiment is a micro LED display, each subpixel (SP) may include a self-emitting micro LED (Micro Light Emitting Diode) made based on inorganic materials as a light-emitting element.

[0069] FIGS. 2 and FIGS. 3 are equivalent circuits of a subpixel (SP) of a display device (100) according to embodiments of the present disclosure.

[0070] Referring to FIG. 2, each of the plurality of subpixels (SP) arranged in the display panel (110) of the display device (100) according to embodiments of the present disclosure may include a light-emitting element (ED), a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst).

[0071] Referring to FIG. 2, the light-emitting element (ED) may include a first electrode (E1) and a second electrode (E2), and may include a light-emitting layer (EL) located between the first electrode (E1) and the second electrode (E2).

[0072] The first electrode (E1) of the light-emitting element (ED) may be a pixel electrode placed for each subpixel (SP), and the second electrode (E2) of the light-emitting element (ED) may be a common electrode placed for all subpixels (SP). Conversely, the first electrode (E1) may be a common electrode and the second electrode (E2) may be a pixel electrode. A base voltage (EVSS), which is a type of common voltage for display driving, may be applied to the second electrode (E2) or the first electrode (E1) corresponding to the common electrode.

[0073] The first electrode (E1) may be an anode electrode and the second electrode (E2) may be a cathode electrode. Conversely, the first electrode (E1) may be a cathode electrode and the second electrode (E2) may be an anode electrode.

[0074] Below, for convenience of explanation, an example is given in which the first electrode (E1) is a pixel electrode and an anode electrode, and the second electrode (E2) is a common electrode and a cathode electrode.

[0075] In addition, for example, the light-emitting device (ED) may be an organic light-emitting diode (OLED), a light-emitting diode (LED), or a quantum dot light-emitting device.

[0076] The first transistor (T1) is a driving transistor for driving a light-emitting element (ED) and may include a first node (N1), a second node (N2), and a third node (N3), etc.

[0077] The first node (N1) of the first transistor (T1) may be the gate node of the first transistor (T1) and may be electrically connected to the source node or drain node of the second transistor (T2).

[0078] The second node (N2) of the first transistor (T1) may be the source node or drain node of the first transistor (T1), and may be electrically connected to the source node or drain node of the third transistor (T3) and may also be electrically connected to the first electrode (E1) of the light-emitting element (ED).

[0079] The third node (N3) of the first transistor (T1) can be electrically connected to a driving voltage line (DVL) that supplies a driving voltage (EVDD), which is another type of common voltage for driving the display.

[0080] The second transistor (T2) is controlled to turn on and off by a scan signal (SC), which is a type of gate signal, and can be connected between the first node (N1) of the first transistor (T1) and the data signal line (DL). The second transistor (T2) is also called a scan transistor.

[0081] The second transistor (T2) can be turned on or turned off according to the scan signal (SC) supplied from the scan signal line (SCL) to control the connection between the data signal line (DL) and the first node (N1) of the first transistor (T1). Here, the scan signal line (SCL) may be a type of gate signal line (GL), and the scan signal (SC) may be a type of gate signal.

[0082] The second transistor (T2) can be turned on by a scan signal (SC) having a turn-on level voltage and transmit a data signal (Vdata) supplied from a data signal line (DL) to the first node (N1) of the first transistor (T1).

[0083] Here, if the second transistor (T2) is an n-type transistor, the turn-on level voltage of the scan signal (SC) may be a high level voltage. If the second transistor (T2) is a p-type transistor, the turn-on level voltage of the scan signal (SC) may be a low level voltage.

[0084] A storage capacitor (Cst) can be connected between the first node (N1) and the second node (N2) of the first transistor (T1).

[0085] The storage capacitor (Cst) is charged with an amount of charge corresponding to the voltage difference between the two ends and serves to maintain the voltage difference between the two ends for a set frame time. Accordingly, the corresponding subpixel (SP) can emit light for a set frame time.

[0086] Referring to FIG. 3, each of the plurality of subpixels (SP) arranged on the display panel (110) of the display device (100) according to embodiments of the present disclosure may further include a third transistor (T3).

[0087] The third transistor (T3) is controlled by a sensing signal (SE), which is a type of gate signal, and can be connected between the second node (N2) of the first transistor (T1) and the reference voltage line (RVL). The third transistor (T3) is also called a sensing transistor.

[0088] In other words, the third transistor (T3) can be turned on or turned off according to the sensing signal (SE) supplied from the sensing signal line (SENL), which is another type of gate signal line (GL), thereby controlling the connection between the reference voltage line (RVL) and the second node (N2) of the first transistor (T1).

[0089] The third transistor (T3) is turned on by a sensing signal (SE) having a turn-on level voltage, and can transmit the reference voltage (Vref) supplied from the reference voltage line (RVL) to the second node (N2) of the first transistor (T1).

[0090] Additionally, the third transistor (T3) can be turned on by a sensing signal (SE) having a turn-on level voltage to transmit the voltage of the second node (N2) of the first transistor (T1) to the reference voltage line (RVL).

[0091] Here, if the third transistor (T3) is an n-type transistor, the turn-on level voltage of the sensing signal (SE) may be a high level voltage. If the third transistor (T3) is a p-type transistor, the turn-on level voltage of the sensing signal (SE) may be a low level voltage.

[0092] The function of the third transistor (T3) transmitting the voltage of the second node (N2) of the first transistor (T1) to the reference voltage line (RVL) can be used during driving to sense the characteristic value of the subpixel (SP). In this case, the voltage transmitted to the reference voltage line (RVL) may be a voltage for calculating the characteristic value of the subpixel (SP) or a voltage reflecting the characteristic value of the subpixel (SP).

[0093] In the present disclosure, the characteristic value of the subpixel (SP) may be the characteristic value of the first transistor (T1) or the light-emitting element (ED). The characteristic value of the first transistor (T1) may include the threshold voltage and mobility of the first transistor (T1). The characteristic value of the light-emitting element (ED) may include the threshold voltage of the light-emitting element (ED).

[0094] In the display panel (110) according to the embodiments of the present disclosure, the first transistor (T1), the second transistor (T2), and the third transistor (T3) may each be an n-type transistor or a p-type transistor. In the present disclosure, for convenience of explanation, the first transistor (T1), the second transistor (T2), and the third transistor (T3) are each given as examples of being n-type.

[0095] In the display panel (110) according to the embodiments of the present disclosure, the first transistor (T1) is also referred to as a driving transistor for current driving, and the second transistor (T2) and the third transistor (T3) are also referred to as switching transistors that perform a switching function.

[0096] The storage capacitor (Cst) may be an external capacitor intentionally designed outside the first transistor (T1), rather than a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor existing between the gate node and the source node (or drain node) of the first transistor (T1).

[0097] The scan signal line (SCL) and the sensing signal line (SENL) may be different gate signal lines (GL). In this case, the scan signal (SC) and the sensing signal (SE) may be separate gate signals, and the on-off timing of the second transistor (T2) and the on-off timing of the third transistor (T3) within a single subpixel (SP) may be independent. That is, the on-off timing of the second transistor (T2) and the on-off timing of the third transistor (T3) within a single subpixel (SP) may be the same or different.

[0098] Alternatively, the scan signal line (SCL) and the sensing signal line (SENL) may be the same gate signal line (GL). That is, the gate node of the second transistor (T2) and the gate node of the third transistor (T3) within a single subpixel (SP) may be connected to a single gate signal line (GL). In this case, the scan signal (SC) and the sensing signal (SE) may be the same gate signal, and the on-off timing of the second transistor (T2) and the on-off timing of the third transistor (T3) within a single subpixel (SP) may be the same.

[0099] The structure of the subpixel (SP) shown in FIGS. 2 and FIGS. 3 is merely an example and can be varied in many ways by including one or more additional transistors or one or more additional capacitors.

[0100] Additionally, in FIGS. 2 and 3, the sub-pixel structure was described assuming that the display device (100) is a self-emissive display device, but if the display device (100) is a liquid crystal display device, each sub-pixel (SP) may include a transistor and a pixel electrode, etc.

[0101] FIG. 4 is an exemplary system configuration diagram of a display device (100) according to embodiments of the present disclosure.

[0102] Referring to FIG. 4, the display panel (110) may include a display area (DA) where an image is displayed and a non-display area (NDA) where an image is not displayed.

[0103] Referring to FIG. 4, when the data driving circuit (120) includes one or more source driver integrated circuits (SDIC) and is implemented in a chip-on-film (COF) manner, each source driver integrated circuit (SDIC) may be mounted on a circuit film (SF) connected to a non-display area (NDA) of a display panel (110).

[0104] Referring to FIG. 4, the gate driving circuit (130) can be implemented as a gate-in-panel (GIP) type. In this case, the gate driving circuit (130) can be formed in a gate driving circuit area (GIPA) included in a non-display area (NDA) of the display panel (110). Unlike FIG. 4, the gate driving circuit (130) can also be implemented as a COF (Chip On Film) type.

[0105] A display device (100) may include at least one source printed circuit board (SPCB) for circuit connection between one or more source driver integrated circuits (SDIC) and other devices, and a control printed circuit board (CPCB) for mounting control components and various electrical devices.

[0106] A film (SF) on which a source driver integrated circuit (SDIC) is mounted can be connected to at least one source printed circuit board (SPCB). That is, one side of the film (SF) on which the source driver integrated circuit (SDIC) is mounted can be electrically connected to a display panel (110) and the other side can be electrically connected to a source printed circuit board (SPCB).

[0107] A controller (140) and a power management integrated circuit (PMIC: Power Management IC, 410) may be mounted on the control printed circuit board (CPCB). The controller (140) can perform overall control functions related to the driving of the display panel (110) and can control the operation of the data driving circuit (120) and the gate driving circuit (130). The power management integrated circuit (410) can supply various voltages or currents to the data driving circuit (120) and the gate driving circuit (130), or control various voltages or currents to be supplied.

[0108] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be circuitously connected through at least one connecting cable (CBL). Here, the connecting cable (CBL) may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc.

[0109] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0110] A display device (100) according to embodiments of the present disclosure may further include a level shifter (400) for adjusting a voltage level. For example, the level shifter (400) may be placed on a control printed circuit board (CPCB) or a source printed circuit board (SPCB).

[0111] In particular, in the display device (100) according to the embodiments of the present disclosure, the level shifter (400) can supply signals required for gate driving to the gate driving circuit (130). For example, the level shifter (400) can supply a plurality of clock signals to the gate driving circuit (130). Accordingly, the gate driving circuit (130) can generate a plurality of gate signals (e.g., scan signal (SC), sensing signal (SE), etc.) based on the plurality of clock signals input from the level shifter (400) and output them to a plurality of gate signal lines (GL, e.g., scan signal line (SCL), sensing signal line (SENL)). Here, the plurality of gate signal lines (GL) can transmit a plurality of gate signals (e.g., scan signal (SC), sensing signal (SE), etc.) to subpixels (SP) placed in the display area (DA) of the substrate (SUB).

[0112] FIG. 5 shows the schematic structure of a display panel (110) according to embodiments of the present disclosure.

[0113] Referring to FIG. 5, each of the plurality of subpixels (SP) placed in the display area (DA) of the display panel (110) may include a light-emitting element (ED), a first transistor (T1) for driving the light-emitting element (ED), a second transistor (T2) for transmitting a data signal (Vdata) to a first node (N1) of the first transistor (T1), and a storage capacitor (Cst) for maintaining a constant voltage for one frame.

[0114] The first transistor (T1) may include a first node (N1) to which a data signal (Vdata) can be applied, a second node (N2) electrically connected to a light-emitting element (ED), and a third node (N3) to which a driving voltage (EVDD) is applied from a driving voltage line (DVL). In the first transistor (T1), the first node (N1) may be a gate node, the second node (N2) may be a source node or a drain node, and the third node (N3) may be a drain node or a source node. Hereinafter, for convenience of explanation, the first node (N1) of the first transistor (T1) is also referred to as a gate node or a gate electrode, the second node (N2) of the first transistor (T1) is also referred to as a source node or a source electrode, and the third node (N3) of the first transistor (T1) is also referred to as a drain node or a drain electrode.

[0115] A light-emitting element (ED) may include a first electrode (E1), a light-emitting layer (EL), and a second electrode (E2). The first electrode (E1) of the light-emitting element (ED) may be electrically connected to the second node (N2) of the first transistor (T1) of each subpixel (SP). The second electrode (E2) of the light-emitting element (ED) may receive a base voltage (EVSS).

[0116] For example, the light-emitting element (ED) may be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting element. When the light-emitting element (ED) is an organic light-emitting diode (OLED), the light-emitting layer (EL) of the light-emitting element (ED) may include an organic light-emitting layer containing organic material.

[0117] The second transistor (T2) is turned on and off by a scan signal (SC), which is a gate signal applied through a scan signal line (SCL), and can be electrically connected between the first node (N1) of the first transistor (T1) and the data signal line (DL).

[0118] A storage capacitor (Cst) can be connected between the first node (N1) and the second node (N2) of the first transistor (T1).

[0119] Referring to FIG. 5, each of the plurality of subpixels (SP) placed in the display area (DA) of the display panel (110) of the display device (100) may basically include a light-emitting element (ED), two transistors (DRT, SCT) and one capacitor (Cst).

[0120] Each of the plurality of subpixels (SP) placed in the display area (DA) of the display panel (110) of the display device (100) may further include one or more transistors or one or more capacitors.

[0121] Referring to FIG. 5, since circuit elements (particularly light-emitting elements (ED)) within each subpixel (SP) are vulnerable to external moisture or oxygen, the display panel (100) may include an encapsulation layer (ENCAP) to prevent external moisture or oxygen from penetrating into the circuit elements (particularly light-emitting elements (ED)).

[0122] The encapsulation layer (ENCAP) can be composed of various types.

[0123] For example, the encapsulation layer (ENCAP) can be arranged to cover the light-emitting elements (ED). The encapsulation layer (ENCAP) may include one or more inorganic films and one or more organic films.

[0124] As another example, the encapsulation layer (ENCAP) may include an encapsulation substrate, a dam located between the thin-film transistor array substrate and the encapsulation substrate along the outer edge of the display area (DA), and a filler that fills the internal space of the dam.

[0125] Meanwhile, the display panel (110) according to the embodiments of the present disclosure may have a top emission structure in which light is emitted in a direction from the substrate (SUB) toward the encapsulation layer (ENCAP), or a bottom emission structure in which light is emitted in a direction from the encapsulation layer (ENCAP) toward the substrate (SUB). Hereinafter, for convenience of explanation, an example is given in which the display panel (110) according to the embodiments of the present disclosure has a top emission structure.

[0126] Each subpixel (SP) of a display panel (110) according to embodiments of the present disclosure is connected to a data signal line (DL) for supplying a data signal (Vdata) and a scan signal line (SCL) for supplying a scan signal (SC), and may include a light-emitting element (ED), a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). Here, the light-emitting element (ED) may include a first electrode (E1), a light-emitting layer (EL), and a second electrode (E2).

[0127] During the manufacturing process of a display panel (110) according to embodiments of the present disclosure, if a first transistor (T1) acting as a driving transistor within each subpixel (SP) is exposed to hydrogen or light, the threshold voltage of the first transistor (T1) may be reduced. The corresponding subpixel (SP) containing the first transistor (T1) with the reduced threshold voltage may be driven abnormally. Such driving failure may lead to a degradation of image quality.

[0128] If the first transistor (T1) has a structure in which the gate insulating film is etched or has a top gate structure, the first transistor (T1) can be easily exposed to hydrogen or light.

[0129] In addition, if the first transistor (T1) is an oxide semiconductor transistor, a phenomenon in which the threshold voltage of the first transistor (T1) fluctuates due to hydrogen or light can easily occur.

[0130] In order to manufacture a display panel (110) in which the first transistor (T1) is not exposed to hydrogen or light, there is a difficulty in manufacturing the display panel (110) using complex processes and many masks.

[0131] Here, hydrogen or light may be generated during the manufacturing process of the display panel (110) or may be generated inside the panel even after the manufacturing of the display panel (110) is completed. For example, hydrogen may be generated from various layers (in particular, various types of insulating layers) located above the first transistor (T1) and directed toward the first transistor (T1). Light emitted from a light-emitting element (ED) located above the first transistor (T1) may be directed toward the first transistor (T1). Additionally, external light may be introduced from above the first transistor (T1) and directed toward the first transistor (T1).

[0132] Accordingly, the display panel (110) according to the embodiments of the present disclosure may have a structure in which the first transistor (T1) is not exposed to hydrogen or light (hereinafter referred to as a hydrogen / light blocking structure). In addition, the display panel (110) according to the embodiments of the present disclosure may have a structure that can be manufactured using a small number of masks.

[0133] Hereinafter, a first transistor (T1) having a hydrogen / light blocking structure in a display panel (110) according to embodiments of the present disclosure is described.

[0134] FIG. 6 is a cross-sectional view of a display panel (110) according to embodiments of the present disclosure. FIG. 7 is a plan view of the display panel (110) of FIG. 6. FIG. 8 is a plan view showing only the parts related to the first transistor (T1) in the plan view of FIG. 7, and FIG. 9 is a plan view showing only the parts related to the storage capacitor (Cst) in the plan view of FIG. 7.

[0135] Referring to FIG. 6, in a display panel (110) according to embodiments of the present disclosure, a light-emitting element (ED), a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst) may be disposed in an area where one subpixel (SP) is formed.

[0136] To this end, a display panel (110) according to embodiments of the present disclosure may include a substrate (SUB) and a buffer layer (BUF) on the substrate (SUB).

[0137] In a display panel (110) according to embodiments of the present disclosure, a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst) may be formed on a buffer layer (BUF).

[0138] A display panel (110) according to embodiments of the present disclosure may include a gate insulating film (GI) to form a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst).

[0139] A display panel (110) according to embodiments of the present disclosure may further include a protection layer (PAS) disposed on a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). The protection layer (PAS) may be a layer for protecting the first transistor (T1), the second transistor (T2), and the storage capacitor (Cst).

[0140] A display panel (110) according to embodiments of the present disclosure may further include a gate insulating film (GI) for insulating between the first and second gate electrodes (G1, G2) and the first and second active layers (ACT1, ACTT2) in the first and second transistors (T1, T2).

[0141] A display panel (110) according to embodiments of the present disclosure may further include a bank (BK) disposed on a protective layer (PAS). The bank (BK) may be a layer for defining a subpixel (SP) and a layer for forming a light-emitting region (EA) of the subpixel (SP).

[0142] For example, the protective layer (PAS) is silicon nitride (SiN x ) or silicon oxide (SiO₂) X It may include various insulating film materials such as ). In particular, the protective layer (PAS) may be silicon nitride (SiN x It may include ).

[0143] For example, the gate insulating film (GI) is silicon oxide (SiO₂). X ) or silicon nitride (SiN x It may include various insulating film materials such as ).

[0144] For example, the buffer layer (BUF) is silicon dioxide (SiO₂). X ) or silicon nitride (SiN x It may include various insulating film materials such as ).

[0145] A display panel (110) according to embodiments of the present disclosure may further include an encapsulation layer (ENCAP) to prevent moisture or oxygen from penetrating into a light-emitting element (ED).

[0146] The encapsulation layer (ENCAP) may include a first encapsulation layer (EPAS1), a second encapsulation layer (PCL), and a third encapsulation layer (EPAS2). The first encapsulation layer (EPAS1) may be located on the second electrode (E2) of the light-emitting element (ED), the second encapsulation layer (PCL) may be located on the first encapsulation layer (EPAS1), and the third encapsulation layer (EPAS2) may be located on the second encapsulation layer (PCL). For example, the first encapsulation layer (EPAS1) and the third encapsulation layer (EPAS2) may be inorganic films, and the second encapsulation layer (PCL) may be an organic film.

[0147] Referring to FIGS. 6 to 9, the first transistor (T1) may include a first active layer (ACT1), a first source electrode (S1), a first drain electrode (D1), and a first gate electrode (G1).

[0148] The first source electrode (S1) can be connected to one side of the first active layer (ACT1).

[0149] The first drain electrode (D1) can be connected to the other side of the first active layer (ACT1).

[0150] The first gate electrode (G1) may overlap with the first active layer (ACT1), overlap with all or part of the first source electrode (S1), and overlap with all or part of the first drain electrode (D1).

[0151] The first active layer (ACT1) may include a first channel region (CH1), a first source connection region (SC1) located on one side of the first channel region (CH1), and a first drain connection region (DC1) located on the other side of the first channel region (CH1).

[0152] For example, the first source electrode (S1) and the first drain electrode (D1) may include copper, aluminum, molybdenum (Mo), titanium (Ti), or molybdenum-titanium (MoTi), etc. For example, the first source electrode (S1) and the first drain electrode (D1) may include a transparent conductive oxide. For example, the transparent conductive oxide (TCO) may include one or more of IZO (Indium Zinc Oxide), ITO (Indium Tin Oxide), IGZO (Indium-Gallium-Zinc Oxide), IGZTO (Indium gallium zinc tin oxide), ZnO (Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), GZO (Gallium-doped Zinc Oxide), ATO (Antimony Tin Oxide), FTO (Flourine-doped Transparent Oxides), etc.

[0153] For example, the second gate electrode (G2) may include copper, aluminum, molybdenum (Mo), titanium (Ti), or molybdenum-titanium (MoTi), etc. For example, the second gate electrode (G2) may include a transparent conductive oxide.

[0154] For example, the first active layer (ACT1) may include an oxide semiconductor material. The oxide semiconductor material is a semiconductor material in which conductivity is controlled and the bandgap is adjusted through doping of an oxide material, and it may generally be a transparent semiconductor material having a wide bandgap. For example, the oxide semiconductor material may include IGZO (Indium gallium zinc oxide), IGZTO (Indium gallium zinc tin oxide), ZnO (zinc oxide), CdO (cadmium oxide), InO (indium oxide), ZTO (zinc tin oxide), ZITO (zinc indium tin oxide), etc. When the active layer (ACT) is an oxide semiconductor material, the transistor (TR) is called an oxide thin film transistor. The first active layer (ACT1) may be a single layer or a multilayer. For example, when the first active layer (ACT1) is a multilayer, the multilayer may be composed of the same semiconductor material or composed of two or more different semiconductor materials.

[0155] The first source electrode (S1) may be placed on the first source connection region (SC1) of the first active layer (ACT1). The first drain electrode (D1) may be placed on the first drain connection region (DC1) of the first active layer (ACT1).

[0156] Referring to FIGS. 6 to 9, the second transistor (T2) may include a second active layer (ACT2), a second source electrode (S2), a second drain electrode (D2), and a second gate electrode (G2).

[0157] The second source electrode (S2) can be connected to one side of the second active layer (ACT2).

[0158] The second drain electrode (D2) can be connected to the other side of the second active layer (ACT2).

[0159] The second gate electrode (G2) may overlap with a part of the second active layer (ACT2) and may not overlap with the second source electrode (S2) and the second drain electrode (D2).

[0160] For example, the second source electrode (S2) and the second drain electrode (D2) may include copper, aluminum, molybdenum (Mo), titanium (Ti), or molybdenum-titanium (MoTi), etc. For example, the second source electrode (S2) and the second drain electrode (D2) may include a transparent conductive oxide. For example, the transparent conductive oxide (TCO) may include one or more of IZO (Indium Zinc Oxide), ITO (Indium Tin Oxide), IGZO (Indium-Gallium-Zinc Oxide), IGZTO (Indium gallium zinc tin oxide), ZnO (Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), GZO (Gallium-doped Zinc Oxide), ATO (Antimony Tin Oxide), FTO (Flourine-doped Transparent Oxides), etc.

[0161] For example, the second gate electrode (G2) may include copper, aluminum, molybdenum (Mo), titanium (Ti), or molybdenum-titanium (MoTi), etc. For example, the second gate electrode (G2) may include a transparent conductive oxide.

[0162] For example, the second active layer (ACT2) may include an oxide semiconductor material. The oxide semiconductor material is a semiconductor material in which conductivity is controlled and the bandgap is adjusted through doping of an oxide material, and it may generally be a transparent semiconductor material having a wide bandgap. For example, the oxide semiconductor material may include IGZO (Indium gallium zinc oxide), IGZTO (Indium gallium zinc tin oxide), ZnO (zinc oxide), CdO (cadmium oxide), InO (indium oxide), ZTO (zinc tin oxide), ZITO (zinc indium tin oxide), etc. When the active layer (ACT) is an oxide semiconductor material, the transistor (TR) is called an oxide thin film transistor. The second active layer (ACT2) may be a single layer or a multilayer. For example, when the second active layer (ACT2) is a multilayer, the multilayer may be composed of the same semiconductor material or composed of two or more different semiconductor materials.

[0163] Referring to FIGS. 6 to 9, as described above, the first gate electrode (G1) of the first transistor (T1) can overlap not only with the first active layer (ACT1) but also with the first source electrode (S1) and the first drain electrode (D1).

[0164] Accordingly, the first gate electrode (G1) can block hydrogen or light from flowing from the protection layer (PAS) to the first active layer (ACT1) of the first transistor (T1). Therefore, the phenomenon of the threshold voltage of the first transistor (T1) being lowered (hereinafter also referred to as the negative shift phenomenon of the threshold voltage) can be prevented. Accordingly, the driving performance of the first transistor (T1), which must act as a driving transistor, can be improved.

[0165] Referring to FIGS. 6 to 9, as described above, the first gate electrode (G1) of the first transistor (T1) may overlap with the first active layer (ACT1) as well as with the first source electrode (S1) and the first drain electrode (D1), but the second gate electrode (G2) of the second transistor (T2) may overlap with only a part of the second active layer (ACT2) and may not overlap with the second source electrode (S2) and the second drain electrode (D2).

[0166] Accordingly, hydrogen or light can flow from the protection layer (PAS) to the second active layer (ACT2) of the second transistor (T2). As a result, a phenomenon in which the threshold voltage of the second transistor (T2) is lowered (negative shift phenomenon of the threshold voltage) may occur. Therefore, the switching performance and reliability of the second transistor (T2), which must act as a switching transistor, can be improved.

[0167] Referring to FIGS. 6 to 9, the connection relationships of the light-emitting element (ED), the first transistor (T1), the second transistor (T2), and the storage capacitor (Cst) are briefly as follows.

[0168] The first gate electrode (G1) of the first transistor (T1) may be electrically connected to the second source electrode (S2) of the second transistor (T2) or the second source electrode (S2) of the second transistor (T2).

[0169] The first source electrode (S1) of the first transistor (T1) may be the first electrode (E1) of the light-emitting element (ED) or may be electrically connected to the first electrode (E1) of the light-emitting element (ED).

[0170] The first drain electrode (D1) of the first transistor (T1) can be electrically connected to the driving voltage line (DVL).

[0171] The second gate electrode (G2) of the second transistor (T2) may be part of the scan signal line (SCL) or electrically connected to the scan signal line (SCL).

[0172] The second drain electrode (D2) of the second transistor (T2) may be part of the data signal line (DL) or electrically connected to the data signal line (DL).

[0173] The second source electrode (S2) of the second transistor (T2) may be the first gate electrode (G1) of the first transistor (T1) or may be electrically connected to the first gate electrode (G1).

[0174] The storage capacitor (Cst) may include a first capacitor electrode (PLT1) and a second capacitor electrode (PLT2).

[0175] The first capacitor electrode (PLT1) may be the first source electrode (S1) of the first transistor (T1) or may be electrically connected to the first source electrode (S1) of the first transistor (T1).

[0176] The second capacitor electrode (PLT2) may be the first gate electrode (G1) of the first transistor (T1) or may be electrically connected to the first gate electrode (G1) of the first transistor (T1).

[0177] The second capacitor electrode (PLT2) may include a second lower capacitor electrode (PLT2a) and a second upper capacitor electrode (PLT2b).

[0178] The second lower capacitor electrode (PLT2a) may include the same material as the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2). That is, the second lower capacitor electrode (PLT2a) may be placed in the same material layer as the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2).

[0179] The second upper capacitor electrode (PLT2b) may include the same semiconductor material as the first and second active layers (ACT1, ACT2). Here, the semiconductor material included in the second upper capacitor electrode (PLT2b) may be in a conductive state or a non-conductive state. That is, the second upper capacitor electrode (PLT2b) may be placed in the same material layer as the first and second active layers (ACT1, ACT2).

[0180] Meanwhile, referring to FIGS. 6 to 9, the display panel (110) according to embodiments of the present disclosure may further include a side shield (SS) disposed between a storage capacitor (Cst) and a first transistor (T1).

[0181] For example, the side shield (SS) can be arranged in a line shape. For example, the side shield (SS) can have a bent line shape. That is, the side shield (SS) can include a bent portion.

[0182] For example, the side shield (SS) may be composed of a contact hole line (CNT_N1) connecting the second capacitor electrode (PLT2) and the first gate electrode (G1). Here, the contact hole line (CNT_N1) may be configured in the form of a trench.

[0183] Meanwhile, referring to FIGS. 6 to 9, the display panel (110) according to embodiments of the present disclosure may further include a lower shield (BS) located between a substrate (SUB) and a buffer layer (BUF) and overlapping with a first active layer (ACT1).

[0184] For example, the lower shield (BS) may include copper, aluminum, molybdenum (Mo), titanium (Ti), or molybdenum-titanium (MoTi).

[0185] Below, the first transistor (T1) and the storage capacitor (Cst) will be described in more detail with reference to FIGS. 6 to 9.

[0186] Referring to FIGS. 6 to 9, the first drain electrode (D1) of the first transistor (T1) can be connected to the driving voltage line (DVL) through a contact hole (CNT_N3), and the first source electrode (S1) of the first transistor (T1) can be connected to the first capacitor electrode (PLT1) included in the storage capacitor (Cst) through a contact hole (CNT_N2).

[0187] Referring to FIGS. 6 through 9, in a display panel (110) according to embodiments of the present disclosure, the storage capacitor (Cst) may further include a third capacitor electrode (PLT3).

[0188] The third capacitor electrode (PLT3) can be electrically connected to the first capacitor electrode (PLT1) through the contact hole (CNT_PLT1,3).

[0189] The first capacitor electrode (PLT1) can be electrically connected to the first source electrode (S1). Accordingly, the third capacitor electrode (PLT3) can be electrically connected to the first source electrode (S1).

[0190] In other words, the first capacitor electrode (PLT1) and the third capacitor electrode (PLT3) can be electrically connected to the first source electrode (S1) of the first transistor (T1).

[0191] The second capacitor electrode (PLT2) can be electrically connected to the first gate electrode (G1) of the first transistor (T1).

[0192] In a display panel (110) according to embodiments of the present disclosure, the storage capacitor (Cst) may include a first storage capacitor (Cst1) between a first capacitor electrode (PLT1) and a second capacitor electrode (PLT2), and a second storage capacitor (Cst2) between a second capacitor electrode (PLT2) and a third capacitor electrode (PLT3).

[0193] The first storage capacitor (Cst1) and the second storage capacitor (Cst2) can be electrically connected in parallel. That is, the storage capacitor (Cst) can be configured by electrically connecting the first storage capacitor (Cst1) and the second storage capacitor (Cst2) in parallel. In this way, as the storage capacitor (Cst) has a dual capacitor parallel structure, the capacitance of the storage capacitor (Cst) can be increased.

[0194] Referring to FIGS. 6 to 9, the second drain electrode (D2) of the second transistor (T2) is connected to a data signal line (DL), and the second source electrode (S2) of the second transistor (T2) may be composed of a second capacitor electrode (PLT2) included in a storage capacitor (Cst) or connected to the second capacitor electrode (PLT2). The second gate electrode (G2) of the second transistor (T2) may be part of a scan signal line (SCL).

[0195] Referring to FIGS. 6 to 9, the lower shield (BS) can be electrically connected to the first source electrode (S1) of the first transistor (T1).

[0196] Accordingly, the first source electrode (S1) of the first transistor (T1) can be electrically connected to the first capacitor electrode (PLT1), the third capacitor electrode (PLT3), and the lower shield (BS).

[0197] As shown in FIGS. 7 and 9, the lower shield (BS) can be formed integrally with the third capacitor electrode (PLT3).

[0198] Referring to FIGS. 6 to 9, in a display panel (110) according to embodiments of the present disclosure, the first gate electrode (G1) of the first transistor (T1) may include a first lower gate electrode (G1a) and a first upper gate electrode (G1b).

[0199] The first upper gate electrode (G1b) can be positioned on the first lower gate electrode (G1a) and placed in contact with the first lower gate electrode (G1a).

[0200] A gate insulating film (GI) may be disposed below the first lower gate electrode (G1a). That is, a gate insulating film (GI) may be disposed between the first lower gate electrode (G1a) and the first active layer (ACT1). Here, the gate insulating film (GI) may be disposed in an etchless structure and may be disposed while covering the first source electrode (S1) and the first drain electrode (D1).

[0201] As the first gate electrode (G1) has a double-layer electrode structure including a first lower gate electrode (G1a) and a first upper gate electrode (G1b), the first lower gate electrode (G1a) may overlap with the first active layer (ACT1), overlap with all or part of the first source electrode (S1), and overlap with all or part of the first drain electrode (D1).

[0202] As the first gate electrode (G1) has a double-layer electrode structure including a first lower gate electrode (G1a) and a first upper gate electrode (G1b), the first lower gate electrode (G1a), which is located below the first lower gate electrode (G1a) and the first upper gate electrode (G1b), can be electrically connected to the second capacitor electrode (PLT2).

[0203] Referring to FIGS. 6 to 9, the first lower gate electrode (G1a) located below the first upper gate electrode (G1b) may include the same material as the first capacitor electrode (PLT1). That is, the first capacitor electrode (PLT1) may be placed on the same material layer as the first lower gate electrode (G1a).

[0204] For example, the first capacitor electrode (PLT1) and the first lower gate electrode (G1a) may include a pixel electrode material. The first upper gate electrode (G1b) may include a gate metal material.

[0205] The material included in the first capacitor electrode (PLT1), which is the uppermost capacitor electrode among the plurality of capacitor electrodes (first to third capacitor electrodes (PLT1, PLT2, PLT3)) constituting the storage capacitor (Cst) between the first source electrode (S1) and the first gate electrode (S2), may be included in the first gate electrode (G1).

[0206] As described above, since the first capacitor electrode (PLT1) is placed on the same material layer as the first lower gate electrode (G1a) and simultaneously performs the role of the first electrode (E1) corresponding to the pixel electrode, the first capacitor electrode (PLT1) and the first electrode (E1) are not configured separately. Therefore, the number of electrode layers in the display panel (110) can be reduced.

[0207] Meanwhile, referring to FIG. 6, in a display panel (110) according to embodiments of the present disclosure, a gate insulating film (GI) may be disposed between a first capacitor electrode (PLT1) and a second capacitor electrode (PLT2) constituting a storage capacitor (Cst), and a buffer layer (BUF) may be disposed between the second capacitor electrode (PLT2) and a third capacitor electrode (PLT3).

[0208] In this way, the gate insulating film (GI) is extended without being etched in the region of the transistors (T1, T2) and is placed between the first capacitor electrode (PLT1) and the second capacitor electrode (PLT2), so that the gate insulating film (GI) can be utilized as an insulating film (dielectric) for the configuration of the storage capacitor (Cst). Accordingly, the gap between the first capacitor electrode (PLT1) and the second capacitor electrode (PLT2) can be reduced. Thus, the capacitance of the storage capacitor (Cst) can be increased.

[0209] In addition, as described above, by configuring the storage capacitor (Cst) in a parallel structure of the first storage capacitor (Cst1) and the second storage capacitor (Cst2), the capacitance of the storage capacitor (Cst) can be increased.

[0210] As such, the display panel (110) according to the embodiments of the present disclosure has a capacitance increasing structure of the storage capacitor (Cst), so that when designing the storage capacitor (Cst) having a desired capacitance, there may be a design advantage of reducing the area of ​​the storage capacitor (Cst).

[0211] Referring to FIGS. 6 to 9, in a display panel (110) according to embodiments of the present disclosure, the second gate electrode (G1) of the second transistor (T2) may include a second lower gate electrode (G2a) and a second upper gate electrode (G2b).

[0212] The second upper gate electrode (G2b) can be positioned on the second lower gate electrode (G2a) and placed in contact with the second lower gate electrode (G2a).

[0213] A gate insulating film (GI) may be disposed below the second lower gate electrode (G2a). That is, a gate insulating film (GI) may be disposed between the second lower gate electrode (G2a) and the second active layer (ACT2). Here, the gate insulating film (GI) may be disposed in an unetched state and may be disposed while covering the second source electrode (S2) and the second drain electrode (D2).

[0214] A protective layer (PAS) is disposed on a first capacitor electrode (PLT1), a first gate electrode (G1), and a second gate electrode (G2), and a bank (BK) can be disposed on the protective layer (PAS).

[0215] The light-emitting layer (EL) is placed on the bank (BK), and the second electrode (E2) can be placed on the light-emitting layer (EL).

[0216] The first capacitor electrode (PLT1) may be the first electrode (E1).

[0217] A portion of the light-emitting layer (EL) can be contacted with the upper surface of the first capacitor electrode (PLT1) corresponding to the first electrode (E1) through the holes of the bank (BK) and the protection layer (PAS).

[0218] Referring to FIG. 6, the light-emitting region (EA) of the subpixel (SP) can overlap with the storage capacitor (Cst). That is, the light-emitting region (EA) of the subpixel (SP) can be located on top of the storage capacitor (Cst).

[0219] FIG. 10 shows the differential characteristics regarding the blocking of light and hydrogen of a display panel (110) according to embodiments of the present disclosure.

[0220] Referring to FIG. 10, in a display panel (110) according to embodiments of the present disclosure, the first transistor (T1) and the second transistor (T2) included in each subpixel (SP) may have different gate electrode structures.

[0221] Referring to FIG. 10, the first gate electrode (G1), which is composed of a double layer of the first transistor (T1), can overlap not only with the first active layer (ACT1) but also with the first source electrode (S1) and the first drain electrode (D1).

[0222] Accordingly, the first gate electrode (G1) can block hydrogen or light from flowing from the protection layer (PAS) to the first active layer (ACT1) of the first transistor (T1). Therefore, the phenomenon of the threshold voltage of the first transistor (T1) being lowered (hereinafter also referred to as the negative shift phenomenon of the threshold voltage) can be prevented. Accordingly, the driving performance of the first transistor (T1), which must act as a driving transistor, can be improved.

[0223] Referring to FIG. 10, the first gate electrode (G1) of the first transistor (T1) may overlap with the first active layer (ACT1) and may also overlap with the first source electrode (S1) and the first drain electrode (D1), but the second gate electrode (G2) of the second transistor (T2) may only overlap with a part of the second active layer (ACT2) and may not overlap with the second source electrode (S2) and the second drain electrode (D2).

[0224] Accordingly, hydrogen or light can flow from the protection layer (PAS) to the second active layer (ACT2) of the second transistor (T2). As a result, a phenomenon in which the threshold voltage of the second transistor (T2) is lowered (negative shift phenomenon of the threshold voltage) may occur. Therefore, the switching performance and reliability of the second transistor (T2), which must act as a switching transistor, can be improved.

[0225] Referring to FIG. 10, a display panel (110) according to embodiments of the present disclosure may include a substrate (SUB) and a first transistor (T1) and a second transistor (T2) on the substrate (SUB).

[0226] The first transistor (T1) may include a first active layer (ACT1), a first source electrode (S1) connected to one side of the first active layer (ACT1), a first drain electrode (D1) connected to the other side of the first active layer (ACT1), and a first gate electrode (G1) that overlaps with all or part of the first active layer (ACT1).

[0227] The second transistor (T2) may include a second active layer (ACT2), a second source electrode (S2) connected to one side of the second active layer (ACT2), a second drain electrode (D2) connected to the other side of the second active layer (ACT2), and a second gate electrode (G2) that overlaps with a part of the second active layer (ACT2).

[0228] Referring to FIG. 10, a gate insulating film (GI) may be further included between the first active layer (ACT1) and the first gate electrode (G1) and between the second active layer (ACT2) and the second gate electrode (G2).

[0229] Hydrogen or light generated at the top of the first gate electrode (G1) is blocked by the first gate electrode (G1) and does not flow down below the first gate electrode (G1).

[0230] However, hydrogen or light generated at the top of the second gate electrode (G2) is not blocked by the second gate electrode (G2) and flows into the side of the second gate electrode (G2) and can flow into the second active layer (ACT2) located below the second gate electrode (G2).

[0231] Accordingly, in the gate insulating film (GI), the hydrogen concentration or light exposure amount in the portion between the first active layer (ACT1) and the first gate electrode (G1) may be lower than the hydrogen concentration or light exposure amount in the portion between the second active layer (ACT2) and the second gate electrode (G2).

[0232] Meanwhile, referring to FIGS. 6 to 10, in the first transistor (T1), since the first gate electrode (G1) overlaps with the first source electrode (S1) and overlaps with the first drain electrode (D1), the capacitance of the parasitic capacitor between the first gate electrode (G1) and the first source electrode (S1) and the capacitance of the parasitic capacitor between the first gate electrode (G1) and the first drain electrode (D1) may increase. Accordingly, the device performance of the first transistor (T1) may decrease.

[0233] A display panel (110) according to embodiments of the present disclosure may have a source-drain asymmetric structure that prevents device performance degradation caused by parasitic capacitors, even though the first gate electrode (G1) overlaps with the first source electrode (S1) and overlaps with the first drain electrode (D1). Hereinafter, the source-drain asymmetric structure of the display panel (110) according to embodiments of the present disclosure will be described with reference to FIG. 11.

[0234] FIG. 11 shows a parasitic capacitor utilization structure of a display panel (110) according to embodiments of the present disclosure.

[0235] Referring to FIG. 11, in the first transistor (T1), since the first gate electrode (G1) overlaps with the first source electrode (S1) and the first drain electrode (D1), a first parasitic capacitor (Cgs) can be formed between the first gate electrode (G1) and the first source electrode (S1), and a second parasitic capacitor (Cgd) can be formed between the first gate electrode (G1) and the first drain electrode (D1).

[0236] Referring to FIG. 11, the larger the capacitance of the storage capacitor (Cst), the more advantageous it is for driving the display. This storage capacitor (Cst) can be formed between the first gate electrode (G1) and the first source electrode (S1).

[0237] Referring to FIG. 11, since the first parasitic capacitor (Cgs) and the storage capacitor (Cst) are formed at the same location, increasing the capacitance of the first parasitic capacitor (Cgs) between the first gate electrode (G1) and the first source electrode (S1) can increase the capacitance of the storage capacitor (Cst).

[0238] Therefore, increasing the capacitance of the first parasitic capacitor (Cgs) between the first gate electrode (G1) and the first source electrode (S1) can be advantageous in terms of display driving.

[0239] However, since the second parasitic capacitor (Cgd) is formed between the first gate electrode (G1) and the first drain electrode (D1), an increase in the capacitance of the second parasitic capacitor (Cgd) may be disadvantageous in terms of display driving.

[0240] Referring to FIG. 11, in a display panel (110) according to embodiments of the present disclosure, a first parasitic capacitor (Cgs) formed between a first gate electrode (G1) and a first source electrode (S1) may be an additional storage capacitor (AUX_Cst). That is, an additional storage capacitor (Cgs) may be configured as the first source electrode (S1) and the first gate electrode (G1) overlap.

[0241] Referring to FIG. 11, a display panel (110) according to embodiments of the present disclosure may have a structure in which the area of ​​the first source electrode (S1) is larger than the area of ​​the first drain electrode (D1). This structure is called a source-drain asymmetric structure.

[0242] In other words, according to the source-drain asymmetric structure of the display panel (110) according to the embodiments of the present disclosure, the area where the first source electrode (S1) and the first gate electrode (G1) overlap may be larger than the area where the first drain electrode (D1) and the first gate electrode (G1) overlap.

[0243] Referring to FIG. 11, the length (Ls1) in one direction of the first source electrode (S1) may be longer than the length (Ld1) in one direction of the first drain electrode (D1).

[0244] Referring to FIG. 11, according to the source-drain asymmetric structure of the display panel (110) according to embodiments of the present disclosure, the capacitance of the first parasitic capacitor (Cgs) formed between the first gate electrode (G1) and the first source electrode (S1) can be maximized, and the capacitance of the second parasitic capacitor (Cgd) formed between the first gate electrode (G1) and the first drain electrode (D1) can be maximized.

[0245] Referring to FIG. 11, according to the source-drain asymmetric structure of the display panel (110) according to embodiments of the present disclosure, the capacitance increase by an additional storage capacitor (AUX_Cst) corresponding to a first parasitic capacitor (Cgs) formed between the first gate electrode (G1) and the first source electrode (S1) may be much larger than the capacitance of a second parasitic capacitor (Cgd) formed between the first gate electrode (G1) and the first drain electrode (D1).

[0246] Therefore, even if the first gate electrode (G1) is extended and overlaps with the first source electrode (S1) and the first drain electrode (D1), the first transistor (T1) has a source-drain asymmetric structure, so device performance degradation due to parasitic capacitors (Cgd, Cgs) can be prevented.

[0247] Since the first transistor (T1) has a source-drain asymmetric structure, an additional storage capacitor (AUX_Cst) is added to the storage capacitor (Cst), which can be advantageous for driving the display.

[0248] For example, the first transistor (T1) may be a top gate transistor and / or an oxide semiconductor transistor. The first transistor (T1) may have a structure in which the gate insulating film (GI) is not etched.

[0249] For example, the second transistor (T2) may be a top gate transistor and / or an oxide semiconductor transistor. The second transistor (T2) may have a structure in which the gate insulating film (GI) is not etched.

[0250] Referring to FIGS. 6 to 11, in a display panel (110) according to embodiments of the present disclosure, when forming the source electrodes (S1, S2) and drain electrodes (D1, D2) of the first and second transistors (T1, T2), a separate mask is not used, and they can be formed together when forming the active layers (ACT1, ACT2) using a halftone mask. Accordingly, the display panel (110) according to embodiments of the present disclosure can be seen as having a structure that can reduce the number of masks required when manufacturing the panel.

[0251] FIG. 12 is another cross-sectional view of a display panel (110) according to embodiments of the present disclosure.

[0252] The cross-sectional structure (vertical structure) of Fig. 12 is identical to the cross-sectional structure (vertical structure) of Fig. 6 except for the connection structure of the lower shield (BS).

[0253] Referring to FIG. 12, the lower shield (BS) is not electrically connected to the first source electrode (S1) of the first transistor (T1), but can be electrically connected to the first gate electrode (G1) of the first transistor (T1) through holes (CNT_BS) in the gate insulating film (GI) and the buffer layer (BUF).

[0254] In this case, the first gate electrode (G1) may be the top gate electrode of the first transistor (T1), and the lower shield (BS) may be the bottom gate electrode of the first transistor (T1).

[0255] In other words, when the lower shield (BS) is electrically connected to the first gate electrode (G1) of the first transistor (T1), the first transistor (T1) may have a double gate electrode structure including both a top gate electrode and a bottom gate electrode.

[0256] Referring to FIG. 12, the first source electrode (S1) of the first transistor (T1) can be electrically connected to the first capacitor electrode (PLT1) and the third capacitor electrode (PLT3).

[0257] Referring to FIG. 12, the first gate electrode (G1) of the first transistor (T1) can be electrically connected to the second capacitor electrode (PLT2) and the lower shield (BS).

[0258] FIG. 13 is a cross-sectional view of a display panel (110) according to embodiments of the present disclosure. FIG. 14 is a plan view of the display panel (110) of FIG. 13. FIG. 15 is a plan view showing only the parts related to the first transistor (T1) in the plan view of FIG. 14, and FIG. 16 is a plan view showing only the parts related to the storage capacitor (Cst) in the plan view of FIG. 14.

[0259] Referring to FIG. 13, in a display panel (110) according to embodiments of the present disclosure, the first gate electrode (G1) may overlap with the first source electrode (S1) and the first drain electrode (D1). This is a common feature with the display panel (110) of FIG. 6.

[0260] However, the display panel (110) of FIG. 13 and the display panel (110) of FIG. 6 may differ in the number of layers of gate electrodes (G1, G2), the material of the first capacitor electrode (PLT1) may differ, and the configuration of the light-emitting element (ED) may differ. Hereinafter, when describing a different structure of the display panel (100) with reference to FIG. 13 to FIG. 16, the description will focus on features that differ from the display panel (100) described with reference to FIG. 6 to FIG. 9.

[0261] Referring to FIG. 13, in a display panel (110) according to embodiments of the present disclosure, a light-emitting element (ED), a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst) may be disposed in an area where one subpixel (SP) is formed.

[0262] To this end, a display panel (110) according to embodiments of the present disclosure may include a substrate (SUB) and a buffer layer (BUF) on the substrate (SUB).

[0263] In a display panel (110) according to embodiments of the present disclosure, a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst) may be formed on a buffer layer (BUF).

[0264] A display panel (110) according to embodiments of the present disclosure may include a gate insulating film (GI) to form a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst).

[0265] A display panel (110) according to embodiments of the present disclosure may further include a protection layer (PAS) disposed on a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). The protection layer (PAS) may be a layer for protecting the first transistor (T1), the second transistor (T2), and the storage capacitor (Cst).

[0266] A display panel (110) according to embodiments of the present disclosure may further include a bank (BK) disposed on a protective layer (PAS). The bank (BK) may be a layer for defining a subpixel (SP) and a layer for forming a light-emitting region (EA) of the subpixel (SP).

[0267] A display panel (110) according to embodiments of the present disclosure may further include an encapsulation layer (ENCAP) to prevent moisture or oxygen from penetrating into a light-emitting element (ED).

[0268] The encapsulation layer (ENCAP) may include a first encapsulation layer (EPAS1), a second encapsulation layer (PCL), and a third encapsulation layer (EPAS2). The first encapsulation layer (EPAS1) may be located on the second electrode (E2) of the light-emitting element (ED), the second encapsulation layer (PCL) may be located on the first encapsulation layer (EPAS1), and the third encapsulation layer (EPAS2) may be located on the second encapsulation layer (PCL). For example, the first encapsulation layer (EPAS1) and the third encapsulation layer (EPAS2) may be inorganic films, and the second encapsulation layer (PCL) may be an organic film.

[0269] Referring to FIGS. 13 to 16, the first transistor (T1) may include a first active layer (ACT1), a first source electrode (S1), a first drain electrode (D1), and a first gate electrode (G1).

[0270] The first source electrode (S1) can be connected to one side of the first active layer (ACT1).

[0271] The first drain electrode (D1) can be connected to the other side of the first active layer (ACT1).

[0272] The first gate electrode (G1) may overlap with the first active layer (ACT1), overlap with all or part of the first source electrode (S1), and overlap with all or part of the first drain electrode (D1).

[0273] The first active layer (ACT1) may include a first channel region (CH1), a first source connection region (SC1) located on one side of the first channel region (CH1), and a first drain connection region (DC1) located on the other side of the first channel region (CH1).

[0274] The first source electrode (S1) may be placed on the first source connection region (SC1) of the first active layer (ACT1). The first drain electrode (D1) may be placed on the first drain connection region (DC1) of the first active layer (ACT1).

[0275] The second transistor (T2) of FIGS. 13 to 16 may include a second active layer (ACT2), a second source electrode (S2), a second drain electrode (D2), and a second gate electrode (G2).

[0276] The second source electrode (S2) can be connected to one side of the second active layer (ACT2).

[0277] The second drain electrode (D2) can be connected to the other side of the second active layer (ACT2).

[0278] The second gate electrode (G2) may overlap with a part of the second active layer (ACT2) and may not overlap with the second source electrode (S2) and the second drain electrode (D2).

[0279] Referring to FIGS. 13 to 16, as described above, the first gate electrode (G1) of the first transistor (T1) can overlap not only with the first active layer (ACT1) but also with the first source electrode (S1) and the first drain electrode (D1).

[0280] Accordingly, the first gate electrode (G1) can block hydrogen or light from flowing from the protection layer (PAS) to the first active layer (ACT1) of the first transistor (T1). Therefore, the phenomenon of the threshold voltage of the first transistor (T1) being lowered (hereinafter also referred to as the negative shift phenomenon of the threshold voltage) can be prevented. Accordingly, the driving performance of the first transistor (T1), which must act as a driving transistor, can be improved.

[0281] Referring to FIGS. 13 to 16, as described above, the first gate electrode (G1) of the first transistor (T1) may overlap with the first active layer (ACT1) as well as with the first source electrode (S1) and the first drain electrode (D1), but the second gate electrode (G2) of the second transistor (T2) may overlap with only a part of the second active layer (ACT2) and may not overlap with the second source electrode (S2) and the second drain electrode (D2).

[0282] Accordingly, hydrogen or light can flow from the protection layer (PAS) to the second active layer (ACT2) of the second transistor (T2). As a result, a phenomenon in which the threshold voltage of the second transistor (T2) is lowered (negative shift phenomenon of the threshold voltage) may occur. Therefore, the switching performance and reliability of the second transistor (T2), which must act as a switching transistor, can be improved.

[0283] Referring to FIGS. 13 to 16, the connection relationships of the light-emitting element (ED), the first transistor (T1), the second transistor (T2), and the storage capacitor (Cst) are briefly examined as follows.

[0284] The first gate electrode (G1) of the first transistor (T1) may be electrically connected to the second source electrode (S2) of the second transistor (T2) or the second source electrode (S2) of the second transistor (T2).

[0285] The first source electrode (S1) of the first transistor (T1) may be the first electrode (E1) of the light-emitting element (ED) or may be electrically connected to the first electrode (E1) of the light-emitting element (ED).

[0286] The first drain electrode (D1) of the first transistor (T1) can be electrically connected to the driving voltage line (DVL).

[0287] The second gate electrode (G2) of the second transistor (T2) may be part of the scan signal line (SCL) or electrically connected to the scan signal line (SCL).

[0288] The second drain electrode (D2) of the second transistor (T2) may be part of the data signal line (DL) or electrically connected to the data signal line (DL).

[0289] The second source electrode (S2) of the second transistor (T2) may be the first gate electrode (G1) of the first transistor (T1) or may be electrically connected to the first gate electrode (G1).

[0290] The storage capacitor (Cst) may include a first capacitor electrode (PLT1) and a second capacitor electrode (PLT2).

[0291] The first capacitor electrode (PLT1) may be the first source electrode (S1) of the first transistor (T1) or may be electrically connected to the first source electrode (S1) of the first transistor (T1).

[0292] Even though the first capacitor electrode (PLT1) is electrically connected to the first source electrode (S1) of the first transistor (T1), it may include the same material as the first gate electrode (G1). That is, the first capacitor electrode (PLT1) may be placed on the same material layer as the first gate electrode (G1).

[0293] The material included in the first capacitor electrode (PLT1), which is the uppermost capacitor electrode among the plurality of capacitor electrodes (first to third capacitor electrodes (PLT1, PLT2, PLT3)) constituting the storage capacitor (Cst) between the first source electrode (S1) and the first gate electrode (S2), may be included in the first gate electrode (G1).

[0294] The second capacitor electrode (PLT2) may be the first gate electrode (G1) of the first transistor (T1) or may be electrically connected to the first gate electrode (G1) of the first transistor (T1).

[0295] The second capacitor electrode (PLT2) may include a second lower capacitor electrode (PLT2a) and a second upper capacitor electrode (PLT2b).

[0296] The second lower capacitor electrode (PLT2a) may include the same material as the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2). That is, the second lower capacitor electrode (PLT2a) may be placed in the same material layer as the first and second source electrodes (S1, S2) and the first and second drain electrodes (D1, D2).

[0297] The second upper capacitor electrode (PLT2b) may include the same semiconductor material as the first and second active layers (ACT1, ACT2). Here, the semiconductor material included in the second upper capacitor electrode (PLT2b) may be in a conductive state or a non-conductive state. That is, the second upper capacitor electrode (PLT2b) may be placed in the same material layer as the first and second active layers (ACT1, ACT2).

[0298] Meanwhile, referring to FIGS. 13 to 16, the display panel (110) according to embodiments of the present disclosure may further include a side shield (SS) disposed between a storage capacitor (Cst) and a first transistor (T1).

[0299] For example, the side shield (SS) can be arranged in a line shape. For example, the side shield (SS) can have a bent line shape. That is, the side shield (SS) can include a bent portion.

[0300] For example, the side shield (SS) may be composed of a contact hole line (CNT_N1) connecting the second capacitor electrode (PLT2) and the first gate electrode (G1). Here, the contact hole line (CNT_N1) may be configured in the form of a trench.

[0301] Meanwhile, referring to FIGS. 13 to 16, the display panel (110) according to embodiments of the present disclosure may further include a lower shield (BS) located between a substrate (SUB) and a buffer layer (BUF) and overlapping with a first active layer (ACT1).

[0302] Below, the first transistor (T1) and the storage capacitor (Cst) will be described in more detail with reference to FIGS. 13 to 16.

[0303] Referring to FIGS. 13 to 16, the first drain electrode (D1) of the first transistor (T1) can be connected to the driving voltage line (DVL) through a contact hole (CNT_N3), and the first source electrode (S1) of the first transistor (T1) can be connected to the first capacitor electrode (PLT1) included in the storage capacitor (Cst) through a contact hole (CNT_N2).

[0304] Referring to FIGS. 13 to 16, in a display panel (110) according to embodiments of the present disclosure, the storage capacitor (Cst) may further include a third capacitor electrode (PLT3).

[0305] The third capacitor electrode (PLT3) can be electrically connected to the first capacitor electrode (PLT1) through the contact hole (CNT_PLT1,3).

[0306] The first capacitor electrode (PLT1) can be electrically connected to the first source electrode (S1). Accordingly, the third capacitor electrode (PLT3) can be electrically connected to the first source electrode (S1).

[0307] In other words, the first capacitor electrode (PLT1) and the third capacitor electrode (PLT3) can be electrically connected to the first source electrode (S1) of the first transistor (T1).

[0308] The second capacitor electrode (PLT2) can be electrically connected to the first gate electrode (G1) of the first transistor (T1).

[0309] In a display panel (110) according to embodiments of the present disclosure, the storage capacitor (Cst) may include a first storage capacitor (Cst1) between a first capacitor electrode (PLT1) and a second capacitor electrode (PLT2), and a second storage capacitor (Cst2) between a second capacitor electrode (PLT2) and a third capacitor electrode (PLT3).

[0310] The first storage capacitor (Cst1) and the second storage capacitor (Cst2) can be electrically connected in parallel. That is, the storage capacitor (Cst) can be configured by electrically connecting the first storage capacitor (Cst1) and the second storage capacitor (Cst2) in parallel. In this way, as the storage capacitor (Cst) has a dual capacitor parallel structure, the capacitance of the storage capacitor (Cst) can be increased.

[0311] Referring to FIGS. 13 to 16, the second drain electrode (D2) of the second transistor (T2) is connected to a data signal line (DL), and the second source electrode (S2) of the second transistor (T2) may be composed of a second capacitor electrode (PLT2) included in a storage capacitor (Cst) or connected to the second capacitor electrode (PLT2). The second gate electrode (G2) of the second transistor (T2) may be part of a scan signal line (SCL).

[0312] Referring to FIGS. 13 to 16, the lower shield (BS) can be electrically connected to the first source electrode (S1) of the first transistor (T1).

[0313] Accordingly, the first source electrode (S1) of the first transistor (T1) can be electrically connected to the first capacitor electrode (PLT1), the third capacitor electrode (PLT3), and the lower shield (BS).

[0314] As shown in FIGS. 14 and 15, the lower shield (BS) can be formed integrally with the third capacitor electrode (PLT3).

[0315] Meanwhile, referring to FIG. 13, in a display panel (110) according to embodiments of the present disclosure, a gate insulating film (GI) may be disposed between a first capacitor electrode (PLT1) and a second capacitor electrode (PLT2) constituting a storage capacitor (Cst), and a buffer layer (BUF) may be disposed between the second capacitor electrode (PLT2) and a third capacitor electrode (PLT3).

[0316] In this way, the gate insulating film (GI) is extended without being etched in the region of the transistors (T1, T2) and is placed between the first capacitor electrode (PLT1) and the second capacitor electrode (PLT2), so that the gate insulating film (GI) can be utilized as an insulating film (dielectric) for the configuration of the storage capacitor (Cst). Accordingly, the gap between the first capacitor electrode (PLT1) and the second capacitor electrode (PLT2) can be reduced. Thus, the capacitance of the storage capacitor (Cst) can be increased.

[0317] In addition, as described above, by configuring the storage capacitor (Cst) in a parallel structure of the first storage capacitor (Cst1) and the second storage capacitor (Cst2), the capacitance of the storage capacitor (Cst) can be increased.

[0318] As such, the display panel (110) according to the embodiments of the present disclosure has a capacitance increasing structure of the storage capacitor (Cst), so that when designing the storage capacitor (Cst) having a desired capacitance, there may be a design advantage of reducing the area of ​​the storage capacitor (Cst).

[0319] Referring to FIG. 13, in a display panel (110) according to embodiments of the present disclosure, the first gate electrode (G1) of the first transistor (T1) may be composed of a single layer, and the second gate electrode (G2) of the second transistor (T2) may also be composed of a single layer. For reference, in the display panel (110) of FIG. 6, the first gate electrode (G1) and the second gate electrode (G2) are each composed of a double layer.

[0320] Referring to FIGS. 13 to 16, the first gate electrode (G1) may include the same material as the first capacitor electrode (PLT1).

[0321] Referring to FIGS. 13 to 16, a protective layer (PAS) may be disposed on a first capacitor electrode (PLT1), a first gate electrode, and a second gate electrode, and a bank (BK) may be disposed on the protective layer (PAS).

[0322] Referring to FIGS. 13 through 16, the first electrode (E1) and the first capacitor electrode (PLT1) may be configured separately. In contrast, in the display panel (110) of FIG. 6, the first capacitor electrode (PLT1) and the first electrode (E1) are not configured separately, and the first capacitor electrode (PLT1) may serve as the first electrode (E1). In this regard, in the display panel (110) of FIG. 6, the first capacitor electrode (PLT1) may include the same material as the first lower gate electrode (G1a). For example, in the display panel (110) of FIG. 6, the first capacitor electrode (PLT1) and the first lower gate electrode (G1a) may include a pixel electrode material.

[0323] Referring to FIGS. 13 to 16, the first electrode (E1) can be placed between the protective layer (PAS) and the bank (BK). The first electrode (E1) can be connected to the first capacitor electrode (PLT1) through a hole in the protective layer (PAS).

[0324] Referring to FIGS. 13 to 16, the light-emitting layer (EL) is disposed on a bank (BK) and can be in contact with the exposed upper surface of the first electrode (E1) through a hole in the bank (BK). The second electrode (E2) can be located on the light-emitting layer (EL).

[0325] Referring to FIG. 13, the light-emitting region (EA) of the subpixel (SP) can overlap with the first transistor (T1). That is, the light-emitting region (EA) of the subpixel (SP) can be located above the first transistor (T1).

[0326] In this way, since the light-emitting region (EA) of the subpixel (SP) is located above the first transistor (T1), the size of the light-emitting region (EA) of each subpixel (SP) in the display panel (110) of FIG. 13 may be larger than the size of the light-emitting region (EA) of each subpixel (SP) in the display panel (110) of FIG. 6.

[0327] FIG. 17 illustrates the differential characteristics regarding the blocking of light and hydrogen of another display panel (110) according to embodiments of the present disclosure.

[0328] Referring to FIG. 17, in a display panel (110) according to embodiments of the present disclosure, the first transistor (T1) and the second transistor (T2) included in each subpixel (SP) may have different gate electrode structures.

[0329] Referring to FIG. 17, the first gate electrode (G1), which is composed of a single layer of the first transistor (T1), can overlap not only with the first active layer (ACT1) but also with the first source electrode (S1) and the first drain electrode (D1).

[0330] Accordingly, the first gate electrode (G1) can block hydrogen or light from flowing from the protection layer (PAS) to the first active layer (ACT1) of the first transistor (T1). Therefore, the phenomenon of the threshold voltage of the first transistor (T1) being lowered (hereinafter also referred to as the negative shift phenomenon of the threshold voltage) can be prevented. Accordingly, the driving performance of the first transistor (T1), which must act as a driving transistor, can be improved.

[0331] Referring to FIG. 17, the first gate electrode (G1) of the first transistor (T1) may overlap with the first active layer (ACT1) and may also overlap with the first source electrode (S1) and the first drain electrode (D1), but the second gate electrode (G2) of the second transistor (T2) may only overlap with a part of the second active layer (ACT2) and may not overlap with the second source electrode (S2) and the second drain electrode (D2).

[0332] Accordingly, hydrogen or light can flow from the protection layer (PAS) to the second active layer (ACT2) of the second transistor (T2). As a result, a phenomenon in which the threshold voltage of the second transistor (T2) is lowered (negative shift phenomenon of the threshold voltage) may occur. Therefore, the switching performance and reliability of the second transistor (T2), which must act as a switching transistor, can be improved.

[0333] Referring to FIG. 17, a display panel (110) according to embodiments of the present disclosure may include a substrate (SUB) and a first transistor (T1) and a second transistor (T2) on the substrate (SUB).

[0334] The first transistor (T1) may include a first active layer (ACT1), a first source electrode (S1) connected to one side of the first active layer (ACT1), a first drain electrode (D1) connected to the other side of the first active layer (ACT1), and a first gate electrode (G1) that overlaps with all or part of the first active layer (ACT1).

[0335] The second transistor (T2) may include a second active layer (ACT2), a second source electrode (S2) connected to one side of the second active layer (ACT2), a second drain electrode (D2) connected to the other side of the second active layer (ACT2), and a second gate electrode (G2) that overlaps with a part of the second active layer (ACT2).

[0336] Referring to FIG. 17, a gate insulating film (GI) may be further included between the first active layer (ACT1) and the first gate electrode (G1) and between the second active layer (ACT2) and the second gate electrode (G2).

[0337] Hydrogen or light generated at the top of the first gate electrode (G1) is blocked by the first gate electrode (G1) and does not flow down below the first gate electrode (G1).

[0338] However, hydrogen or light generated at the top of the second gate electrode (G2) is not blocked by the second gate electrode (G2) and flows into the side of the second gate electrode (G2) and can flow into the second active layer (ACT2) located below the second gate electrode (G2).

[0339] Accordingly, in the gate insulating film (GI), the hydrogen concentration or light exposure amount in the portion between the first active layer (ACT1) and the first gate electrode (G1) may be lower than the hydrogen concentration or light exposure amount in the portion between the second active layer (ACT2) and the second gate electrode (G2).

[0340] Here, hydrogen or light may be generated during the manufacturing process of the display panel (110) or may be generated inside the panel even after the manufacturing of the display panel (110) is completed. For example, hydrogen may be generated from various layers (in particular, various types of insulating layers) located above the first transistor (T1) and directed toward the first transistor (T1). Light emitted from a light-emitting element (ED) located above the first transistor (T1) may be directed toward the first transistor (T1). Additionally, external light may be introduced from above the first transistor (T1) and directed toward the first transistor (T1).

[0341] Referring to FIGS. 13 to 17, in the first transistor (T1), since the first gate electrode (G1) overlaps with the first source electrode (S1) and overlaps with the first drain electrode (D1), the capacitance of the parasitic capacitor between the first gate electrode (G1) and the first source electrode (S1) and the capacitance of the parasitic capacitor between the first gate electrode (G1) and the first drain electrode (D1) may increase. Accordingly, the device performance of the first transistor (T1) may decrease.

[0342] A display panel (110) according to embodiments of the present disclosure may have a source-drain asymmetric structure that prevents device performance degradation caused by parasitic capacitors, even though a first gate electrode (G1) composed of a single layer overlaps with a first source electrode (S1) and overlaps with a first drain electrode (D1). Hereinafter, the source-drain asymmetric structure of a display panel (110) according to embodiments of the present disclosure will be described with reference to FIG. 18.

[0343] FIG. 18 shows a parasitic capacitor utilization structure of another display panel (110) according to embodiments of the present disclosure.

[0344] Referring to FIG. 18, in the first transistor (T1), since the first gate electrode (G1) overlaps with the first source electrode (S1) and the first drain electrode (D1), a first parasitic capacitor (Cgs) can be formed between the first gate electrode (G1) and the first source electrode (S1), and a second parasitic capacitor (Cgd) can be formed between the first gate electrode (G1) and the first drain electrode (D1).

[0345] Referring to FIG. 18, the larger the capacitance of the storage capacitor (Cst), the more advantageous it is for driving the display. This storage capacitor (Cst) can be formed between the first gate electrode (G1) and the first source electrode (S1).

[0346] Referring to FIG. 18, since the first parasitic capacitor (Cgs) and the storage capacitor (Cst) are formed at the same location, increasing the capacitance of the first parasitic capacitor (Cgs) between the first gate electrode (G1) and the first source electrode (S1) can increase the capacitance of the storage capacitor (Cst).

[0347] Therefore, increasing the capacitance of the first parasitic capacitor (Cgs) between the first gate electrode (G1) and the first source electrode (S1) can be advantageous in terms of display driving.

[0348] However, since the second parasitic capacitor (Cgd) is formed between the first gate electrode (G1) and the first drain electrode (D1), an increase in the capacitance of the second parasitic capacitor (Cgd) may be disadvantageous in terms of display driving.

[0349] Referring to FIG. 18, in a display panel (110) according to embodiments of the present disclosure, a first parasitic capacitor (Cgs) formed between a first gate electrode (G1) and a first source electrode (S1) may be an additional storage capacitor (AUX_Cst). That is, an additional storage capacitor (Cgs) may be configured as the first source electrode (S1) and the first gate electrode (G1) overlap.

[0350] Referring to FIG. 18, a display panel (110) according to embodiments of the present disclosure may have a structure in which the area of ​​the first source electrode (S1) is larger than the area of ​​the first drain electrode (D1). This structure is called a source-drain asymmetric structure.

[0351] In other words, according to the source-drain asymmetric structure of the display panel (110) according to the embodiments of the present disclosure, the area where the first source electrode (S1) and the first gate electrode (G1) overlap may be larger than the area where the first drain electrode (D1) and the first gate electrode (G1) overlap.

[0352] Referring to FIG. 18, the length (Ls1) in one direction of the first source electrode (S1) may be longer than the length (Ld1) in one direction of the first drain electrode (D1).

[0353] Referring to FIG. 18, according to the source-drain asymmetric structure of the display panel (110) according to embodiments of the present disclosure, the capacitance of the first parasitic capacitor (Cgs) formed between the first gate electrode (G1) and the first source electrode (S1) can be maximized, and the capacitance of the second parasitic capacitor (Cgd) formed between the first gate electrode (G1) and the first drain electrode (D1) can be maximized.

[0354] Referring to FIG. 18, according to the source-drain asymmetric structure of the display panel (110) according to embodiments of the present disclosure, the capacitance increase by an additional storage capacitor (AUX_Cst) corresponding to a first parasitic capacitor (Cgs) formed between the first gate electrode (G1) and the first source electrode (S1) may be much larger than the capacitance of a second parasitic capacitor (Cgd) formed between the first gate electrode (G1) and the first drain electrode (D1).

[0355] Therefore, even if the first gate electrode (G1) is extended and overlaps with the first source electrode (S1) and the first drain electrode (D1), the first transistor (T1) has a source-drain asymmetric structure, so device performance degradation due to parasitic capacitors (Cgd, Cgs) can be prevented.

[0356] Since the first transistor (T1) has a source-drain asymmetric structure, an additional storage capacitor (AUX_Cst) is added to the storage capacitor (Cst), which can be advantageous for driving the display.

[0357] For example, the first transistor (T1) may be a top gate transistor and / or an oxide semiconductor transistor. The first transistor (T1) may have a structure in which the gate insulating film (GI) is not etched.

[0358] For example, the second transistor (T2) may be a top gate transistor and / or an oxide semiconductor transistor. The second transistor (T2) may have a structure in which the gate insulating film (GI) is not etched.

[0359] Referring to FIGS. 13 to 18, in a display panel (110) according to embodiments of the present disclosure, when forming the source electrodes (S1, S2) and drain electrodes (D1, D2) of the first and second transistors (T1, T2), a separate mask is not used, and they can be formed together when forming the active layers (ACT1, ACT2) using a halftone mask. Accordingly, the display panel (110) according to embodiments of the present disclosure can be seen as having a structure that can reduce the number of masks required when manufacturing the panel.

[0360] FIG. 19 is another cross-sectional view of another display panel (110) according to embodiments of the present disclosure.

[0361] The cross-sectional structure (vertical structure) of Fig. 19 is identical to the cross-sectional structure (vertical structure) of Fig. 13 except for the connection structure of the lower shield (BS).

[0362] Referring to FIG. 19, the lower shield (BS) is not electrically connected to the first source electrode (S1) of the first transistor (T1), but can be electrically connected to the first gate electrode (G1) of the first transistor (T1) through holes (CNT_BS) in the gate insulating film (GI) and the buffer layer (BUF).

[0363] In this case, the first gate electrode (G1) may be the top gate electrode of the first transistor (T1), and the lower shield (BS) may be the bottom gate electrode of the first transistor (T1).

[0364] In other words, when the lower shield (BS) is electrically connected to the first gate electrode (G1) of the first transistor (T1), the first transistor (T1) may have a double gate electrode structure including both a top gate electrode and a bottom gate electrode.

[0365] Referring to FIG. 19, the first source electrode (S1) of the first transistor (T1) is electrically connected to the first capacitor electrode (PLT1) and the third capacitor electrode (PLT3), and the first gate electrode (G1) of the first transistor (T1) can be electrically connected to the lower shield (BS).

[0366] The embodiments of the present disclosure described above are briefly explained as follows.

[0367] A display panel according to embodiments of the present disclosure may include a data signal line for supplying a data signal, a scan signal line for supplying a scan signal, and a subpixel connected to the data signal line and the scan signal line and including a first transistor.

[0368] The first transistor may include a first active layer, a first source electrode connected to one side of the first active layer, a first drain electrode connected to the other side of the first active layer, and a first gate electrode that overlaps with the first active layer, overlaps with all or part of the first source electrode, and overlaps with all or part of the first drain electrode.

[0369] The subpixel may further include a light-emitting element, a second transistor, and a storage capacitor.

[0370] The light-emitting element may include a first electrode, a light-emitting layer, and a second electrode.

[0371] The second transistor may include a second active layer, a second source electrode connected to one side of the second active layer, a second drain electrode connected to the other side of the second active layer, and a first gate electrode that overlaps with a part of the second active layer and does not overlap with the second source electrode and the second drain electrode.

[0372] The first transistor is a driving transistor, and the second transistor may be a scan transistor, which is a type of switching transistor.

[0373] The first gate electrode is the second source electrode or is electrically connected to the second source electrode, and the first source electrode is the first electrode or can be electrically connected to the first electrode.

[0374] The second gate electrode is part of the scan signal line or is electrically connected to the scan signal line, the second drain electrode is part of the data signal line or is electrically connected to the data signal line, and the second source electrode may be the first gate electrode or be electrically connected to the first gate electrode.

[0375] The storage capacitor may include a first capacitor electrode and a second capacitor electrode. The first capacitor electrode may be a first source electrode or may be electrically connected to the first source electrode. The second capacitor electrode may be a first gate electrode or may be electrically connected to the first gate electrode.

[0376] A display panel according to embodiments of the present disclosure may further include a side shield disposed between a storage capacitor and a first transistor. The side shield may include a trench-shaped contact hole line in which a second capacitor electrode and a first gate electrode are connected.

[0377] The side shield may include a bent section.

[0378] A display panel according to embodiments of the present disclosure may further include a substrate, a buffer layer on the substrate, and a lower shield located between the substrate and the buffer layer and overlapping with a first active layer.

[0379] The storage capacitor may further include a third capacitor electrode electrically connected to a first source electrode and a first capacitor electrode.

[0380] A storage capacitor may include a first storage capacitor between a first capacitor electrode and a second capacitor electrode, and a second storage capacitor between a second capacitor electrode and a third capacitor electrode. The first storage capacitor and the second storage capacitor may be electrically connected in parallel.

[0381] The lower shield can be electrically connected to the first source electrode.

[0382] Alternatively, the lower shield can be electrically connected to the first gate electrode.

[0383] The first gate electrode may include a first lower gate electrode and a first upper gate electrode. The first lower gate electrode is in contact with the second capacitor electrode and may include the same material as the first capacitor electrode.

[0384] A display panel according to embodiments of the present disclosure may include a first capacitor electrode, a first gate electrode, a protective layer disposed on a second gate electrode, and a bank on the protective layer.

[0385] The light-emitting layer is disposed on the bank, and the second electrode can be disposed on the light-emitting layer.

[0386] The first capacitor electrode may be the first electrode.

[0387] A portion of the light-emitting layer can be in contact with the upper surface of the first capacitor electrode corresponding to the first electrode through the holes of the bank and the protective layer.

[0388] In a display panel according to embodiments of the present disclosure, the light-emitting region of a subpixel may be located above a storage capacitor.

[0389] In a display panel according to embodiments of the present disclosure, the first gate electrode is composed of a single layer and may include the same material as the first capacitor electrode.

[0390] A display panel according to embodiments of the present disclosure may further include a first capacitor electrode, a first gate electrode, a protective layer disposed on a second gate electrode, and a bank disposed on the protective layer.

[0391] The first electrode is placed between the protective layer and the bank, and the first electrode can be connected to the first capacitor electrode through a hole in the protective layer.

[0392] The light-emitting layer is disposed on the bank, and can be in contact with the exposed upper surface of the first electrode through the hole of the bank.

[0393] In a display panel according to embodiments of the present disclosure, the light-emitting region of a subpixel may overlap with a first transistor and be located above the first transistor.

[0394] In a display panel according to embodiments of the present disclosure, the area where the first source electrode and the first gate electrode overlap may be larger than the area where the first drain electrode and the first gate electrode overlap.

[0395] In a display panel according to embodiments of the present disclosure, an additional storage capacitor may be configured as the first source electrode and the first gate electrode overlap.

[0396] A display device according to embodiments of the present disclosure may include a substrate, and a first transistor and a second transistor on the substrate.

[0397] The first transistor may include a first active layer, a first source electrode connected to one side of the first active layer, a first drain electrode connected to the other side of the first active layer, and a first gate electrode that overlaps all or part of the first active layer.

[0398] The second transistor may include a second active layer, a second source electrode connected to one side of the second active layer, a second drain electrode connected to the other side of the second active layer, and a second gate electrode that overlaps with a part of the second active layer.

[0399] The first gate electrode of the first transistor may be a top gate electrode located on the first active layer, and the second gate electrode of the second transistor may be a top gate electrode located on the second active layer.

[0400] It may further include a gate insulating film disposed between the first active layer and the first gate electrode and between the second active layer and the second gate electrode.

[0401] In the gate insulating film, the hydrogen concentration or light exposure amount in the portion between the first active layer and the first gate electrode may be lower than the hydrogen concentration or light exposure amount in the portion between the second active layer and the second gate electrode.

[0402] The hydrogen concentration or light exposure amount of the first active layer may be lower than the hydrogen concentration or light exposure amount of the second active layer.

[0403] The first gate electrode may overlap with all or part of the first source electrode and may overlap with all or part of the first drain electrode. In contrast, the second gate electrode does not overlap with the second source electrode and the second drain electrode.

[0404] The display panel may include a storage capacitor comprising a first capacitor electrode and a second capacitor electrode.

[0405] The first gate electrode may include a material included in the first capacitor electrode. The first capacitor electrode may be electrically connected to the first source electrode, and the second capacitor electrode may be electrically connected to the first gate electrode.

[0406] The storage capacitor may further include a third capacitor electrode, and the third capacitor electrode may be electrically connected to the first source electrode.

[0407] The material included in the uppermost capacitor electrode (first capacitor electrode) among the plurality of capacitor electrodes (first to third capacitor electrodes) constituting the storage capacitor between the first source electrode and the first gate electrode may be included in the first gate electrode.

[0408] According to the embodiments of the present disclosure described above, a display panel and a display device comprising a first transistor having a structure robust to exposure to light or hydrogen, etc. Herein, the first transistor may be a driving element (driving transistor).

[0409] According to embodiments of the present disclosure, a display panel and a display device can be provided that include a first transistor having a structure that is not exposed to light or hydrogen, even if the first transistor has a top gate structure that is highly likely to be exposed to light or hydrogen, etc.

[0410] According to embodiments of the present disclosure, a display panel and a display device can be provided, comprising a first transistor having a structure that is not exposed to light or hydrogen, in a display panel having an upper light-emitting structure that is likely to be exposed to light or hydrogen, etc.

[0411] According to embodiments of the present disclosure, a display panel and a display device may be provided that include different types of transistors having structures differentiated according to the advantages and disadvantages of changes in device characteristics due to exposure to light or hydrogen.

[0412] Here, other types of transistors may include a first transistor corresponding to a driving transistor (driving element) and a second transistor corresponding to a switching transistor (switching element, e.g., scan transistor, sensing transistor).

[0413] When a driving transistor (driving element) is exposed to light or hydrogen, its driving performance may be degraded, and when a switching transistor (switching element) is exposed to light or hydrogen, its switching performance may be improved.

[0414] Accordingly, the first transistor, which is a driving transistor, may have a gate electrode structure that prevents exposure to light or hydrogen, and the second transistor, which is a switching transistor, may have a gate electrode structure that allows exposure to light or hydrogen.

[0415] The foregoing description is merely an illustrative explanation of the technical concept of the present disclosure, and those skilled in the art to which the present disclosure pertains may make various modifications and variations within the scope of the essential characteristics of the present disclosure. Furthermore, the embodiments disclosed in the present disclosure are intended to explain, not limit, the technical concept of the present disclosure, and thus the scope of the technical concept of the present disclosure is not limited by these embodiments. The scope of protection of the present disclosure shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present disclosure.

Claims

Claim 1 A display panel comprising: a data signal line for supplying a data signal; a scan signal line for supplying a scan signal; and a subpixel connected to the data signal line and the scan signal line, and comprising a first transistor and a storage capacitor, wherein the first transistor comprises a first active layer, a first source electrode connected to one side of the first active layer, a first drain electrode connected to the other side of the first active layer, and a first gate electrode that overlaps with the first active layer, overlaps with all or part of the first source electrode, and overlaps with all or part of the first drain electrode, and an additional storage capacitor is configured as the first source electrode and the first gate electrode overlap. Claim 2 A display panel according to claim 1, wherein the subpixel further comprises a light-emitting element and a second transistor, the light-emitting element comprises a first electrode, a light-emitting layer, and a second electrode, and the second transistor comprises a second active layer, a second source electrode connected to one side of the second active layer, a second drain electrode connected to the other side of the second active layer, and a second gate electrode that overlaps with a part of the second active layer and does not overlap with the second source electrode and the second drain electrode. Claim 3 A display panel according to claim 2, wherein the first gate electrode is a top gate electrode located on the first active layer, the second gate electrode is a top gate electrode located on the second active layer, the first gate electrode is the second source electrode or is electrically connected to the second source electrode, the first source electrode is the first electrode or is electrically connected to the first electrode, the second gate electrode is a part of the scan signal line or is electrically connected to the scan signal line, the second drain electrode is a part of the data signal line or is electrically connected to the data signal line, and the second source electrode is the first gate electrode or is electrically connected to the first gate electrode. Claim 4 In paragraph 2, the storage capacitor comprises a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is the first source electrode or is electrically connected to the first source electrode, and the second capacitor electrode is the first gate electrode or is electrically connected to the first gate electrode, and the display panel. Claim 5 A display panel according to claim 4, further comprising a side shield disposed between the storage capacitor and the first transistor, wherein the side shield includes a trench-shaped contact hole line connecting the second capacitor electrode and the first gate electrode. Claim 6 In paragraph 5, the side shield is a display panel including a bent portion. Claim 7 A display panel according to claim 4, further comprising: a substrate; a buffer layer on the substrate; and a lower shield located between the substrate and the buffer layer and overlapping with the first active layer. Claim 8 In claim 7, the storage capacitor further comprises a third capacitor electrode electrically connected to the first source electrode and the first capacitor electrode, and the storage capacitor comprises a first storage capacitor between the first capacitor electrode and the second capacitor electrode; and a second storage capacitor between the second capacitor electrode and the third capacitor electrode, wherein the first storage capacitor and the second storage capacitor are electrically connected in parallel to a display panel. Claim 9 In claim 7, the lower shield is a display panel electrically connected to the first source electrode. Claim 10 In claim 9, the lower shield is a display panel integrally formed with one capacitor electrode included in the storage capacitor. Claim 11 In claim 7, the lower shield is a display panel electrically connected to the first gate electrode. Claim 12 In claim 4, the first gate electrode comprises a first lower gate electrode and a first upper gate electrode, the first lower gate electrode is in contact with the second capacitor electrode, and the display panel comprises the same material as the first capacitor electrode. Claim 13 A display panel according to claim 12, comprising: a protective layer disposed on the first capacitor electrode, the first gate electrode, and the second gate electrode; and a bank on the protective layer, wherein the light-emitting layer is disposed on the bank, the second electrode is disposed on the light-emitting layer, the first capacitor electrode is the first electrode, and a portion of the light-emitting layer is in contact with the upper surface of the first capacitor electrode corresponding to the first electrode through a hole in the bank and the protective layer. Claim 14 In paragraph 4, the light-emitting region of the subpixel is a display panel located above the storage capacitor. Claim 15 In paragraph 4, the first gate electrode is composed of a single layer and is a display panel comprising the same material as the first capacitor electrode. Claim 16 A display panel according to claim 4, further comprising: a protective layer disposed on the first capacitor electrode, the first gate electrode, and the second gate electrode; and a bank disposed on the protective layer, wherein the first electrode is disposed between the protective layer and the bank, and the first electrode is connected to the first capacitor electrode through a hole in the protective layer, and the light-emitting layer is disposed on the bank and contacts the exposed upper surface of the first electrode through a hole in the bank. Claim 17 In paragraph 4, the light-emitting region of the subpixel is a display panel located above the first transistor. Claim 18 A display panel according to claim 1, wherein the area where the first source electrode and the first gate electrode overlap is larger than the area where the first drain electrode and the first gate electrode overlap. Claim 19 delete Claim 20 Substrate; The apparatus comprises a first transistor, a second transistor, and a storage capacitor on the substrate, wherein the first transistor comprises a first active layer, a first source electrode connected to one side of the first active layer, a first drain electrode connected to the other side of the first active layer, and a first gate electrode that overlaps all or part of the first active layer, and the second transistor comprises a second active layer, a second source electrode connected to one side of the second active layer, a second drain electrode connected to the other side of the second active layer, and a second gate electrode that overlaps part of the second active layer, and further comprises a gate insulating film disposed between the first active layer and the first gate electrode and between the second active layer and the second gate electrode, wherein in the gate insulating film, the hydrogen concentration or light exposure amount in the portion between the first active layer and the first gate electrode is lower than the hydrogen concentration or light exposure amount in the portion between the second active layer and the second gate electrode, and an additional storage capacitor is configured as the first source electrode and the first gate electrode overlap. Device. Claim 21 A display device according to claim 20, wherein the first gate electrode overlaps with all or part of the first source electrode and overlaps with all or part of the first drain electrode, and the second gate electrode does not overlap with the second source electrode and the second drain electrode. Claim 22 In claim 20, the storage capacitor is disposed between the first source electrode and the first gate electrode, and the material included in the uppermost capacitor electrode among the plurality of capacitor electrodes constituting the storage capacitor is a display device included in the first gate electrode.

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