Semiconductor device including capacitor structure and method for manufacturing the same

Abstract

A semiconductor device of the present disclosure comprises: a substrate; a capacitor contact structure electrically connected to the substrate; a lower electrode connected to the capacitor contact structure; a capacitor insulating film covering the lower electrode; and an upper electrode covering the capacitor insulating film. The upper electrode comprises a multilayer film on the capacitor insulating film and a cover film on the multilayer film. The multilayer film comprises a first electrode film, a second electrode film, and a first metal silicide film between the first and second electrode films. The work function of the first metal silicide film is greater than the work function of the first electrode film and the work function of the second electrode film.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device. More specifically, the present disclosure relates to a semiconductor device comprising a capacitor structure. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements. As the electronics industry advances, demands regarding the characteristics of semiconductor devices are steadily increasing. For example, there is a growing demand for high reliability, high speed, and / or multifunctionality in semiconductor devices. To meet these requirements, the internal structures of semiconductor devices are becoming increasingly complex, and the devices are becoming more highly integrated. Prior art literature

[65535] U.S. Patent Publication No. US 2021 / 0066446 The problem to be solved

[0003] The objective of the present invention is to provide a semiconductor device with improved characteristics of a capacitor structure. means of solving the problem

[0004] A semiconductor device according to some embodiments of the present disclosure comprises: a substrate; a capacitor contact structure electrically connected to the substrate; a lower electrode connected to the capacitor contact structure; a capacitor insulating film covering the lower electrode; and an upper electrode covering the capacitor insulating film, wherein the upper electrode comprises a multilayer film on the capacitor insulating film and a cover film on the multilayer film, and the multilayer film comprises a first electrode film, a second electrode film and a first metal silicide film between the first and second electrode films, and the work function of the first metal silicide film may be greater than the work function of the first electrode film and the work function of the second electrode film.

[0005] A semiconductor device according to some embodiments of the present disclosure comprises: a substrate having an active pattern; a gate structure on the active pattern; a bitline structure electrically connected to the active pattern; a capacitor contact structure electrically connected to the active pattern; a lower electrode connected to the capacitor contact structure; a capacitor insulating film covering the lower electrode; and an upper electrode covering the capacitor insulating film, wherein the upper electrode comprises a first electrode film and a first metal silicide film having a work function greater than that of the first electrode film, and the first electrode film may comprise a metal nitride.

[0006] A semiconductor device according to some embodiments of the present disclosure comprises a substrate; and a capacitor structure electrically connected to the substrate, wherein the capacitor structure comprises: a lower electrode; an upper electrode; and a capacitor insulating film between the lower electrode and the upper electrode, wherein the upper electrode comprises a first metal silicide film and a first electrode film on the first metal silicide film, and the work function of the first electrode film may be smaller than the work function of the first metal silicide film. Effects of the invention

[0007] A semiconductor device according to the embodiments of the present disclosure may have the effect of reducing leakage current without deteriorating the characteristics of the upper electrode, as the upper electrode of the capacitor structure includes a metal silicide film. Brief explanation of the drawing

[0008] FIG. 1a is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Figure 1b is a cross-sectional view along the line A-A' of Figure 1a. FIG. 2 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 3 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 4 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 5a is a plan view of a semiconductor device according to some embodiments of the present disclosure. Figure 5b is a cross-sectional view along the line B-B' of Figure 5a. Fig. 5c is a cross-sectional view along the line C-C' of Fig. 5a. FIG. 6a is a perspective view of a semiconductor device according to some embodiments of the present disclosure. Figure 6b is a cross-sectional view along the line D-D' of Figure 6a. Fig. 6c is a cross-sectional view along the line E-E' of Fig. 6a. Specific details for implementing the invention

[0009] FIG. 1a is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG. 1b is a cross-sectional view along the line A-A' of FIG. 1a.

[0010] Referring to FIGS. 1a and 1b, the semiconductor device may include a substrate (100). In some embodiments, the substrate (100) may be a semiconductor substrate. For example, the substrate (100) may include silicon, germanium, silicon-germanium, GaP, or GaAs. In some embodiments, the substrate (100) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. The substrate (100) may have the form of a plate extending along a plane extending in a first direction (D1) and a second direction (D2). The first direction (D1) and the second direction (D2) may intersect each other. For example, the first direction (D1) and the second direction (D2) may be horizontal directions orthogonal to each other.

[0011] An interlayer insulating film (110) covering a substrate (100) may be provided. In some embodiments, the interlayer insulating film (110) may be a multiple insulating film comprising a plurality of insulating films.

[0012] Capacitor contact structures (120) penetrating an interlayer insulating film (110) may be provided. The capacitor contact structures (120) may be electrically connected to a substrate (100). In some embodiments, the capacitor contact structures (120) may be connected to an impurity region formed within the substrate (100). In some embodiments, each capacitor contact structure (120) may be a multi-conducting film comprising a plurality of conductive films. The capacitor contact structures (120) may include, for example, tungsten.

[0013] A capacitor structure (130) may be provided on an interlayer insulating film (110). The capacitor structure (130) may be electrically connected to capacitor contact structures (120). The capacitor structure (130) may be electrically connected to a substrate (100) through capacitor contact structures (120). The capacitor structure (130) may include lower electrodes (LE), a capacitor insulating film (CI), a supporter (SU), and an upper electrode (UE).

[0014] The lower electrodes (LE) may have the form of pillars extending in a third direction (D3). The third direction (D3) may intersect the first direction (D1) and the second direction (D2). For example, the third direction (D3) may be a vertical direction orthogonal to the first direction (D1) and the second direction (D2). The lower electrodes (LE) may be connected to a capacitor contact structure (120). A supporter (SU) may support the lower electrodes (LE). The side wall of the supporter (SU) may be in contact with the side wall of the lower electrode (LE) so that the supporter (SU) may support the side wall of the lower electrode (LE). In some embodiments, a single lower electrode (LE) may be supported by a plurality of supporters (SU). In this case, the plurality of supporters (SU) supporting the single lower electrode (LE) may be located at different levels.

[0015] The lower electrode (LE) may include a conductive material. For example, the lower electrode (LE) may include at least one of TiN, TiAlN, TiSiN, TaN, TaAlN, TaSiN, or WN. The supporter (SU) may include an insulating material. For example, the supporter (SU) may include SiCN.

[0016] A capacitor insulating film (CI) may cover the lower electrodes (LE) and the supporter (SU). A capacitor insulating film (CI) may surround the lower electrodes (LE) and the supporter (SU). A capacitor insulating film (CI) may cover an interlayer insulating film (110). The capacitor insulating film (CI) may include an insulating material. For example, the capacitor insulating film (CI) may include a metal oxide, and the metal may be at least one of Nb, Zr, Hf, Al, or Ti. In some embodiments, the capacitor insulating film (CI) may be a multi-layer insulating film.

[0017] In some embodiments, unlike illustrated, the capacitor insulating film (CI) may include a portion surrounded by the lower electrode (LE). During the process of forming the lower electrode (LE), a void space surrounded by the lower electrode (LE) may be formed, and a portion of the capacitor insulating film (CI) may be formed within the void space so that a portion of the capacitor insulating film (CI) is surrounded by the lower electrode (LE).

[0018] The upper electrode (UE) can cover the capacitor insulating film (CI). The upper electrode (UE) can surround the lower electrodes (LE), the supporter (SU), and the capacitor insulating film (CI). A portion of the capacitor insulating film (CI) can be provided between the lower electrode (LE) and the upper electrode (UE). A portion of the capacitor insulating film (CI) can be provided between the supporter (SU) and the upper electrode (UE).

[0019] The upper electrode (UE) may include a multilayer film (MU) and a cover film (CV) on the multilayer film (MU). The multilayer film (MU) may be provided on a capacitor insulating film (CI). The cover film (CV) may include, for example, SiGe.

[0020] The multilayer film (MU) may include a first electrode film (EL1), a second electrode film (EL2), and a metal silicide film (SL). The metal silicide film (SL) may be provided between the first and second electrode films (EL1, EL2). The second electrode film (EL2) may be provided on a capacitor insulating film (CI), the metal silicide film (SL) may be provided on the second electrode film (EL2), and the first electrode film (EL1) may be provided on the metal silicide film (SL). The thickness of the metal silicide film (SL) may be smaller than the thickness of the first electrode film (EL1) and the thickness of the second electrode film (EL2).

[0021] The first electrode film (EL1) and the second electrode film (EL2) may include a metal nitride. The first and second electrode films (EL1, EL2) may include at least one of, for example, TiN, TiAlN, TiSiN, TaN, TaAlN, TaSiN, or WN. The metal silicide film (SL) may include, for example, at least one of TiSi2, TiSi, Ti5Si3, VSi2, CrSi2, FeSi2, CoSi2, NiSi, Ni2Si, Cu3Si, YSi1.7, ZrSi2, NbSi2, MoSi2, Pd2Si, HfSi2, TaSi2, WSi2, ReSi2, OsSi1.6, IrSi, IrSi3, PtSi, or Pt2Si.

[0022] The work function of the metal silicide film (SL) may be greater than the work function of the first electrode film (EL1) and the work function of the second electrode film (EL2). For example, when the first and second electrode films (EL1, EL2) contain TiN, the metal silicide film (SL) may contain one of CoSi2, NiSi, Ni2Si, Pd2Si, ReSi2, OsSi1.6, IrSi, IrSi3, PtSi, or Pt2Si, which has a work function greater than that of TiN. For another example, the work function of the first and second electrode films (EL1, EL2) may be equal to or less than 4.6 eV, and the work function of the metal silicide film (SL) may be greater than 4.6 eV.

[0023] A semiconductor device according to embodiments of the present disclosure may have the effect of reducing leakage current as the multilayer film (MU) of the upper electrode (UE) of the capacitor structure (130) includes a metal silicide film (SL) having a relatively large work function.

[0024] In a semiconductor device according to embodiments of the present disclosure, since the metal silicide film (SL) does not contain oxygen, oxygen-induced vacancies can be prevented from forming within the upper electrode (UE) and deteriorating the characteristics of the upper electrode (UE).

[0026] FIG. 2 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0027] Referring to FIG. 2, the semiconductor device may include a substrate (100a), an interlayer insulating film (110a), capacitor contact structures (120a), and a capacitor structure (130a). The capacitor structure (130a) may include lower electrodes (LEa), a supporter (SUa), a capacitor insulating film (CIa), and an upper electrode (UEa).

[0028] The upper electrode (UEa) may include a multilayer film (MUa) and a cover film (CVa). The multilayer film (MUa) of the upper electrode (UEa) may include a metal silicide film (SLa) and an electrode film (ELa). The metal silicide film (SLa) may be provided on a capacitor insulating film (CIa), and the electrode film (ELa) may be provided on the metal silicide film (SLa). The work function of the metal silicide film (SLa) may be greater than the work function of the electrode film (ELa).

[0030] FIG. 3 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0031] Referring to FIG. 3, the semiconductor device may include a substrate (100b), an interlayer insulating film (110b), capacitor contact structures (120b), and a capacitor structure (130b). The capacitor structure (130b) may include lower electrodes (LEb), a supporter (SUb), a capacitor insulating film (CIb), and an upper electrode (UEb).

[0032] The upper electrode (UEb) may include a multilayer film (MUb) and a cover film (CVb). The multilayer film (MUb) of the upper electrode (UEb) may include a first electrode film (EL1b), a second electrode film (EL2b), a first metal silicide film (SL1b), and a second metal silicide film (SL2b). The second electrode film (EL2b) may be provided on a capacitor insulating film (CIb), the second metal silicide film (SL2b) may be provided on the second electrode film (EL2b), the first metal silicide film (SL1b) may be provided on the second metal silicide film (SL2b), and the first electrode film (EL1b) may be provided on the first metal silicide film (SL1b). The first and second metal silicide films (SL1b, SL2b) may be provided between the first and second electrode films (EL1b, EL2b).

[0033] The work function of the first and second metal silicide films (SL1b, SL2b) may be greater than the work function of the first and second electrode films (EL1b, EL2b). The first and second metal silicide films (SL1b, SL2b) may contain different materials. The work function of the first metal silicide film (SL1b) may be different from the work function of the second metal silicide film (SL2b). For example, if the first metal silicide film (SL1b) contains IrSi, the second metal silicide film (SL2b) may contain PtSi, which has a different work function from IrSi.

[0035] FIG. 4 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0036] Referring to FIG. 4, the semiconductor device may include a substrate (100c), an interlayer insulating film (110c), capacitor contact structures (120c), and a capacitor structure (130c). The capacitor structure (130c) may include lower electrodes (LEc), a supporter (SUc), a capacitor insulating film (CIc), and an upper electrode (UEc).

[0037] The upper electrode (UEc) may include a multilayer film (MUc) and a cover film (CVc). The multilayer film (MUc) of the upper electrode (UEc) may include a first electrode film (EL1c), a second electrode film (EL2c), a first metal silicide film (SL1c), a second metal silicide film (SL2c), and a third metal silicide film (SL3c). The second electrode film (EL2c) may be provided on a capacitor insulating film (CIc), the third metal silicide film (SL3c) may be provided on the second electrode film (EL2c), the second metal silicide film (SL2c) may be provided on the third metal silicide film (SL3c), the first metal silicide film (SL1c) may be provided on the second metal silicide film (SL2c), and the first electrode film (EL1c) may be provided on the first metal silicide film (SL1c). The first to third metal silicide films (SL1c, SL2c, SL3c) may be provided between the first and second electrode films (EL1c, EL2c).

[0038] The work function of the first to third metal silicide films (SL1c, SL2c, SL3c) may be greater than the work function of the first and second electrode films (EL1c, EL2c). The first and second metal silicide films (SL1c, SL2c) may comprise different materials. The work function of the first metal silicide film (SL1c) may be different from the work function of the second metal silicide film (SL2c). The second and third metal silicide films (SL2c, SL3c) may comprise different materials. The work function of the second metal silicide film (SL2c) may be different from the work function of the third metal silicide film (SL3c).

[0039] In some embodiments, the first and third metal silicide films (SL1c, SL3c) may comprise the same material. The work function of the first metal silicide film (SL1c) may be the same as the work function of the third metal silicide film (SL3c).

[0040] In some embodiments, the first and third metal silicide films (SL1c, SL3c) may comprise different materials. The work function of the first metal silicide film (SL1c) may be different from the work function of the third metal silicide film (SL3c).

[0042] FIG. 5a is a plan view of a semiconductor device according to some embodiments of the present disclosure. FIG. 5b is a cross-sectional view along the line B-B' of FIG. 5a. FIG. 5c is a cross-sectional view along the line C-C' of FIG. 5a.

[0043] Referring to FIGS. 5a, 5b and 5c, the semiconductor device may include a substrate (100d).

[0044] The substrate (100d) may include active patterns (AP). The upper portions of the substrate (100d) protruding in a third direction (D3) may be defined as active patterns (AP). The active patterns (AP) may be spaced apart from each other.

[0045] A device isolation layer (STI) may be provided within the space provided between active patterns (AP). The active patterns (AP) may be defined by the device isolation layer (STI). Each active pattern (AP) may be surrounded by the device isolation layer (STI). The device isolation layer (STI) may include an insulating material. For example, the device isolation layer (STI) may include an oxide.

[0046] Gate structures (GT) extending in a second direction (D2) may be provided. Gate structures (GT) may be spaced apart from each other in a first direction (D1). Gate structures (GT) may be provided on a device isolation layer (STI) and active patterns (AP). Gate structures (GT) may be embedded gate structures embedded within the active patterns (AP) and the device isolation layer (STI). The active patterns (AP) may include impurity regions. A cell transistor comprising the impurity regions of the gate structures (GT) and the active patterns (AP) may be defined.

[0047] Each gate structure (GT) may include a gate insulating film (GI), a gate electrode (GE), and a gate capping film (GP). The gate insulating film (GI) may cover the surfaces of active patterns (AP) and the device isolation layer (STI). The gate electrode (GE) and the gate capping film (GP) may be provided within the gate insulating film (GI). The gate electrode (GE) may be separated from the active pattern (AP) by the gate insulating film (GI). The gate capping film (GP) may cover the upper surface of the gate electrode (GE). The gate insulating film (GI) and the gate capping film (GP) may include an insulating material. The gate electrode (GE) may include a conductive material.

[0048] Bitline structures (BT) extending in a first direction (D1) may be provided. Bitline structures (BT) may be spaced apart from each other in a second direction (D2). Bitline structures (BT) may be electrically connected to an active pattern (AP).

[0049] Each bitline structure (BT) may include a bitline (BL), a bitline capping film (BP), and bitline spacers (BS). The bitline (BL) may be connected to an active pattern (AP). The bitline (BL) may include a conductive material. The bitline capping film (BP) may be provided on the bitline (BL). The bitline capping film (BP) may include an insulating material. Bitline spacers (BS) may be provided on both sides of the bitline (BL) and the bitline capping film (BP). The bitline spacers (BS) may include an insulating material.

[0050] An interlayer insulating film (110d) covering a substrate (100d), gate structures (GT) and bitline structures (BT) may be provided. The interlayer insulating film (110d) may include first and second insulating patterns (111, 112), insulating fences (113), separation patterns (114), and an etch stop film (115).

[0051] Capacitor contact structures (120d) electrically connected to active patterns (AP) of the substrate (100d) may be provided. Each capacitor contact structure (120d) may include a buried contact (BC) and a landing pad (LP).

[0052] First and second insulating patterns (111, 112) may be provided on a substrate (100d). A second insulating pattern (112) may be provided on a first insulating pattern (111). The first and second insulating patterns (111, 112) may include different insulating materials.

[0053] Insulating fences (113) may be provided on the gate capping film (GP) of the gate structure (GT). Insulating fences (113) may be provided between adjacent bitline structures (BT). The insulating fences (113) may include an insulating material.

[0054] The berid contact (BC) can be connected to the active pattern (AP). The berid contact (BC) can be provided between adjacent insulating fences (113). The berid contact (BC) may include a conductive material.

[0055] A landing pad (LP) may be provided on a buried contact (BC). A landing pad (LP) may be provided between adjacent insulating fences (113). A landing pad (LP) may be electrically connected to an active pattern (AP) through the buried contact (BC). The landing pad (LP) may comprise a conductive material. In some embodiments, the landing pad (LP) may comprise a diffusion barrier film. In some embodiments, a metal silicide film may be provided between the landing pad (LP) and the buried contact (BC).

[0056] A separation pattern (114) may be provided on bitline structures (BT) and insulating fences (113). The separation pattern (114) may separate landing pads (LP) from each other. The separation pattern (114) may include an insulating material.

[0057] An etch stop layer (115) may be provided on a separation pattern (114). The etch stop layer (115) may include an insulating material.

[0058] A capacitor structure (130d) may be provided on an etch stop layer (115). The capacitor structure (130d) may include lower electrodes (LEd), a capacitor insulating layer (CId), supporters (SUd), and an upper electrode (UEd). The capacitor structure (130d) may be connected to a landing pad (LP). The capacitor structure (130d) may be electrically connected to an active pattern (AP) through the landing pad (LP) and a buried contact (BC).

[0059] The upper electrode (UEd) may include a multilayer film (MUd) on the capacitor insulating film (CId) and a cover film (CVd) on the multilayer film (MUd). The multilayer film (MUd) may include at least one electrode film and at least one metal silicide film. The metal silicide film may have a greater work function than the electrode film.

[0061] FIG. 6a is a perspective view of a semiconductor device according to some embodiments of the present disclosure. FIG. 6b is a cross-sectional view along the line D-D' of FIG. 6a. FIG. 6c is a cross-sectional view along the line E-E' of FIG. 6a.

[0062] Referring to FIGS. 6a, 6b and 6c, the semiconductor device may include a substrate (210), a plurality of first conductive lines (220), a channel film (230), a gate electrode (240), a gate insulating film (250), and a capacitor structure (280). The semiconductor device may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length of the channel film (230) extends along a vertical direction from the substrate (210).

[0063] A lower insulating film (212) may be disposed on a substrate (210), and a plurality of first conductive lines (220) may be spaced apart from each other in a first direction (D1) and extended in a second direction (D2) on the lower insulating film (212). A plurality of first insulating structures (222) may be disposed on the lower insulating film (212) to fill the space between the plurality of first conductive lines (220). The plurality of first insulating structures (222) may be extended in the second direction (D2), and the upper surface of the plurality of first insulating structures (222) may be disposed at the same level as the upper surface of the plurality of first conductive lines (220). The plurality of first conductive lines (220) may function as bit lines of a semiconductor device.

[0064] In some embodiments, a plurality of first conductive lines (220) may comprise doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, a plurality of first conductive lines (220) may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x..., or a combination thereof, but is not limited thereto. A plurality of first conductive lines (220) may comprise a single film or multiple films of the aforementioned materials. In some embodiments, a plurality of first conductive lines (220) may comprise a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may comprise graphene, carbon nanotubes, or a combination thereof.

[0065] The channel membrane (230) may be arranged in a matrix form spaced apart in a first direction (D1) and a second direction (D2) on a plurality of first conductive lines (220). The channel membrane (230) may have a first width according to the first direction (D1) and a first height according to the third direction (D3), and the first height may be greater than the first width. For example, the first height may be about 2 to 10 times the first width, but is not limited thereto. The bottom portion of the channel membrane (230) functions as a first source / drain region (not shown), the upper portion of the channel membrane (230) functions as a second source / drain region (not shown), and a portion of the channel membrane (230) between the first and second source / drain regions may function as a channel region (not shown).

[0066] In some embodiments, the channel film (230) may include an oxide semiconductor, for example, the oxide semiconductor is In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zrx Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga y It may include O or a combination thereof. The channel film (230) may include a single film or multiple films of the oxide semiconductor. In some embodiments, the channel film (230) may have a bandgap energy greater than the bandgap energy of silicon. For example, the channel film (230) may have a bandgap energy of about 1.5 eV to 5.6 eV. For example, the channel film (230) may have optimal channel performance when it has a bandgap energy of about 2.0 eV to 4.0 eV. For example, the channel film (230) may be polycrystalline or amorphous, but is not limited thereto. In some embodiments, the channel film (230) may include a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0067] The gate electrode (240) may extend in a first direction (D1) on both sidewalls of the channel film (230). The gate electrode (240) may include a first sub-gate electrode (240P1) facing the first sidewall of the channel film (230) and a second sub-gate electrode (240P2) facing the second sidewall opposite the first sidewall of the channel film (230). As one channel film (230) is disposed between the first sub-gate electrode (240P1) and the second sub-gate electrode (240P2), the semiconductor device may have a dual-gate transistor structure. However, the present disclosure is not limited thereto, and a single-gate transistor structure may be realized by omitting the second sub-gate electrode (240P2) and forming only the first sub-gate electrode (240P1) facing the first sidewall of the channel film (230).

[0068] The gate electrode (240) may comprise doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, the gate electrode (240) may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x It may be composed of , or a combination thereof, but is not limited to these.

[0069] The gate insulating film (250) surrounds the sidewalls of the channel film (230) and may be interposed between the channel film (230) and the gate electrode (240). For example, the entire sidewall of the channel film (230) may be surrounded by the gate insulating film (250), and a portion of the sidewall of the gate electrode (240) may be in contact with the gate insulating film (250). In some embodiments, the gate insulating film (250) extends in the direction of extension of the gate electrode (240), and only two sidewalls of the channel film (230) facing the gate electrode (240) may be in contact with the gate insulating film (250).

[0070] In some embodiments, the gate insulating film (250) may be made of a silicon oxide film, a silicon oxynitride film, a high dielectric film having a dielectric constant higher than that of a silicon oxide film, or a combination thereof. The high dielectric film may be made of a metal oxide or a metal oxynitride. For example, a high dielectric film that can be used as the gate insulating film (250) may be made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0071] A plurality of second insulating structures (232) may be extended along a second direction (D2) on a plurality of first insulating structures (222), and a channel membrane (230) may be disposed between two adjacent second insulating structures (232) among the plurality of second insulating structures (232). Additionally, between two adjacent second insulating structures (232), a first filling layer (234) and a second filling layer (236) may be disposed in the space between two adjacent channel membranes (230). The first filling layer (234) may be disposed at the bottom of the space between two adjacent channel membranes (230), and the second filling layer (236) may be formed on the first filling layer (234) to fill the remainder of the space between two adjacent channel membranes (230). The upper surface of the second buried layer (236) is positioned at the same level as the upper surface of the channel film (230), and the second buried layer (236) can cover the upper surface of the gate electrode (240). Alternatively, a plurality of second insulating structures (232) may be formed as a continuous material layer with a plurality of first insulating structures (222), or the second buried layer (236) may be formed as a continuous material layer with the first buried layer (234).

[0072] A capacitor contact structure (260) may be disposed on the channel film (230). The capacitor contact structure (260) may be arranged in a matrix form that is vertically overlapped with the channel film (230) and spaced apart in a first direction (D1) and a second direction (D2). The capacitor contact structure (260) may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x, or a combination thereof, but is not limited thereto. The upper insulating film (262) may surround the sidewall of the capacitor contact structure (260) on a plurality of second insulating structures (232) and a second embedded layer (236).

[0073] An etch stop layer (270) may be disposed on the upper insulating layer (262), and a capacitor structure (280) may be disposed on the etch stop layer (270). The capacitor structure (280) may include lower electrodes (282), a capacitor insulating layer (284), supporters (286), and an upper electrode (287). The upper electrode (287) may include a multilayer film (288) on the capacitor insulating layer (284) and a cover film (289) on the multilayer film (288). The multilayer film (288) may include at least one electrode film and at least one metal silicide film. The work function of the metal silicide film may be greater than the work function of the electrode film.

[0074] The lower electrode (282) can be electrically connected to the upper surface of the capacitor contact structure (260) by penetrating the etch stop layer (270). In some embodiments, the lower electrode (282) may be arranged in a matrix form that is positioned to overlap vertically with the capacitor contact structure (260) and spaced apart in a first direction (D1) and a second direction (D2).

[0075] Although embodiments according to the technical concept of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. The embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0076] 100: Substrate 130: Capacitor structure LE: Lower electrode SU: Supporter UE: Upper electrode CI: Capacitor insulation film MU: Multiple membranes CV: Cover

Claims

Claim 1 A semiconductor device comprising: a substrate; a capacitor contact structure electrically connected to the substrate; a lower electrode connected to the capacitor contact structure; a capacitor insulating film covering the lower electrode; and an upper electrode covering the capacitor insulating film, wherein the upper electrode comprises a multilayer film on the capacitor insulating film and a cover film on the multilayer film, wherein the multilayer film comprises a first electrode film, a second electrode film, and a first metal silicide film between the first and second electrode films, and wherein the work function of the first metal silicide film is greater than the work function of the first electrode film and the work function of the second electrode film. Claim 2 In claim 1, the first and second electrode films are semiconductor devices comprising metal nitrides. Claim 3 A semiconductor device according to claim 1, wherein the first metal silicide film comprises one of TiSi2, TiSi, Ti5Si3, VSi2, CrSi2, FeSi2, CoSi2, NiSi, Ni2Si, Cu3Si, YSi1.7, ZrSi2, NbSi2, MoSi2, Pd2Si, HfSi2, TaSi2, WSi2, ReSi2, OsSi1.6, IrSi, IrSi3, PtSi, or Pt2Si. Claim 4 In claim 1, the cover film is a semiconductor device comprising SiGe. Claim 5 A semiconductor device according to claim 1, wherein the multilayer further comprises a second metal silicide film between the first metal silicide film and the second electrode film, the work function of the second metal silicide film is different from the work function of the first metal silicide film, and the work function of the second metal silicide film is greater than the work function of the first electrode film and the work function of the second electrode film. Claim 6 A semiconductor device according to claim 5, wherein the multilayer further comprises a third metal silicide film between the second metal silicide film and the second electrode film, the work function of the third metal silicide film is different from the work function of the second metal silicide film, and the work function of the third metal silicide film is greater than the work function of the first electrode film and the work function of the second electrode film. Claim 7 In claim 6, the first and third metal silicide films are semiconductor devices comprising the same material. Claim 8 A semiconductor device comprising: a substrate including an active pattern; a gate structure on the active pattern; a bitline structure electrically connected to the active pattern; a capacitor contact structure electrically connected to the active pattern; a lower electrode connected to the capacitor contact structure; a capacitor insulating film covering the lower electrode; and an upper electrode covering the capacitor insulating film, wherein the upper electrode comprises a first electrode film and a first metal silicide film having a work function greater than that of the first electrode film, wherein the first electrode film comprises a metal nitride, and the upper electrode further comprises a second electrode film having a work function smaller than that of the first metal silicide film, and wherein the first metal silicide film is provided between the first and second electrode films. Claim 9 In claim 8, the first electrode film is provided on the first metal silicide film in a semiconductor device. Claim 10 delete

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