Semiconductor device

Abstract

A semiconductor device according to exemplary embodiments comprises a substrate having a cell array region and a peripheral region, a plurality of lower electrodes disposed on the cell array region, at least one support layer extending in a direction parallel to the upper surface of the substrate and in contact with the plurality of lower electrodes, a dielectric film covering the plurality of lower electrodes and the support layer, an upper electrode covering the dielectric film, an interlayer insulating layer covering the upper surface and side of the upper electrode, a peripheral contact plug penetrating the interlayer insulating layer on the peripheral region of the substrate, and a first oxide layer between the upper electrode and the peripheral contact plug, wherein the upper electrode includes at least one protruding region protruding laterally, the lateral direction is a horizontal direction from the cell array region toward the peripheral region, and the first oxide layer is disposed between at least one of the at least one protruding region and the peripheral contact plug.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0003] Driven by the advancement of the electronics industry and user demands, electronic devices are becoming smaller and higher-performing. Consequently, semiconductor devices used in these devices are also required to be highly integrated and high-performing. For example, in DRAM memory devices, technology is required to reduce the margin area between the cell array region and the peripheral circuit region.

[0004] delete Prior art literature

[65535] U.S. Patent No. 10,332,888 B2 (June 25, 2019) The problem to be solved

[0005] The problem that the technical concept of the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and high integration. means of solving the problem

[0007] A semiconductor device according to exemplary embodiments comprises a substrate having a cell array region and a peripheral region, a plurality of lower electrodes disposed on the cell array region, at least one support layer extending in a direction parallel to the upper surface of the substrate and in contact with the plurality of lower electrodes, a dielectric film covering the plurality of lower electrodes and the support layer, an upper electrode covering the dielectric film, an interlayer insulating layer covering the upper surface and side of the upper electrode, a peripheral contact plug penetrating the interlayer insulating layer on the peripheral region of the substrate, and a first oxide layer between the upper electrode and the peripheral contact plug, wherein the upper electrode includes at least one protruding region protruding in a lateral direction, the lateral direction is a horizontal direction from the cell array region toward the peripheral region, and the first oxide layer may be disposed between at least one of the at least one protruding region and the peripheral contact plug.

[0009] A semiconductor device according to exemplary embodiments may include a substrate having a cell array region and a peripheral region, a plurality of lower electrodes disposed on the cell array region, a dielectric film on the plurality of lower electrodes, and a capacitor structure including an upper electrode covering the dielectric film, an interlayer insulating layer covering the capacitor structure, an upper electrode contact plug penetrating the interlayer insulating layer and extending into the upper electrode and electrically connected to the upper electrode, and an upper oxide layer between a portion of the side of the upper electrode contact plug and the upper electrode.

[0011] A semiconductor device according to exemplary embodiments may include a substrate having a cell array region and a peripheral region, a plurality of word lines extending in a first direction on the substrate, a plurality of bit lines extending in a second direction intersecting the first direction on the substrate, cell landing pads and peripheral landing pads disposed at a higher level than the plurality of word lines and the plurality of bit lines, a plurality of lower electrodes on the cell landing pads on the cell array region, a dielectric film covering the plurality of lower electrodes, an upper electrode covering the dielectric film, an interlayer insulating layer covering the upper surface and side of the upper electrode, an upper electrode contact plug penetrating the interlayer insulating layer on the cell array region and penetrating a portion of the upper surface of the upper electrode to be electrically connected to the upper electrode, a peripheral contact plug penetrating the interlayer insulating layer on the peripheral region and contacting the peripheral landing pad, an upper oxide layer between a portion of the side of the upper electrode contact plug and the upper electrode, and a lower oxide layer between the upper electrode and the peripheral contact plug. Effects of the invention

[0013] According to embodiments of the present invention, a highly integrated semiconductor device can be provided while being electrically isolated from a surrounding contact plug by forming an oxide layer that contacts a portion of the upper electrode of a capacitor structure.

[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0016] FIG. 1 is a schematic plan view of a semiconductor device according to exemplary embodiments. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 2 illustrates cross-sections of the semiconductor device of FIG. 1 along the cutting lines I-I' and II-II'. FIGS. 3a and FIGS. 4a are partial enlarged cross-sectional views of a semiconductor device according to exemplary embodiments. FIG. 3a shows a partial enlarged view corresponding to region 'A' of FIG. 2, and FIG. 4a shows a partial enlarged view corresponding to region 'B' of FIG. 2. FIGS. 3b and FIGS. 4b are partial enlarged cross-sectional views of variations of semiconductor devices according to exemplary embodiments. FIG. 3b shows a partial enlarged view corresponding to region 'A' of FIG. 2, and FIG. 4b shows a partial enlarged view corresponding to region 'B' of FIG. 2. FIG. 5 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 7 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIGS. 9a to 9g are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0017] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0019] FIG. 1 is a schematic plan view of a semiconductor device (100) according to exemplary embodiments. FIG. 2 is a schematic cross-sectional view of a semiconductor device (100) according to exemplary embodiments. FIG. 2 shows cross-sections of the semiconductor device (100) of FIG. 1 along the cutting lines I-I' and II-II'.

[0020] FIG. 3a is a partial enlarged cross-sectional view of a semiconductor device (100) according to exemplary embodiments. FIG. 3a shows a partial enlarged view corresponding to region 'A' of FIG. 2.

[0021] FIG. 4a is a partial enlarged cross-sectional view of a semiconductor device (100) according to exemplary embodiments. FIG. 4a shows a partial enlarged view corresponding to region 'B' of FIG. 2.

[0023] Referring to FIGS. 1 and 2, a semiconductor device (100) may include a lower structure (LS), an etching stop layer (130) on the lower structure (LS), a plurality of lower electrodes (140), a dielectric film (150), a capacitor structure (CS) including an upper electrode (160), oxide layers (171, 174), an interlayer insulating layer (180), and contact plugs (191, 194).

[0025] The substructure (LS) may include a substrate (101) including active regions (102a), a device isolation region (103) defining the active regions (102a) within the substrate (101), a word line structure (WLS) embedded and extended within the substrate (101) and including a word line (WL), and a bit line structure (BLS) extending across the word line structure (WLS) on the substrate (101) and including a bit line (BL).

[0026] The semiconductor device (100) may include, for example, a cell array of Dynamic Random Access Memory (DRAM). For example, a bit line (BL) is connected to a first impurity region among the active regions (102a), and a capacitor structure (CS) is electrically connected to a second impurity region among the active regions (102a), and data may be stored in the capacitor structure (CS).

[0028] The substrate (101) may include a cell array region (CAR) and a peripheral region (PR). A capacitor structure (CS) on which data is stored may be placed on the cell array region (CAR). Thus, the cell array region (CAR) of the substrate (101) can be defined as an area of ​​the substrate (101) that overlaps with the capacitor structure (CS) on which data is stored. A peripheral region (PR) may be placed around the cell array region (CAR). A word line driver, a sense amplifier, row and column decoders, and control circuits may be placed on the peripheral circuit region.

[0029] The substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (101) may further include impurities. The substrate (101) may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0030] Active regions (102a) may be defined within the substrate (101) by a device isolation region (103). The active region (102a) may be in the form of a bar and may be arranged in an island shape extending in one direction, e.g., in the W direction, within the substrate (101). The active regions (102a) may have first and second impurity regions of a predetermined depth from the upper surface of the substrate (101). The first and second impurity regions may be spaced apart from each other. The first and second impurity regions may be provided as source / drain regions of a transistor formed by a word line (WL). In exemplary embodiments, the depths of the first and second impurity regions may differ from each other in the source region and the drain region. The active regions (102a) may be placed in a cell array region (CAR). In an exemplary embodiment, the semiconductor device (100) may further include dummy active regions (102b) placed in a peripheral region (PR). Dummy active regions (102b) can be defined within the substrate (101) by the device isolation region (103), just like the active regions (102a).

[0031] The device isolation region (103) may be formed by a shallow trench isolation (STI) process. The device isolation region (103) may surround active regions (102a) and electrically isolate them from one another. The device isolation region (103) may be made of an insulating material, for example, silicon oxide, silicon nitride, or a combination thereof. The device isolation region (103) may include a plurality of regions having different bottom depths depending on the width of the trench etched in the substrate (101). The device isolation region (103) may include a first device isolation layer defining active regions (102a) on a cell array region (CAR) and a second device isolation layer defining dummy active regions (102b) on a peripheral region (PR). A dummy gate structure may be placed on the dummy active regions (102b), but is not limited thereto. On the surrounding region (PR), the device isolation region (103) may include a plurality of layers. For example, as shown in FIG. 2, in a region adjacent to the word line (WL), the device isolation region (103) may include a first insulating liner (103-1), a second insulating liner (103-2), and a buried insulating layer (103-3). The first insulating liner (103-1), the second insulating liner (103-2), and the buried insulating layer (103-3) may be formed sequentially within an etched trench of the substrate (101) on which the device isolation region (103) is placed. In an exemplary embodiment, the first insulating liner (103-1) and the buried insulating layer (113) may include silicon oxide, and the second insulating liner (103-2) may include silicon nitride.

[0033] A word line structure (WLS) may include a word line (WL1), a gate dielectric layer (WL2), and a gate capping layer (WL3). The word line (WL1) may be arranged to extend in a first direction (X) across active regions (102a). For example, a pair of adjacent word lines (WL1) may be arranged to cross one active region (102a). The upper surface of the word line (WL1) may be located at a lower level than the upper surface of the substrate (101). As used herein, the high and low of the term “level” may be defined with respect to a substantially flat upper surface of the substrate (101). The word line (WL1) may constitute the gate of a buried channel array transistor (BCAT), but is not limited thereto. According to embodiments, the word line (WL1) may also have a form positioned on the upper surface of the substrate (101). The word line (WL1) may include at least one of a conductive material, for example, polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). According to embodiments, the word line (WL) may have a double-layer structure formed of different materials.

[0034] The gate dielectric layer (WL2) can conformally cover the side and bottom surfaces of the word line (WL1). The gate dielectric layer (WL2) may comprise at least one of silicon oxide, silicon nitride, and silicon oxynitride. The gate dielectric layer (WL2) may be, for example, a silicon oxide film or an insulating film having a high dielectric constant.

[0035] The gate capping layer (WL3) can be placed on top of the word line (W1). The gate capping layer (WL3) can be formed of an insulating material, for example, silicon nitride.

[0037] The bit line structure (BLS) may be extended in one direction, for example, in the Y direction, perpendicular to the word line (WL1). The bit line structure (BLS) may include bit lines (BL1, BL2) and a bit line capping pattern (BL3) on the bit lines (BL1, BL2).

[0038] Bit lines (BL1, BL2) may include a first conductive pattern (BL1) and a second conductive pattern (BL2) stacked in sequence. The first conductive pattern (BL1) may include a semiconductor material such as polycrystalline silicon. The first conductive pattern (BL1) may be in direct contact with the first impurity region. The second conductive pattern (BL2) may include a metallic material such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). According to embodiments, a separate conductive pattern may be disposed between the first and second conductive patterns (BL1, BL2), and said conductive pattern may be, for example, a layer formed by silicidetizing a portion of the first conductive pattern (BL1). However, according to embodiments, the number and thickness of the conductive patterns forming the bit line may vary.

[0039] A bit line capping pattern (BL3) may be placed on bit lines (BL1, BL2). The bit line capping pattern (BL3) may include an insulating material, for example, a silicon nitride film. According to embodiments, the bit line capping pattern (BL3) may include a plurality of capping pattern layers and may be made of different materials. That is, the number of capping patterns and / or the type of material forming the bit line capping pattern (BL3) may vary depending on the embodiments.

[0040] In an exemplary embodiment, a bit line structure (BLS) may be placed on a word line structure (WLS), and a buffer insulating layer (105) may be placed between the bit line structure (BLS) and the word line structure (WLS).

[0042] In an exemplary embodiment, the substructure (LS) may further include a bit line contact pattern (106) that penetrates the first conductive pattern (BL1) and contacts the first impurity region of the active regions (102a). The bit line contact pattern (106) may be electrically connected to the bit line structure (BLS). The lower surface of the bit line contact pattern (106) may be located at a higher level than the upper surface of the word line (WL1). According to embodiments, the bit line contact pattern (106) may be formed integrally with the first conductive pattern (BL1).

[0044] In an exemplary embodiment, the substructure (LS) may further include a lower electrode contact pattern (104), cell landing pads (LP), a dummy pattern (PW), and a peripheral landing pad (PL).

[0045] The lower electrode contact pattern (104) may be connected to one region of the active regions (102a), for example, the second impurity region. The lower electrode contact pattern (104) may be positioned between the bit lines (BL1, BL2) and between the word lines (WL1). The lower surface of the lower electrode contact pattern (104) may be located at a lower level than the upper surface of the substrate (101) and at a higher level than the lower surface of the bit line contact pattern (106). The lower electrode contact pattern (104) may be insulated from the bit line contact pattern (106) by a spacer structure. The lower electrode contact pattern (104) may be made of a conductive material and may include, for example, at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In an exemplary embodiment, the lower electrode contact pattern (104) may have a semiconductor layer (104-1) and a metal-semiconductor compound layer (104-2) disposed on the semiconductor layer (104-1). The metal-semiconductor compound layer (104-2) may be a layer formed by silicideizing a portion of the semiconductor layer (104-1) and may include, for example, cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. Depending on the embodiments, the metal-semiconductor compound layer (104-2) may be omitted.

[0046] The cell landing pad (LP), dummy pattern (PW), and peripheral landing pad (PL) may be conductive patterns placed on the bit line structure (BLS) and the lower electrode contact pattern (104). The cell landing pad (LP), dummy pattern (PW), and peripheral landing pad (PL) may be defined by the conductive layer being separated by an insulating pattern (109-1). The cell landing pad (LP) may be placed on the cell array region (CAR) and may be electrically connected to the lower electrode contact pattern (104). The dummy pattern (PW) may be placed on the dummy region at the edge of the cell array region (CAR). The peripheral landing pad (PL) may be electrically connected to the bit line structure (BLS) in the peripheral region (PR). However, depending on the embodiments, the peripheral landing pad (PL) may be electrically connected to the word line structure (WLS) or connected to other peripheral circuit elements. In an exemplary embodiment, the cell landing pad (LP), dummy pattern (PW), and peripheral landing pad (PL) may include a barrier layer and a conductive layer. The barrier layer may include at least one metal nitride, for example, titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), covering the bottom surface and sides of the conductive layer. The conductive layer may include at least one conductive material, for example, polycrystalline silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

[0047] In an exemplary embodiment, the semiconductor device (100) may include an insulating pattern (109-1) and an insulating liner (108) penetrating a cell landing pad (LP), a dummy pattern (PW), and a peripheral landing pad (PL). The cell landing pad (LP) may be separated into multiple parts by the insulating pattern (109-1). The insulating pattern (109-1) may include at least one of an insulating material, for example, silicon oxide, silicon nitride, and silicon oxynitride. The insulating liner (108) may cover peripheral transistors placed in a peripheral region (PR) and may separate the insulating pattern (109-1) from the peripheral transistors.

[0049] The etching stop layer (130) may be placed on the substructure (LS). The etching stop layer (130) may extend to the surrounding area (PR) while covering the substructure (LS) on the cell array area (CAR).

[0051] A capacitor structure (CS) can be placed on a cell array region (CAR) of a lower structure (LS). The capacitor structure (CS) may be composed of a plurality of lower electrodes (140), at least one support layer (145), a dielectric film (150), and an upper electrode (160).

[0052] A plurality of lower electrodes (140) may be made of a conductive material, for example, impurity-doped polysilicon or titanium nitride (TiN). The plurality of lower electrodes may have a pillar shape or a cylinder shape. Each of the plurality of lower electrodes (140) may penetrate the etching stop layer (130) and be electrically connected to the cell landing pad (LP).

[0053] Support layers (145) are spaced apart from each other in the z direction perpendicular to the upper surface of the lower structure (LS) and may extend in a horizontal direction perpendicular to the Z direction. Support layers (145) may contact a plurality of lower electrodes (140) and may connect the side walls of adjacent lower electrodes (140). Support layers (145) may be a structure that supports a plurality of lower electrodes (140) having a high aspect ratio. Support layers (145) may include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride. In an exemplary embodiment, support layers (145) may include a first support layer (145a) that is stacked in turn, a second support layer (145b) disposed on the first support layer (145a), and a third support layer (145c) disposed on the second support layer (145b). The first support layer (145a) may have a thinner thickness than the second support layer (145b), and the second support layer (145b) may have a thinner thickness than the third support layer (145c). The distance between the lower surface of the first support layer (145a) and the lower surface of the first support layer (145a) may be greater than the distance between the upper surface of the first support layer (145a) and the lower surface of the second support layer (145b). Additionally, the distance between the upper surface of the first support layer (145a) and the lower surface of the second support layer (145b) may be greater than the distance between the upper surface of the second support layer (145b) and the lower surface of the third support layer (145c). However, the number, thickness, and arrangement relationship of the support layers are not limited to this and may be varied.

[0054] A dielectric film (150) may cover a plurality of lower electrodes (140) and support layers (145) on a lower structure (LS). The dielectric film (150) may conformally cover the upper and side surfaces of the plurality of lower electrodes (140), the upper surface of the etch stop layer (130), and the exposed surfaces of the support layers. The dielectric film (150) may comprise a high dielectric material or silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, depending on the embodiments, the dielectric film (150) may be an oxide, nitride, silicide, oxynitride, or silicide-oxynitride comprising one of hafnium (Hf), aluminum (Al), zirconium (Zr), and lanthanum (La).

[0055] The upper electrode (160) may be a structure covering a plurality of lower electrodes (140), support layers (145), and dielectric film (150). The upper electrode (160) may be a structure filling the space between the plurality of lower electrodes (140) and the space between the support layers (145).

[0056] The upper electrode (160) may include a metal-containing film (161), a first material layer (162), and a second material layer (163) formed sequentially on a plurality of lower electrodes (140). The metal-containing film (161) may be a conductive layer that conformally covers the dielectric film (150). The metal-containing film (161) may be, for example, titanium nitride (TiN). The first material layer (162) may cover the metal-containing film (161) and fill the space between the plurality of lower electrodes (140) and the space between the support layers (145). The first material layer (162) may include a semiconductor material, for example, silicon germanium (SiGe) containing impurities. The second material layer (163) may conformally cover the upper surface and the side surface of the first material layer (162). The second material layer (163) may have a thickness thinner than that of the first material layer (162). The second material layer (163) may contain a material different from that of the first material layer (162). The second material layer (163) may contain a semiconductor material, for example, silicon (Si) containing impurities. As the first and second material layers (162, 163) contain doped semiconductor materials, they may form an upper electrode (160) together with a metal-containing film (161).

[0057] The upper electrode (160) may include at least one protruding region (PP) that protrudes horizontally from the cell array region (CAR) toward the surrounding region (PR). The protruding region (PP) may be positioned on the side of the upper electrode (160). The side of the upper electrode (160) may include a portion having a convex shape in the horizontal direction due to the protruding region (PP). The protruding region (PP) may be a structure formed by covering the support layers (145) that extend horizontally from a plurality of lower electrodes (140). Accordingly, the protruding region (PP) may include portions located at substantially the same level as the support layers (145).

[0058] In an exemplary embodiment, the second material layer (163) may include protruding regions (PP). The protruding regions (PP) of the second material layer (163) may include a first protrusion (163a), a second protrusion (163b), and a third protrusion (163c). The first protrusion (163a) may be a protrusion including a portion located at substantially the same level as the first support layer (145a), the second protrusion (163b) may be a protrusion including a portion located at substantially the same level as the second support layer (145b), and the third protrusion (163c) may be a protrusion including a portion located at substantially the same level as the third support layer (145c). The first to third protrusions (163a, 163b, 163c) may have different protruding distances depending on the thickness of the support layers (145a, 145b, 145c) corresponding to each protrusion (163a, 163b, 163c). In an exemplary embodiment, at least some of the first to third protrusions (163a, 163b, 163c) may protrude from the cell array region (CAR) and be disposed on the surrounding region (PR).

[0059] Referring to FIG. 3a, the second material layer (163) may be spaced apart in the z-direction from the lower structure (LS) including the substrate (101) and the etching stop layer (130).

[0060] The first material layer (162) may further include an extended region (162P) extending between the spaced-apart spaces. The second material layer (163) may overlap the extended region (162P) of the first material layer (162) in the Z direction. The second material layer (163) may cover the upper surface of the extended region (162P) while leaving the side of the extended region (162P) exposed without covering it. In an exemplary embodiment, the outer surface of the second material layer (163) may co-face with the exposed side of the extended region (162P), but is not limited thereto. Depending on the embodiments, an end may be formed between the outer surface of the second material layer (163) and the exposed side of the extended region (162P). This may be a structure that occurs as the etching selectivity differs as the first material layer (162) and the second material layer (163) contain different materials.

[0062] The interlayer insulating layer (180) may cover the capacitor structure (CS) and the etch stop layer (130) on the lower structure (LS). The interlayer insulating layer (180) may cover the upper surface and the side surface of the upper electrode (160). The interlayer insulating layer (180) may comprise silicon oxide. According to embodiments, the interlayer insulating layer (180) may be formed of a PE (plasma Enhanced)-TEOS (Tetra Ethyl Ortho Silcate) film, PSG (Phosphorous Silicate Glass), or HDP (High Density Plasma) oxide.

[0064] The contact plugs (191, 194) may include an upper electrode contact plug (191) electrically connected to an upper electrode (160) and a peripheral contact plug (194) electrically connected to a lower structure (LS).

[0065] The upper electrode contact plug (191) can be electrically connected to the upper electrode (160) by penetrating a portion of the interlayer insulating layer (180) and the upper electrode (160) on the cell array region (CAR). In an exemplary embodiment, the upper electrode contact plug (191) can be connected to the upper electrode (160) by penetrating the second material layer (163) and extending into the first material layer (162). However, depending on the embodiments, the upper electrode contact plug (191) may penetrate only a portion of the second material layer (163) and not come into contact with the first material layer (162).

[0066] The peripheral contact plug (194) can be electrically connected to the lower structure (LS) by penetrating the interlayer insulating layer (180) and the etch stop layer (130) on the peripheral region (PR). In an exemplary embodiment, the peripheral contact plug (194) can be electrically connected to the bit line structure (BLS) by contacting the peripheral landing pad (PL), but is not limited thereto. The peripheral contact plug (194) may include a conductive material identical or similar to that of the upper electrode contact plug (191).

[0068] The oxide layers (171, 174) may include an upper oxide layer (171) between the upper electrode (160) and the upper electrode contact plug (191), and a lower oxide layer (174) between the upper electrode (160) and the peripheral contact plug (194). In this specification, the lower oxide layer (174) may be referred to as the 'first oxide layer', and the upper oxide layer (171) may be referred to as the 'second oxide layer'.

[0069] Referring to FIG. 2 and FIG. 4a, the upper oxide layer (171) may surround at least a portion of the outer surface of the upper electrode contact plug (191). At least a portion of the side of the upper electrode contact plug (191) may be in contact with the upper oxide layer (171), and the lower surface of the upper electrode contact plug (191) may be in contact with the upper electrode (160). In an exemplary embodiment, the upper oxide layer (171) may include a lower oxide region (171-1) between the first material layer (162) and the upper electrode contact plug (191), and an upper oxide region (171-2) between the second material layer (163) and the upper electrode contact plug (191). The lower oxide region (171-1) may be an area where at least a portion of the first material layer (162) is oxidized through a contact hole to form the upper electrode contact plug (191). The upper oxide region (171-2) may be a region in which at least a portion of the second material layer (163) is oxidized through the contact hole. The lower oxide region (171-1) and the upper oxide region (171-2) may contain different materials. In an exemplary embodiment, the lower oxide region (171-1) may contain silicon germanium oxide, and the upper oxide region (171-2) may contain silicon oxide.

[0070] Referring to FIG. 2, the lower oxide layer (174) may be disposed between at least one of the protruding regions (PP) and the surrounding contact plug (194). In an exemplary embodiment, the lower oxide layer (174) may include a lower oxide layer (174b) disposed between the second protrusion (163b) of the second material layer (163) and the surrounding contact plug (194), and a lower oxide layer (174a) disposed between the third protrusion (163c) of the second material layer (163) and the surrounding contact plug (194). One side of the lower oxide layer (174) may be in contact with the second material layer (163), and the other side of the lower oxide layer (174) may be in contact with the surrounding contact plug (194). The lower oxide layer (174) may be an area in which at least a portion of the second material layer (163) is oxidized through a contact hole to form the surrounding contact plug (194). In an exemplary embodiment, the lower oxide layer (174) may comprise silicon oxide. The lower oxide layer (174) can electrically isolate the upper electrode (160) and the surrounding contact plug (194). The lower oxide layer (174) can reduce the margin area required between the upper electrode (160) and the surrounding contact plug (194) due to the structure of the upper electrode (160) including protruding regions (PP). The lower oxide layer (174) can electrically isolate the upper electrode (160) and the surrounding contact plug (194) even if the relative distance between the upper electrode (160) and the surrounding contact plug (194) is shortened. Accordingly, a semiconductor device (100) with high integration density can be provided while having improved electrical characteristics. The oxide of the second material layer (163) may have a relatively higher insulating property than the oxide of the first material layer (162). Accordingly, the lower oxide layer (174), which is the oxide of the second material layer (163), can efficiently improve the problem of current leakage between the upper electrode (160) and the surrounding contact plug (194).

[0072] FIG. 3b is a partial enlarged cross-sectional view of a modified example of a semiconductor device according to exemplary embodiments. FIG. 3b shows a partial enlarged view corresponding to region 'A' of FIG. 2.

[0073] Referring to FIG. 3b, the upper electrode (160) of the semiconductor device (100a) may have a structure in which the lower region of the upper electrode (160) is recessed to a certain depth in a direction toward the interior of the upper electrode (160). In an exemplary embodiment, the lower region of the second material layer (163) and the extended region (162P) of the first material layer (162) may be recessed into the interior of the upper electrode (160) to have a recessed region. The second material layer (163) may have a step due to the recessed region. This may be a structure formed by performing an etching process relatively deeper than in FIG. 3a to electrically isolate the first and second material layers (162, 163) from the surrounding contact plug (194). The interlayer insulating layer (180) may include a protrusion (180P) that extends into the recessed region of a portion of the first material layer (162) and the second material layer (163). However, according to the embodiments, conversely, as the etching process is performed relatively thinner compared to FIG. 3a during the process of forming the first and second material layers (162, 163), the lower region of the second material layer (163) and the extended region (162P) of the first material layer (162) may include a protrusion in a direction toward the interlayer insulating layer (180).

[0075] FIG. 4b is a partial enlarged cross-sectional view of a modified example of a semiconductor device according to exemplary embodiments. FIG. 4b shows a partial enlarged view corresponding to region 'B' of FIG. 2.

[0076] Referring to FIG. 4b, a semiconductor device (100b) according to exemplary embodiments may have an upper contact plug (191) structure different from that of the semiconductor device (100) of FIG. 2. The upper electrode contact plug (191) may be further extended in a direction toward the lower structure (LS) from the region in contact with the upper oxide layer (171). Accordingly, a portion of the lower region of the side of the upper electrode contact plug (191) may not be in contact with the upper oxide layer (171). This may be a structure formed by forming the upper oxide layer (171) through a contact hole for forming the upper electrode contact plug (191), and then forming a hole deeper than the contact hole through a subsequent process.

[0078] FIG. 5 is a schematic cross-sectional view of a semiconductor device (100c) according to exemplary embodiments. FIG. 5 illustrates regions corresponding to the cross-sections along the cutting lines I-I' and II-II' of FIG. 1.

[0079] Referring to FIG. 5, the lower oxide layer (174) may have a portion extending into the interior of the peripheral contact plug (194) along the side of the upper electrode contact plug (191). The peripheral contact plug (194) may include a recess (194CP), which is a recessed portion into the interior of the peripheral contact plug (194), in at least a portion of the area in contact with the lower oxide layer (174). The recess (194CP) may be a layer formed by proceeding an oxidation process without etching a portion of the second material layer (163) during the process of forming a contact hole to form the peripheral contact plug (194).

[0081] FIG. 6 is a schematic cross-sectional view of a semiconductor device (100d) according to exemplary embodiments. FIG. 6 illustrates regions corresponding to the cross-sections along the cutting lines I-I' and II-II' of FIG. 1.

[0082] Referring to FIG. 6, the upper electrode (160) of the semiconductor device (100d) according to exemplary embodiments may not include a second material layer (163) as in FIG. 2. That is, the upper electrode (160) may be composed of a metal-containing film (161) and a first material layer (162).

[0083] The first material layer (162) may include at least one protruding region (PP) that protrudes horizontally from the cell array region (CAR) toward the surrounding region (PR). The protruding region (PP) may be disposed on the side of the first material layer (162). The side of the first material layer (162) may include a portion having a convex shape in the horizontal direction due to the protruding region (PP). The protruding region (PP) may include portions located at substantially the same level as the support layers (145). The distance of each protruding region (PP) may differ depending on the thickness, etc., of the support layer (145) corresponding to each protruding region (PP).

[0084] A lower oxide layer (174) may be disposed between at least one of the protruding regions (PP) of the first material layer (162) and the surrounding contact plug (194). One side of the lower oxide layer (174) may be in contact with the first material layer (162), and the other side of the lower oxide layer (174) may be in contact with the surrounding contact plug (194). The lower oxide layer (174) may electrically isolate the first material layer (162) and the surrounding contact plug (194). Unlike FIG. 2, a semiconductor device (100d) with a high production yield may be provided by omitting the step of forming the second material layer (163) during the manufacturing process of the upper electrode (160).

[0086] FIG. 7 is a schematic cross-sectional view of a semiconductor device (100e) according to exemplary embodiments. FIG. 7 illustrates regions corresponding to the cross-sections along the cutting lines I-I' and II-II' of FIG. 1.

[0087] Referring to FIG. 7, the peripheral contact plug (194) and the lower oxide layer (174) may be spaced apart from each other. An interlayer insulating layer (180) may be disposed between the peripheral contact plug (194) and the lower oxide layer (174). Although the second material layer (163) of the upper electrode (160) may not be exposed by the contact hole for forming the peripheral contact plug (194), the lower oxide layer (174) may be formed by oxidizing a portion of the second material layer (163) through a separate oxidation process. Accordingly, the lower oxide layer (174) may be spaced apart from the peripheral contact plug (194) and in contact with at least a portion of the protruding regions (PP) of the second material layer (163).

[0089] FIG. 8 is a schematic cross-sectional view of a semiconductor device (100f) according to exemplary embodiments. FIG. 8 illustrates regions corresponding to the cross-sections along the cutting lines I-I' and II-II' of FIG. 1.

[0090] Referring to FIG. 8, the peripheral contact plug (194) may include a second plug layer (194a) and a second spacer layer (194b) surrounding the sidewall of the second plug layer (194a). The second spacer layer (194b) may be a structure for electrical isolation between the upper electrode (160) and the second plug layer (194a). A semiconductor device (100f) with improved electrical characteristics may be provided through the peripheral contact plug (194) including the second spacer layer (194b). The second spacer layer (194b) may include an insulating material, for example, silicon oxide. The second spacer layer (194b) may be in contact with the peripheral contact plug (194) and the lower oxide layer (174).

[0091] Similarly, the upper electrode contact plug (191) may include a first plug layer (191a) and a first spacer layer (191b) surrounding the side wall of the first plug layer (191a).

[0093] FIGS. 9a through 9g are cross-sectional views for illustrating a method of manufacturing a semiconductor device (100) according to exemplary embodiments. FIGS. 9a through 9g illustrate cross-sections of the semiconductor device of FIG. 1 along the cutting lines I-I' and II-II'.

[0095] Referring to FIG. 9a, a lower structure (LS) is formed, and mold layers (118) and pre-support layers (145') are alternately stacked on the lower structure (LS), and a plurality of lower electrodes (140) that penetrate the mold layers (118) and pre-support layers (145') can be formed.

[0096] First, active regions (102a) and a device isolation region (103) defining the active regions (102a) can be formed on a substrate (101) including a cell array region (CAR) and a peripheral region (PR). In an exemplary embodiment, the cell array region (CAR) may be a memory cell array region of a memory device such as a DRAM, and the peripheral region (PR) may be a region including peripheral circuits around the memory cell array region. A portion of the substrate (101) may be removed to form trenches extending in a first direction and a word line structure (WLS) may be formed within the trenches. Next, impurity regions may be formed on both sides of the word line structure (WLS), and a buffer insulating layer (105) and a bit line structure (BLS) extending in a second direction intersecting the first direction may be formed on the word line structure (WLS). A lower electrode contact pattern (104) can be formed by filling a lower electrode contact hole that penetrates at least a portion of the bit line structure (BLS) in the cell array region (CAR) with a conductive material. An opening can be formed that penetrates a portion of the bit line structure (BLS) and exposes a portion of the bit line structure (BLS), and an insulating pattern (109-1) that separates the opening and the bit line structure (BLS) with a conductive material can be formed to form a cell landing pad (LP) on the cell array region (CAR), a peripheral landing pad (PL) on the peripheral region (PR), and vias connected to the cell landing pad (LP) or the peripheral landing pad (PL). Accordingly, a lower structure (LS) including a substrate (101), a bit line structure (BLS), and a word line structure (WLS) can be formed.

[0097] Next, an etch stop layer (130) may be conformally formed on the substructure (LS), and mold layers (118) and pre-support layers (145') may be alternately stacked on the etch stop layer (130). The etch stop layer (130) may include at least one insulating material having etch selectivity under specific etching conditions, such as silicon nitride (SiN) or silicon carbonitride (SiCN), with respect to the mold layers (118). In an exemplary embodiment, the mold layers (118) and the pre-support layers (145') may each consist of three layers. The pre-support layers (145') may include a first pre-support layer (145a'), a second pre-support layer (145b'), and a third pre-support layer (145c') that are stacked in sequence. The first pre-support layer (145a') may have a thickness smaller than the second pre-support layer (145b'), and the second pre-support layer (145b') may have a thickness smaller than the third pre-support layer (145c'). The mold layers (118) may include first to third mold layers (118a, 118b, 118c) stacked in sequence. The first mold layer (118a) may have a thickness larger than the second mold layer (118b), and the second mold layer (118b) may have a thickness larger than the third mold layer (118c). The mold layers (118) and the pre-support layers (145') may be materials having etch selectivity under specific etching conditions. For example, the mold layers (118) may include silicon oxide, and the pre-support layers (145') may include silicon nitride. However, depending on the embodiments, the mold layers (118) may include different materials, and for example, the third mold layer (118c) may include a nitride-based material unlike the first and second mold layers (118a, 118b).

[0098] Next, a plurality of holes can be formed penetrating the mold layers (118) and the pre-support layers (145') on the cell array region (CAR), and a plurality of lower electrodes (140) can be formed by filling the plurality of holes with a conductive material. The plurality of holes can penetrate the etch stop layer (130) to expose the cell landing pad (LP). A plurality of lower electrodes (140) can be formed by filling the plurality of holes with a conductive material and performing a chemical mechanical polishing (CMP) process.

[0099] Next, a first mask (M1) can be formed on the uppermost pre-support layer (145') in the cell array region (CAR). The first mask (M1) may be a structure comprising a plurality of hole-shaped openings that expose at least a portion of the plurality of lower electrodes (140).

[0101] Referring to FIG. 9b, at least a portion of the mold layers (118) and preliminary support layers (145') can be removed using the first mask (M1) as an etching mask to form support layers (145), and the remaining mold layers (118) can be removed.

[0102] The first mask (M1) may be a mask for forming support layers (145). Support layers (145) can be formed by using the first mask (M1) as an etching mask to perform an etching process on portions of mold layers (118) and preliminary support layers (145') that do not overlap with the first mask (M1) in the Z direction. Each of the support layers (145) may have a shape having a plurality of openings by being patterned according to the structure of the first mask (M1). During the etching process, at least a portion of the upper surface of the plurality of lower electrodes (140) may be etched together. The support layers (145) may connect adjacent lower electrodes (140). The remaining mold layers (118) may be selectively removed with respect to the support layers (145). In an exemplary embodiment, the third pre-support layer (145c') can be etched by an anisotropic etching process to form the third support layer (145c), and the third mold layer (118c) can be removed by an isotropic etching process before etching the second pre-support layer (145b'). Similarly, the second pre-support layer (145b') can be etched by an anisotropic etching process to form the second support layer (145b), and then the second mold layer (118b) can be removed by an isotropic etching process, and the first pre-support layer (145a') can be etched by an anisotropic etching process to form the first support layer (145a), and then the first mold layer (118a) can be removed by an isotropic etching process. The first mask (M1) can be removed after etching the mold layers (118) or while etching the mold layers (118).

[0104] Referring to FIG. 9c, a dielectric film (150), a metal-containing film (161), a first material layer (162'), and a second material layer (163') covering a plurality of lower electrodes (140) and support layers (145) connected thereto may be formed in sequence.

[0105] A dielectric film (150) may be formed to conformally cover the exposed sides of a plurality of lower electrodes (140) and the surfaces of support layers (145) together with an etch stop layer (130). The dielectric film (150) may comprise a high-k dielectric, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. A metal-containing film (161) may be a metal layer that conformally covers the dielectric film (150). The metal-containing film (161) may comprise, for example, titanium nitride (TiN). A first material layer (162') may cover a plurality of lower electrodes (140) and support layers (145) while filling the spaces between the plurality of lower electrodes (140) on the dielectric film (150). A first material layer (162') may cover the etch stop layer (130) while extending from the cell array region (CAR) to the surrounding region (PR). The first material layer (162') may include a semiconductor material, for example, Doppt silicon germanium. The second material layer (163') may extend from the cell array region (CAR) to the surrounding region (PR) while covering the top and side surfaces of the first material layer (162').

[0106] The first material layer (163') and the second material layer (163') may include regions protruding from the support layers (145) as they are formed to cover the support layers (145) extending from the plurality of lower electrodes (140). In an exemplary embodiment, the second material layer (163') may include at least one protruding region (PP) that protrudes horizontally from the cell array region (CAR) toward the peripheral region (PR). The protruding region (PP) may be disposed on the outer surface of the second material layer (163').

[0107] In an exemplary embodiment, the protruding regions (PP) may include a first protruding region (163a) having a portion located at substantially the same level as the first support layer (145a), a second protruding region (163b) having a portion located at substantially the same level as the second support layer (145b), and a third protruding region (163c) having a portion located at substantially the same level as the third support layer (145c). The size and protruding distance of the first to third protrusions (163a, 163b, 163c) may vary depending on the thickness of the support layers (145), etc.

[0109] Referring to FIG. 9d, a second mask (M2) covering a portion of the second material layer (163') can be formed, and a portion of the second material layer (163') and the first material layer (162') can be removed to form a capacitor structure (CS).

[0110] A second mask (M2) can be formed to cover the upper surface and the side surface including the protruding regions (PP) of the second material layer (163') covering a plurality of lower electrodes (140) on the cell array region (CAR). The second mask (M2) may be an etching mask for separating the capacitor structure (CS) and the structures on the surrounding region (PR). By using the second mask (M2) as an etching mask, a portion of the second material layer (163') and a portion of the first material layer (162') on the surrounding region (PR) can be removed. Accordingly, the etching stop layer (130) on the surrounding region (PR) may be exposed.

[0111] Next, as an additional etching process is performed using the second mask (M2), the respective sides of the first material layer (162) and the second material layer (163) may be recessed in the direction in which the plurality of lower electrodes (140) are arranged, without forming a co-plane with the side of the second etching mask (M2). In an exemplary embodiment, the recessed depth may be substantially equal to the thickness of the second mask (M2), so that the side of the second material layer (163) in contact with the second mask (M2) and the side of the second material layer (163) not in contact with the second mask (M2) may form a co-plane. However, depending on the embodiments, the recessed depth may be adjusted according to the additional etching process.

[0113] Referring to FIG. 9e, the second mask (M2) can be removed to form an interlayer insulating layer (180) covering the etching stop layer (130) of the capacitor structure (CS) and the surrounding region (PR). The interlayer insulating layer (180) may include an insulating material, for example, silicon oxide.

[0115] Referring to FIG. 9f, a first opening (OP1) penetrating at least a portion of the upper electrode (160) and a second opening (OP2) penetrating at least a portion of the etching stop layer (130) of the surrounding region (PR) can be formed.

[0116] The first opening (OP1) may penetrate at least a portion of the interlayer insulating layer (180) and the upper electrode (160) on the cell array region (CAR) to expose at least a portion of the first material layer (162). However, according to embodiments, the first opening (OP1) may penetrate only at least a portion of the second material layer (163) and may not extend into the first material layer (162). The first opening (OP1) may be an area where an upper electrode contact plug (191, see FIG. 2) is formed through a subsequent process.

[0117] The second opening (OP2) may penetrate at least a portion of the interlayer insulating layer (180) and the etch stop layer (130) on the surrounding area (PR). In an exemplary embodiment, the second and third protrusions (163b, 163c) of the second material layer (163) may be partially exposed by the second opening (OP2). The second and third protrusions (163b, 163c) may be partially etched during the process of forming the second opening (OP2). The second opening (OP2) may not completely penetrate the etch stop layer (130). This may be to prevent the surrounding landing pad (PL) from being oxidized in a subsequent process.

[0118] In this step, as parts of the second and third protrusions (163b, 163c) remain unetched, the semiconductor device (100c) of FIG. 5 can be formed.

[0120] Referring to FIG. 9g, at least a portion of the upper electrode (160) exposed through the first opening (OP1) and the second opening (OP2) can be oxidized to form oxide layers (171, 174).

[0121] In an exemplary embodiment, when the first opening (OP1) penetrates the second material layer (163) and extends into the first material layer (162), at least a portion of the first and second material layers (162, 163) exposed through the inner wall and bottom surface of the first opening (OP1) may be replaced with a first oxide layer (171) through an oxidation process. Next, the bottom surface of the first opening (OP1) may be further etched to expose the second material layer (163). Accordingly, the first oxide layer (171) may surround the inner wall of the first opening (OP1) and come into contact with the upper electrode (160).

[0122] At least a portion of the second and third protrusions (163b, 163c) of the second material layer (163) exposed through the second opening (OP2) may be replaced with a second oxide layer (174) through the oxidation process. Accordingly, the second oxide layer (174) may be positioned between the protruding regions (PP) of the second material layer and the second opening (OP2). The thickness of the second oxide layer (174) may be adjusted according to the conditions of the oxidation process. According to embodiments, the second oxide layer (174) may extend further inward as well as into the second and third protrusions (163b, 163c).

[0124] Next, referring to FIG. 2, the bottom surface of the second opening (OP2) can be further etched to expose the peripheral landing pad (PL). Next, a conductive material can be filled into the first opening (OP1) to form an upper electrode contact plug (191), and a conductive material can be filled into the second opening (OP2) to form a peripheral contact plug (194). The peripheral contact plug (194) can be electrically separated from the upper electrode (160) by the second oxide layer (174). Accordingly, a semiconductor device (100) with improved electrical characteristics can be provided while minimizing the margin area between the upper electrode (160) and the peripheral contact plug (194) caused by the protruding regions (PP) of the upper electrode (160).

[0126] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, changes, and combinations of embodiments may be made by those skilled in the art without departing from the technical spirit of the invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0128] CAR: Cell array area PR: Peripheral area PL: Peripheral landing pad LS: Substructure CS: Capacitor structure PP: Protruding areas 130: Etching stop layer 140: Multiple lower electrodes 150: Dielectric film 160: Top electrode 161: Metal-containing film 162: First material layer 163: Second material layer 171: Upper oxide layer 174: Lower oxide layer 191: Upper electrode contact plug 194: Peripheral contact plug

Claims

Claim 1 A semiconductor device comprising: a substrate having a cell array region and a peripheral region; a plurality of lower electrodes disposed on the cell array region; at least one support layer extending in a direction parallel to the upper surface of the substrate and in contact with the plurality of lower electrodes; a dielectric film covering the plurality of lower electrodes and the support layers; an upper electrode covering the dielectric film; an interlayer insulating layer covering the upper surface and side of the upper electrode; a peripheral contact plug penetrating the interlayer insulating layer on the peripheral region of the substrate; and a first oxide layer between the upper electrode and the peripheral contact plug, wherein the upper electrode includes at least one protruding region protruding in a lateral direction, the lateral direction is a horizontal direction from the cell array region toward the peripheral region, and the first oxide layer disposed between at least one of the at least one protruding region and the peripheral contact plug. Claim 2 A semiconductor device according to claim 1, wherein the upper electrode comprises a first material layer and a second material layer covering the first material layer and having a material different from the material of the first material layer. Claim 3 A semiconductor device according to claim 2, wherein the first material layer comprises Doppt silicon germanium (SiGe) and the second material layer comprises Doppt silicon (Si). Claim 4 A semiconductor device according to claim 2, wherein the first material layer covers the upper surfaces and sides of the plurality of lower electrodes, and the second material layer covers the upper surface of the first material layer and covers at least a portion of the sides of the first material layer. Claim 5 A semiconductor device according to claim 1, further comprising: an upper electrode contact plug that penetrates a portion of the upper electrode and is electrically connected to the upper electrode; and a second oxide layer between a portion of the side of the upper electrode contact plug and the upper electrode, wherein the lower surface of the upper electrode contact plug is in contact with the upper electrode. Claim 6 A semiconductor device according to claim 5, wherein the upper electrode comprises a first material layer and a second material layer covering the first material layer and having a material different from that of the first material layer, the upper electrode contact plug extends into the first material layer by penetrating the second material layer, and the second oxide layer comprises a lower oxide region between the side of the upper electrode contact plug and the first material layer and an upper oxide region between the side of the upper electrode contact plug and the second material layer, and the lower and upper oxide regions comprise different materials. Claim 7 A semiconductor device comprising: a substrate having a cell array region and a peripheral region; a capacitor structure including a plurality of lower electrodes disposed on the cell array region, a dielectric film on the plurality of lower electrodes, and an upper electrode covering the dielectric film; an interlayer insulating layer covering the capacitor structure; an upper electrode contact plug penetrating the interlayer insulating layer and extending into the upper electrode to be electrically connected to the upper electrode; and an upper oxide layer between a portion of the side of the upper electrode contact plug and the upper electrode. Claim 8 In claim 7, the interlayer insulating layer covers the upper surface of the upper oxide layer in a semiconductor device. Claim 9 A semiconductor device according to claim 7, wherein the lower surface of the upper electrode contact plug is positioned at a lower level than the upper oxide layer. Claim 10 A semiconductor device according to claim 7, further comprising: a peripheral contact plug disposed on the peripheral region and penetrating the interlayer insulating layer; and a lower oxide layer between the peripheral contact plug and the upper electrode.

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