Semiconductor device

Abstract

A semiconductor device according to an embodiment of the present invention may include: a substrate; storage node contacts on the substrate; lower electrode structures disposed on the storage node contacts; a supporter structure provided on at least a portion of the outer surface of the lower electrode structures and connecting lower electrode structures adjacent to each other among the lower electrode structures; a dielectric layer disposed on the lower electrode structures and the supporter structure; and an upper electrode structure disposed on the dielectric layer. Each of the lower electrode structures may include a pillar portion in contact with each of the storage node contacts; and a cylinder portion disposed on the pillar portion. The pillar portion may include a first lower electrode layer having a cylinder shape having a bottom surface and a side surface; and a first portion covering at least the inner wall of the first lower electrode layer. The cylinder portion may include a second portion extending from the first portion and covering the top of the first lower electrode layer.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0003] delete

[0004] (Patent Document 1) JP Published Patent Application No. JP 2011-061067 A (Date of publication: March 24, 2011) The problem to be solved

[0005] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and high integration. means of solving the problem

[0007] A semiconductor device according to exemplary embodiments may include: a substrate; storage node contacts on the substrate; lower electrode structures disposed on the storage node contacts; a support structure provided on at least a portion of the outer surface of the lower electrode structures and connecting adjacent lower electrode structures among the lower electrode structures; a dielectric layer disposed on the lower electrode structures and the support structure; and an upper electrode structure disposed on the dielectric layer. Each of the lower electrode structures may include a pillar portion in contact with each of the storage node contacts; and a cylinder portion disposed on the pillar portion. The pillar portion may include a first lower electrode layer having a cylinder shape having a bottom surface and a side surface; and a first portion covering at least the inner wall of the first lower electrode layer. The cylinder portion may include a second portion extending from the first portion and covering the top of the first lower electrode layer.

[0008] A semiconductor device according to exemplary embodiments may include: a lower electrode structure comprising a pillar portion and a cylinder portion disposed on the pillar portion and extending from the pillar portion; a dielectric layer disposed on the lower electrode structure; and an upper electrode structure disposed on the dielectric layer. The pillar portion may include a first lower electrode layer and a second lower electrode layer disposed on the first lower electrode layer.

[0009] A semiconductor device according to exemplary embodiments may include a substrate; a plurality of storage node contacts on the substrate; and capacitors disposed on each of the storage node contacts. Each of the capacitors may include lower electrode structures comprising a pillar portion and a cylinder portion disposed on the pillar portion; a dielectric layer disposed on the lower electrode structures; and an upper electrode structure disposed on the dielectric layer. The pillar portion may include a first lower electrode layer and a second lower electrode layer disposed on the first lower electrode layer. Effects of the invention

[0011] By depositing a conductive material for the lower electrode structure of a capacitor twice, the lengths of the lower pillar stack and the upper single cylinder stack can be made constant for each capacitor. This makes it possible to provide a semiconductor device with constant capacitance for each capacitor.

[0012] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0014] FIG. 1 is a schematic layout diagram of a semiconductor device according to exemplary embodiments. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 4 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 5 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIGS. 6a to 6n are schematic cross-sectional views illustrating the manufacturing process of a semiconductor device according to exemplary embodiments. FIG. 7 is a schematic layout diagram of a semiconductor device according to exemplary embodiments. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0015] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0016] In the following, terms such as "upper," "middle," and "lower" may be replaced with other terms, such as "first," "second," and "third," to describe the components of the specification. While terms such as "first," "second," and "third" may be used to describe various components, they are not limited by these terms, and "first component" may be named "second component."

[0018] With reference to FIGS. 1 and FIGS. 2, a semiconductor device according to exemplary embodiments will be described.

[0019] FIG. 1 is a schematic layout diagram of a semiconductor device (100) according to exemplary embodiments. FIG. 2 is a schematic cross-sectional view of a semiconductor device (100) according to exemplary embodiments. FIG. 2 shows a cross-section along I-I' of FIG. 1.

[0021] Referring to FIGS. 1 and 2, the semiconductor device (100) may include a substrate (110), a storage node contact (150) on the substrate (110), and a capacitor (CP) in contact with the storage node contact (150). The semiconductor device (100) may further include a landing pad (155) between the storage node contact (150) and the capacitor (CP).

[0023] The substrate (110) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (110) may further include impurities. The substrate (110) may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0025] The substrate (110) may include a device isolation region (120) and active regions (125) defined by the device isolation region (120).

[0026] The active regions (125) may be in the form of a bar and may be arranged in an island shape extending in one direction within the substrate (110). The active regions (125) may be arranged, for example, at an angle inclined with respect to the x and y directions and may be arranged repeatedly at equal intervals. By the inclined arrangement of the active regions (125), the cell density per unit area of ​​the substrate (110) can be increased while ensuring a spacing between adjacent active regions (125).

[0027] The active regions (125) may have first and second impurity regions (not shown) at a predetermined depth from the upper surface of the substrate (110). The first and second impurity regions may be spaced apart from each other. The first and second impurity regions may be provided as source / drain regions of a transistor formed by a word line (gate electrode layer (133)). In exemplary embodiments, the depths of the first and second impurity regions in the source region and the drain region may be different from each other.

[0029] The device isolation region (120) can be formed by a shallow trench isolation (STI) process. The device isolation region (120) can surround active regions (125) and electrically isolate them from one another. The device isolation region (120) can be made of an insulating material, for example, silicon oxide, silicon nitride, or a combination thereof. The device isolation region (125) may include multiple regions having different bottom depths depending on the width of the trench etched in the substrate (110). The device isolation region (125) can define the active regions (125).

[0031] The substrate (110) may further include a buried gate structure (130) that is embedded within the substrate (110) and extends in a first direction (Y direction).

[0032] The buried gate structure (130) may include a gate electrode layer (133), a gate dielectric film (136), and a gate capping layer (139). The gate electrode layer (133) may be provided in a line shape extending along a first direction (Y direction) to form a word line. The word line may be arranged to extend in the first direction (Y direction) across an active region (125). For example, a pair of adjacent word lines may be arranged to cross one active region (125).

[0033] The upper surface of the gate electrode layer (133) may be located at a lower level than the upper surface of the substrate (110). As used herein, the high and low of the term “level” may be defined with respect to the substantially flat upper surface of the substrate (101). The gate electrode layer (133) may constitute the gate of a buried channel array transistor (BCAT), but is not limited thereto. According to embodiments, the gate electrode layer (133) may have a form disposed on the upper surface of the substrate (110).

[0034] The gate electrode layer (133) may include at least one of a conductive material, for example, polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). According to embodiments, the gate electrode layer (133) may have a double-layer structure formed of different materials.

[0035] The gate dielectric film (136) can conformally cover the side and bottom surfaces of the gate electrode layer (133). The gate dielectric film (136) may comprise at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0036] The gate capping layer (139) may be disposed on top of the gate electrode layer (133). The gate capping layer (139) may include an insulating material, for example, silicon nitride.

[0038] The semiconductor device (100) may further include an interlayer insulating layer (140) disposed on a substrate (110). The interlayer insulating layer (140) may be formed in a plurality. The interlayer insulating layer (140) may include, for example, first to third interlayer insulating layers (143, 146, 149). The first to third interlayer insulating layers (143, 146, 149) may each include an insulating material. For example, the first to third interlayer insulating layers (143, 146, 149) may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0040] A storage node contact (150) may be disposed on a substrate (110). The storage node contact (150) may be formed by penetrating at least a portion of the interlayer insulating layer (140). In an exemplary embodiment, the storage node contact (150) may be disposed by penetrating the first and second interlayer insulating layers (143, 146).

[0041] A storage node contact (150) may be connected to a portion of an active region (125). A storage node contact (150) may be positioned between word lines (gate electrode layers (136)). The lower surface of the storage node contact (150) may be located at a lower level than the upper surface of the substrate (110). The storage node contact (150) may include a conductive material. The storage node contact (150) may be made of, for example, doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto.

[0043] The semiconductor device (100) may further include a landing pad (155) disposed between the storage node contact (150) and the capacitor (CP). The landing pad (155) may electrically connect the storage node contact (150) and the lower electrode structure (170) of the capacitor (CP). The landing pad (155) may be disposed through at least a portion of the interlayer insulating layer (140) on the storage node contact (150). In an exemplary embodiment, the landing pad (155) may be disposed through the third interlayer insulating layer (149). The landing pad (155) may include a conductive material and may include, for example, at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), and tungsten nitride (WN).

[0045] The semiconductor device (100) may further include an etch stop layer (160) disposed on an interlayer insulating layer (140). A lower electrode structure (170) of the capacitor (CP) may penetrate the etch stop layer (160) and come into contact with a landing pad (155). The etch stop layer (160) may include an insulating material having etch selectivity under specific etching conditions with mold layers (ML1, ML2, ML3 of FIG. 6a, etc.). In an exemplary embodiment, where the mold layers (ML1, ML2, ML3 of FIG. 6a, etc.) include silicon oxide, the etch stop layer (160) may include at least one of silicon nitride (SiN) or silicon carbonitride (SiCN).

[0047] The capacitor (CP) may include a lower electrode structure (170), a dielectric film (180), and an upper electrode structure (190). A supporter structure (SS) may be provided on the side of the lower electrode structure (170) of the capacitor (CP).

[0048] The lower electrode structure (170) can be positioned to penetrate the etching stop layer (160) and contact the landing pad (155).

[0049] The lower electrode structure (170) may include a first lower electrode layer (171) and a second lower electrode layer (173) disposed on the first lower electrode layer (171). The first and second lower electrode layers (171, 173) may each include at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al).

[0050] The first lower electrode layer (171) may have a cylindrical shape having a bottom surface and a side surface. The second lower electrode layer (173) may include a first portion (173L) covering at least the inner wall of the first lower electrode layer (171), and a second portion extending from the first portion (173L) and covering the top of the first lower electrode layer (171). The second portion may include a first side wall portion (173F) and a second side wall portion (173S). The first portion (173L) may fill part or all of the empty space defined by the cylindrical shape of the first lower electrode layer (171). The first side wall portion (173F) and the second side wall portion (173S) may be arranged to extend from the first portion (173L) and cover the top of the first lower electrode layer (171). The second part may include a side that is aligned with at least a portion of the side of the first lower electrode layer (171).

[0051] The lower electrode structure (170) may include a column portion (170P) and a cylinder portion (170C) disposed on the upper part of the column portion (170P). The first portion (173L) of the first lower electrode layer (171) and the second lower electrode layer (173) may form the column portion (170P). The first and second sidewall portions (173F, 173S) of the second lower electrode layer (173) may form the cylinder portion (170C).

[0052] In an exemplary embodiment, the column portion (170P) may extend to a level between the first support layer (SS1) and the second support layer (SS2). The first side wall portion (173F) may extend from the first portion (173L) to, for example, the level of the upper surface of the third support layer (SS3). The second side wall portion (173S) may extend from the first portion (173L) to a level lower than that of the first side wall portion (173F). For example, the second side wall portion (173S) may extend to a level below the lower surface of the third support layer (SS3).

[0053] In an exemplary embodiment, the first lower electrode structure (170) may include protrusions (P1, P2, P3) that protrude toward the support structure (SS). The first protrusion (P1) may protrude from the first lower electrode layer (171) toward the first support layer (SS1). The second protrusion (P2) may protrude from the first side wall portion (173F) toward the second support layer (SS2). The third protrusion (P3) may protrude from the first side wall portion (173F) toward the third support layer (SS3).

[0054] In an exemplary embodiment, the second sidewall (173S) may have a shape in which its width decreases toward the top. For example, one side of the second sidewall (173S) may be perpendicular to the substrate (110), and the other side may be inclined toward the other side. However, the length and shape of the column portion (170P) and the cylinder portion (170C) are not limited thereto. Depending on the embodiments, the ratio of the column portion (170P) and the cylinder portion (170C), the shape of the cylinder portion (170C), the shape of the support structure (SS), etc., may be changed.

[0056] As described above, the capacitor (CP) according to exemplary embodiments may include a pillar portion (170P) disposed at the bottom and a cylinder portion (170C) disposed at the top. The capacitor (CP) can uniformly adsorb the dielectric film (180) by including the pillar portion (170P), while also securing the electrical capacitance required for the semiconductor device by including the cylinder portion (170C). The capacitor (CP) according to exemplary embodiments of the present invention may have improved electrical characteristics.

[0057] The semiconductor device (100) may include a plurality of capacitors (CP). Each capacitor (CP) may include first and second lower electrode layers (171, 173) of the same height. Additionally, each capacitor (CP) may include a column portion (170P) and a cylinder portion (170C) of the same height. Thus, each capacitor (CP) may have a constant electrical capacitance.

[0059] A support structure (SS) may be disposed on the side of the lower electrode structure (170). In an exemplary embodiment, the support structure (SS) may include a plurality of support layers, for example, first to third support layers (SS1, SS2, SS3). The first to third support layers (SS1, SS2, SS3) are spaced apart from each other in the Z direction perpendicular to the upper surface of the substrate (110) and may extend in a horizontal direction perpendicular to the Z direction.

[0060] The first to third support layers (SS1, SS2, SS3) can be in contact with a plurality of lower electrode structures (170) and can connect adjacent lower electrode structures (170) to each other. In an exemplary embodiment, the first support layer (SS1) can be in contact with the outer surface of the column portion (170P), and the second and third support layers (SS2, SS3) can be in contact with the outer surface of the cylinder portion (170C). For example, the first support layer (SS1) can be in contact with the first lower electrode layer (171) of the column portion (170P), and the second support layer (SS2) can be in contact with the first side wall portion (173F) of the cylinder portion (170C).

[0061] The first to third support layers (SS1, SS2, SS3) may be structures that support a plurality of lower electrode structures (170) having a high aspect ratio. The first to third support layers (SS1, SS2, SS3) may include, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0062] In an exemplary embodiment, the first and second support layers (SS1, SS2) may have a thinner thickness than the third support layer (SS3). The distance between the upper surface of the interlayer insulation layer (140) and the lower surface of the first support layer (SS1) may be greater than the distance between the upper surface of the first support layer (SS1) and the lower surface of the second support layer (SS2). The distance between the upper surface of the first support layer (SS1) and the lower surface of the second support layer (SS2) may be greater than the distance between the upper surface of the second support layer (SS2) and the lower surface of the third support layer (SS3). However, the number, thickness, arrangement relationship, etc. of the support layers are not limited thereto and may be varied according to the embodiments.

[0064] The dielectric film (180) may be positioned to cover the lower electrode structure (170) and the support structure (SS) on the etching stop layer (160). The dielectric film (180) may conformally cover the upper and side surfaces of the plurality of lower electrode structures (170), the upper surface of the etching stop layer (160), and the exposed surfaces of the support structure (SS). In exemplary embodiments, the dielectric film (180) may include a portion extending into the pillar portion (170P) of the lower electrode structure (170).

[0065] The dielectric film (180) may include a high dielectric material, silicon oxide, silicon nitride, or a combination thereof. However, according to the embodiments, the dielectric film (180) may include an oxide, nitride, silicide, oxynitride, or silicide-oxynitride comprising one of hafnium (Hf), aluminum (Al), zirconium (Zr), and lanthanum (La).

[0067] The upper electrode structure (190) may be a structure covering a plurality of lower electrode structures (170), a support structure (SS), and a dielectric film (180). The upper electrode structure (190) may be a structure filling the space between the plurality of lower electrode structures (170) and the space between the support structures (SS).

[0068] The upper electrode structure (190) may include a single or multiple upper electrode layers. In an exemplary embodiment, the upper electrode structure (190) may include a first upper electrode layer (191) and a second upper electrode layer (192) formed sequentially on the lower electrode structure (170).

[0069] The first upper electrode layer (191) may be a conductive layer that conformally covers the dielectric film (180). The first upper electrode layer (191) may include a metal, for example, titanium nitride (TiN).

[0070] The second upper electrode layer (192) can cover the first upper electrode layer (191) and fill the space between the plurality of lower electrode structures (170) and the space between the support structures (SS). The second upper electrode layer (192) may include a semiconductor material, for example, polycrystalline silicon (Si) containing impurities.

[0072] FIGS. 3 to 5 illustrate schematic cross-sectional views of semiconductor devices according to exemplary embodiments.

[0073] The embodiments of FIGS. 3 to 5 differ from the embodiments of FIGS. 1 and 2 in terms of the shape, structure, etc. of the capacitor. In the embodiments of FIGS. 3 to 5, if the same reference numerals as FIGS. 1 and 2 are used but the alphabet is different, it is intended to describe embodiments different from FIGS. 1 and 2. The features described by the same reference numerals described above may be identical or similar.

[0075] The semiconductor device (100a) of FIG. 3 differs from the embodiments of FIG. 1 and FIG. 2 in the ratio of the pillar portion (170Pa) and the cylinder portion (170Ca) of the capacitor (CPa).

[0076] Referring to FIG. 3, the column portion (170Pa) may extend to a level between the etching stop layer (160) and the first support layer (SS1). The cylinder portion (170Ca) may be positioned above the column portion (170Pa). The cylinder portion (170Ca) may extend from a level between the etching stop layer (160) and the first support layer (SS1) to an upper surface level of the third support layer (SS3). The cylinder portion (170Ca) may have a height greater than the height of the column portion (170Pa).

[0077] A dielectric film (180) may be disposed on the inner and outer surfaces of the first and second sidewalls (173Fa, 173Sa) of the cylinder portion (170Ca). A dielectric film (180) may be disposed on the outer surface of the column portion (170Pa). As the ratio of the height of the cylinder portion (170Ca) to the total height of the capacitor (CPa) increases, the electrical capacitance of the capacitor (CPa) may increase. The capacitor (CPa) illustrated in FIG. 3 may have a larger electrical capacitance than the capacitor (CP) illustrated in FIG. 1 and FIG. 2.

[0078] The height ratio of the cylinder part (170Ca) to the total height of the capacitor (CPa) is not limited to that shown and may be changed depending on the electrical capacitance of the product, the size and shape of the capacitor, the thickness of the dielectric film, etc.

[0080] The semiconductor device (100b) of FIG. 4 differs from the embodiments of FIG. 1 and FIG. 2 in the shape of the pillar portion (170Pb) and the dielectric film (180b).

[0081] Referring to FIG. 4, the column portion (170Pb) may not contain a seam inside. The dielectric film (180b) may be conformally positioned on the upper surface and sides of the lower electrode structure (170b). The dielectric film (180b) may be positioned on the upper surface of the column portion (170Pb) of the lower electrode structure (170b) and may not extend into the column portion (170Pb). The shape of the column portion (170Pb) and the dielectric film (180b) may vary depending on the size and spacing of the capacitors (CPb), the thickness and material of the first and second lower electrode layers (171, 173b), etc.

[0083] The semiconductor device (100c) of FIG. 5 differs from the embodiments of FIG. 1 and FIG. 2 in the shape of the cylinder portion (170Cc).

[0084] Referring to FIG. 5, the first and second side walls (170Fc, 170Sc) of the cylinder portion (170Cc) may have the same shape. The first and second side walls (170Fc, 170Sc) may extend to the upper surface level of the third support layer (SS3). In an exemplary embodiment, the first and second side walls (170Fc, 170Sc) may have a uniform width over the entire height. However, the shape of the first and second side walls (170Fc, 170Sc) is not limited thereto. The shape of the first and second side walls (170Fc, 170Sc) may be changed according to the etching method of the mold layers (ML1, ML2, ML3 of FIG. 6a, etc.) and the preliminary support layers (SL1, SL2, SL3 of FIG. 6a, etc.) during the manufacturing process.

[0086] FIGS. 6a to 6n are schematic cross-sectional views illustrating the manufacturing process of a semiconductor device according to exemplary embodiments. The cross-sectional views of FIGS. 6a to 6n illustrate a cross-section corresponding to FIG. 2.

[0088] Referring to FIG. 6a, a substructure including a substrate (110) can be formed, and mold layers (ML1, ML2, ML3) and pre-support layers (SL1, SL2, SL3) can be alternately stacked on the substructure. Holes (H) penetrating the mold layers (ML1, ML2, ML3) and pre-support layers (SL1, SL2, SL3) can be formed.

[0089] Active regions (125) and device isolation regions (120) defining the active regions (125) can be formed on the substrate (110). A portion of the substrate (110) can be removed to form trenches extending in a first direction (Y direction), and buried gate structures (130) can be formed within the trenches. Impurity regions (not shown) can be formed on both sides of the buried gate structures (130), and bit line structures (not shown) can be formed along a second direction (X direction) intersecting the first direction (Y direction).

[0090] First and second interlayer insulating layers (143, 146) covering the substrate (110) may be formed. An opening may be formed through the first and second interlayer insulating layers (143, 146) to expose a portion of the active region (125). The opening may be filled with a conductive material to form storage node contacts (150). In an exemplary embodiment, the storage node contacts (150) may include at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al).

[0091] A third interlayer insulating layer (149) covering the second interlayer insulating layer (146) and the storage node contacts (150) may be formed. An opening may be formed through the third interlayer insulating layer (149) to expose at least a portion of the storage node contacts (150). The opening may be filled with a conductive material to form landing pads (155). In an exemplary embodiment, the landing pads (155) may comprise doped polycrystalline silicon (Si).

[0092] An etch stop layer (160) covering the third interlayer insulating layer (149) and the landing pads (155) may be formed. The etch stop layer (160) may include an insulating material having etch selectivity under specific etching conditions with the mold layers (ML1, ML2, ML3). In an exemplary embodiment, where the mold layers (ML1, ML2, ML3) include silicon oxide, the etch stop layer (160) may include at least one of silicon nitride (SiN) or silicon carbonitride (SiCN).

[0093] A stacked structure (D) can be formed by alternately stacking mold layers (ML1, ML2, ML3) and pre-support layers (SL1, SL2, SL3) on an etching stop layer (160). In an exemplary embodiment, the mold layers (ML1, ML2, ML3) and the pre-support layers (SL1, SL2, SL3) may each include three layers, but the number of layers is not limited thereto. The mold layers (ML1, ML2, ML3) and the pre-support layers (SL1, SL2, SL3) may have the same thickness or different thicknesses. In an exemplary embodiment, the first mold layer (ML1) may have a greater thickness than the second mold layer (ML2), and the second mold layer (ML2) may have a greater thickness than the third mold layer (ML3). The third pre-support layer (SL3) may have a greater thickness than the first and second pre-support layers (SL1, SL2).

[0094] Multiple holes (H) can be formed penetrating the stacked structure (D). The multiple holes (H) can penetrate the etching stop layer (160) to expose the landing pad (LP).

[0096] Referring to FIG. 6b, a first preliminary lower electrode layer (171') can be conformally formed inside a plurality of holes (H) and on the upper surface of a laminated structure (D). The first preliminary lower electrode layer (171') can be formed with a thin thickness relative to the diameter of each hole (H).

[0097] The first preliminary lower electrode layer (171') can be formed by a process such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The first preliminary lower electrode layer (171') may include a conductive material. For example, the first preliminary lower electrode layer (171') may include at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al).

[0099] Referring to FIG. 6c, a sacrificial layer (OM) can be formed on the upper surface of the first pre-lower electrode layer (171'). The first pre-lower electrode layer (171') can be formed to fill the interior of a plurality of holes (H) and cover the laminated structure (D).

[0100] The sacrificial layer (OM) may include an organic material. The organic material included in the sacrificial layer (OM) may have low viscosity and characteristics that allow for easy removal in the process described later. In an exemplary embodiment, the sacrificial layer (OM) may include BARC (Bottom Anti-Reflection Coating). In another embodiment, the sacrificial layer (OM) may include HELP (Heat Eliminable Polymer). HELP can be adsorbed in a solid form inside the device at 170°C or lower, and can be removed by thermal decomposition in a gaseous form at 170°C or higher. When the sacrificial layer (OM) includes HELP, the process of forming the sacrificial layer (OM) can be performed at a temperature of 170°C or lower.

[0101] In the process of FIG. 6c, by forming a sacrificial layer (OM) containing an organic material on the first pre-subordinate electrode layer (171'), the inside of the hole (H) can be coated without a seam. When the inside of the hole (H) is filled with a conductive material such as titanium nitride (TiN), the morphology of the conductive material may be uneven, and a seam may be formed inside the hole (H). When the conductive material is etched in such a state, a problem may arise in which the recess distribution becomes uneven. As a result, the length of a single cylinder stack may differ for each of the multiple capacitors, and a problem may arise in which the electrical capacitance is not uniform.

[0102] In the process of FIG. 6c, a first pre-lower electrode layer (171') is conformally formed inside the hole (H), and then the inside of the hole (H) is filled with a sacrificial layer (OM) containing an organic material, thereby filling the inside of the hole (H) without a seam.

[0104] Referring to FIG. 6d, a sacrificial layer (OM) formed on a stacked structure (D) can be removed. In an exemplary embodiment, the sacrificial layer (OM) can be removed by wet etching using hydrogen gas (H2) and nitrogen gas (N2). However, the etching method is not limited thereto and may be changed depending on the type of organic material contained in the sacrificial layer (OM), etc.

[0106] Referring to FIG. 6e, at least a portion of the sacrificial layer (OM) inside the plurality of holes (H) can be removed. The method for removing the sacrificial layer (OM) may be the wet etching described above in FIG. 6d.

[0107] Since no seam is formed in the sacrificial layer (OM) within the plurality of holes (H), the sacrificial layer (OM) in each hole (H) can be etched to the same depth. Each sacrificial layer (OM) remaining within the plurality of holes (H) can have the same height. In an exemplary embodiment, the sacrificial layer (OM) can be etched to a depth between the first pre-support layer (SL1) and the second pre-support layer (SL2). However, the etching depth is not limited thereto. For example, when the sacrificial layer (OM) is etched to a depth between the etching stop layer (160) and the first pre-support layer (SL1), a capacitor (CPa) shown in FIG. 3 can be formed.

[0109] Referring to FIG. 6f, at least a portion of the first preliminary lower electrode layer (171') formed on the upper surface of the laminated structure (D) and inside the plurality of holes (H) can be etched.

[0110] The first preliminary lower electrode layer (171') can be etched to the same height as the sacrificial layer (OM) remaining inside the hole (H). Since the sacrificial layer (OM) remaining inside each hole (H) has the same height, the first preliminary lower electrode layer (171') inside each hole (H) can also be etched to have the same height.

[0112] Referring to FIG. 6g, the sacrificial layer (OM) inside the plurality of holes (H) can be completely removed. The method for removing the sacrificial layer (OM) may be applied using wet etching as described above in FIG. 6d, but is not limited thereto. For example, if the sacrificial layer (OM) contains HELP, the sacrificial layer (OM) may be removed by thermal decomposition at a temperature of 170°C or higher.

[0113] A first preliminary lower electrode layer (171') in the shape of a cylinder having a lower surface can be formed inside each hole (H). The first preliminary lower electrode layer (171') formed inside each hole (H) can have the same height.

[0115] Referring to FIG. 6h, a second preliminary lower electrode layer (173') can be formed inside a plurality of holes (H) and on the upper surface of a laminated structure (D).

[0116] A first portion (173L') of the second preliminary lower electrode layer (173') may be formed to cover a first preliminary lower electrode layer (171') formed inside a plurality of holes (H). The first portion (173L') may fill part or all of the space defined by the first preliminary lower electrode layer (171'). The first preliminary lower electrode layer (171') and the first portion (173L') may form a column shape.

[0117] A seam may be formed between the first portion (173L'). However, depending on the size of the hole (H), the thickness of the second preliminary lower electrode layer (173'), the material, etc., the internal space of the first preliminary lower electrode layer (171') may be completely filled without a seam. In this case, a capacitor (CPb) as shown in FIG. 4 may be formed.

[0118] The second portion (173U') of the second preliminary lower electrode layer (173') can cover the side of the hole (H) where the first preliminary lower electrode layer (171') is not formed. The second portion (173U') can have a cylindrical shape.

[0119] The third portion (173T') of the second preliminary lower electrode layer (173') can be formed to cover the upper surface of the laminated structure (D).

[0120] The second preliminary lower electrode layer (173') may include a conductive material. For example, the second preliminary lower electrode layer (173') may include at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al).

[0122] Referring to FIG. 6i, the second preliminary lower electrode layer (173') can be etched to remove the third portion (173T'). Inside the plurality of holes (H), the first preliminary lower electrode layer (171') and the first portion (173L') of the second lower electrode layer (173') may have a columnar shape, and the second portion (173U') of the second lower electrode layer (173') may have a cylinder shape.

[0124] Referring to FIG. 6j, a mask (M) can be formed on a stacked structure (D). The mask (M) can be provided as an etching mask for etching the first to third mold layers (ML1, ML2, ML3). The mask (M) can define an area where a lower electrode structure (170 in FIG. 2) is placed. The mask (M) may be a structure including a plurality of hole-shaped openings.

[0126] Referring to FIG. 6k, the mold layers (ML1, ML2, ML3) can be removed using the mask (M) as an etching mask, and a portion of the pre-support layers (SL1, SL2, SL3) can be removed.

[0127] An etching process can be performed on portions of the mold layers (ML1, ML2, ML3) and pre-support layers (SL1, SL2, SL3) that do not overlap with the mask (M) in the z-direction. In an exemplary embodiment, the third pre-support layer (SL3) can be etched by an anisotropic etching process, and the third mold layer (ML3) can be removed by an isotropic etching process before etching the second pre-support layer (SL2). Similarly, the second pre-support layer (SL2) can be etched by an anisotropic etching process, and the second mold layer (ML2) can be removed by an isotropic etching process before etching the first pre-support layer (SL1). After etching the first pre-support layer (SL1) by an anisotropic etching process, the first mold layer (ML1) can be removed by an isotropic etching process. The mask (M) can be removed after etching the mold layers (ML1, ML2, ML3) or while etching the mold layers (ML1, ML2, ML3).

[0129] Referring to FIG. 6L, the lower electrode structure (170) can be formed by performing an etching process so that the thickness of the preliminary lower electrode structure (170') is reduced.

[0130] By performing the etching process of FIG. 6L, the gap between adjacent lower electrode structures (170) can be widened. This prevents short circuit defects between the lower electrode structures (170). The lower electrode structure (170) may have a shape similar to the preliminary lower electrode structure (170'), except that its thickness has been reduced.

[0131] The preliminary support layers (SL1, SL2, SL3 in FIG. 6k) and adjacent preliminary lower electrode structures may remain unetched. The remaining preliminary support layers (SL1, SL2, SL3 in FIG. 6k) may be defined as first to third support layers (SS1, SS3, SS3). The first to third support layers (SS1, SS2, SS3) are disposed on the sides of the lower electrode structures (170) to connect adjacent lower electrode structures among the lower electrode structures (170).

[0132] The lower electrode structure (170) adjacent to the first to third support layers (SS1, SS2, SS3) may remain unetched. As a result, protrusions (P1, P2, P3) may be formed that protrude from the lower electrode structure (170) toward the first to third support layers (SS1, SS2, SS3). In an exemplary embodiment, the first protrusion (P1) may protrude from the first lower electrode layer (171) and come into contact with the first support layer (SS1). The second protrusion (P2) may protrude from the first sidewall (173F) of the second lower electrode layer (173) and come into contact with the second support layer (SS2). The third protrusion (P3) may protrude from the first sidewall (173F) of the second lower electrode layer (173) and come into contact with the third support layer (SS3).

[0134] Referring to FIG. 6m, a dielectric film (180) covering a plurality of lower electrode structures (170) and first to third support layers (SS1, SS2, SS3) connected thereto can be formed.

[0135] The dielectric film (180) can conformally cover the upper and side surfaces of a plurality of lower electrode structures (170), the upper surface of the etch stop layer (160), and the exposed surfaces of the first to third support layers (SS1, SS2, SS3). If a seam is formed in the first portion (173L) of the second lower electrode layer (173), the dielectric film (180) can be extended to fill the seam. The dielectric film (180) may comprise a high-k dielectric, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0137] Referring to FIG. 6n, a first upper electrode layer (191) can be formed on a dielectric film (180). The first upper electrode layer (191) can conformally cover the dielectric film (180). The first upper electrode layer (191) may include, for example, titanium nitride (TiN).

[0139] Referring again to FIG. 2, a second upper electrode layer (192) can be formed on the first upper electrode layer (191).

[0140] The second upper electrode layer (192) fills between the plurality of lower electrode structures (170) and can cover the plurality of lower electrode structures (170) and the first to third support layers (SS1, SS2, SS3).

[0141] The second upper electrode layer (192) may include a semiconductor material, for example, polycrystalline silicon (Si) containing impurities. The second upper electrode layer (192) may form an upper electrode structure (190) together with the first upper electrode layer (191).

[0143] According to exemplary embodiments of the present invention, the lower electrode structure (170) of the capacitor (CP) may be formed by adsorbing lower electrode layers twice. When the lower electrode structure (170) of the capacitor (CP) is analyzed by transmission electron microscopy (TEM), the first and second lower electrode layers (171, 173) can be identified.

[0144] In an exemplary embodiment, a column portion (170C) of a lower electrode structure (170) may be found to have a first lower electrode layer (171) in a cylindrical shape having a bottom surface and a side surface, and a first portion (173L) of a second lower electrode layer (173) filling the internal space of the first lower electrode layer (171). In a column portion (170P) of a lower electrode structure (170), side wall portions (173F, 173S) extending from the first portion (173L) of the second lower electrode layer (173) may be found.

[0146] FIGS. 7 and FIGS. 8 illustrate a semiconductor device (200) according to exemplary embodiments.

[0147] FIG. 7 is a layout diagram of a semiconductor device (200) according to exemplary embodiments. FIG. 8 is a cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 8 shows a cross-section along II-II' and III-III' of FIG. 7.

[0149] Referring to FIGS. 7 and 8, the semiconductor device (200) may include a substrate (210), a plurality of first conductive lines (220), a channel layer (230), a gate electrode layer (240), a gate insulating layer (250), and a capacitor (CP). The semiconductor device (200) may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length of the channel layer (230) extends along a vertical direction from the substrate (210).

[0150] A lower insulating layer (212) may be disposed on a substrate (210), and a plurality of first conductive lines (220) may be spaced apart from each other in the X direction and extended in the Y direction on the lower insulating layer (212). A plurality of first insulating patterns (222) may be disposed on the lower insulating layer (212) to fill the space between the plurality of first conductive lines (220). The plurality of first insulating patterns (222) may be extended in the Y direction, and the upper surface of the plurality of first insulating patterns (222) may be disposed at the same level as the upper surface of the plurality of first conductive lines (220). The plurality of first conductive lines (220) may function as bit lines of a semiconductor device (200).

[0151] In exemplary embodiments, a plurality of first conductive lines (220) may comprise doped polycrystalline silicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, a plurality of first conductive lines (220) may comprise doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x ..., or a combination thereof, but is not limited thereto. A plurality of first conductive lines (220) may comprise a single layer or a multilayer of the aforementioned materials. In exemplary embodiments, a plurality of first conductive lines (220) may comprise a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may comprise graphene, carbon nanotubes, or a combination thereof.

[0152] The channel layer (230) may be arranged in a matrix form spaced apart in the X and Y directions on a plurality of first conductive lines (220). The channel layer (230) may have a first width in the X direction and a first height in the Z direction, and the first height may be greater than the first width. For example, the first height may be about 2 to 10 times the first width, but is not limited thereto. The bottom portion of the channel layer (230) functions as a first source / drain region (not shown), the upper portion of the channel layer (230) functions as a second source / drain region (not shown), and a portion of the channel layer (230) between the first and second source / drain regions may function as a channel region (not shown).

[0153] In exemplary embodiments, the channel layer (230) may include an oxide semiconductor, for example, the oxide semiconductor is In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga yIt may include O or a combination thereof. The channel layer (230) may include a single layer or a multilayer of oxide semiconductor. In some examples, the channel layer (230) may have a bandgap energy greater than the bandgap energy of silicon. For example, the channel layer (230) may have a bandgap energy of about 1.5 eV to 5.6 eV. For example, the channel layer (230) may have optimal channel performance when it has a bandgap energy of about 2.0 eV to 4.0 eV. For example, the channel layer (230) may be polycrystalline or amorphous, but is not limited thereto. In exemplary embodiments, the channel layer (230) may include a two-dimensional semiconductor material, for example, said two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0154] The gate electrode layer (240) may extend in the X direction on both sidewalls of the channel layer (230). The gate electrode layer (240) may include a first sub-gate electrode (240P1) facing the first sidewall of the channel layer (230) and a second sub-gate electrode (240P2) facing the second sidewall opposite the first sidewall of the channel layer (230). As one channel layer (230) is disposed between the first sub-gate electrode (240P1) and the second sub-gate electrode (240P2), the semiconductor device (200) may have a dual-gate transistor structure. However, the technical concept of the present invention is not limited thereto, and a single-gate transistor structure may be realized by omitting the second sub-gate electrode (240P2) and forming only the first sub-gate electrode (240P1) facing the first sidewall of the channel layer (230).

[0155] The gate electrode layer (240) may comprise doped polycrystalline silicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, the gate electrode layer (240) may comprise doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x It may be composed of , or a combination thereof, but is not limited to these.

[0156] The gate insulating layer (250) surrounds the sidewalls of the channel layer (230) and may be interposed between the channel layer (230) and the gate electrode layer (240). For example, as shown in FIG. 7, the entire sidewall of the channel layer (230) may be surrounded by the gate insulating layer (250), and a portion of the sidewall of the gate electrode layer (240) may be in contact with the gate insulating layer (250). In other embodiments, the gate insulating layer (250) may be extended in the extension direction of the gate electrode layer (240) (i.e., the first direction (X direction)), and only two sidewalls of the channel layer (230) facing the gate electrode layer (240) may be in contact with the gate insulating layer (250).

[0157] In exemplary embodiments, the gate insulating layer (250) may be made of a silicon oxide film, a silicon oxynitride film, a high dielectric film having a dielectric constant higher than that of a silicon oxide film, or a combination thereof. The high dielectric film may be made of a metal oxide or a metal oxynitride. For example, a high dielectric film that can be used as the gate insulating layer (250) may be made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0158] A plurality of second insulation patterns (232) may be extended along a second direction (Y direction) on a plurality of first insulation patterns (222), and a channel layer (230) may be disposed between two adjacent second insulation patterns (232) among the plurality of second insulation patterns (232). Additionally, between two adjacent second insulation patterns (232), a first filling layer (234) and a second filling layer (236) may be disposed in the space between two adjacent channel layers (230). The first filling layer (234) may be disposed at the bottom of the space between two adjacent channel layers (230), and the second filling layer (236) may be formed on the first filling layer (234) to fill the remainder of the space between two adjacent channel layers (230). The upper surface of the second buried layer (236) is positioned at the same level as the upper surface of the channel layer (230), and the second buried layer (236) can cover the upper surface of the gate electrode layer (240). Alternatively, a plurality of second insulating patterns (232) may be formed as a material layer continuous with a plurality of first insulating patterns (222), or the second buried layer (236) may be formed as a material layer continuous with the first buried layer (234).

[0159] Storage node contacts (260) may be disposed on the channel layer (230). The storage node contacts (260) may be arranged in a matrix form that is vertically overlapped with the channel layer (230) and spaced apart in the X and Y directions. The storage node contacts (260) may be made of doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x , or a combination thereof, but is not limited thereto. The upper insulating layer (262) may surround the sidewall of the storage node contact (260) on a plurality of second insulating patterns (232) and a second embedded layer (236).

[0160] An etching stop layer (261) is disposed on the upper insulating layer (262), and a capacitor (CP) may be disposed on the etching stop layer (261). The capacitor (CP) may include a lower electrode structure (170), a dielectric film (280), and an upper electrode structure (290). In an exemplary embodiment, the capacitor (CP) may have the same or similar structure as described with reference to FIGS. 1 through 5.

[0162] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0164] 100: Semiconductor device 110: Substrate 120: Device isolation area 125: Active area 130: Landfill gate structure 140: Interlayer insulation layer 150: Storage Node Contact 155: Landing Pad 160: Etching stop layer CP: Capacitor 170: Lower electrode structure 180: Dielectric film 190: Upper electrode structure SS: Supporter structure D: Laminated structure H: Hole ML: Mold layer SL: Pre-support layer OM: Victim Layer M: Mask

Claims

Claim 1 A semiconductor device comprising: a substrate; storage node contacts on the substrate; lower electrode structures disposed on the storage node contacts; a support structure provided on at least a portion of the outer surface of the lower electrode structures and connecting adjacent lower electrode structures among the lower electrode structures; a dielectric layer disposed on the lower electrode structures and the support structure; and an upper electrode structure disposed on the dielectric layer, wherein each of the lower electrode structures comprises: a pillar portion in contact with each of the storage node contacts; and a cylinder portion disposed on the pillar portion, wherein the pillar portion comprises: a first lower electrode layer having a cylinder shape having a lower surface and a side surface; and a first portion covering at least the inner wall of the first lower electrode layer, wherein the cylinder portion comprises a second portion extending from the first portion and covering the upper end of the first lower electrode layer, wherein the second portion of the cylinder portion comprises a first side wall and a second side wall, and the first side wall has a height greater than the height of the second side wall. Claim 2 A semiconductor device according to claim 1, wherein the cylinder portions of each of the lower electrode structures have the same height. Claim 3 A semiconductor device according to claim 1, wherein the second portion comprises a side that is aligned with at least a portion of the side of the first lower electrode layer. Claim 4 A semiconductor device according to claim 1, wherein at least a portion of the supporter structure is in contact with the first side wall. Claim 5 delete Claim 6 A semiconductor device according to claim 1, wherein the support structure comprises first to third support layers sequentially spaced apart from the upper surface of the substrate. Claim 7 A semiconductor device according to claim 6, wherein the upper portion of the first lower electrode layer is disposed at a level between the first support layer and the second support layer. Claim 8 A semiconductor device comprising: a substrate; storage node contacts on the substrate; lower electrode structures disposed on the storage node contacts; a support structure provided on at least a portion of the outer surface of the lower electrode structures and connecting adjacent lower electrode structures among the lower electrode structures; a dielectric layer disposed on the lower electrode structures and the support structure; and an upper electrode structure disposed on the dielectric layer, wherein each of the lower electrode structures comprises a pillar portion in contact with each of the storage node contacts; and a cylinder portion disposed on the pillar portion, wherein the pillar portion comprises a first lower electrode layer having a cylinder shape having a lower surface and a side surface; and a first portion covering at least the inner wall of the first lower electrode layer, and the cylinder portion comprises a second portion extending from the first portion and covering the top of the first lower electrode layer, and each of the lower electrode structures comprises protrusions protruding toward the support structure. Claim 9 A semiconductor device according to claim 1, wherein the dielectric layer comprises a portion extending into the column portion of each of the lower electrode structures. Claim 10 A semiconductor device according to claim 1, wherein the substrate comprises active regions defined by a device isolation region; and embedded gate structures extending in a first direction intersecting the active regions and spaced apart in a second direction intersecting the first direction. Claim 11 A semiconductor device according to claim 10, wherein the storage node contacts contact at least a portion of the active regions disposed between the buried gate structures. Claim 12 A semiconductor device according to claim 1, further comprising landing pads disposed between the storage node contacts and the lower electrode structures. Claim 13 A semiconductor device comprising: a lower electrode structure including a first lower electrode layer and a second lower electrode layer disposed on the first lower electrode layer; a dielectric layer disposed on the lower electrode structure; and an upper electrode structure disposed on the dielectric layer, wherein the first lower electrode layer has a cylindrical shape having a bottom surface and a side surface, and the second lower electrode layer includes a first portion covering the inner wall of the first lower electrode layer and a second portion extending from the first portion to cover the top of the first lower electrode layer, and the second portion includes a first side wall and a second side wall, and the upper electrode structure extending on the first portion between the first side wall and the second side wall of the second portion. Claim 14 A semiconductor device according to claim 13, wherein the dielectric layer includes a portion extending into the first portion of the second lower electrode layer. Claim 15 A semiconductor device according to claim 13, wherein the first lower electrode layer has a cylindrical shape with a closed lower surface, and the first portion of the second lower electrode layer includes a portion covering the inner wall of a space defined by the cylindrical shape of the first lower electrode layer. Claim 16 delete Claim 17 A semiconductor device comprising: a substrate; a plurality of storage node contacts on the substrate; capacitors disposed on each of the storage node contacts; wherein each of the capacitors comprises: lower electrode structures including a first lower electrode layer and a second lower electrode layer disposed on the first lower electrode layer; a dielectric layer disposed on the lower electrode structures; and an upper electrode structure disposed on the dielectric layer, wherein the first lower electrode layer has a cylindrical shape having a bottom surface and a side surface, and the second lower electrode layer comprises a first portion covering the inner wall of the first lower electrode layer and a second portion extending from the first portion to cover the top of the first lower electrode layer, and the second portion includes a first side wall and a second side wall, and the upper electrode structure extends between the first side wall and the second side wall of the second portion and does not extend into the first portion. Claim 18 A semiconductor device according to claim 17, wherein the second side wall has a shape that narrows toward the top. Claim 19 A semiconductor device according to claim 17, further comprising a plurality of support layers spaced apart from the upper surface of the substrate, wherein the support layers include: a first support layer in contact with the outer surface of the first lower electrode layer; and a second support layer in contact with the outer surface of the second portion of the second lower electrode layer. Claim 20 In claim 19, the semiconductor device, wherein the second support layer contacts the first sidewall of the second portion of the second lower electrode layer.

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