Semiconductor device

Abstract

A semiconductor device according to exemplary embodiments comprises: a plurality of lower electrodes disposed on a substrate; at least one support layer in contact with the plurality of lower electrodes; a dielectric layer on the lower electrodes; an upper electrode on the dielectric layer; and a first interface film between the lower electrodes and the dielectric layer. and a second interface film between the upper electrode and the dielectric layer, wherein at least one of the first interface film and the second interface film comprises a plurality of layers, and each of the upper surface and lower surface of the at least one supporter layer comprises a region spaced apart from the first interface film, and the plurality of layers comprises a first metal element and a second metal element different from the first metal element, and the lower electrodes comprise the first metal element, and the first interface film comprises a first region and a second region, wherein the first region is adjacent to the at least one supporter layer than the second region, and in the first region the first interface film comprises the second metal element at a first concentration, and in the second region the first interface film comprises the second metal element at a second concentration, and the first concentration is smaller than the second concentration.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0003] In response to the demand for high integration and miniaturization of semiconductor devices, the size of capacitors in semiconductor devices is also being reduced. Accordingly, various studies are being conducted to optimize the structure of capacitors capable of storing information in Dynamic Random-Access Memory (DRAM).

[0004] delete Prior art literature

[65535] 1. U.S. Registered Patent Publication US 11,133,314 B2 The problem to be solved

[0005] One of the technical problems according to the embodiments of the present invention is to provide a semiconductor device with improved electrical characteristics and reliability. means of solving the problem

[0007] A semiconductor device according to exemplary embodiments comprises: a substrate; a plurality of lower electrodes disposed on the substrate; at least one support layer in contact with the plurality of lower electrodes and extending in a direction parallel to the upper surface of the substrate; a dielectric layer on the lower electrodes; an upper electrode on the dielectric layer; and a first interface film between the lower electrodes and the dielectric layer. The apparatus comprises a second interface film between the upper electrode and the dielectric layer, wherein at least one of the first interface film and the second interface film comprises a plurality of layers, and each of the upper surface and lower surface of the at least one supporter layer comprises a region spaced apart from the first interface film, and the plurality of layers comprises at least one element among oxygen (O) and nitrogen (N), a first metal element, and a second metal element different from the first metal element, and the lower electrodes comprise the first metal element, and the first interface film comprises a first region and a second region, wherein the first region is adjacent to the at least one supporter layer than the second region, and in the first region the first interface film comprises the second metal element at a first concentration, and in the second region the first interface film comprises the second metal element at a second concentration, and the first concentration may be smaller than the second concentration.

[0008] A semiconductor device according to exemplary embodiments comprises: a substrate; a plurality of lower electrodes disposed on the substrate; a support layer extending in a direction parallel to the upper surface of the substrate and in contact with the plurality of lower electrodes; a dielectric layer on the lower electrodes; an upper electrode on the dielectric layer; a first interface film between the lower electrodes and the dielectric layer; and a second interface film between the upper electrode and the dielectric layer, wherein at least one of the first interface film and the second interface film comprises a plurality of layers, and the first interface film may include a portion whose thickness decreases as it approaches the support layer.

[0009] A semiconductor device according to exemplary embodiments comprises: a device isolation layer defining active regions on a substrate; gate electrodes extending into the device isolation layer across the active regions; first impurity regions and second impurity regions disposed within the active regions on both sides of the gate electrodes; bit lines disposed on the gate electrodes and electrically connected to the first impurity regions; upper conductive patterns disposed on the sides of the bit lines and electrically connected to the second impurity regions; lower electrodes extending perpendicularly on the upper conductive patterns and connected to the upper conductive patterns, wherein the lower electrodes include a first electrode pattern and a second electrode pattern adjacent to each other; at least one supporter layer disposed between the first electrode pattern and the second electrode pattern and in contact with the first electrode pattern and the second electrode pattern; an upper electrode on the lower electrodes; a dielectric layer between the lower electrodes and the upper electrode; and a first interface film between the lower electrodes and the dielectric layer. and a second interface film between the upper electrode and the dielectric layer, wherein each of the upper and lower surfaces of the at least one supporter layer includes a portion exposed from the first interface film and in direct contact with the dielectric layer, and at least one of the first interface film and the second interface film includes a plurality of layers, and the lower electrodes, the upper electrode, the first interface film, and the second interface film all commonly include a first metal element, and the first interface film includes a second metal element different from the first metal element, and the first interface film may include a portion in which the concentration of the second metal element decreases as it gets closer to the at least one supporter layer. Effects of the invention

[0011] By placing multiple layers of interfacial films between the lower electrode and the dielectric layer and between the upper electrode and the dielectric layer, respectively, a semiconductor device with improved electrical characteristics and reliability can be provided.

[0012] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0014] FIG. 1 is a schematic plan view of a semiconductor device according to exemplary embodiments. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIGS. 3 to 6 are partially enlarged cross-sectional views illustrating an enlarged area including a capacitor of a semiconductor device according to exemplary embodiments. FIGS. 7 to 14 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0015] Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings.

[0017] FIG. 1 is a schematic plan view of a semiconductor device according to exemplary embodiments.

[0018] FIG. 2 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIG. 2 illustrates cross-sections of the semiconductor device of FIG. 1 along the cutting lines I-I' and II-II'.

[0019] FIG. 3 is a partially enlarged cross-sectional view illustrating an enlarged area including a capacitor of a semiconductor device according to exemplary embodiments. FIG. 3 illustrates an enlarged area of ​​region 'A' of FIG. 2.

[0021] Referring to FIGS. 1 to 3, the semiconductor device (100) may include a substrate (101) comprising active regions (ACT), a device isolation layer (110) defining the active regions (ACT) within the substrate (101), a word line structure (WLS) embedded and extended within the substrate (101) and comprising a word line (WL), a bit line structure (BLS) extending intersecting the word line structure (WLS) on the substrate (101) and comprising a bit line (BL), and a capacitor structure (CAP) on the bit line structure (BLS). The semiconductor device (100) may further include a lower conductive pattern (150) on the active region (ACT), an upper conductive pattern (160) on the lower conductive pattern (150), and an insulating pattern (165) penetrating the upper conductive pattern (160).

[0022] A semiconductor device (100) may include, for example, a cell array of a Dynamic Random Access Memory (DRAM). For example, a bit line (BL) may be connected to a first impurity region (105a) of an active region (ACT), and a second impurity region (105b) of an active region (ACT) may be electrically connected to a capacitor structure (CAP) on an upper conductive pattern (160) through lower and upper conductive patterns (150, 160). The capacitor structure (CAP) may include lower electrodes (170), a dielectric layer (180) on the lower electrodes (170), an upper electrode (190) on the dielectric layer (180), a first interface film (175) between the lower electrodes (170) and the dielectric layer (180), and a second interface film (185) between the upper electrode (190) and the dielectric layer (180). The capacitor structure (CAP) may further include an etch stop layer (168) and support layers (171, 172).

[0023] A semiconductor device (100) may include a cell array region in which a cell array is disposed and a peripheral circuit region in which peripheral circuits for driving memory cells disposed in the cell array are disposed. The peripheral circuit region may be disposed around the cell array region.

[0025] The substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (101) may further include impurities. The substrate (101) may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0027] Active regions (ACTs) can be defined within the substrate (101) by a device isolation layer (110). The active regions (ACTs) may be in the form of a bar and may be arranged in an island shape extending in one direction within the substrate (101). The one direction may be inclined with respect to the extension direction of the word lines (WL) and bit lines (BL). The active regions (ACTs) may be arranged parallel to each other, such that the end of one active region (ACT) is arranged adjacent to the center of another active region (ACT) adjacent thereto.

[0028] The active region (ACT) may have first and second impurity regions (105a, 105b) at a predetermined depth from the upper surface of the substrate (101). The first and second impurity regions (105a, 105b) may be spaced apart from each other. The first and second impurity regions (105a, 105b) may be provided as source / drain regions of a transistor formed by a word line (WL). The source region and the drain region are formed by the first and second impurity regions (105a, 105b) by doping or ion implantation of substantially the same impurities, and may be referred to interchangeably depending on the circuit configuration of the transistor finally formed. The impurities may include dopants having a conductivity type opposite to that of the substrate (101). In exemplary embodiments, the depths of the first and second impurity regions (105a, 105b) in the source region and the drain region may differ from each other.

[0030] The device isolation layer (110) can be formed by a shallow trench isolation (STI) process. The device isolation layer (110) can surround active regions (ACTs) and electrically isolate them from one another. The device isolation layer (110) may be made of an insulating material, for example, silicon oxide, silicon nitride, or a combination thereof. The device isolation layer (110) may include multiple regions having different bottom depths depending on the width of the trench etched in the substrate (101).

[0032] Word line structures (WLS) may be disposed within gate trenches (115) extending within the substrate (101). Each of the word line structures (WLS) may include a gate dielectric layer (120), a word line (WL), and a gate capping layer (125). In this specification, 'gate (120, WL)' may be referred to as a structure comprising a gate dielectric layer (120) and a word line (WL), the word line (WL) may be referred to as a 'gate electrode', and the word line structure (WLS) may be referred to as a 'gate structure'.

[0033] Word lines (WL) may be arranged to extend in a first direction (X) across an active region (ACT). For example, a pair of adjacent word lines (WL) may be arranged to cross one active region (ACT). Word lines (WL) may constitute the gate of a buried channel array transistor (BCAT), but are not limited thereto. In exemplary embodiments, word lines (WL) may have a form in which they are arranged on the upper surface of the substrate (101). Word lines (WL) may be arranged with a predetermined thickness on the lower surface of the gate trench (115). The upper surface of the word lines (WL) may be located at a lower level than the upper surface of the substrate (101). As used herein, the high and low of the term "level" may be defined with respect to the substantially flat upper surface of the substrate (101).

[0034] The word line (WL) may include at least one of a conductive material, for example, polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). As an example, the word line (WL) may include a lower pattern and an upper pattern formed of different materials, wherein the lower pattern may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN), and the upper pattern may be a semiconductor pattern comprising polysilicon doped with P-type or N-type impurities.

[0035] The gate dielectric layer (120) may be disposed on the bottom surface and inner surface of the gate trench (115). The gate dielectric layer (120) may conformally cover the inner wall of the gate trench (115). The gate dielectric layer (120) may comprise at least one of silicon oxide, silicon nitride, and silicon oxynitride. The gate dielectric layer (120) may be, for example, a silicon oxide film or an insulating film having a high dielectric constant. In exemplary embodiments, the gate dielectric layer (120) may be a layer formed by oxidizing the active region (ACT) or a layer formed by deposition.

[0036] The gate capping layer (125) may be positioned to fill the gate trench (115) above the word line (WL). The upper surface of the gate capping layer (125) may be located at substantially the same level as the upper surface of the substrate (101). The gate capping layer (125) may be formed of an insulating material, for example, silicon nitride.

[0038] The bit line structure (BLS) may be extended in one direction, for example, in a second direction (Y), perpendicular to the word line (WL). The bit line structure (BLS) may include a bit line (BL) and a bit line capping pattern (BC) on the bit line (BL).

[0039] A bit line (BL) may include a first conductive pattern (141), a second conductive pattern (142), and a third conductive pattern (143) stacked in sequence. A bit line capping pattern (BC) may be placed on the third conductive pattern (143). A buffer insulating layer (128) may be placed between the first conductive pattern (141) and the substrate (101), and a portion of the first conductive pattern (141) (hereinafter, bit line contact pattern (DC)) may be in contact with the first impurity region (105a) of the active region (ACT). The bit line (BL) may be electrically connected to the first impurity region (105a) through the bit line contact pattern (DC). The lower surface of the bit line contact pattern (DC) may be located at a lower level than the upper surface of the substrate (101) and may be located at a higher level than the upper surface of the word line (WL). In an exemplary embodiment, a bit line contact pattern (DC) may be formed within a substrate (101) and locally disposed within a bit line contact hole that exposes a first impurity region (105a).

[0040] The first conductive pattern (141) may include a semiconductor material such as polycrystalline silicon. The first conductive pattern (141) may be in direct contact with the first impurity region (105a). The second conductive pattern (142) may include a metal-semiconductor compound. The metal-semiconductor compound may, for example, be a layer in which a portion of the first conductive pattern (141) has been silicided. For example, the metal-semiconductor compound may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. The third conductive pattern (143) may include a metallic material such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). The number of conductive patterns forming the bit line (BL), the type of material, and / or the stacking order may vary depending on the embodiments.

[0041] The bit line capping pattern (BC) may include a first capping pattern (146), a second capping pattern (147), and a third capping pattern (148) stacked sequentially on the third conductive pattern (143). The first to third capping patterns (146, 147, 148) may each include an insulating material, for example, a silicon nitride film. The first to third capping patterns (146, 147, 148) may be made of different materials, and even if they include the same material, the boundaries may be distinguished by differences in physical properties. The thickness of the second capping pattern (147) may be smaller than the thickness of the first capping pattern (146) and the thickness of the third capping pattern (148), respectively. The number of capping patterns and / or types of materials forming the bit line capping pattern (BC) may vary depending on the embodiments.

[0043] Spacer structures (SS) may be positioned on both side walls of each of the bit line structures (BLS) and may extend in one direction, e.g., the Y direction. Spacer structures (SS) may be positioned between the bit line structure (BLS) and the lower conductive pattern (150). Spacer structures (SS) may be positioned to extend along the side walls of the bit line (BL) and the side walls of the bit line capping pattern (BC). A pair of spacer structures (SS) positioned on both sides of a single bit line structure (BLS) may have an asymmetrical shape with respect to the bit line structure (BLS). Each of the spacer structures (SS) may include a plurality of spacer layers and may further include air spacers according to embodiments.

[0045] The lower conductive pattern (150) may be connected to one area of ​​the active region (ACT), for example, the second impurity region (105b). The lower conductive pattern (150) may be placed between the bit lines (BL) and between the word lines (WL). The lower conductive pattern (150) may be connected to the second impurity region (105b) of the active region (ACT) by penetrating the buffer insulating layer (128). The lower conductive pattern (150) may be in direct contact with the second impurity region (105b). The lower surface of the lower conductive pattern (150) may be located at a lower level than the upper surface of the substrate (101) and at a higher level than the lower surface of the bit line contact pattern (DC). The lower conductive pattern (150) may be insulated from the bit line contact pattern (DC) by a spacer structure (SS). The lower conductive pattern (150) may be made of a conductive material and may include, for example, at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In an exemplary embodiment, the lower conductive pattern (150) may include a plurality of layers.

[0046] A metal-semiconductor compound layer (155) may be disposed between the lower conductive pattern (150) and the upper conductive pattern (160). The metal-semiconductor compound layer (155) may be, for example, a layer in which a portion of the lower conductive pattern (150) is silicided, where the lower conductive pattern (150) comprises a semiconductor material. The metal-semiconductor compound layer (155) may include, for example, cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. Depending on the embodiments, the metal-semiconductor compound layer (155) may be omitted.

[0048] An upper conductive pattern (160) may be placed on a lower conductive pattern (150). The upper conductive pattern (160) may extend between spacer structures (SS) to cover the upper surface of a metal-semiconductor compound layer (155). The upper conductive pattern (160) may include a barrier layer (162) and a conductive layer (164). The barrier layer (162) may cover the lower surface and sides of the conductive layer (164). The barrier layer (162) may include at least one of a metal nitride, for example, titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). The conductive layer (164) may include at least one of a conductive material, for example, polycrystalline silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

[0050] Insulating patterns (165) may be positioned to penetrate the upper conductive pattern (160). The upper conductive pattern (160) may be separated into multiple parts by the insulating patterns (165). The insulating patterns (165) may include at least one insulating material, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0052] The capacitor structure (CAP) will be described in detail below with reference to Fig. 3.

[0053] The etch stop layer (168) may cover the insulating patterns (165) between the lower electrodes (170). The etch stop layer (168) may be in contact with the lower regions of the sides of the lower electrodes (170). The etch stop layer (168) may be positioned below the support layers (171, 172). The upper surface of the etch stop layer (168) may include a portion exposed from the first interface film (175) and in direct contact with the dielectric layer (180). The etch stop layer (168) may include, for example, at least one of silicon nitride and silicon oxynitride.

[0055] Lower electrodes (170) may be placed on upper conductive patterns (160). Lower electrodes (170) may penetrate the etch stop layer (168) and come into contact with the upper conductive patterns (160). Lower electrodes (170) may be in the shape of a cylinder or may have a hollow cylinder or cup shape. At least one support layer (171, 172) supporting the lower electrodes (170) may be provided between adjacent lower electrodes (170). For example, as shown in FIG. 3, a first support layer (171) and a second support layer (172) in contact with the first electrode pattern (170A) and the second electrode pattern (170B) may be provided between the first electrode pattern (170A) and the second electrode pattern (170B) that are adjacent to each other among the lower electrodes (170). Each of the lower electrodes (170) may include at least one of polycrystalline silicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al).

[0057] The support layers (171, 172) may include a first support layer (171) and a second support layer (172) on the first support layer (171). The support layers (171, 172) may be in contact with the lower electrodes (170) and may extend in a direction parallel to the upper surface of the substrate (101). Each of the upper and lower surfaces of the support layers (171, 172) may include a region spaced apart from the first interface film (175). For example, each of the upper and lower surfaces of the support layers (171, 172) may include a portion exposed from the first interface film (175) and in direct contact with the dielectric layer (180). The second support layer (172) may have a thicker thickness than the first support layer (171), but is not limited thereto. The support layers (171, 172) may be layers that support lower electrodes (170) having a high aspect ratio. Each of the support layers (171, 172) may comprise, for example, at least one of silicon nitride and silicon oxynitride, or a similar material. The number, thickness, and / or arrangement relationship of the support layers (171, 172) are not limited to those illustrated and may vary according to the embodiments.

[0059] The dielectric layer (180) may cover a first interface film (175) formed on the surface of the lower electrodes (170). The dielectric layer (180) may be disposed between the first interface film (175) and the second interface film (185). The dielectric layer (180) may cover portions exposed from the first interface film (175) on the upper and lower surfaces of each of the support layers (171, 172). The dielectric layer (180) may cover portions exposed from the first interface film (175) on the upper surface of the etch stop layer (168). The dielectric layer (180) may be in contact with at least a portion of the upper and lower surfaces of each of the support layers (171, 172). The dielectric layer (180) may comprise a high dielectric material or silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, depending on the embodiments, the dielectric layer (180) may include an oxide, nitride, silicide, oxynitride, or silicide-oxynitride comprising one of hafnium (Hf), aluminum (Al), zirconium (Zr), and lanthanum (La). The dielectric layer (180) may cover the first interface film (175), and the second interface film (185) may cover the dielectric layer (180). By forming the first interface film (175) and the second interface film (185), leakage current within the capacitor structure (CAP) can be reduced, and the capacitance of the capacitor structure (CAP) can be increased.

[0061] The first interface film (175) may be disposed between the lower electrodes (170) and the dielectric layer (180) and may extend conformally along the surface of the lower electrodes (170). However, the first interface film (175) may extend intermittently around the etch stop layer (168) and the support layers (171, 172). For example, the first interface film (175) may not extend horizontally along the upper and lower surfaces of the support layers (171, 172). The first interface film (175) may include a first interface pattern (175A) in contact with the first electrode pattern (170A) and a second interface pattern (175B) in contact with the second electrode pattern (170B), and the first interface pattern (175A) and the second interface pattern (175B) may be disposed between the first electrode pattern (170A) and the second electrode pattern (170B) and may be spaced apart from each other in the horizontal direction. The first interface pattern (175A) and the second interface pattern (175B) may be disposed between the etch stop layer (168) and the first support layer (171) and between the first support layer (171) and the second support layer (172).

[0062] The first interface film (175) may include a plurality of layers (71, 72). The plurality of layers (71, 72) may include a metal, a metal nitride, a metal oxide, or a metal oxynitride. The plurality of layers (71, 72) may include, for example, a first layer (71) and a second layer (72) that include different metal elements as the central metal element, and may commonly include at least one of oxygen (O) and nitrogen (N). The first layer (71) may be formed of a first metal element, and the second layer (72) may be formed of a second metal element different from the first metal element, and the second metal element may diffuse by mutual substitution with the first metal element during the process of forming the first interface film (175). The first metal element may be the same as the central metal element forming the lower electrodes (170). The first metal element and the second metal element may each correspond to any one of tin (Sn), molybdenum (Mo), neobium (Nb), tantalum (Ta), titanium (Ti), indium (In), nickel (Ni), cobalt (Co), tungsten (W), ruthenium (Ru), zirconium (Zr), and hafnium (Hf). The interface between the plurality of layers (71, 72) may be distinguished, but if it is difficult to distinguish the interface, the type and concentration distribution (or profile) of the elements included in the plurality of layers (71, 72) can be confirmed through X-ray fluorescence spectrometry (XRF), X-ray photoelectron spectrometry (XPS), or secondary ion mass spectrometry (SIMS). Since the thickness of each layer of the first layer (71) and the second layer (72) is thin and diffusion of material occurs within them, even if it is difficult to distinguish the interface between the first layer (71) and the second layer (72), at least three or more elements or at least four or more elements can be detected in the first interface film (175).

[0063] The first interface film (175) is formed of a plurality of layers (71, 72), and the diffusion by mutual substitution of the first metal element and the second metal element may occur relatively less in the region where the first interface film (175) is adjacent to the etching stop layer (168) and the support layers (171, 172). Accordingly, the concentration of the second metal element contained in the first interface film (175) may decrease as it gets closer to the etching stop layer (168) and the support layers (171, 172). For example, the first interface film (175) includes a first region and a second region, the first region is adjacent to the support layers (171, 172) than the second region, the first interface film (175) in the first region contains the second metal element at a first concentration, the first interface film (175) in the second region contains the second metal element at a second concentration, and the first concentration may be smaller than the second concentration.

[0064] When the first interface film (175) is formed as a plurality of layers (71, 72), the first interface film (175) may have etch resistance for selective etching for subsequent node separation due to diffusion between metal materials. For example, the etch resistance of the first interface film (175) in the region adjacent to the lower electrodes (170) containing the first metal element may be higher than the etch resistance of the first interface film (175) formed around the support layers (171, 172). Thus, during the selective etching process, a portion of the first interface film (175) may be left on the lower electrodes (170), while a portion of the first interface film (175) may be selectively removed on the support layers (171, 172) and the etch stop layer (168). That is, when the first interface film (175) is formed in multiple layers, selective etching is easier than when it is formed in a single layer, so the occurrence of electrical bridges between the lower electrodes (170) can be reduced, and the first interface film (175) can be left on the surface of the lower electrodes (170) to improve the electrical characteristics of the capacitor structure (CAP).

[0065] In one example, the lower electrodes (170) may include an oxidized oxide region from a surface adjacent to the first interface film (175). For example, the lower electrodes (170) may be formed of titanium nitride (TiN) and may include titanium oxynitride (TiON) in a region adjacent to the first interface film (175).

[0067] The second interface film (185) may be conformally extended along the surface of the dielectric layer (180). The second interface film (185) may be continuously extended around the etch stop layer (168) and the support layers (171, 172). For example, the second interface film (185) may include a portion that extends horizontally in an area adjacent to the support layers (171, 172).

[0068] The second interface film (185) may include a plurality of layers (81, 82). The plurality of layers (81, 82) may include a metal, a metal nitride, a metal oxide, or a metal oxynitride. The plurality of layers (81, 82) may include, for example, a first layer (81) and a second layer (82) that include different metal elements as the central metal element, and may commonly include at least one of oxygen (O) and nitrogen (N). Each metal element forming the first layer (81) and the second layer (82) may correspond to any one of tin (Sn), molybdenum (Mo), neobium (Nb), tantalum (Ta), titanium (Ti), indium (In), nickel (Ni), cobalt (Co), tungsten (W), ruthenium (Ru), zirconium (Zr), and hafnium (Hf). Since the second interface film (185) covers the front surface of the dielectric layer (180) and the upper electrode (190) covers the front surface of the second interface film (185), leakage current within the capacitor structure (CAP) can be reduced and the capacitance of the capacitor structure (CAP) can be increased. Therefore, the electrical characteristics of the capacitor structure (CAP) can be improved.

[0070] FIGS. 4 to 6 are partially enlarged cross-sectional views illustrating an enlarged area including a capacitor of a semiconductor device according to exemplary embodiments. FIGS. 4 to 6 illustrate an area corresponding to region 'A' of FIG. 2.

[0072] Referring to FIG. 4, the first interface film (175) of the semiconductor device (100A) may include a portion (175R) whose thickness decreases as it gets closer to the support layers (171, 172). For example, the first interface film (175) may include a first region and a second region, wherein the second region is positioned closer to the support layers (171, 172) than the first region, and the first distance (d1) between the first interface pattern (175A) and the second interface pattern (175B) in the first region may be greater than the second distance (d2) between the first interface pattern (175A) and the second interface pattern (175B) in the second region. Alternatively, the thickness (t1) of the first interface film (175) in the first region may be smaller than the thickness (t2) of the first interface film (175) in the second region. The first interface film (175) has a side profile as shown in FIG. 4 between the first electrode pattern (170A) and the second electrode pattern (170B), and the dielectric layer (180), the second interface film (185), and the upper electrode (190) may also have sides corresponding to the side profile of the first interface film (175). For example, the dielectric layer (180) placed between the first electrode pattern (170A) and the second electrode pattern (170B) may include a portion that is curved toward the lower electrodes (170). The first interface film (175) may also include a portion whose thickness decreases as it approaches the etch stop layer (168).

[0073] Referring to FIG. 5, the capacitor structure (CAP) of the semiconductor device (100B) may not include a second interface film (185) on the dielectric layer (180), and the upper electrode (190) may be in direct contact with the dielectric layer (180). The first interface film (175) may include a portion in which the concentration of the second metal element decreases as it gets closer to the support layers (171, 172) and the etch stop layer (168), or a portion in which the thickness decreases.

[0074] Referring to FIG. 6, an oxidized region (170_o) may be formed inwardly from a surface adjacent to a first interface film (175) at the lower electrodes (170) of a semiconductor device (100C), and the oxidized region (170_o) may form part of the first interface film (175) together with a plurality of layers (71, 72). The oxidized region (170_o) may include, for example, titanium oxide or titanium oxynitride, and the region (170_e) excluding the oxidized region (170_o) of the lower electrodes (170) may include titanium or titanium nitride, but is not limited thereto.

[0076] FIGS. 7 to 14 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 7 to 14 illustrate the process of forming a capacitor structure located in region 'A' of FIG. 2.

[0078] First, referring to FIG. 2, an active region (ACT) can be defined by forming a device isolation layer (110) on a substrate (101). A device isolation trench can be formed on the substrate (101), and the device isolation layer (110) can fill the device isolation trench. Planar, the active region (ACT) may be in the shape of an elongated bar extending in an oblique direction to the extension direction of the word line (WL). Impurity regions can be formed on top of the active region (ACT) by performing an ion implantation process using the device isolation layer (110) as an ion implantation mask. A gate trench (115) can be formed by patterning the active region (ACT) and the device isolation layer (110). A pair of gate trenches (115) may cross the active region (ACT), but are not limited thereto. The impurity regions can also be separated by the gate trench (115) to form a first impurity region (105a) and a second impurity region (105b).

[0079] A gate dielectric layer (120) can be formed on the inner surface of the gate trench (115) with a substantially conformal thickness. Subsequently, a word line (WL) can be formed to fill at least a portion of the gate trench (115). The upper surface of the word line (WL) can be recessed so as to be lower than the upper surface of the active region (ACT). An insulating layer can be laminated on the substrate (101) to fill the gate trench (115) and etched to form a gate capping layer (125) on the word line (WL).

[0080] An insulating layer and a conductive layer can be formed sequentially on the front surface of a substrate (101) and patterned to form a buffer insulating layer (128) and a first conductive pattern (141) that are stacked sequentially. The buffer insulating layer (128) can be formed from at least one of silicon oxide, silicon nitride, and silicon oxynitride. A plurality of buffer insulating layers (128) can be formed in a spaced-apart manner. The first conductive pattern (141) can have a shape corresponding to the planar shape of the buffer insulating layer (128). The buffer insulating layer (128) can be formed to simultaneously cover the ends of two adjacent active regions (ACT), that is, adjacent second impurity regions (105b). Bit line contact holes can be formed by etching the upper portions of the device isolation layer (110), the substrate (101), and the gate capping layer (125) using the buffer insulating layer (128) and the first conductive pattern (141) as an etching mask. The bit line contact hole can expose the first impurity region (105a).

[0081] A bit line contact pattern (DC) that fills a bit line contact hole can be formed. Forming the bit line contact pattern (DC) may include forming a conductive layer that fills the bit line contact hole and performing a planarization process. As an example, the bit line contact pattern (DC) may be formed of polysilicon. After forming a second conductive pattern (142), a third conductive pattern (143), and first to third capping patterns (146, 147, 148) in sequence on a first conductive pattern (141), the first to third conductive patterns (141, 142, 143) may be etched in sequence using the first to third capping patterns (146, 147, 148) as an etching mask. As a result, a bit line structure (BLS) can be formed including a bit line (BL) including first to third challenge patterns (141, 142, 143) and a bit line capping pattern (BC) including first to third capping patterns (146, 147, 147).

[0082] Spacer structures (SS) can be formed on the sides of the bit line structure (BLS). The spacer structures (SS) can be formed of multiple layers. Fence insulation patterns (154) can be formed between the spacer structures (SS). The fence insulation patterns (154) may include silicon nitride or silicon oxynitride. An anisotropic etching process can be performed using the fence insulation patterns (154) and the third capping pattern (148) as an etching mask to form an opening that exposes the second impurity region (105b).

[0083] A lower conductive pattern (150) can be formed at the bottom of the opening. The lower conductive pattern (150) can be formed from a conductive material such as polysilicon. For example, the lower conductive pattern (150) can be formed by forming a polysilicon layer that fills the opening and then performing an etch-back process.

[0084] A metal-semiconductor compound layer (155) can be formed on the lower conductive pattern (150). The formation of the metal-semiconductor compound layer (155) may include a metal layer deposition process and a heat treatment process.

[0085] An upper conductive pattern (160) may be formed on the upper portion of the first opening. Forming the upper conductive pattern (160) may include forming a barrier layer (162) and a conductive layer (164) in sequence. Subsequently, a patterning process may be performed on the barrier layer (162) and the conductive layer (164) to form insulating patterns (165) that penetrate therefrom. Accordingly, a lower structure including a substrate (101), a word line structure (WLS), and a bit line structure (BLS), etc., may be formed.

[0086] Next, referring to FIG. 7, an etch stop layer (168) may be conformally formed on the substructure, and mold layers (118) and pre-support layers (171', 172') may be alternately stacked on the etch stop layer (168). The etch stop layer (168) may include at least one insulating material having etch selectivity under specific etching conditions with the mold layers (118), for example, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon carbonitride. The mold layers (118) may include a first mold layer (118a) and a second mold layer (118b) on the first mold layer (118a). A first pre-support layer (171') may be formed between a first mold layer (118a) and a second mold layer (118b), and a second pre-support layer (172') may be formed on the second mold layer (118b). For example, the mold layers (118) may be formed of silicon oxide, and the pre-support layers (171', 172') may be formed of silicon nitride.

[0088] Referring to FIG. 8, a plurality of holes (H) can be formed penetrating the mold layers (118) and the pre-support layers (171', 172'). In the step of forming the plurality of holes (H), the etch stop layer (168) can act as a stopper to stop the progress of the etching process. The plurality of holes (H) can penetrate the etch stop layer (168) to expose the upper conductive patterns (160). The plurality of holes (H) are areas where the lower electrodes (170) are to be formed, and can be formed in a regular arrangement spaced apart at a predetermined interval on a plane, as shown in FIG. 1.

[0090] Referring to FIG. 9, a plurality of holes (H) can be filled with a conductive material to form lower electrodes (170). The lower electrodes (170) can be formed to be connected to an upper conductive pattern (160) at the bottom of the plurality of holes (H). Forming the lower electrodes (170) may include forming a layer of conductive material inside the plurality of holes (H) and on the plurality of holes (H), and performing a planarization process, for example, a chemical mechanical polishing (CMP) process, on the conductive material layer. Through this, the lower electrodes (170) can be formed into a plurality of node-separated and spaced-apart patterns.

[0092] Referring to FIG. 10, a separate mask may be formed on the second pre-support layer (172'), and at least a portion of the mold layers (118) and pre-support layers (171', 172') may be removed using the mask. Accordingly, the pre-support layers (171', 172') may be formed into support layers (171, 172). The support layers (171, 172) may be patterned according to the structure of the mask to have a shape including a plurality of openings. The support layers (171, 172) may connect adjacent lower electrodes (170) to each other. The mold layers (118) may be selectively removed with respect to the support layers (171, 172). The above mask can be removed after etching the mold layers (118) or while etching the mold layers (118).

[0094] Referring to FIG. 11, a first interface film (175) can be conformally formed on the substructure. The first interface film (175) can be formed of a plurality of layers (71, 72), and the plurality of layers (71, 72) can be formed using, for example, at least one of Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or a doping process. The first interface film (175) covers the lower electrodes (170) and can be formed to cover both the exposed upper and lower surfaces of the etch stop layer (168) and the support layers (171, 172). During the formation of the first interface film (175), the lower electrodes (170) may also be partially oxidized from the surface.

[0096] Referring to FIG. 12, a selective etch process can be performed on the first interface film (175). When the first interface film (175) is formed of a conductive material, adjacent lower electrodes (170) can be electrically connected to each other. To electrically separate the lower electrodes (170), a portion formed on the support layers (171, 172) and the etch stop layer (168) of the first interface film (175) can be removed. The first interface film (175) is formed of a plurality of layers (71, 72), but as previously mentioned, since there is a difference in the concentration of metal elements contained in the first interface film (175), during the selective etch process, the first interface film (175) can be left on the lower electrodes (170) and selectively removed on the support layers (171, 172) and the etch stop layer (168). In this step, as described above, the first interface film (175) formed on the etching stop layer (168) can also be optionally and easily removed.

[0097] In one example, energy capable of diffusing metal elements within the lower electrodes (170) or the first layer (71) may be required when forming the first interface film (175). To this end, in this step, plasma treatment, annealing treatment, ozone treatment, or extreme ultraviolet treatment processes may be performed in-situ simultaneously with the deposition of the first interface film (175). Alternatively, it may be possible to apply energy ex-situ by performing the above post-treatment processes after the first interface film (175) has been deposited.

[0098] In one example, the first interface film (175) may be formed to have a first thickness on the lower electrodes (170), a second thickness smaller than the first thickness on the support layers (171, 172), and a third thickness smaller than the first thickness and equal to or similar to the second thickness on the etch stop layer (168), so that the etching process may be performed such that the first interface film (175) remains only on the lower electrodes (170).

[0100] Referring to FIG. 13, after performing a selective etching process, a dielectric layer (180) can be formed on the first interface film (175). The dielectric layer (180) can be formed conformally on the underlying structure. The dielectric layer (180) can cover the first interface film (175), support layers (171, 172), and etch stop layer (168). During the process of forming the dielectric layer (180), at least one of the components of the dielectric layer (180), for example, hafnium (Hf) or zirconium (Zr), can diffuse or migrate into the first interface film (175).

[0102] Referring to FIG. 14, a second interface film (185) can be formed on the dielectric layer (180). The second interface film (185) can be conformally formed on the underlying structure. The second interface film (185) can cover the dielectric layer (180). The second interface film (185) can be formed of a plurality of layers (81, 82), and the plurality of layers (81, 82) can be formed using, for example, at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), or a doping process.

[0104] Next, referring to FIG. 3, an upper electrode (190) can be formed on the second interface film (185). Thus, a capacitor structure (CAP) comprising lower electrodes (170), a dielectric layer (180), an upper electrode (190), and the first interface film (175) and the second interface film (185) can be formed on the lower structure, and a semiconductor device (100) including the same can be manufactured.

[0106] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, changes, and combinations of embodiments may be made by those skilled in the art without departing from the technical spirit of the invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0108] 100: Semiconductor device 105a, 105b: Impurity region 110: Device isolation layer 115: Gate trench 120: Gate dielectric layer 125: Gate capping layer 141, 142, 143: Challenge Patterns 146, 147, 148: Capping Patterns 150: Lower conductive pattern 155: Metal-semiconductor compound layer 160: Upper conduction pattern 162: Barrier layer 164: Conductive layer 165: Insulation pattern 170: Lower electrode 175: First interface film 180: Dielectric layer 85: Second interface film 190: Top electrode ACT: Active area BL: Bit Line WL: Word Line

Claims

Claim 1 A substrate; a plurality of lower electrodes disposed on the substrate; at least one support layer in contact with the plurality of lower electrodes and extending in a direction parallel to the upper surface of the substrate; a dielectric layer on the lower electrodes; an upper electrode on the dielectric layer; a first interface film between the lower electrodes and the dielectric layer; A semiconductor device comprising a second interface film between the upper electrode and the dielectric layer, wherein at least one of the first interface film and the second interface film comprises a plurality of layers, and each of the upper surface and lower surface of the at least one supporter layer comprises a region spaced apart from the first interface film, wherein the plurality of layers comprise at least one element among oxygen (O) and nitrogen (N), a first metal element, and a second metal element different from the first metal element, wherein the lower electrodes comprise the first metal element, wherein the first interface film comprises a first region and a second region, wherein the first region is adjacent to the at least one supporter layer than the second region, wherein in the first region the first interface film comprises the second metal element at a first concentration, wherein in the second region the first interface film comprises the second metal element at a second concentration, and wherein the first concentration is smaller than the second concentration. Claim 2 A semiconductor device according to claim 1, wherein the first metal element and the second metal element are each selected from tin (Sn), molybdenum (Mo), neobium (Nb), tantalum (Ta), titanium (Ti), indium (In), nickel (Ni), cobalt (Co), tungsten (W), ruthenium (Ru), zirconium (Zr), and hafnium (Hf). Claim 3 A semiconductor device according to claim 1, wherein the first interface film comprises a plurality of first layers and the second interface film comprises a plurality of second layers. Claim 4 A semiconductor device according to claim 3, wherein the plurality of first layers extend intermittently around the at least one support layer, and the plurality of second layers extend continuously around the at least one support layer. Claim 5 A semiconductor device according to claim 3, further comprising an etching stop layer disposed below the at least one support layer and in contact with lower regions of the sides of the plurality of lower electrodes, wherein the plurality of first layers extend vertically on the upper surface of the etching stop layer but do not extend horizontally along the surface of the at least one support layer in a region adjacent to the at least one support layer. Claim 6 A semiconductor device comprising: a substrate; a plurality of lower electrodes disposed on the substrate; a support layer extending in a direction parallel to the upper surface of the substrate while in contact with the plurality of lower electrodes; a dielectric layer on the lower electrodes; an upper electrode on the dielectric layer; a first interface film between the lower electrodes and the dielectric layer; and a second interface film between the upper electrode and the dielectric layer, wherein at least one of the first interface film and the second interface film comprises a plurality of layers, and the first interface film comprises a portion having a thickness that decreases as it approaches the support layer. Claim 7 A semiconductor device according to claim 6, wherein the plurality of lower electrodes include a first electrode pattern and a second electrode pattern disposed adjacently with the supporter layer in between, and the first interface film includes a first interface pattern in contact with the first electrode pattern and a second interface pattern in contact with the second electrode pattern. Claim 8 In claim 7, the first interface pattern and the second interface pattern are spaced apart from each other in a semiconductor device. Claim 9 A semiconductor device according to claim 7, wherein the first interface film comprises a first region and a second region, the first region is positioned closer to the support layer than the second region, and the first distance between the first interface pattern and the second interface pattern in the first region is greater than the second distance between the first interface pattern and the second interface pattern in the second region. Claim 10 A device isolation layer defining active regions on a substrate; gate electrodes extending into the device isolation layer across the active regions; first impurity regions and second impurity regions disposed within the active regions on both sides of the gate electrodes; bit lines disposed on the gate electrodes and electrically connected to the first impurity regions; upper conductive patterns disposed on the sides of the bit lines and electrically connected to the second impurity regions; lower electrodes extending perpendicularly on the upper conductive patterns and connected to the upper conductive patterns, wherein the lower electrodes include a first electrode pattern and a second electrode pattern adjacent to each other; at least one supporter layer disposed between the first electrode pattern and the second electrode pattern and in contact with the first electrode pattern and the second electrode pattern; an upper electrode on the lower electrodes; a dielectric layer between the lower electrodes and the upper electrode; and a first interface film between the lower electrodes and the dielectric layer. A semiconductor device comprising a second interface film between the upper electrode and the dielectric layer, wherein each of the upper and lower surfaces of the at least one supporter layer includes a portion exposed from the first interface film and in direct contact with the dielectric layer, and at least one of the first interface film and the second interface film includes a plurality of layers, wherein the lower electrodes, the upper electrode, the first interface film, and the second interface film commonly include a first metal element, wherein the first interface film includes a second metal element different from the first metal element, and the first interface film includes a portion in which the concentration of the second metal element decreases as it approaches the at least one supporter layer.

Images