Universal logic memory block using a plurality of universal logic memory cells

Abstract

The present invention relates to a general-purpose logic memory block using a plurality of general-purpose logic memory cells. A general-purpose logic memory block according to one embodiment of the present invention can implement various combinational logic operations in a single structure by combining the results of logic operations in a plurality of general-purpose logic memory cells using triple-gate silicon devices driven by a positive feedback loop.

Description

Technology Field

[0001] The present invention relates to a general-purpose logic memory block using a plurality of general-purpose logic memory cells, and more specifically, to a technology for implementing a general-purpose logic memory block that implements various combinational logic operations in a single structure by combining the results of logic operations in a plurality of general-purpose logic memory cells using triple-gate silicon devices driven by a positive feedback loop. Background Technology

[0002] In existing von Neumann-based computer systems, the processor and memory are separated, and data is transmitted via a bus.

[0003] However, as computing performance increased, bottlenecks occurred due to the difference in data processing speeds between processors and memory, and limitations in processing large amounts of data began to be revealed.

[0004] In other words, while Von Neumann-based systems, a revolutionary advancement in the semiconductor industry, improved the integration density and performance of modern computers, they have the disadvantage of consuming a lot of energy and having long data transmission and latency times due to the physical separation between the processor and memory hierarchy.

[0005] Given the increase in data-intensive applications such as 5G communication standards, the Internet of Things (IoT), and artificial intelligence (AI) since the Fourth Industrial Revolution, a new computing paradigm is essential for large-scale data processing requirements.

[0006] To solve the aforementioned problems, research on logic-in-memory (LIM) technology, which fuses computation and memory functions, is being concentrated and accelerated.

[0007] Because logic memory technology performs the computational functions of a processor and the memory functions of memory in the same space, it can reduce latency and power consumption during data transmission and significantly improve the integration density of the system.

[0008] Conventional logic memory technology has been actively researched based on volatile memory devices such as SRAM (static random access memory) and DRAM (dynamic RAM), and non-volatile memory devices such as ReRAM (resistive RAM), MRAM (magnetoresistive RAM), and PCRAM (phase-change RAM).

[0009] Logic memory technology based on volatile memory devices has limitations in that it requires a large number of transistors for stable operation, resulting in high overall area and power consumption.

[0010] Furthermore, logic memory technology based on non-volatile memory devices requires complex manufacturing processes due to the use of non-silicon materials, and commercialization is difficult due to low device uniformity and stability.

[0011] In addition, previously studied logic memory technologies have low integration density because they cannot implement all basic CMOS logic operations in a single cell and require individual circuits and wiring depending on the logic operation.

[0012] Therefore, there is a need to develop general-purpose logic memory cell technology that can be fabricated using a silicon-based CMOS process, performs all basic logic operations within a single cell, and stores the value.

[0013] Conventional logic memory technology has been researched using various types of memory, including volatile memory devices such as DRAM (dynamic random access memory) and SRAM (static RAM), and non-volatile memory devices such as PRAM (phase-change RAM), ReRAM (resistive RAM), and MRAM (magnetoresistive RAM).

[0014] However, since they cannot define n-channels and p-channels, there are difficulties in applying them to existing CMOS logic operations.

[0015] In particular, logic-memory technology based on non-volatile memory devices requires new process steps rather than silicon-based CMOS processes, and is difficult to commercialize due to low device uniformity and reliability.

[0016] Combinational logic operations are performed in a structure where basic logic operations are arranged sequentially, and since a logic operation circuit of a specific structure is required for each logic operation, there are difficulties in improving integration density. Prior art literature

[0017] Korean Registered Patent No. 10-2475066, "Variable logic-in-memory cell" Korean Published Patent No. 10-2023-0020840, "Variable logic-in-memory device using silicon transistor" Korean Published Patent No. 10-2022-0145226, "Multi-operation circuit and multiplication-accumulation operator and processing-in-memory device including the same" Korean Published Patent No. 10-2022-0014996, "Semiconductor memory device" The problem to be solved

[0018] The present invention aims to implement a general-purpose logic memory block that implements various combinational logic operations in a single structure by combining the results of logic operations in a plurality of general-purpose logic memory cells using triple-gate silicon devices driven by a positive feedback loop.

[0019] The present invention aims to implement a general-purpose logic memory block that performs a combinational logic operation by combining the results of a logic operation using a CMOS process and stores the results of the combinational logic operation.

[0020] The present invention aims to implement a general-purpose logic memory cell by utilizing a triple-gate silicon device, which is a silicon-based feedback memory device using a conventional CMOS process, and to implement a general-purpose logic memory block capable of performing binary combinational logic operations in a general-purpose logic memory block using the general-purpose logic memory cell and storing the result of the operation.

[0021] The present invention aims to improve processing speed and integration limitations caused by data bottlenecks through the convergence of logical operation and storage functions.

[0022] The present invention aims to implement a general-purpose logic memory block that significantly improves computational efficiency compared to existing CMOS logic circuits by performing various binary combinational logic operations in a single structure through the channel mode reconstruction characteristics of a triple-gate silicon device.

[0023] The present invention aims to improve standby power efficiency by utilizing channel mode reconfiguration characteristics to maintain logical operation values ​​without structural changes or external bias, thereby providing excellent memory characteristics. means of solving the problem

[0024] A general-purpose logic memory block according to one embodiment of the present invention includes a general-purpose logic memory cell comprising a first network element and a second network element using a plurality of triple-gate silicon elements, a switch box that determines the direction of an input voltage applied to the general-purpose logic memory cell and an output voltage output from the general-purpose logic memory cell, and a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell, and in a structure in which a plurality of general-purpose logic memory cells are arranged according to a preset, combinational logic operation functions and memory functions can be performed according to the interconnection control for the logic operation functions of the general-purpose logic memory cells according to the direction of the determined input voltage and output voltage.

[0025] According to the above configuration, the general-purpose logic memory cells are arranged in a plurality of rows and a plurality of columns, the switch box and the line switch are arranged between the general-purpose logic memory cells, the number of the line switches is determined to correspond to the number of input voltages transmitted through the switch box, and the combinational logic operation function can be implemented with at least one output based on the output voltage.

[0026] The above switch box has a first input voltage (V) to a general-purpose logic memory cell operating as an XOR gate and a general-purpose logic memory cell operating as an AND gate among the general-purpose logic memory cells arranged in the above plurality of rows and columns, among the general-purpose logic memory cells operating as a logic operation function. IN1 ) and the second input voltage (V IN2 It is possible to apply ) and control the output from the general-purpose logic memory cell operating as the XOR gate to be output as a sum (S), and the output from the general-purpose logic memory cell operating as the AND gate to be output as a carry (COUT).

[0027] The above switch box provides a first input voltage (V) to a general-purpose logic memory cell operating as a first XOR gate and a second XOR gate and a general-purpose logic memory cell operating as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in the above plurality of rows and columns. IN1 ), second input voltage (V IN2 ) and third input voltage (V CIN It is possible to apply ) and control the output from the general-purpose logic memory cell operating as the second XOR gate to be output as a sum (S), and the output from the general-purpose logic memory cell operating as the first AND gate and the second AND gate to be transmitted to the input of the general-purpose logic memory cell operating as an OR gate, and then control the output voltage to be output as a carry number (COUT).

[0028] The above switch box inputs an input voltage (V) to a general-purpose logic memory cell that operates as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in the plurality of rows and plurality of columns. IN ) is applied, and a selection voltage (V) is applied to a general-purpose logic memory cell that operates as a NOT gate among the above logic operation functions. S It is possible to control the output from the general-purpose logic memory cell operating as the first AND gate to be output as the first output (OUT1), and the output from the general-purpose logic memory cell operating as the second AND gate to be output as the second output (OUT2).

[0029] The above switch box has a first input voltage (V) to a general-purpose logic memory cell that operates as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in the plurality of rows and plurality of columns. IN1 ) and the second input voltage (V IN2 Applying ) and a selection voltage (V) to a general-purpose logic memory cell operating as a NOT gate among the above logic operation functions. SIt is possible to apply ) and control the output from the general-purpose logic memory cell operating as the first AND gate and the output from the general-purpose logic memory cell operating as the second AND gate to be transmitted to the input of the general-purpose logic memory cell operating as the OR gate, and then output the output voltage to the output (OUT).

[0030] The above switch box has a first input voltage (V) to a general-purpose logic memory cell operating as a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate among the general-purpose logic memory cells arranged in the plurality of rows and columns, and to a general-purpose logic memory cell operating as a first NOT gate and a second NOT gate among the logic operation functions. IN1 ) and the second input voltage (V IN2 ) can be selectively applied, and the output of the general-purpose logic memory cell operating with the first AND gate can be controlled to the first output (OUT1), the output of the general-purpose logic memory cell operating with the second AND gate can be controlled to the second output (OUT2), the output of the general-purpose logic memory cell operating with the third AND gate can be controlled to the fourth output (OUT4), and the output of the general-purpose logic memory cell operating with the fourth AND gate can be controlled to the third output (OUT3).

[0031] The above switch box provides a second input voltage (V) to a general-purpose logic memory cell operating as a first OR gate and a second OR gate among the general-purpose logic memory cells arranged in the plurality of rows and plurality of columns. IN2 ), third input voltage (V IN3 ) and the fourth input voltage (V IN4 ) can be applied, and the output of the general-purpose logic memory cell operating as the first OR gate can be controlled as the first output (OUT1), and the output of the general-purpose logic memory cell operating as the second OR gate can be controlled as the second output (OUT2).

[0032] The above switch box has a first input voltage (V) to a general logic memory cell operating as an XNOR gate and an XOR gate, a general logic memory cell operating as a first NOT gate and a second NOT gate, and a general logic memory cell operating as a first AND gate and a second AND gate among the general logic memory cells arranged in the plurality of rows and columns. IN1 ) and the second input voltage (V IN2 ) can be selectively applied, and the output of the general-purpose logic memory cell operating as the XNOR gate can be controlled to the first output (OUT1), the output of the general-purpose logic memory cell operating as the XOR gate can be controlled to the second output (OUT2), the output of the general-purpose logic memory cell operating as the second AND gate can be controlled to the third output (OUT3), and the output of the general-purpose logic memory cell operating as the first AND gate can be controlled to the fourth output (OUT4).

[0033] The above switch box provides a first input voltage (V) to a general-purpose logic memory cell operating as a first XOR gate and a second XOR gate among the general-purpose logic memory cells arranged in the plurality of rows and plurality of columns. IN1 ), second input voltage (V IN2 ) and third input voltage (V IN3 ) is selectively applied, and the first input voltage (V IN1 ) can be controlled as a first output (OUT1), the output of a general-purpose logic memory cell operating as a first XOR gate can be controlled as a second output (OUT2), and the output of a general-purpose logic memory cell operating as a second XOR gate can be controlled as a third output (OUT3).

[0034] The above general-purpose logic memory cell includes a first network element and a second network element using a plurality of triple-gate silicon elements, each of the plurality of triple-gate silicon elements includes a drain region, a channel region, and a source region, a supply voltage is applied to the drain region and the source region, and includes a gate region in which first and second programming gate electrodes and a control gate electrode are formed on the channel region, and a program voltage (V) applied through the first and second programming gate electrodes. PG Depending on the level of ), the channel region under the first and second programming gate electrodes in the channel region performs either the first channel mode or the second channel mode, and the control voltage (V) applied through the control gate electrode CG It is determined to be either an on state or an off state based on the level of ), and the first network element and the second network element have an output voltage (V) that changes according to the one state in the one channel mode performed above. OUT Depending on the level of ), the above logical operation function and memory function can be performed.

[0035] The first network element and the second network element are composed of a first parallel connection section in which a common drain region is connected between a first series connection section in which the drain region and source region of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, and a second parallel connection section in which a common source region is connected between a second series connection section in which the drain region and source region of the remaining two triple-gate silicon elements are connected in series, and a drain voltage (V) among the common voltages is connected through the first parallel connection section of the first network element. DD) is applied, and through the second parallel connection of the second network element, the source voltage (V) among the common voltages is applied. SS ) is applied, and at the part where the second parallel connection part of the first network element and the first parallel connection part of the second network element are connected, an output voltage (V) to any one of the above is applied. OUT ) can be measured.

[0036] The above triple-gate silicon device has a drain region in a p-doped state, a source region in an n-doped state, and a channel region in an intrinsic state, and the channel region below the first and second programming gate electrodes in the channel region is the programming voltage (V PG When the level of ) is a positive level, it operates as n channels corresponding to the first channel mode, and the program voltage (V PG When the level of ) is a voice level, it can operate as a p channel corresponding to the second channel mode above.

[0037] The above general-purpose logic memory cell is a drain voltage (V) applied to the drain region. DD ), source voltage (V) applied to the source region SS ), the above program voltage (V PG ) and the control voltage (V CG When ) is applied at a zero level, the output voltage (V OUT The above memory function can be performed by maintaining the level of ). Effects of the invention

[0038] The present invention can implement a general-purpose logic memory block that implements various combinational logic operations in a single structure by combining the results of logic operations in a plurality of general-purpose logic memory cells using triple-gate silicon devices driven by a positive feedback loop.

[0039] The present invention can implement a general-purpose logic memory block that performs a combinational logic operation by combining the results of a logic operation using a CMOS process and stores the results of the combinational logic operation.

[0040] The present invention implements a general-purpose logic memory cell by utilizing a triple-gate silicon device, which is a silicon-based feedback memory device using a conventional CMOS process, and can implement a general-purpose logic memory block capable of performing binary combinational logic operations in a general-purpose logic memory block using the general-purpose logic memory cell and storing the result of the operation.

[0041] The present invention can improve processing speed and integration limitations caused by data bottlenecks through the fusion of logical operation and storage functions.

[0042] The present invention can implement a general-purpose logic memory block that significantly improves computational efficiency compared to existing CMOS logic circuits by performing various binary combinational logic operations in a single structure through the channel mode reconstruction characteristics of a triple-gate silicon device.

[0043] The present invention can improve standby power efficiency by utilizing channel mode reconfiguration characteristics to maintain logical operation values ​​without structural changes or external bias, thereby providing excellent memory characteristics. Brief explanation of the drawing

[0044] FIGS. 1a and 1b are drawings illustrating a triple-gate silicon device constituting a general-purpose logic memory cell according to an embodiment of the present invention. FIGS. 2a to 2c are drawings illustrating the operating principle of a triple-gate silicon device according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a general-purpose logic memory cell according to an embodiment of the present invention. FIGS. 4a to 4e are drawings illustrating binary logic operations of a general-purpose logic memory cell according to an embodiment of the present invention. FIG. 5 is a diagram illustrating a general-purpose logic memory block using a plurality of general-purpose logic memory cells according to an exemplary embodiment of the present invention. FIGS. 6 and 7 are drawings illustrating the operation of a half adder of a general-purpose logic memory block according to an embodiment of the present invention. FIGS. 8 and 9 are drawings illustrating the operation of a full adder of a general-purpose logic memory block according to an embodiment of the present invention. FIGS. 10 and FIGS. 11 are drawings illustrating the operation of a demultiplexer of a general-purpose logic memory block according to an embodiment of the present invention. FIGS. 12 and FIGS. 13 are drawings illustrating the operation of a multiplexer of a general-purpose logic memory block according to an embodiment of the present invention. FIGS. 14 and FIGS. 15 are drawings illustrating the decoder operation of a general-purpose logic memory block according to an embodiment of the present invention. FIGS. 16 and FIGS. 17 are drawings illustrating the encoder operation of a general-purpose logic memory block according to an embodiment of the present invention. FIGS. 18 and 19 are drawings illustrating the operation of a bit comparator of a general-purpose logic memory block according to an embodiment of the present invention. FIGS. 20 and 21 are drawings illustrating the operation of a bit binary to gray code converter of a general-purpose logic memory block according to an embodiment of the present invention. Specific details for implementing the invention

[0045] Hereinafter, various embodiments of this document are described with reference to the attached drawings.

[0046] The embodiments and terms used therein are not intended to limit the technology described in this document to specific embodiments and should be understood to include various modifications, equivalents, and / or substitutions of said embodiments.

[0047] In describing various embodiments below, if it is determined that a detailed description of related known functions or configurations could unnecessarily obscure the essence of the invention, such detailed description will be omitted.

[0048] Furthermore, the terms described below are defined considering their functions in various embodiments, and these may vary depending on the intentions or practices of the user or operator. Therefore, their definitions should be based on the content throughout this specification.

[0049] In relation to the description of the drawings, similar reference numerals may be used for similar components.

[0050] A singular expression may include a plural expression unless the context clearly indicates otherwise.

[0051] In this document, expressions such as "A or B" or "at least one of A and / or B" may include all possible combinations of the items listed together.

[0052] Expressions such as "first," "second," "first," or "second" may modify the relevant components regardless of order or importance, and are used merely to distinguish one component from another without limiting the components.

[0053] Where it is stated that a certain (e.g., first) component is "(functionally or telecommunicationally) connected" or "connected" to another (e.g., second) component, said certain component may be directly connected to said other component or connected through another component (e.g., third component).

[0054] In this specification, "configured to" may be used interchangeably with, depending on the context, for example, in hardware or software, "suitable for," "capable of," "modified to," "made to," "capable of," or "designed to."

[0055] In some situations, the expression "device configured to..." may mean that the device is "able to..." together with other devices or parts.

[0056] For example, the phrase “a processor configured (or set) to perform A, B, and C” may mean a dedicated processor for performing said operations (e.g., an embedded processor), or a general-purpose processor capable of performing said operations by executing one or more software programs stored in a memory device (e.g., a CPU or an application processor).

[0057] Also, the term 'or' means an inclusive disjunction rather than an exclusive disjunction.

[0058] That is, unless otherwise noted or is not clear from the context, the expression 'x uses a or b' means any one of the natural inclusive permutations.

[0059] Terms such as '..bu', '..gi' used below refer to a unit that processes at least one function or operation, and this may be implemented in hardware or software, or a combination of hardware and software.

[0061] FIGS. 1a and 1b are drawings illustrating a triple-gate silicon device constituting a general-purpose logic memory cell according to an embodiment of the present invention.

[0062] FIG. 1a illustrates the structure of a triple-gate silicon device constituting a general-purpose logic memory cell according to an embodiment of the present invention.

[0063] Referring to FIG. 1a, a triple gate silicon device (100) according to one embodiment of the present invention includes a drain region (101), a channel region (102), a source region (103), and a gate region, and the gate region includes first and second programming gate electrodes (106) and a control gate electrode (105) formed on a gate insulating film (104).

[0064] For example, a drain electrode may be connected to the drain region (101) to apply a drain voltage, and a source electrode may be connected to the source region (103) to apply a source voltage.

[0065] According to one embodiment of the present invention, a triple-gate silicon device (100) includes a drain region (101), a channel region (102), and a source region (103) which are pin nanostructures.

[0066] For example, the drain region (101) may be in a p-doped state, the source region (103) may be in an n-doped state, and the channel region (102) may be in an intrinsic state.

[0067] In the channel region (102), the channel region below the first and second programming gate electrodes (106) is the programming voltage (V PG When the level of ) is a positive level, it operates as n channels corresponding to the first channel mode, and the program voltage (V PG When the level of ) is a voice level, it can operate as a p channel corresponding to the second channel mode.

[0068] The triple-gate silicon device (100) can be composed of multiple units to form a general-purpose logic memory cell.

[0069] That is, the triple-gate silicon device (100) is composed of multiple units to form a general-purpose logic memory cell, some of which may be composed of a first network device and some of which may be composed of a second network device.

[0070] A triple-gate silicon device (100) has a program voltage (V) applied through the first and second programming gate electrodes (106). PG Depending on the level of ), the channel region under the first and second programming gate electrodes (106) in the channel region can perform either the first channel mode or the second channel mode.

[0071] Additionally, the triple-gate silicon device (100) has a control voltage (V) applied through the control gate electrode. CG It can be determined to be either an on state or an off state based on the level of ).

[0072] Therefore, the general-purpose logic memory cell has an output voltage (V) that changes according to a certain state in any one of the previously performed channel modes. OUT Logical operation functions and memory functions can be performed based on the level of ).

[0073] For example, as the first and second programming gate electrodes (106) are electrically connected, the same programming voltage (V) at once PG ) may be authorized.

[0074] FIG. 1b illustrates circuit symbols related to the operating state of a general-purpose logic memory cell according to an embodiment of the present invention.

[0075] Referring to FIG. 1b, the circuit symbol (111) according to one embodiment of the present invention illustrates a circuit symbol when the channel region of a triple-gate silicon device performs a first channel mode and operates as an n-channel.

[0076] For example, the circuit symbol (110) illustrates a circuit symbol in which the channel region of a triple-gate silicon device performs a second channel mode and operates as a p-channel.

[0077] Circuit symbols (110) and (111) represent a structure in which, in a nanostructure comprising a drain region, a channel region, a source region, and a gate region, a first and second programming gate electrode and a control gate electrode are formed in the gate region to connect a programming gate terminal (PG) and a control gate terminal (CG), a drain electrode is formed in the drain region to connect a drain terminal (D), and a source electrode is formed in the source region to connect a source terminal (S).

[0078] The circuit symbol (111) indicates that the triple-gate silicon device is in the first channel mode state through the channel mode state region.

[0079] In other words, the circuit symbol (111) can represent the channel mode state region in a solid form to indicate that the triple-gate silicon device is operating in n-channel mode.

[0080] The circuit symbol (110) indicates that the triple-gate silicon device is in a second channel mode state through the channel mode state region.

[0081] The circuit symbol (110) can represent the channel mode state region as empty to indicate that the triple-gate silicon device is operating as a p-channel.

[0082] For example, a triple-gate silicon device can be referred to as a triple-gate feedback field-effect device.

[0084] FIGS. 2a to 2c are drawings illustrating the operating principle of a triple-gate silicon device according to an embodiment of the present invention.

[0085] FIG. 2a illustrates the operating principle when a triple-gate silicon device according to an embodiment of the present invention operates as a p-channel.

[0086] Referring to FIG. 2a, in the case where a triple-gate silicon device (200) according to one embodiment of the present invention receives a positive voltage through the drain terminal and a negative voltage corresponding to a negative level of program voltage is applied at the programming gate terminal, the channel region below the programming gate electrode (PG) among the channel regions is programmed as a p-channel and operates as a p-channel.

[0087] When a triple-gate silicon device (200) according to one embodiment of the present invention operates as a p-channel, the operating state is determined to be ON when the level of the control voltage applied through the control gate terminal is lower than the latch-up voltage, which is the voltage when the current increases rapidly, and is determined to be OFF when the level of the applied control voltage is higher than the latch-up voltage.

[0088] For example, a triple-gate silicon device is determined to be on or off based on the level of the control voltage applied through the control gate terminal.

[0089] The on and off operating states of the triple-gate silicon device can be further explained through the energy band (201) corresponding to the off state and the energy band (202) corresponding to the on state.

[0090] When a triple-gate silicon device according to one embodiment of the present invention operates as a p-channel, the energy band (202) when in the ON state and the energy band (201) when in the OFF state can be identified based on the level of the control voltage.

[0091] According to the energy band (201) and energy band (202), when the channel region under the first and second programming gate electrodes in the channel region performs a second channel mode corresponding to a p-channel mode, the control voltage (V CGWhen the level of ) is reduced to a level lower than the latch-up voltage, the height of the potential barrier between the channel region below the control gate electrode and the channel region below the first programming gate electrode adjacent to the drain region is lowered, and due to the lowered potential barrier, a second positive feedback loop occurs in which holes are injected from the drain region, and the ON state is reached in which current flows.

[0092] That is, the triple-gate silicon device can switch from the energy band (201) to the energy band (202) by generating a second positive feedback loop.

[0093] It can be confirmed that the repeated injection and accumulation of charge generate a positive feedback loop, switching to an ON state where current flows.

[0094] For example, the second positive feedback loop may be a positive feedback loop in which holes become the majority carriers in the channel region.

[0095] FIG. 2b illustrates the operating principle when a triple-gate silicon device according to an embodiment of the present invention operates as an n-channel.

[0096] Referring to FIG. 2b, in the case where a triple gate silicon device (210) according to one embodiment of the present invention receives a negative voltage through a source terminal and a positive voltage corresponding to a positive level of program voltage is applied at a programming gate terminal, the channel region below the programming gate electrode (PG) among the channel regions is programmed as n channels and operates as n channels.

[0097] For example, a triple-gate silicon device is determined to be on or off based on the level of the control voltage applied through the control gate terminal.

[0098] When a triple gate silicon device (210) according to one embodiment of the present invention operates as an n-channel, the operating state is determined to be on when the level of the control voltage applied through the control gate terminal is higher than the latch-up voltage, which is the voltage when the current increases rapidly, and is determined to be off when the level is lower than the latch-up voltage.

[0099] When a triple-gate silicon device according to one embodiment of the present invention operates as an n-channel, an energy band (211) is exemplified when it is in an off state based on the level of the control voltage, and an energy band (212) is exemplified when it is in an on state.

[0100] Referring to the energy band (211) and energy band (212), when the channel region under the first and second programming gate electrodes in the channel region performs the first channel mode corresponding to the n-channel mode, the control voltage (V CG When the level of ) increases to a level higher than the latch-up voltage, the height of the potential barrier between the channel region below the control gate electrode and the channel region below the second programming gate electrode adjacent to the source region is lowered, and due to the lowered potential barrier, a first positive feedback loop occurs in which electrons are injected from the source region, and the ON state is reached in which current flows.

[0101] That is, the triple-gate silicon device is switched from the energy band (201) to the energy band (202) by the occurrence of a first positive feedback loop.

[0102] It can be confirmed that the repeated injection and accumulation of charge generate a positive feedback loop, switching to an ON state where current flows.

[0103] For example, the first positive feedback loop may be a positive feedback loop in which electrons become majority carriers in the channel region.

[0104] FIG. 2c illustrates the operation related to the first and second positive feedback loops when a triple-gate silicon device according to an embodiment of the present invention operates as an n-channel and a p-channel.

[0105] Referring to FIG. 2c, graph (220) shows the operating characteristics of the n-channel mode of the triple-gate silicon device, and graph (221) shows the operating characteristics of the p-channel mode of the triple-gate silicon device.

[0106] Graph (220) shows that when a triple-gate silicon device operating in n-channel mode has an on state and an off state depending on the voltage applied to the control gate electrode, if the control gate voltage is smaller than the latch-up voltage which is the voltage when the current increases rapidly, the flow of electrons and holes is blocked by the potential barrier and the device has an off state. It also shows that as the control gate voltage increases and becomes larger than the latch-up voltage, electrons in the source region are injected into the channel by crossing the potential barrier and accumulate in the potential well adjacent to the drain region, and the height of the potential barrier decreases.

[0107] Accordingly, holes in the drain region are injected into the channel and accumulate in the potential well adjacent to the source region, and the potential barrier height is lowered.

[0108] The repeated injection and accumulation of charge generate a positive feedback loop, resulting in an ON state where current flows.

[0109] Graph (221) shows that for a triple-gate silicon device operating in p-channel mode, when the control gate voltage is greater than the latch-up voltage, the flow of electrons and holes is blocked by the potential barrier and the device becomes off, and when the control gate voltage decreases to become less than the latch-up voltage, holes in the drain region are injected into the channel by crossing the potential barrier and accumulate in the potential well adjacent to the source region, and the height of the potential barrier decreases.

[0110] According to one embodiment of the present invention, a triple-gate silicon device may be a device in which a first positive feedback loop or a second positive feedback loop is formed according to the level of a control voltage applied to a gate region, and the on or off state in a first channel mode and a second channel mode is variably controlled together. Here, the first channel mode is an n-channel mode and the second channel mode is a p-channel mode.

[0111] In addition, triple-gate silicon devices are turned on as charge carriers accumulate in the potential wells of the channel region, forming a positive feedback loop, which can be utilized as a memory function to store data in the channel region.

[0112] Accordingly, the present invention can implement a general-purpose logic memory cell by utilizing a triple-gate silicon device, which is a silicon-based feedback memory device using a conventional CMOS process.

[0114] FIG. 3 is a diagram illustrating a general-purpose logic memory cell according to an embodiment of the present invention.

[0115] FIG. 3 illustrates a circuit diagram of a general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements according to an embodiment of the present invention.

[0116] Referring to FIG. 3, a general-purpose logic memory cell (300) according to one embodiment of the present invention is composed of a first network element (310) and a second network element (311), and the first network element (310) and the second network element (311) are composed of a plurality of triple-gate silicon elements (301).

[0117] More specifically, the first network element (310) and the second network element (311) are composed of a first parallel connection unit in which a common drain area is connected between a first series connection unit in which the drain area and source area of ​​two of the four triple-gate silicon elements are connected in series, and a second parallel connection unit in which a common source area is connected between a second series connection unit in which the drain area and source area of ​​the remaining two triple-gate silicon elements are connected in series.

[0118] The first network element (310) may be referred to as a pull-up network element, and the second network element (311) may be referred to as a pull-down network element.

[0119] According to one embodiment of the present invention, a general-purpose logic memory cell (300) performs a memory function that maintains a preset voltage state by controlling the supply voltage, the voltage corresponding to the voltage applied to the program gate electrode, and the input voltage applied to the control gate electrode to "0".

[0120] According to one embodiment of the present invention, each of the first network element (310) and the second network element (311) is composed of four triple-gate silicon elements and may be referred to as two triple-gate silicon elements divided into upper, lower, left, and right sides, or as one triple-gate silicon element divided into upper left, upper right, lower left, and lower right sides.

[0121] The triple-gate silicon devices arranged at each position can be selectively driven in either a first channel mode or a second channel mode.

[0122] The above-described configuration can be changed according to the arrangement of network elements, and can be referred to by variations depending on the changed connection configuration.

[0123] The first network element (310) is a drain voltage (V) among the common voltages through the first parallel connection of the first network element (310). DD ) is authorized.

[0124] The second network element (311) is a source voltage (V) among the common voltages through the second parallel connection of the second network element (311). SS ) is authorized.

[0125] A general-purpose logic memory cell (300) according to one embodiment of the present invention has an output voltage (V) at the portion where the second parallel connection portion of the first network element (310) and the first parallel connection portion of the second network element (311) are connected. OUT ) can be measured.

[0126] The general-purpose logic memory cell (300) is composed of a first network element (310) and a second network element (311), and a drain voltage (V) according to the operating state of the triple-gate silicon element (301). DD ) and source voltage (V SS ) is the output voltage (V OUT Implement logical operations based on the content measured in ).

[0127] A general-purpose logic memory cell (300) according to one embodiment of the present invention utilizes a plurality of triple-gate silicon elements.

[0128] Each of the plurality of triple-gate silicon devices includes a drain region, a channel region, and a source region, and a supply voltage is applied to the drain region and the source region, and includes a gate region in which a first and second programming gate electrode and a control gate electrode are formed on the channel region.

[0129] In addition, each of the plurality of triple-gate silicon devices has a program voltage (V) applied through the first and second programming gate electrodes. PGDepending on the level of ), the channel region under the first and second programming gate electrodes in the channel region operates in either the first channel mode or the second channel mode, and the control voltage (V) applied through the control gate electrode CG It can be determined to be either an on state or an off state based on the level of ).

[0130] The first network element (310) and the second network element (311) can perform logical operation functions and memory functions according to one of the determined states in one of the previously performed channel modes.

[0131] Logical operation functions are logical operation functions related to NOT, YES, NAND, NOR, AND, OR, XNOR, and XOR gates.

[0132] Accordingly, the present invention can implement a general-purpose logic memory cell that provides logic operation and memory functions by using a triple-gate silicon device driven by a positive feedback loop.

[0133] In addition, the present invention can implement a general-purpose logic memory cell that performs all basic logic operations in a single structure and stores the operation results by using a triple-gate silicon device.

[0135] FIG. 4a is a diagram illustrating the NOT gate operation of a general-purpose logic memory cell according to an embodiment of the present invention.

[0136] FIG. 4a illustrates a circuit diagram and a timing diagram in the NOT gate operation of a general-purpose logic memory cell according to an embodiment of the present invention.

[0137] Referring to FIG. 4a, a general-purpose logic memory cell (400) according to one embodiment of the present invention performs a second channel mode with triple-gate silicon devices constituting a first network device based on a programming voltage applied through a programming gate terminal (PG), and performs a first channel mode with triple-gate silicon devices constituting a second network device.

[0138] At this time, the general-purpose logic memory cell (400) is a control voltage (V), which is an input voltage (IN) applied through the control gate terminal (CG). CG The output voltage (V) measured through the output terminal when the level of ) is an audio level OUT The level of ) is a positive level, and the control voltage (V CG When the level of ) is a positive level, the output voltage (V OUT The level of ) can perform a logical operation function corresponding to a NOT gate operation at a voice level.

[0139] The timing diagram (401) is the input voltage (V) of the voice level corresponding to "0". IN The positive level output voltage (V) corresponding to "1" when ) is applied OUT ) is an example of the output resulting from a logical operation.

[0140] Additionally, the timing diagram (401) is a positive level input voltage (V) corresponding to "1". IN The output voltage (V) of the voice level corresponding to "0" when ) is applied OUT ) is an example of the output resulting from a logical operation.

[0141] Also, the supply voltage (V SUP ), program voltage (V PG ), input voltage (V IN It indicates that it performs a memory function that maintains (Holds) the calculated logical value even when ) is removed.

[0142] For example, supply voltage (V SUP ) is the drain voltage (V DD ) and source voltage (VSS It is composed of ), and the program voltage (VPG) is the program voltage (V) corresponding to the n-channel. PG N ) and the program voltage (V) corresponding to the p-channel PG P It consists of ).

[0143] Additionally, the general-purpose logic memory cell, based on the programming voltage applied through the programming gate terminal (PG), triple-gate silicon devices constituting the first network element perform a first channel mode, triple-gate silicon devices constituting the second network element perform a second channel mode, and the control voltage (V), which is the input voltage (IN) applied through the control gate terminal (CG), CG The output voltage (V) measured through the output terminal when the level of ) is a positive level OUT The level of ) is a positive level, and the control voltage (V CG When the level of ) is at the voice level, the output voltage (V OUT The level of ) can perform a logical operation function corresponding to a YES gate operation at a voice level.

[0145] FIG. 4b is a diagram illustrating the AND gate operation of a general-purpose logic memory cell according to an exemplary embodiment of the present invention.

[0146] FIG. 4b illustrates a circuit diagram and timing diagram in the AND gate operation of a general-purpose logic memory cell according to an embodiment of the present invention.

[0147] Referring to FIG. 4b, a general-purpose logic memory cell (410) according to one embodiment of the present invention performs a first channel mode with triple-gate silicon devices constituting a first network device based on a programming voltage applied through a programming gate terminal (PG), and performs a second channel mode with triple-gate silicon devices constituting a second network device.

[0148] In addition, the general-purpose logic memory cell (410) has a control voltage (V CGAmong ), the first control voltage (IN1) is applied to the upper side of the first network element and the left side of the second network element, and the control voltage (V CG The second control voltage (IN2) among them is applied to the lower side of the first network element and the right side of the second network element.

[0149] Accordingly, the general-purpose logic memory cell (410) has a first control voltage (V IN1 ) and the second control voltage (V IN2 When any one of the levels of ) is a voice level, the output voltage (V OUT Performs a logical operation to determine the level of ) as the voice level.

[0150] In addition, the general-purpose logic memory cell (410) has a first control voltage (V IN1 ) and the second control voltage (V IN2 When the levels of ) are all positive, the output voltage (V OUT Performs an AND gate operation to determine the level of ) as a positive level.

[0151] The timing diagram (411) has two input voltages (V IN1 , V IN2 When inputs corresponding to "00", "01" and "10" and "11" are applied to ), the output voltage (V OUT It indicates that binary logical operation functions are performed as values ​​corresponding to "0", "0", "0" and "1" are operated on in ).

[0152] Also, the supply voltage (V SUP ), program voltage (V PG ), input voltage (V IN1 , V IN2 It indicates that it performs a memory function that maintains (Holds) the calculated logical value even when ) is removed.

[0153] For example, supply voltage (V SUP ) is the drain voltage (V DD ) and source voltage (V SS It consists of ), and the program voltage (VPG ) is the program voltage (V) corresponding to the n-channel PG N ) and the program voltage (V) corresponding to the p-channel PG P It consists of ).

[0155] FIG. 4c is a diagram illustrating the OR gate operation of a general-purpose logic memory cell according to an exemplary embodiment of the present invention.

[0156] FIG. 4c illustrates a circuit diagram and timing diagram in the operation of an OR gate of a general-purpose logic memory cell according to an embodiment of the present invention.

[0157] Referring to FIG. 4c, a general-purpose logic memory cell (420) according to one embodiment of the present invention performs a first channel mode with triple-gate silicon devices constituting a first network device based on a programming voltage applied through a programming gate terminal (PG), and performs a second channel mode with triple-gate silicon devices constituting a second network device.

[0158] In addition, the general-purpose logic memory cell (420) has a control voltage (V CG Among ), the first control voltage (IN1) is applied to the left side of the first network element and the upper side of the second network element, and the control voltage (V CG The second control voltage (IN2) among them is applied to the right side of the first network element and the lower side of the second network element.

[0159] Accordingly, the general-purpose logic memory cell (420) has a first control voltage (V IN1 ) and the second control voltage (V IN2 When any one of the levels of ) is a positive level, the output voltage (V OUT Determine the level of ) as a positive level.

[0160] In addition, the general-purpose logic memory cell (420) has a first control voltage (V IN1 ) and the second control voltage (V IN2When the levels of ) are all at voice levels, the output voltage (V OUT Determine the level of ) as the voice level.

[0161] Timing diagram (421) has two input voltages (V IN1 , V IN2 When inputs corresponding to "00", "01" and "10" and "11" are applied to ), the output voltage (V OUT It indicates that binary logical operation functions are performed as values ​​corresponding to "0", "1", "1" and "1" are operated on in ).

[0162] Also, the supply voltage (V SUP ), program voltage (V PG ), input voltage (V IN1 , V IN2 It indicates that it performs a memory function that maintains (Holds) the calculated logical value even when ) is removed.

[0163] For example, supply voltage (V SUP ) is the drain voltage (V DD ) and source voltage (V SS It consists of ), and the program voltage (V PG ) is the program voltage (V) corresponding to the n-channel PG N ) and the program voltage (V) corresponding to the p-channel PG P It consists of ).

[0165] FIG. 4d is a diagram illustrating the operation of an XNOR gate of a general-purpose logic memory cell according to an exemplary embodiment of the present invention.

[0166] FIG. 4d illustrates a circuit diagram and timing diagram in the operation of an XNOR gate of a general-purpose logic memory cell according to an embodiment of the present invention.

[0167] Referring to FIG. 4d, a general-purpose logic memory cell (430) according to an embodiment of the present invention has a triple-gate silicon element constituting a first network element, the left side performs a first channel mode and the right side performs a second channel mode, and among the triple-gate silicon elements constituting a second network element, the upper left side performs a second channel mode and the upper right side performs a first channel mode, the lower left side performs a first channel mode and the lower right side performs a second channel mode.

[0168] A general-purpose logic memory cell (430) according to one embodiment of the present invention has a control voltage (V CG ) among the first control voltage (V IN1 ) is applied to the upper side of the first network element and the second network element, and a control voltage (V CG ) among the second control voltage (V IN2 ) is applied to the lower side of the first network element and the second network element.

[0169] According to one embodiment of the present invention, the general-purpose logic memory cell (430) has a first control voltage (V IN1 ) and the second control voltage (V IN2 When the levels of ) are at the same level, the output voltage (V OUT Outputs the level of ) as a positive level, and the first control voltage (V IN1 ) and the second control voltage (V IN2 If the levels of ) are different, the output voltage (V OUT It can perform an XNOR logic operation function to determine the level of ) as the voice level.

[0170] Timing diagram (431) has two input voltages (V IN1 , V IN2 When inputs corresponding to "00", "01" and "10" and "11" are applied to ), the output voltage (V OUT It indicates that binary logical operation functions are performed as values ​​corresponding to "1", "0", "0" and "1" are operated on in ).

[0171] Also, the supply voltage (V SUP ), program voltage (V PG ), input voltage (V IN1 , V IN2 It indicates that it performs a memory function that maintains (Holds) the calculated logical value even when ) is removed.

[0172] For example, supply voltage (V SUP ) is the drain voltage (V DD ) and source voltage (V SS It consists of ), and the program voltage (V PG ) is the program voltage (V) corresponding to the n-channel PG N ) and the program voltage (V) corresponding to the p-channel PG P It consists of ).

[0174] FIG. 4e is a diagram illustrating the operation of an XOR gate of a general-purpose logic memory cell according to an exemplary embodiment of the present invention.

[0175] FIG. 4e illustrates a circuit diagram and timing diagram in the operation of an XOR gate of a general-purpose logic memory cell according to an embodiment of the present invention.

[0176] Referring to FIG. 4e, a general-purpose logic memory cell (440) according to an embodiment of the present invention has a triple-gate silicon element constituting a first network element, the upper left side performs a second channel mode, the upper right side performs a first channel mode, the lower left side performs a first channel mode, the lower right side performs a second channel mode, and the left side of the triple-gate silicon element constituting a second network element performs a first channel mode, and the right side performs a second channel mode.

[0177] A general-purpose logic memory cell (440) according to one embodiment of the present invention has a control voltage (V CG ) among the first control voltage (V IN1 ) is applied to the upper side of the first network element and the second network element, and a control voltage (VCG ) among the second control voltage (V IN2 ) is applied to the lower side of the first network element and the second network element.

[0178] For example, the general-purpose logic memory cell (440) has a first control voltage (V IN1 ) and the second control voltage (V IN2 When the levels of ) are all positive or all negative, the output voltage (V OUT Determine the level of ) as the voice level.

[0179] In addition, the general-purpose logic memory cell (440) has a first control voltage (V IN1 ) and the second control voltage (V IN2 When the levels of ) are different, the output voltage (V OUT Outputs the level of ) as a positive level.

[0180] Timing diagram (441) has two input voltages (V IN1 , V IN2 When inputs corresponding to "00", "01" and "10" and "11" are applied to ), the output voltage (V OUT It indicates that binary logical operation functions are performed as values ​​corresponding to "0", "1", "1" and "0" are operated on in ).

[0181] Also, the supply voltage (V SUP ), program voltage (V PG ), input voltage (V IN1 , V IN2 It indicates that it performs a memory function that maintains (Holds) the calculated logical value even when ) is removed.

[0182] For example, supply voltage (V SUP ) is the drain voltage (V DD ) and source voltage (V SS It consists of ), and the program voltage (V PG ) is the program voltage (V) corresponding to the n-channel PG N ) and the program voltage (V) corresponding to the p-channel PGP It consists of ).

[0183] Therefore, the present invention can improve processing speed and integration limitations caused by data bottlenecks through the fusion of logical operation and storage functions.

[0184] In addition, the present invention can improve standby power efficiency by utilizing channel type variable characteristics to maintain logical operation values ​​without structural changes or external bias, thereby providing excellent memory characteristics.

[0186] FIG. 5 is a diagram illustrating a general-purpose logic memory block using a plurality of general-purpose logic memory cells according to an exemplary embodiment of the present invention.

[0187] FIG. 5 illustrates the components of a general-purpose logic memory block using a plurality of general-purpose logic memory cells according to an embodiment of the present invention.

[0188] Referring to FIG. 5, according to one embodiment of the present invention, a general-purpose logic memory block (500) includes a general-purpose logic memory cell (510) comprising a first network element and a second network element using a plurality of triple-gate silicon elements, and is implemented using a plurality of such cells.

[0189] For example, the switch box (520) can determine the direction of the input voltage applied to the general-purpose logic memory cell and the output voltage output from the general-purpose logic memory cell (510).

[0190] A line switch (530) according to one embodiment of the present invention controls the interconnection between a switch box (520) and a general-purpose logic memory cell (510).

[0191] According to one embodiment of the present invention, a general-purpose logic memory block (500) can perform combinational logic operation functions and memory functions according to interconnection control of the logic operation functions of the general-purpose logic memory cells (510) according to the direction of the input voltage and output voltage determined in a structure in which a plurality of general-purpose logic memory cells (510) are arranged according to a preset configuration.

[0192] For example, in a general-purpose logic memory block (500), the general-purpose logic memory cells (510) are arranged in a plurality of rows and a plurality of columns according to a preset configuration, and a switch box (520) and a line switch (530) are arranged between the general-purpose logic memory cells (510).

[0193] The number of line switches (530) in the general-purpose logic memory block (500) is determined to correspond to the number of input voltages transmitted through the switch box (520), and a combinational logic operation function is implemented with at least one output based on the output voltage.

[0194] The general-purpose logic memory block (500) can implement various combinational logic operation functions in a single structure as the general-purpose logic memory cell (510) selectively implements binary logic operation functions.

[0195] Combinational logic operation functions are implemented through a combination of logic operation functions related to NOT, YES, NAND, NOR, AND, OR, XNOR, and XOR gates based on binary logic operation functions.

[0196] Combinational logic operation functions may include half adder operations, full adder operations, demultiplexer operations, multiplexer operations, encoder operations, bit comparator operations, bit binary to gray code converter operations, etc.

[0197] The general-purpose logic memory block (500) can implement not only the aforementioned combinational logic operation function but also various combinations of logic operations in a single structure.

[0198] Combinational logic operations are performed in a structure where basic logic operations are arranged sequentially, and since the structure is designed to allow interconnection between the input / output ports of each cell, when an input voltage is applied, various combinational logic operations are performed according to the logic gate type and connection method of each cell, and the results of the performed operations can be stored.

[0199] Accordingly, the present invention can implement a general-purpose logic memory cell by utilizing a triple-gate silicon device, which is a silicon-based feedback memory device using a conventional CMOS process, and can implement a general-purpose logic memory block capable of performing binary combinational logic operations in a general-purpose logic memory block using the general-purpose logic memory cell and storing the result of the operation.

[0201] FIGS. 6 and 7 are drawings illustrating the operation of a half adder of a general-purpose logic memory block according to an embodiment of the present invention.

[0202] FIG. 6 illustrates a structure related to the half-adder operation of a general-purpose logic memory block according to an embodiment of the present invention.

[0203] Referring to FIG. 6, a general-purpose logic memory block (600) according to an embodiment of the present invention implements a half-adder operation based on the control of a switch box (620) and a line switch (630) for a general-purpose logic memory cell (610) operating as an XOR gate and a general-purpose logic memory cell (611) operating as an AND gate.

[0204] The switch box (620) has a first input voltage (V) to a general-purpose logic memory cell (610) that operates as an XOR gate and a general-purpose logic memory cell (611) that operates as an AND gate among the general-purpose logic memory cells arranged in multiple rows and multiple columns. IN1 ) and the second input voltage (V IN2 authorizes ).

[0205] Additionally, the switch box (620) controls the output from the general-purpose logic memory cell (610) operating as an XOR gate to be output as a sum (S), and the output from the general-purpose logic memory cell (611) operating as an AND gate to be output as a carry number (COUT).

[0206] FIG. 7 illustrates a timing diagram related to the operation of a half adder of a general-purpose logic memory block according to an embodiment of the present invention.

[0207] Referring to FIG. 7, the timing diagram (700) according to one embodiment of the present invention is a first input voltage (V IN1 ) and the second input voltage (V IN2 This describes the operation of a half-adder of a general-purpose logic memory block that derives the result of an operation with a sum (S) and a carry (COUT) for ).

[0208] The general-purpose logic memory block (600) outputs a logic operation value corresponding to a half-adder according to the distribution of input / output voltages and performs a memory function that maintains the operation result even when all voltages are removed.

[0210] FIGS. 8 and 9 are drawings illustrating the operation of a full adder of a general-purpose logic memory block according to an embodiment of the present invention.

[0211] FIG. 8 illustrates a structure related to the full adder operation of a general-purpose logic memory block according to an embodiment of the present invention.

[0212] Referring to FIG. 8, a general-purpose logic memory block (800) according to an embodiment of the present invention implements a half-adder operation based on the control of a switch box (820) and a line switch (830) for a general-purpose logic memory cell operating as a first XOR gate (810) and a second XOR gate (811), a general-purpose logic memory cell operating as a first AND gate (812) and a second AND gate (813), and a general-purpose logic memory cell operating as an OR gate (814).

[0213] For example, the switch box (820) has a first input voltage (V) to a general-purpose logic memory cell that operates as a first XOR gate (810) and a second XOR gate (811) among the logic operation functions, and a general-purpose logic memory cell that operates as a first AND gate (812) and a second AND gate (813) among the general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns. IN1 ), second input voltage (V IN2 ) and third input voltage (V CIN authorizes ).

[0214] Additionally, the switch box (820) outputs the output from the general-purpose logic memory cell operating as the second XOR gate (811) as a sum (S), transmits the output from the general-purpose logic memory cell operating as the first AND gate (812) and the second AND gate (813) to the input of the general-purpose logic memory cell operating as the OR gate (814), and controls the output voltage to be output as a carry number (COUT).

[0215] FIG. 9 illustrates a timing diagram related to the full adder operation of a general-purpose logic memory block according to an embodiment of the present invention.

[0216] Referring to FIG. 9, the timing diagram (900) according to one embodiment of the present invention is a first input voltage (V IN1 ), second input voltage (V IN2 ) and third input voltage (V CIN This describes the operation of a full adder in a general-purpose logic memory block that derives the result of an operation with a sum (S) and a carry (COUT) for ).

[0217] The general-purpose logic memory block (800) outputs a logic operation value corresponding to a full adder according to the distribution of input / output voltages and performs a memory function that maintains the operation result even when all voltages are removed.

[0219] FIGS. 10 and FIGS. 11 are drawings illustrating the operation of a demultiplexer of a general-purpose logic memory block according to an embodiment of the present invention.

[0220] FIG. 10 illustrates a structure related to the demultiplexer operation of a general-purpose logic memory block according to an embodiment of the present invention.

[0221] Referring to FIG. 10, a general-purpose logic memory block (1000) according to an embodiment of the present invention implements a demultiplexer operation based on the control of a switch box (1020) and a line switch (1030) for a general-purpose logic memory cell operating as a first AND gate (1011) and a second AND gate (1012) and a general-purpose logic memory cell operating as a NOT gate (1010).

[0222] For example, the switch box (1020) inputs a voltage (V) to a general-purpose logic memory cell that operates as a first AND gate (1011) and a second AND gate (1012) among general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns. IN authorizes ).

[0223] Additionally, the switch box (1020) selects a voltage (V) to a general-purpose logic memory cell that operates as a NOT gate (1010) among logic operation functions. S authorizes ).

[0224] Accordingly, the switch box (1020) controls the output from a general-purpose logic memory cell operating as a first AND gate (1011) to be output to the first output (OUT1), and the output from a general-purpose logic memory cell operating as a second AND gate (1012) to be output to the second output (OUT2).

[0225] FIG. 11 illustrates a timing diagram related to the demultiplexer operation of a general-purpose logic memory block according to an embodiment of the present invention.

[0226] Referring to FIG. 11, the timing diagram (1100) according to one embodiment of the present invention is an input voltage (V IN) and selected voltage (V S Demultiplexer operation according to the order of outputting to the first output (OUT1) and the second output (OUT2) for ).

[0227] The general-purpose logic memory block (1000) outputs a logic operation value corresponding to a demultiplexer according to the distribution of input / output voltages and performs a memory function that maintains the operation result even when all voltages are removed.

[0229] FIGS. 12 and FIGS. 13 are drawings illustrating the operation of a multiplexer of a general-purpose logic memory block according to an embodiment of the present invention.

[0230] FIG. 12 illustrates a structure related to the operation of a 2*1 multiplexer of a general-purpose logic memory block according to an embodiment of the present invention.

[0231] Referring to FIG. 12, a general-purpose logic memory block (1200) according to an embodiment of the present invention implements a 2*1 multiplexer operation based on the control of a switch box (1220) and a line switch (1230) for a general-purpose logic memory cell operating as a first AND gate (1211) and a second AND gate (1212), a general-purpose logic memory cell operating as a NOT gate (1210), and a general-purpose logic memory cell operating as an OR gate (1213).

[0232] For example, the switch box (1220) has a first input voltage (V) to a general-purpose logic memory cell that operates as a first AND gate (1211) and a second AND gate (1212) among general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns. IN1 ) and the second input voltage (V IN2 authorizes ).

[0233] A switch box (1220) according to one embodiment of the present invention applies a selection voltage (V) to a general-purpose logic memory cell that operates as a NOT gate (1210) among logic operation functions. S authorizes ).

[0234] For example, the switch box (1220) can control the output from a general-purpose logic memory cell operating as a first AND gate (1211) and the output from a general-purpose logic memory cell operating as a second AND gate (1212) to be transmitted to the input of a general-purpose logic memory cell operating as an OR gate (1213), and then output the output voltage to the output (OUT).

[0235] FIG. 13 illustrates a timing diagram related to the operation of a 2*1 multiplexer of a general-purpose logic memory block according to an embodiment of the present invention.

[0236] Referring to FIG. 13, the timing diagram (1300) according to one embodiment of the present invention is a first input voltage (V IN1 ) and the second input voltage (V IN2 ) and selected voltage (V S It shows the multiplexer operation according to the order of outputting to the output (OUT) for ).

[0237] The general-purpose logic memory block (1200) outputs a logic operation value corresponding to a 2*1 multiplexer according to the distribution of input / output voltages and performs a memory function that retains the operation result even when all voltages are removed.

[0239] FIGS. 14 and FIGS. 15 are drawings illustrating the decoder operation of a general-purpose logic memory block according to an embodiment of the present invention.

[0240] FIG. 14 illustrates a structure related to the decoder operation of a general-purpose logic memory block according to an embodiment of the present invention.

[0241] Referring to FIG. 14, a general-purpose logic memory block (1400) according to an embodiment of the present invention implements a 2*4 decoder operation based on the control of a switch box (1420) and a line switch (1430) for a general-purpose logic memory cell operating as a first NOT gate (1410) and a second NOT gate (1411), and a general-purpose logic memory cell operating as a first AND gate (1412), a second AND gate (1413), a third AND gate (1414), and a fourth AND gate (1415).

[0242] For example, the switch box (1420) has a first input voltage (V) to a general-purpose logic memory cell that operates as a first AND gate (1412), a second AND gate (1413), a third AND gate (1414), and a fourth AND gate (1415) among general-purpose logic memory cells arranged in multiple rows and multiple columns, and a general-purpose logic memory cell that operates as a first NOT gate (1410) and a second NOT gate (1411) among logic operation functions. IN1 ) and the second input voltage (V IN2 Optionally authorizes ).

[0243] The switch box (1420) controls the output of a general-purpose logic memory cell operating with a first AND gate (1412) to a first output (OUT1), controls the output of a general-purpose logic memory cell operating with a second AND gate (1413) to a second output (OUT2), controls the output of a general-purpose logic memory cell operating with a third AND gate (1414) to a fourth output (OUT4), and controls the output of a general-purpose logic memory cell operating with a fourth AND gate (1415) to a third output (OUT3).

[0244] FIG. 15 illustrates a timing diagram related to the decoder operation of a general-purpose logic memory block according to an embodiment of the present invention.

[0245] Referring to FIG. 15, the timing diagram (1500) according to one embodiment of the present invention is a first input voltage (V IN1) and the second input voltage (V IN2 It shows the decoder operation according to the order of outputting to the first output (OUT1), second output (OUT2), third output (OUT3), and fourth output (OUT4) for ).

[0246] The general-purpose logic memory block outputs a logical operation value corresponding to a 2*4 decoder according to the distribution of input / output voltages, and performs a memory function that retains the operation result even when all voltages are removed.

[0248] FIGS. 16 and FIGS. 17 are drawings illustrating the encoder operation of a general-purpose logic memory block according to an embodiment of the present invention.

[0249] FIG. 16 illustrates a structure related to the encoder operation of a general-purpose logic memory block according to an embodiment of the present invention.

[0250] Referring to FIG. 16, a general-purpose logic memory block (1600) according to an embodiment of the present invention implements an encoder operation based on the control of a switch box (1620) and a line switch (1630) for a general-purpose logic memory cell that operates as a first OR gate (1610) and a second OR gate (1611).

[0251] For example, the switch box (1620) has a second input voltage (V) to a general-purpose logic memory cell that operates as a first OR gate (1610) and a second OR gate (1611) among general-purpose logic memory cells arranged in multiple rows and multiple columns. IN2 ), third input voltage (V IN3 ) and the fourth input voltage (V IN4 It controls to apply ). Here, the first input voltage (V IN1 ) is not authorized as a general-purpose logic memory cell.

[0252] The switch box (1620) controls the output of a general-purpose logic memory cell operating as a first OR gate (1610) to a first output (OUT1) and controls the output of a general-purpose logic memory cell operating as a second OR gate (1611) to a second output (OUT2).

[0253] FIG. 17 illustrates a timing diagram related to the encoder operation of a general-purpose logic memory block according to an embodiment of the present invention.

[0254] Referring to FIG. 17, the timing diagram (1700) according to one embodiment of the present invention is a first input voltage (V IN1 ), second input voltage (V IN2 ), third input voltage (V IN3 ) and the fourth input voltage (V IN4 It shows the encoder operation according to the order of outputting to the first output (OUT1) and the second output (OUT2) for ).

[0255] The general-purpose logic memory block outputs a logical operation value corresponding to a 4*2 encoder according to the distribution of input / output voltages, and performs a memory function that retains the operation result even when all voltages are removed.

[0257] FIGS. 18 and 19 are drawings illustrating the operation of a bit comparator of a general-purpose logic memory block according to an embodiment of the present invention.

[0258] FIG. 18 illustrates a structure related to the operation of a bit comparator of a general-purpose logic memory block according to an embodiment of the present invention.

[0259] Referring to FIG. 18, a general-purpose logic memory block (1800) according to an embodiment of the present invention implements encoder operation based on the control of a switch box (1820) and a line switch (1830) for a general-purpose logic memory cell operating as an XNOR gate (1810) and an XOR gate (1811), a general-purpose logic memory cell operating as a first NOT gate (1812) and a second NOT gate (1813), and a general-purpose logic memory cell operating as a first AND gate (1814) and a second AND gate (1815).

[0260] For example, the switch box (1820) is configured with a general-purpose logic memory cell that operates as an XNOR gate (1810) and an XOR gate (1811), a general-purpose logic memory cell that operates as a first NOT gate (1812) and a second NOT gate (1813), and a general-purpose logic memory cell that operates as a first AND gate (1814) and a second AND gate (1815), among general-purpose logic memory cells arranged in multiple rows and multiple columns, and a first input voltage (V IN1 ) and the second input voltage (V IN2 Optionally authorizes ).

[0261] Additionally, the switch box (1820) controls the output of a general-purpose logic memory cell operating as an XNOR gate (1810) to a first output (OUT1), controls the output of a general-purpose logic memory cell operating as an XOR gate (1811) to a second output (OUT2), controls the output of a general-purpose logic memory cell operating as a second AND gate (1815) to a third output (OUT3), and controls the output of a general-purpose logic memory cell operating as a first AND gate (1814) to a fourth output (OUT4).

[0262] FIG. 19 illustrates a timing diagram related to the operation of a bit comparator of a general-purpose logic memory block according to an embodiment of the present invention.

[0263] Referring to FIG. 19, the timing diagram (1900) according to one embodiment of the present invention is a first input voltage (VIN1 ) and the second input voltage (V IN2 It shows the operation of a bit comparator according to the order of outputting to the first output (OUT1) to the fourth output (OUT4) for ).

[0264] The general-purpose logic memory block outputs a logical operation value corresponding to a bit comparator based on the distribution of input and output voltages, and performs a memory function that retains the operation result even when all voltages are removed.

[0266] FIGS. 20 and 21 are drawings illustrating the operation of a bit binary to gray code converter of a general-purpose logic memory block according to an embodiment of the present invention.

[0267] FIG. 20 illustrates a structure related to the operation of a bit binary-to-gray code converter of a general-purpose logic memory block according to an embodiment of the present invention.

[0268] Referring to FIG. 20, a general-purpose logic memory block (2000) according to an embodiment of the present invention implements a binary-to-gray code converter operation based on the control of a switch box (2020) and a line switch (2030).

[0269] For example, the switch box (2020) has a first input voltage (V) to a general-purpose logic memory cell that operates as a first XOR gate (2010) and a second XOR gate (2011) among general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns. IN1 ), second input voltage (V IN2 ) and third input voltage (V IN3 Optionally authorizes ).

[0270] Accordingly, the switch box (2020) has a first input voltage (V IN1) is controlled as a first output (OUT1), the output of a general-purpose logic memory cell operating as a first XOR gate (2010) is controlled as a second output (OUT2), and the output of a general-purpose logic memory cell operating as a second XOR gate (2011) is controlled as a third output (OUT3).

[0271] FIG. 21 illustrates a timing diagram related to the operation of a binary-to-gray code converter of a general-purpose logic memory block according to an embodiment of the present invention.

[0272] Referring to FIG. 21, the timing diagram (2100) according to one embodiment of the present invention is a first input voltage (V IN1 ) to the third input voltage (V IN3 It shows the operation of a binary-to-gray code converter according to the order of outputting to the first output (OUT1) to the third output (OUT3) for ).

[0273] The general-purpose logic memory block outputs a logical operation value corresponding to the binary-to-gray code converter based on the distribution of input and output voltages, and performs a memory function that retains the operation result even when all voltages are removed.

[0274] Accordingly, the present invention can implement a general-purpose logic memory block that implements various combinational logic operations in a single structure by combining the results of logic operations in a plurality of general-purpose logic memory cells using triple-gate silicon devices driven by a positive feedback loop.

[0276] In the specific embodiments described above, the components included in the invention are expressed in the singular or plural according to the specific embodiments presented.

[0277] However, singular or plural expressions are selected to suit the situation presented for convenience of explanation, and the embodiments described above are not limited to singular or plural components; even if a component is expressed in the plural, it may be composed of a singular component, or even if a component is expressed in the singular, it may be composed of a plural component.

[0278] Meanwhile, although specific embodiments have been described in the description of the invention, it is obvious that various modifications are possible within the scope of the technical concept inherent in the various embodiments.

[0279] Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims set forth below as well as equivalents thereof. Explanation of the symbols

[0280] 500: General-purpose logic memory block 510: General-purpose logic memory cell 520: Switch box 530: Line switch

Claims

Claim 1 A general-purpose logic memory cell comprising a first network element and a second network element, each composed of a plurality of triple-gate silicon elements; and a switch box determining the direction of an input voltage applied to the general-purpose logic memory cell and an output voltage output from the general-purpose logic memory cell; The invention includes a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell, and in a structure in which the general-purpose logic memory cell is arranged in multiple numbers according to a preset, the invention performs combinational logic operation functions and memory functions according to the interconnection control for the logic operation functions of the general-purpose logic memory cell according to the direction of the determined input voltage and output voltage, wherein the general-purpose logic memory cell is arranged in multiple rows and multiple columns according to the preset, and the switch box and the line switch are arranged between the general-purpose logic memory cells, and the number of the line switches is determined to correspond to the number of input voltages transmitted through the switch box, and the combinational logic operation function is implemented with at least one output based on the output voltage, and the switch box provides a first input voltage (V) to the general-purpose logic memory cell operating as a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate among the general-purpose logic memory cells arranged in multiple rows and multiple columns, and to the general-purpose logic memory cell operating as a first NOT gate and a second NOT gate among the logic operation functions. IN1 ) and the second input voltage (V IN2 A general-purpose logic memory block characterized by selectively applying ) and performing a function to control the output of a general-purpose logic memory cell operating with the first AND gate to the first output (OUT1), control the output of a general-purpose logic memory cell operating with the second AND gate to the second output (OUT2), control the output of a general-purpose logic memory cell operating with the third AND gate to the fourth output (OUT4), and control the output of a general-purpose logic memory cell operating with the fourth AND gate to the third output (OUT3). Claim 2 delete Claim 3 In claim 1, in addition to the function performed, the switch box provides a first input voltage (V) to a general logic memory cell operating as an XOR gate and a general logic memory cell operating as an AND gate among the general logic memory cells arranged in a plurality of rows and a plurality of columns among the logic operation functions. IN1 ) and the second input voltage (V IN2 A general-purpose logic memory block characterized by applying ) and controlling the output from a general-purpose logic memory cell operating as an XOR gate to output a sum (S), and the output from a general-purpose logic memory cell operating as an AND gate to output a carry (COUT). Claim 4 In claim 1, in addition to the function performed, the switch box provides a first input voltage (V) to a general-purpose logic memory cell operating as a first XOR gate and a second XOR gate and a general-purpose logic memory cell operating as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns among the logic operation functions. IN1 ), second input voltage (V IN2 ) and third input voltage (V CIN A general-purpose logic memory block characterized by applying ) and outputting the output from the general-purpose logic memory cell operating as the second XOR gate as a sum (S), and transmitting the output from the general-purpose logic memory cell operating as the first AND gate and the second AND gate to the input of the general-purpose logic memory cell operating as the OR gate, and then controlling the output voltage to be output as a carry (COUT). Claim 5 In claim 1, in addition to the function performed, the switch box inputs an input voltage (V) to a general-purpose logic memory cell operating as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns. IN ) is applied, and a selection voltage (V) is applied to a general-purpose logic memory cell that operates as a NOT gate among the above logic operation functions. S A general-purpose logic memory block characterized by applying ) and controlling to output the output from a general-purpose logic memory cell operating as the first AND gate to the first output (OUT1), and to output the output from a general-purpose logic memory cell operating as the second AND gate to the second output (OUT2). Claim 6 In claim 1, in addition to the function performed, the switch box provides a first input voltage (V) to a general-purpose logic memory cell operating as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns. IN1 ) and the second input voltage (V IN2 Applying ) and a selection voltage (V) to a general-purpose logic memory cell operating as a NOT gate among the above logic operation functions. S A general-purpose logic memory block characterized by applying ) and controlling the output from a general-purpose logic memory cell operating as a first AND gate and the output from a general-purpose logic memory cell operating as a second AND gate to be transmitted as inputs to a general-purpose logic memory cell operating as an OR gate, and then outputting the output voltage as an output (OUT). Claim 7 delete Claim 8 In claim 1, in addition to the function performed, the switch box provides a second input voltage (V) to a general-purpose logic memory cell operating as a first OR gate and a second OR gate among the general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns. IN2 ), third input voltage (V IN3 ) and the fourth input voltage (V IN4 A general-purpose logic memory block characterized by applying ) and controlling the output of a general-purpose logic memory cell operating as the first OR gate to the first output (OUT1), and controlling the output of a general-purpose logic memory cell operating as the second OR gate to the second output (OUT2). Claim 9 A general-purpose logic memory cell comprising a first network element and a second network element, each composed of a plurality of triple-gate silicon elements; and a switch box determining the direction of an input voltage applied to the general-purpose logic memory cell and an output voltage output from the general-purpose logic memory cell; The invention includes a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell, and in a structure in which the general-purpose logic memory cell is arranged in multiple numbers according to a preset, the invention performs combinational logic operation functions and memory functions according to the interconnection control for the logic operation functions of the general-purpose logic memory cell according to the direction of the determined input voltage and output voltage, wherein the general-purpose logic memory cell is arranged in multiple rows and multiple columns according to the preset, and the switch box and the line switch are arranged between the general-purpose logic memory cells, and the number of the line switches is determined to correspond to the number of input voltages transmitted through the switch box, and the combinational logic operation function is implemented with at least one output based on the output voltage, and the switch box provides a first input voltage (V) to the general-purpose logic memory cell operating as an XNOR gate and an XOR gate, the general-purpose logic memory cell operating as a first NOT gate and a second NOT gate, and the general-purpose logic memory cell operating as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in multiple rows and multiple columns. IN1 ) and the second input voltage (V IN2 A general-purpose logic memory block characterized by selectively applying ), controlling the output of a general-purpose logic memory cell operating as an XNOR gate to a first output (OUT1), controlling the output of a general-purpose logic memory cell operating as an XOR gate to a second output (OUT2), controlling the output of a general-purpose logic memory cell operating as a second AND gate to a third output (OUT3), and controlling the output of a general-purpose logic memory cell operating as a first AND gate to a fourth output (OUT4). Claim 10 In claim 1, in addition to the function performed, the switch box provides a first input voltage (V) to a general-purpose logic memory cell operating as a first XOR gate and a second XOR gate among the general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns. IN1 ), second input voltage (V IN2 ) and third input voltage (V IN3 ) is selectively applied, and the first input voltage (V IN1 A general-purpose logic memory block characterized by controlling ) to a first output (OUT1), controlling the output of a general-purpose logic memory cell operating as a first XOR gate to a second output (OUT2), and controlling the output of a general-purpose logic memory cell operating as a second XOR gate to a third output (OUT3). Claim 11 In claim 1, the general-purpose logic memory cell comprises a first network element and a second network element using a plurality of triple-gate silicon elements, each of the plurality of triple-gate silicon elements comprises a drain region, a channel region, and a source region, a supply voltage is applied to the drain region and the source region, and includes a gate region in which a first and second programming gate electrode and a control gate electrode are formed on the channel region, and a program voltage (V) applied through the first and second programming gate electrodes PG Depending on the level of ), the channel region under the first and second programming gate electrodes in the channel region performs either the first channel mode or the second channel mode, and the control voltage (V) applied through the control gate electrode CG It is determined to be either an on state or an off state based on the level of ), and the first network element and the second network element have an output voltage (V) that changes according to the one state in the one channel mode performed above. OUT A general-purpose logic memory block characterized by performing the above-mentioned logical operation function and memory function according to the level of ). Claim 12 In claim 11, the first network element and the second network element are composed of a first parallel connection section in which a common drain region is connected between a first series connection section in which the drain region and source region of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, and a second parallel connection section in which a common source region is connected between a second series connection section in which the drain region and source region of the remaining two triple-gate silicon elements are connected in series, and a drain voltage (V) among the common voltages is connected through the first parallel connection section of the first network element. DD ) is applied, and through the second parallel connection of the second network element, the source voltage (V) among the common voltages is applied. SS ) is applied, and at the part where the second parallel connection part of the first network element and the first parallel connection part of the second network element are connected, an output voltage (V) to any one of the above is applied. OUT A general-purpose logic memory block characterized by the measurement of ). Claim 13 In claim 12, the triple-gate silicon device has the drain region in a p-doped state, the source region in an n-doped state, and the channel region in an intrinsic state, and the channel region below the first and second programming gate electrodes in the channel region is the programming voltage (V PG When the level of ) is a positive level, it operates as n channels corresponding to the first channel mode, and the program voltage (V PG A general-purpose logic memory block characterized by operating as a p-channel corresponding to the second channel mode when the level of ) is a voice level. Claim 14 In paragraph 13, the general-purpose logic memory cell is a drain voltage (V) applied to the drain region. DD ), source voltage (V) applied to the source region SS ), the above program voltage (V PG ) and the control voltage (V CG When ) is applied at a zero level, the output voltage (V OUT A general-purpose logic memory block characterized by performing the above memory function by maintaining the level of ).

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