Semiconductor device structures and methods of forming the same

Abstract

Methods for forming a semiconductor device structure are described together. The semiconductor device structure includes an active region, and the active region includes a pin extending over a substrate, a first dummy gate electrode layer disposed on the pin, a second dummy gate electrode layer adjacent to the first dummy gate electrode layer, a third dummy gate electrode layer disposed on the pin, and a fourth dummy gate electrode layer adjacent to the third dummy gate electrode layer. The second dummy gate electrode layer and the third dummy gate electrode layer are disposed between the first dummy gate electrode layer and the fourth dummy gate electrode layer. The active region further includes an active gate electrode layer disposed on the pin, and the active gate electrode layer is disposed between the second dummy gate electrode layer and the third dummy gate electrode layer.

Description

Technology Field

[0001] This application claims priority to U.S. Provisional Application No. 63 / 673,682 filed July 20, 2024, the entirety of which is incorporated herein by reference. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have created generations of ICs, each featuring smaller and more complex circuits than the previous generation. Throughout the evolution of ICs, functional density (e.g., the number of interconnected devices per chip area) has generally increased, while geometric size (e.g., the smallest component (or line) that can be produced using the manufacturing process) has decreased. This scaling down process generally offers benefits by increasing production efficiency and lowering associated costs.

[0003] With the scaling down of devices, manufacturers began using new and different materials and / or combinations of materials to facilitate this process. Scaling down, both alone and in combination with new and different materials, has posed challenges in larger geometries that may not have been presented by previous generations. Prior art literature

[65535] (Patent Document 0001) US 9362275 B1 Brief explanation of the drawing

[0004] The aspects of this disclosure are best understood from the following detailed description when read together with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be increased or decreased at will for the sake of clarity of discussion. FIGS. 1, FIGS. 2 and FIGS. 3 are perspective views of a semiconductor device structure according to some embodiments. FIG. 4 is a cross-sectional view of a semiconductor device structure according to some embodiments. FIG. 5 is a perspective view of a semiconductor device structure according to some embodiments. FIG. 6 is a cross-sectional view of a semiconductor device structure according to some embodiments. FIGS. 7a, FIGS. 8a, FIGS. 9a, and FIGS. 10a are side cross-sectional views of various stages for manufacturing the semiconductor device structure of FIG. 5 taken along line AA according to some embodiments. FIGS. 7b, FIGS. 8b, FIGS. 9b, and FIGS. 10b are side cross-sectional views of various stages for manufacturing the semiconductor device structure of FIG. 5 taken along line BB according to some embodiments. FIGS. 7c, FIGS. 8c, FIGS. 9c, and FIGS. 10c are side cross-sectional views of various stages for manufacturing the semiconductor device structure of FIG. 5 taken along line CC according to some embodiments. FIG. 11 is a cross-sectional view of a semiconductor device structure according to some embodiments. FIGS. 12a, FIGS. 12b, and FIGS. 12c are side cross-sectional views of various stages for manufacturing the semiconductor device structure of FIG. 5, taken along lines AA, BB, and CC, respectively, according to some embodiments. FIG. 13 is a cross-sectional view of a semiconductor device structure according to some embodiments. FIGS. 14a, FIGS. 14b, and FIGS. 14c are side cross-sectional views of various stages for manufacturing the semiconductor device structure of FIG. 5, taken along lines AA, BB, and CC, respectively, according to some embodiments. FIG. 15 is a cross-sectional view of a semiconductor device structure according to some embodiments. FIGS. 16a and FIGS. 16b are side cross-sectional views of various stages for manufacturing the semiconductor device structure of FIG. 5, taken along lines AA and BB, respectively, according to some embodiments. FIG. 17 is a cross-sectional view of a semiconductor device structure according to some embodiments. FIGS. 18a and FIGS. 18b are side cross-sectional views of various stages for manufacturing the semiconductor device structure of FIG. 5, taken along lines AA and BB, respectively, according to some embodiments. FIG. 19 is a cross-sectional view of a semiconductor device structure according to some embodiments. FIGS. 20, FIGS. 21 and FIGS. 22 are plan views of a semiconductor device structure according to some embodiments. FIGS. 23a, FIGS. 23b, FIGS. 23c and FIGS. 23d are plan views of a semiconductor device structure according to some embodiments. FIG. 24 is a plan view of a semiconductor device structure according to some embodiments. Specific details for implementing the invention

[0005] The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0006] Additionally, spatially relative terms such as “bottom,” “below,” “lower,” “above,” “over,” “top,” “top,” and “top” may be used herein for convenience of description to explain the relationship of one element or feature to other element(s) or feature(s) as illustrated in the drawings. Spatial terms are intended to include different orientations of the device during use or operation, in addition to the orientations shown in the drawings. The device may be oriented in different ways (rotated 90 degrees or in other directions), and spatial descriptors used herein may be interpreted accordingly.

[0007] FIGS. 1 through 24 illustrate various stages for manufacturing a semiconductor device structure (100) according to various embodiments of the present disclosure. For additional embodiments of the method, it should be understood that additional operations may be provided before, during, and after the process illustrated by FIGS. 1 through 24, and some of the operations described below may be replaced or removed. The order of operations / processes may be interchangeable.

[0008] FIGS. 1, FIGS. 2 and FIGS. 3 are perspective views of a semiconductor device structure (100) according to some embodiments. In FIG. 1, a first semiconductor layer (104) is formed on a substrate (102). The substrate may be part of a chip within a wafer. In some embodiments, the substrate (102) is a bulk semiconductor substrate, such as a semiconductor wafer. For example, the substrate (102) is a silicon wafer. The substrate (102) may include silicon or other elemental semiconductor materials, such as germanium. In some embodiments, the substrate (102) includes a compound semiconductor. The compound semiconductor may include gallium arsenide, silicon carbide, indium arsenide, indium phosphide, other suitable semiconductor materials, or a combination thereof. In some embodiments, the substrate (102) is a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be manufactured using a SIMOX (separation by implantation of oxygen) process, a wafer bonding process, other applicable methods, or a combination thereof.

[0009] The substrate (102) may be doped with P-type or N-type impurities. As illustrated in FIG. 1, according to some embodiments, the substrate (102) has a P-type metal oxide semiconductor region (102P) (PMOS region (102P)) and an N-type metal oxide semiconductor region (102N) (NMOS region (102N)) adjacent to the PMOS region (102P). Although not illustrated in some drawings at actual scale, the PMOS region (102P) and the NMOS region (102N) belong to a continuous substrate (102). In some embodiments of the present disclosure, the PMOS region (102P) is used to form a PMOS structure thereon, while the NMOS region (102N) is used to form an NMOS structure thereon. In some embodiments, as illustrated in FIG. 1, an N-well region (103N) and a P-well region (103P) are formed on the substrate (102). For example, the N-well region (103N) is formed on the substrate (102) in the PMOS region (102P), while the P-well region (103P) is formed on the substrate (102) in the NMOS region (102N). The P-well region (103P) and the N-well region (103N) may be formed by any suitable technique, for example, by a separate ion implantation process in some embodiments. By using two different implantation mask layers (not shown), the P-well region (103P) and the N-well region (103N) may be formed sequentially by different ion implantation processes.

[0010] As illustrated in FIG. 1, a first semiconductor layer (104) is deposited on a substrate (102). The first semiconductor layer (104) may be made of any suitable semiconductor material, such as silicon, germanium, III-V semiconductor material, or a combination thereof. In some embodiments, the first semiconductor layer (104) is made substantially of silicon. The first semiconductor layer (104) can be formed by an epitaxial growth process, such as metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), plasma-enhanced chemical vapor deposition (PECVD), remote plasma chemical vapor deposition (rema-CVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), or any other suitable process.

[0011] In FIG. 2, a portion of the first semiconductor layer (104) placed over the N-well region (103N) is removed, and a second semiconductor layer (106) is formed over the N-well region (103N) and adjacent to the portion of the first semiconductor layer (104) placed over the P-well region (103P). A patterned mask layer (not shown) may first be formed on the portion of the first semiconductor layer (104) placed over the P-well region (103P), and the portion of the first semiconductor layer (104) placed over the N-well region (103N) may be exposed. To remove the portion of the first semiconductor layer (104) placed over the N-well region (103N), a removal process such as dry etching, wet etching, or a combination thereof may be performed, and the N-well region (103N) may be exposed. The removal process substantially does not affect the mask layer (not shown) formed on the portion of the first semiconductor layer (104) placed over the P-well region (103P), which protects the portion of the first semiconductor layer (104) placed over the P-well region (103P). Next, a second semiconductor layer (106) is formed on the exposed N-well region (103N). The second semiconductor layer (106) may be manufactured from any suitable semiconductor material, such as silicon, germanium, III-V semiconductor material, or a combination thereof. In some embodiments, the second semiconductor layer (106) is manufactured substantially from silicon germanium. The second semiconductor layer (106) may be formed by the same process as the first semiconductor layer (104). For example, the second semiconductor layer (106) can be formed on the exposed N-well region (103N) by an epitaxial growth process, which does not form the second semiconductor layer (106) on a mask layer (not shown) placed on the first semiconductor layer (104). As a result, the first semiconductor layer (104) is placed on the P-well region (103P) in the NMOS region (102N), and the second semiconductor layer (106) is placed on the N-well region (103N) in the PMOS region (102P).

[0012] Parts of the first semiconductor layer (104) can serve as channels in an NMOS structure subsequently formed in an NMOS region (102N). Parts of the second semiconductor layer (106) can serve as channels in a PMOS structure subsequently formed in a PMOS region (102P). In some embodiments, the NMOS structure and the PMOS structure are FinFETs. Although the embodiments described in this disclosure are described in the context of FinFETs, implementations of some aspects of this disclosure may be used in other processes and / or other devices, such as planar FETs, nanostructured channel FETs, HGAA (Horizontal Gate All Around) FETs, VGAA (Vertical Gate All Around) FETs, and other suitable devices.

[0013] In FIG. 3, a plurality of pins (108a, 108b, 110a, 110b) are formed from first and second semiconductor layers (104, 106). The pins (108a, 108b, 110a, 110b) can be patterned by any suitable method. For example, the pins (108a, 108b, 110a, 110b) can be patterned using one or more photolithography processes including a double patterning or multi-patterning process. Generally, a double patterning or multi-patterning process combines photolithography and a self-aligning process to produce a pattern having a smaller pitch than that can be obtained, for example, using a single direct photolithography process. For example, in one embodiment, a sacrificial layer (not shown) is formed on a substrate and patterned using a photolithography process. Spacers (not shown) are formed along the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and the remaining spacers can then be used to pattern the substrate and form pins.

[0014] Each pin (108a, 108b) may include a first semiconductor layer (104), and a portion of the first semiconductor layer (104) may serve as an NMOS channel. Each pin (108a, 108b) may also include a P-well region (103P). Likewise, each pin (110a, 110b) may include a second semiconductor layer (106), and a portion of the second semiconductor layer (106) may serve as a PMOS channel. Each pin (110a, 110b) may also include an N-well region (103N). A mask (not shown) may be formed on the first and second semiconductor layers (104, 106) and may remain on the pins (108a-b and 110a-b).

[0015] Next, an insulating structure (112) is formed between adjacent pins (108a-b, 110a-b). The insulating structure (112) can first be formed between adjacent pins (108a-b, 110a-b) and on top of the pins (108a-b, 110a-b), and accordingly, the pins (108a-b, 110a-b) are embedded in the insulating structure (112). The insulating structure (112) may include an oxygen-containing material such as silicon oxide, carbon or nitrogen-doped oxide, or fluorine-doped silicate glass (FSG); a nitrogen-containing material such as silicon nitride, silicon oxynitride (SiON), SiOCN, or SiCN; a low K dielectric material (e.g., a material having a K value lower than that of silicon dioxide); or any suitable dielectric material. The insulating structure (112) can be formed by any suitable method such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or flowable CVD (FCVD).

[0016] Next, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed to expose the top of the pins (108a-b, 110a-b). In some embodiments, the planarization process exposes the top of a mask (not shown) placed on the pins (108a-b and 110a-b). Then, the insulating structure (112) is reset by removing portions of the insulating structure (112) located on both sides of each pin (108a-b, 110a-b). The reset insulating structure (112) may be a shallow trench isolation (STI) region.

[0017] FIG. 4 is a cross-sectional view of a semiconductor device structure (100) according to some embodiments. In some embodiments, as shown in FIG. 4, one or more of the pins (108a-b, 110a-b) are defined along the X direction. The length of one or more of the pins (108a-b, 110a-b) along the X direction may define the dimensions of the active region (101) along the X direction. One or more edges of the pins (108a-b, 110a-b) along the X direction may be inclined as a result of a process for forming the pins (108a-b, 110a-b), as shown in FIG. 4. FIG. 4 illustrates a pin (108a). However, the pin illustrated in FIG. 4 may be any pin, such as any pin among the pins (108a-b, 110a-b).

[0018] FIG. 5 is a perspective view of a semiconductor device structure (100) according to some embodiments. In FIG. 5, one or more sacrificial gate stacks (128) are formed on portions of pins (108a-b, 110a-b). Each sacrificial gate stack (128) may include a sacrificial gate dielectric layer (130), a sacrificial gate electrode layer (132), and a mask structure (134). The sacrificial gate dielectric layer (130) may include one or more layers of dielectric material such as SiO2, SiN, high-k dielectric material, and / or other suitable dielectric material. In some embodiments, the sacrificial gate dielectric layer (130) may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, an FCVD process, an ALD process, a PVD process, or other suitable process. The sacrificial gate electrode layer (132) may include polycrystalline silicon (polysilicon). The mask structure (134) may include an oxygen-containing layer and a nitrogen-containing layer. In some embodiments, the sacrificial gate electrode layer (132) and the mask structure (134) are formed by various processes such as layer deposition, e.g., CVD (including both LPCVD and PECVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof.

[0019] Sacrificial gate stacks (128) can be formed by first depositing blanket layers of a sacrificial gate dielectric layer (130), a sacrificial gate electrode layer (132), and a mask structure (134), and then by a patterning and etching process. For example, the patterning process includes a lithography process (e.g., photolithography or e-beam lithography), which may further include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof. By patterning the sacrifice gate stacks (128), the pins (108a-108b, 110a-110b) are partially exposed on opposite sides of the sacrifice gate stacks (128). Parts of the insulating structure (112) are exposed as a result of the etching process(s) for forming the sacrifice gate stacks (128). Although three sacrifice gate stacks (128) are shown in FIG. 4, they are for illustrative purposes only and it will be understood that any number of sacrifice gate stacks (128) can be formed.

[0020] FIG. 6 is a cross-sectional view of a semiconductor device structure (100) according to some embodiments. As shown in FIG. 6, in some embodiments, a plurality of sacrifice gate stacks (128) are formed in an active region (101). The cross-sectional shape of the sacrifice gate stacks (128) is for illustrative purposes only, and details of the sacrifice gate stacks (128) are omitted for clarity. In some embodiments, the sacrifice gate stacks (128) have an inverted trapezoidal cross section as shown in FIG. 6. In some embodiments, the sacrifice gate stacks (128) have a rectangular cross section as shown in FIG. 5. In some embodiments, the sacrifice gate stacks (128) located at the edges of the active region (101) each have a length (L1), and the sacrifice gate stacks (128) located between them each have a length (L2). In some embodiments, the length (L1) is the same as the length (L2). The sacrifice gate stacks (128) positioned at the edge are intended to cover the edge of the pin (108a) (or pins (108a-b and 110a-b)). If the edge of the pin (108a) is not covered, subsequent processes for forming source / drain (S / D) regions (152, 154) (Figs. 9a to 9c) may form epitaxial features at the edge of the pin (108a), which may cause problems during subsequent processes. Accordingly, in some embodiments, the sacrifice gate stacks (128) positioned at the edge of the pin (108a) may have a longer length (L1) to ensure that the edge of the pin (108) is covered. In some embodiments, the length (L1) of the edge sacrifice gate stacks (128) located at the edges is greater than the length (L2) of the central sacrifice gate stacks (128) located between the two edge sacrifice gate stacks (128). In some embodiments, the central sacrifice gate stacks (128) have the same length (L2) as shown in FIG. 6.

[0021] FIGS. 7a, FIGS. 8a, FIGS. 9a, and FIGS. 10a are side cross-sectional views of various stages for manufacturing the semiconductor device structure (100) of FIG. 5 taken along line AA according to some embodiments. FIGS. 7b, FIGS. 8b, FIGS. 9b, and FIGS. 10b are side cross-sectional views of various stages for manufacturing the semiconductor device structure (100) of FIG. 5 taken along line BB according to some embodiments. FIGS. 7c, FIGS. 8c, FIGS. 9c, and FIGS. 10c are side cross-sectional views of various stages for manufacturing the semiconductor device structure (100) of FIG. 5 taken along line CC according to some embodiments. FIGS. 7a through 7c illustrate a stage after sacrificial gate stacks (128) are formed on parts of the pins (108a-b, 110a-b). In FIGS. 8a through 8c, a spacer (140) is formed on exposed portions of the sacrificial gate stacks (128) and the first and second semiconductor layers (104, 106). The spacer (140) may be conformally deposited on the exposed surfaces of the semiconductor device structure (100). The conformal spacer (140) may be formed by ALD or any suitable process. Then, anisotropic etching is performed on the spacer (140), for example using RIE. During the anisotropic etching process, most of the spacer (140) is removed from horizontal surfaces, such as the top of the sacrificial gate stacks (128) and the top of the pins (108a-b, 110a-b), leaving the spacer (140) on vertical surfaces, such as the opposite sidewalls of the sacrificial gate stacks (128). As illustrated in FIG. 8a, the spacers (140) may remain partially on the opposite sidewalls of the pins (108a-b, 110a-b). In some embodiments, the spacers (140) formed on the S / D regions of the pins (108a-b, 110a-b) are completely removed.

[0022] The spacer (140) may be made of dielectric materials such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), air gap, and / or any combination thereof. In some embodiments, the spacer (140) comprises one or more layers of the dielectric materials discussed above.

[0023] In various embodiments in which the spacer (140) comprises multiple layers, the top portion of the pins (108a-b, 110a-b) not covered by the sacrificial gate stacks (128) may have a tapered profile (149) as illustrated in FIG. 8b and FIG. 8c. The tapered profile (149) may be formed as a result of multiple exposures of the first and second semiconductor layers (104, 106) to the etchants used during the formation of the spacer (140). The tapered profile (149) between adjacent sacrificial gate stacks (128) forms a shallow V-shaped top surface on each of the first and second semiconductor layers (104, 106).

[0024] In FIGS. 9a through 9c, the first and second semiconductor layers (104, 106) of the pins (108a-b, 110a-b) not covered by the sacrificial gate stacks (128) and spacers (140) are reset, and S / D regions (152, 154) are formed. In the present disclosure, the source region and the drain region are used interchangeably, and their structures are substantially identical. Additionally, the source / drain region(s) may refer to the source or drain individually or collectively depending on the context. For devices in the NMOS region (102N), each S / D region (152) may include one or more layers of Si, SiP, SiC, SiCP, SiAs, or Group III-V materials (InP, GaAs, AlAs, InAs, InAlAs, InGaAs). In some embodiments, each S / D region (152) comprises two or more layers of Si, SiP, SiC, SiCP, or Group III-V material, and each layer may have a different silicon concentration. Each S / D region (152) may comprise N-type dopants, such as phosphorus (P), arsenic (As), or other suitable N-type dopants. The S / D regions (152) may be formed by any suitable method, such as CVD, CVD epitaxy, MBE, or other suitable method. As shown in FIG. 9b, the S / D region (152) may be formed on the exposed surfaces of the pins (108a-b) on both sides of each sacrificial gate stack (128). In some embodiments, portions of the first semiconductor layer (104) on both sides of each sacrifice gate stack (128) are completely removed, and S / D regions (152) are formed on the P-well regions (103P) of the pins (108a-b). The S / D regions (152) can grow vertically and horizontally to form facets that correspond to the crystalline planes of the material used in the substrate (102).In some embodiments, as shown in FIG. 9a, S / D regions (152) formed on the P-well region (103P) of the pins (108a and 108b) are merged. As shown in FIG. 9b, each of the S / D regions (152) may have a top surface at a higher level than the top surface of the first semiconductor layer (104).

[0025] For devices in the PMOS region (102P), each S / D region (154) may comprise one or more layers of Si, SiGe, SiGeB, Ge, or Group III-V materials (InSb, GaSb, InGaSb), and each layer may have different silicon or germanium concentrations. Each S / D region (154) may comprise P-type dopants, such as boron (B) or other suitable P-type dopants. In some embodiments, the S / D regions (152) in the NMOS region (102N) and the S / D regions (154) in the PMOS region (102P) are both Si. In some embodiments, the S / D regions (152) in the NMOS region (102N) are Si, and the S / D regions (154) in the PMOS region (102P) are SiGe. S / D regions (154) may be formed by any suitable method, such as CVD, CVD epitaxy, MBE, or other suitable method. In some embodiments, portions of the second semiconductor layer (106) on both sides of each sacrificial gate stack (128) are completely removed, and S / D regions (154) are formed on the N-well region (103N) of the pins (110a-b). The S / D regions (154) may be grown vertically and horizontally to form facets that correspond to the crystalline planes of the material used in the substrate (102). In some embodiments, as shown in FIG. 9a, the S / D regions (154) formed on the N-well region (103N) of the pins (110a and 110b) are merged. As illustrated in FIG. 9c, the S / D regions (154) may each have a top surface at a higher level than the top surface of the second semiconductor layer (106).

[0026] In FIGS. 10a to 10c, a contact etch stop layer (CESL) (160) is conformally formed on exposed surfaces of a semiconductor device structure (100). The CESL (160) covers the sidewalls of the sacrificial gate stacks (128), the insulating structure (112), and the S / D regions (152, 154). The CESL (160) may comprise an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique.

[0027] Next, an interlayer dielectric (ILD) layer (162) is formed on the CESL (160). The material for the ILD layer (162) may include compounds containing Si, O, C and / or H such as SiOCH, oxides formed using TEOS (tetraethylorthosilicate), undoped silicate glass, silicon oxide, or doped silicon oxides such as BPSG (borophosphosilicate glass), FSG (fused silica glass), PSG (phosphosilicate glass), BSG (boron-doped silicon glass), and / or other suitable dielectric materials. The ILD layer (162) may be deposited by a PECVD process or other suitable deposition technique.

[0028] After the formation of the ILD layer (162), a planarization process is performed to expose the sacrificial gate electrode layer (132). The planarization process may be any suitable process, such as a CMP process. The planarization process removes portions of the ILD layer (162) and CESL (160) placed on the sacrificial gate stacks (128). The planarization process may also remove the mask structure (134).

[0029] FIG. 11 is a cross-sectional view of a semiconductor device structure (100) according to some embodiments. In FIG. 11, the CESL (160), spacer (140), mask structure (134), and S / D regions (152, 154) are omitted for clarity. In some embodiments, because maximum strain occurs at the interface between the ILD layer (162) and the pin (108a), each sacrifice gate stack (128) is under strain caused by the ILD layer (162), and the edge sacrifice gate stacks (128) are under the highest strain. The chart below the semiconductor device structure (100) illustrates the strain applied by the ILD layer (162) on the corresponding sacrifice gate stacks (128). The edge sacrifice gate stacks (128) have the highest strain, and the strain decreases in the direction away from the edge of the pin (108a). In some embodiments, the longer the ILD layer (162) is along the X direction, the higher the strain applied by the ILD layer (162) on the sacrifice gate stacks (128).

[0030] FIGS. 12a, FIGS. 12b, and FIGS. 12c are side cross-sectional views of various stages for manufacturing the semiconductor device structure (100) of FIG. 5, taken along lines AA, BB, and CC, respectively, according to some embodiments. In FIGS. 12a through 12c, a mask structure (134) (if not removed during the CMP process), sacrificial gate electrode layers (132) ( FIG. 10b), and sacrificial gate dielectric layers (130) ( FIG. 10b) are removed to form an opening (135). The sacrificial gate electrode layers (132) and the sacrificial gate dielectric layers (130) may be removed by one or more etching processes, such as a dry etching process, a wet etching process, or a combination thereof. One or more etching processes selectively remove the sacrificial gate electrode layers (132) and sacrificial gate dielectric layers (130) without substantially affecting the spacer (140), CESL (160), and ILD layer (162). The removal of the sacrificial gate electrode layers (132) and sacrificial gate dielectric layers (130) exposes the uppermost portions of the first and second semiconductor layers (104, 106) in the channel region.

[0031] FIG. 13 is a cross-sectional view of a semiconductor device structure (100) according to some embodiments. In FIG. 13, the CESL (160), spacer (140), mask structure (134), and S / D regions (152, 154) are omitted for clarity. As shown in FIG. 13, the sacrificial gate stacks (128) are removed, and openings (135a-c) are formed. The openings (135a-c) may each have a length (L3, L4, L5) along the X direction. As described above, the sacrificial gate stacks (128) are under strain from the ILD layer (162). In other words, a force (F) is applied to the openings (135a-c) by the ILD layer (162). Accordingly, in some embodiments, the removal of the sacrifice gate stacks (128) causes the openings (135a-b) at high strain locations to contract along the X direction. For example, the length (L3) of the opening (135a) formed by removing the edge sacrifice gate stacks (128) may be substantially smaller than the length (L1) of the edge sacrifice gate stacks (128) (Fig. 6), and the length (L4) of the opening (135b) formed by removing the sacrifice gate stacks (128) adjacent to the edge sacrifice gate stacks (128) may be substantially smaller than the length (L2) of the sacrifice gate stacks (128) adjacent to the edge sacrifice gate stacks (128) (Fig. 6). In some embodiments, the length (L5) of the openings (135c) at the center of the active region (101) may be substantially the same as the length (L2) (Fig. 6) of the central sacrificial gate stacks (128), because the strain is lowest at those locations compared to the locations of the openings (135a, 135b). In other words, the opening closer to the portion of the ILD layer outside the active region (101) has a greater amount of shrinkage.

[0032] In some embodiments, the openings (135c) all have a length (L5), which is greater than the length (L4) of the openings (135b) as a result of higher strain on the openings (136b). In some embodiments, the length (L1) (Fig. 6) of the edge sacrifice gate stacks (128) is equal to the length (L2) (Fig. 6) of the center sacrifice gate stacks (128), and the length (L3) is smaller than the length (L4) as a result of higher strain on the openings (135a). In some embodiments, the length (L1) (Fig. 6) of the edge sacrifice gate stacks (128) is greater than the length (L2) (Fig. 6) of the center sacrifice gate stacks (128), and the length (L3) is greater than the length (L4).

[0033] In FIGS. 14a through 14c, alternate gate structures (177) are formed. The alternate gate structure (177) may include a gate dielectric layer (166) and gate electrode layers (168p, 168n) formed on the gate dielectric layer (166). As can be seen in FIGS. 14b and 14c, the gate dielectric layer (166) is formed on the first and second semiconductor layers (104, 106). The gate dielectric layer (166) may include one or more dielectric layers and may include the same material(s) as the sacrificial gate dielectric layer (130). In some embodiments, the gate dielectric layers (166) may be deposited by one or more ALD processes or other suitable processes. The gate electrode layer (168p, 186n) may comprise one or more layers of electrically conductive materials such as polysilicon, aluminum, copper, titanium, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, AlTi, AlTiO, AlTiC, AlTiN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. For devices in the NMOS region (102N), the gate electrode layer (168n) may comprise an N-type material such as AlTiO, AlTiC, or a combination thereof. For devices in the PMOS region (102P), the gate electrode layer (168p) may comprise a P-type material such as AlTiO, AlTiC, AlTiN, or a combination thereof. The gate electrode layers (168n, 168p) can be formed by PVD, CVD, ALD, electroplating, or other suitable methods. The gate electrode layers (168n, 168p) can be formed at different times using one or more masks.For example, in some embodiments, gate electrode layers (168p) are formed on pins (108a-b, 110a-b), and an etching process is performed to remove portions of the gate electrode layers (168p) located on the pins (108a-b). Next, gate electrode layers (168n) are formed on the pins (108a-b) and the gate electrode layers (168p). Then, a planarization process is performed to remove portions of the gate electrode layers (168n) to expose the gate electrode layers (168p).

[0034] FIG. 15 is a cross-sectional view of a semiconductor device structure (100) according to some embodiments. In FIG. 15, CESL (160), spacer (140), gate dielectric layer (166), and S / D regions (152, 154) are omitted for clarity. As shown in FIG. 15, a plurality of gate electrode layers (168n) are formed in an active region (101). Gate electrode layers (168n1) are located at the edge of the pin (108a), gate electrode layers (168n2) are located adjacent to the gate electrode layers (168n1), and gate electrode layers (168n3) are located between the gate electrode layers (168n2). In some embodiments, each gate electrode layer (168n1) has a gate length (L6), each gate electrode layer (168n2) has a gate length (L7), and each gate electrode layer (168n3) has a gate length (L8). As described above, the gate length (L6) may be the smallest, the gate length (L7) may be larger than the gate length (L6), and the gate length (L8) may be larger than the gate length (L7) as a result of the force (F) applied by the ILD layer (162). In some applications, such as radio frequency (RF) devices, active devices with mismatched gate lengths may result in a mismatch in gate resistance, gate-to-environment total capacitance, and maximum power gain cutoff frequency. Accordingly, in some embodiments, a plurality of gate electrode layers (168n3) having a uniform gate length (L8) are active gates, while gate electrode layers (168n1, 168n2) located at the periphery of the active region (101) are dummy gates. The term “dummy gate” may refer to a gate electrode layer that is not a functional part of an active or passive device and can be electrically isolated from other structures.By manufacturing gate electrode layers (168n3) having uniform gate length active gates, the gate resistance, gate-to-environment total capacitance, and mismatch at the maximum power gain cutoff frequency are reduced.

[0035] In some embodiments, as described in FIG. 6, the length (L1) is substantially larger than the length (L2) to cover the edge of the pin (108a). As a result, the gate length (L6) may be larger than the gate lengths (L7, L8). The gate length (L6) may be 1 / 10 to 10 times the length (L8), and the gate length (L7) is smaller than the gate length (L8). In some embodiments, the distance between the gate electrode layer (168n1) and the gate electrode layer (168n2) is about 1 / 10 to about 10 times the distance between adjacent gate electrode layers (168n3).

[0036] In some embodiments, the gate electrode layers (168n1) comprise materials different from those of the gate electrode layers (168n2, 168n3). For example, the gate electrode layers (168n1) comprise the same material as the sacrificial gate electrode layer (132). An alternative gate process is not performed on the sacrificial gate electrode layers (132) located at the edge of the active region (101). In other words, the gate electrode layers (168n1) are the sacrificial gate electrode layers (132). During the process for removing the sacrificial gate electrode layers (132) illustrated in FIG. 12b and FIG. 12c, a mask (not shown) may be formed on the sacrificial gate electrode layers (132) located at the edge of the active region (101). In some embodiments, the gate electrode layers (168n2) comprise the same materials as the gate electrode layers (168n3). In other words, the gate electrode layers (168n2, 168n3) are formed as a result of an alternative gate process, and the gate electrode layers (168n2, 168n3) comprise the same materials. In some embodiments, each of the gate electrode layers (168n1) comprises polysilicon, and each of the gate electrode layers (168n2, 168n3) comprises Ti, Ta, TiN, TaN, tungsten, or other suitable materials.

[0037] FIGS. 16a and FIGS. 16b are side cross-sectional views of various stages for manufacturing the semiconductor device structure (100) of FIG. 5, taken along lines AA and BB, respectively, according to some embodiments. In some embodiments, a conductive feature (172) is formed in the ILD layer (162) and CESL (160), and a silicide layer (170) is formed between the conductive feature (172) and the S / D region (152) or the S / D region (154). The conductive feature (172) may comprise any suitable electrically conductive material. In some embodiments, the conductive feature (172) may comprise tungsten (W), platinum (Pt), tantalum (Ta), titanium (Ti), copper (Cu), cobalt (Co), ruthenium (Ru), rhodium (Rh), iridium (Ir), molybdenum (Mo), or other suitable metal. The silicide layer (170) may include any suitable material such as titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, copper silicide, or molybdenum silicide.

[0038] FIG. 17 is a cross-sectional view of a semiconductor device structure (100) according to some embodiments. In FIG. 17, CESL (160), spacer (140), gate dielectric layer (166), and S / D regions (152, 154) are omitted for clarity. As shown in FIG. 17, conductive features (172) are formed between adjacent gate electrode layers (168n1-3). In some embodiments, conductive features (172) are formed between gate electrode layer (168n1) and gate electrode layer (168n2), and the conductive features (172) are dummy conductive features that are not functional parts of the active or passive device and can be electrically isolated from other structures.

[0039] FIGS. 18a and FIGS. 18b are side cross-sectional views of various stages for manufacturing the semiconductor device structure (100) of FIG. 5, taken along lines AA and BB, respectively, according to some embodiments. As shown in FIGS. 18a and FIGS. 18b, an etching stop layer (180) is deposited on the semiconductor device structure (100), and another ILD layer (182) is deposited on the etching stop layer (180). The etching stop layer (180) may comprise the same material as CESL (160), and the ILD layer (182) may comprise the same material as ILD layer (162). Next, conductive features (184) are formed on the ILD layer (182) and the etching stop layer (180). The conductive features (184) may comprise any suitable electrically conductive material, such as metal. In some embodiments, conductive features (184) are formed on active gate electrode layers (168n), such as gate electrode layers (168n3) (Fig. 19).

[0040] FIG. 19 is a cross-sectional view of a semiconductor device structure (100) according to some embodiments. In FIG. 18, CESL (160), spacer (140), gate dielectric layer (166), S / D regions (152, 154), conductive features (172), etching stop layer (180), and ILD layer (182) are omitted for clarity. As shown in FIG. 19, conductive features (184) are formed on the gate electrode layer (168n3) but not on the gate electrode layers (168n1, 168n2). Since the gate electrode layers (168n1, 168n2) are dummy gates, conductive features (184) are not formed on them. Instead, the etching stop layer (180) (Fig. 18a) is in direct contact with the top surface of the gate electrode layers (168n1, 168n2).

[0041] FIGS. 20, FIGS. 21 and FIGS. 22 are top views of a semiconductor device structure (100) according to some embodiments. In FIGS. 20 to 22, CESL (160), spacer (140), gate dielectric layer (166), S / D regions (152, 154), conductive features (172), etching stop layer (180), ILD layer (182) and conductive features (184) are omitted for clarity. As shown in FIG. 20, the semiconductor device structure (100) includes a pin (200), which may be any of the pins (108a-b, 110a-b). In the active region (101), the semiconductor device structure (100) comprises a plurality of active gate electrode layers (168a) disposed between at least four dummy gate electrode layers (168d), and there are at least two dummy gate electrode layers (168d) on each side of the plurality of active gate electrode layers (168a). The number of active gate electrode layers (168a) can be any suitable number, for example, from one to about 100. In some embodiments, the outermost dummy gate electrode layers (168d) are gate electrode layers (168n1) (Fig. 15) having a gate length (L6), the dummy gate electrode layer (168d) located adjacent to the outermost dummy gate electrode layers (168d) is a gate electrode layer (168n2) (Fig. 15) having a gate length (L7), and the active gate electrode layers (168a) are gate electrode layers (168n3) (Fig. 15) having a gate length (L8). Because the active gate electrode layers (168a) have a uniform gate length (L8), the mismatch in gate resistance, gate-to-environment total capacitance, and maximum power gain cutoff frequency is reduced.

[0042] In some embodiments, as described above, the gate electrode layers (168n1) and the gate electrode layers (168n2) may comprise different materials. Accordingly, the dummy gate electrode layers (168d) may comprise different materials. For example, a first dummy gate electrode layer (168d) located on the first side of the active region (101) comprises a first material, and a second dummy gate electrode layer (168d) located adjacent to the first dummy gate electrode layer (168d) comprises a second material different from the first material. In some embodiments, the first material is polysilicon, and the second material is a metal.

[0043] In some embodiments, as illustrated in FIG. 21, the active region (101) includes a central region (202), a first side region (204), and a second side region (206). The central region (202) includes active gate electrode layers (168a), the first side region (204) includes a first number of dummy gate electrode layers (168d), and the second side region (206) includes a second number of dummy gate electrode layers (168d). A portion of the ILD layer (162) located adjacent to the first side region (204) has a length (L9) along the X direction, and a portion of the ILD layer (162) located adjacent to the second side region (206) has a length (L10) along the X direction. Each portion of the ILD layer (162) having lengths (L9, L10) is continuous and is not interrupted by any features, such as gate electrode layers in an active region adjacent to the active region (101) or dummy gate electrode layers in an isolation region surrounding the active region (101).

[0044] In some embodiments, lengths (L9, L10) determine the first and second number of dummy gate electrode layers (168d). The force (F) (Fig. 13) is based on the length of the portion of the ILD layer (162) along the X direction adjacent to the active region (101). The longer the length, the greater the force (F). With a greater force (F), more openings (135) (Fig. 13) are contracted along the X direction, which can result in more gate electrode layers having a smaller gate length. In some embodiments, gate electrode layers having a smaller gate length are designated as dummy gate electrode layers to reduce the gate resistance, the gate-to-environment total capacitance, and the mismatch at the maximum power gain cutoff frequency. Referring again to FIG. 21, in some embodiments, length (L9) determines a first number of dummy gate electrode layers (168d) in a first side region (204), and length (L10) determines a second number of dummy gate electrode layers (168d) in a second side region (206). The longer the length (L9), the larger the first number, and the longer the length (L10), the larger the second number. For example, in one embodiment, length (L9) is about 100 nm, and the first number is 1. In another embodiment, length (L9) is about 1000 nm, and the first number is 20. A similar relationship may be found between length (L10) and the second number of dummy gate electrode layers (168d) in the second side region (206). In some embodiments, length (L9) and the first number have a positive relationship, and length (L10) and the second number have a positive relationship. In some embodiments, the length (L9) is the same as the length (L10), and the first number is the same as the second number. In some embodiments, the length (L9) is different from the length (L10), and the first number is different from the second number. For example, the length (L9) is greater than the length (L10), and the first number is greater than the second number.

[0045] In some embodiments, as shown in FIG. 22, since the S / D regions (152, 154) located adjacent to the dummy gate electrode layers (168d) are dummy S / D regions, there are no conductive features (172) located between the dummy gate electrode layers (168d). Therefore, there is no need to provide an electrical path for the dummy S / D regions. In some embodiments, as shown in FIG. 20, conductive features (172) are formed between the dummy gate electrode layers (168d), and conductive features (172) are formed to assist in the loading effect.

[0046] FIGS. 23a, FIGS. 23b, FIGS. 23c and FIGS. 23d are top views of a semiconductor device structure (100) according to some embodiments. In FIGS. 23a through 23d, various components of the semiconductor device structure (100) are omitted for clarity. As shown in FIG. 23a, the semiconductor device structure (100) includes pins (108a-b, 110a-b), a plurality of active gate electrode layers (168a), and a plurality of dummy gate electrode layers (168d). In some embodiments, each active gate electrode layer (168a) and dummy gate electrode layer (168d) includes a gate electrode layer (168p) placed over the pins (110a-b) and a gate electrode layer (168n) placed over the pins (108a-b).

[0047] As illustrated in FIG. 23b, in some embodiments, the outermost dummy gate electrode layers (168d) are sacrificial gate electrode layers (132), because a mask (not shown) is formed on the outermost sacrificial gate electrode layer (132) during the alternative gate process described in FIG. 12a to FIG. 12c.

[0048] As illustrated in FIG. 23c, in some embodiments, all dummy gate electrode layers (168d) are sacrificial gate electrode layers (132). During the replacement gate process described in FIG. 12a through FIG. 12c, a mask (not shown) is formed on all sacrificial gate electrode layers (132) designated as dummy gate electrode layers (168d).

[0049] As illustrated in FIG. 23d, in some embodiments, all dummy gate electrode layers (168d) include gate electrode layers (168p) (or gate electrode layers (168n)) but do not include gate electrode layers (168n) (or gate electrode layers (168p)). During the formation of the gate electrode layers (168n, 168p), and after the formation of the gate electrode layers (168p), a mask (not shown) may be formed over the gate electrode layers (168p) designated as dummy gate electrode layers (168d). The portions of the gate electrode layers (168p) designated as dummy gate electrode layers (168d) placed over the pins (108a-b) are not removed during the removal of the portions of the gate electrode layers (168p) designated as active gate electrode layers (168a) placed over the pins (108a-b).

[0050] The embodiments illustrated in FIGS. 23a to 23d can be combined with each other or with the embodiments illustrated in FIGS. 20 to 22.

[0051] FIG. 24 is a plan view of a semiconductor device structure (100) according to some embodiments. As shown in FIG. 24, the semiconductor device structure (100) includes an active region (101) surrounded by dummy regions (210). Each dummy region (210) includes a pin (212) and one or more dummy gate electrode layers (168d). In some embodiments, the pins (212) aligned with the pin (200) along the X direction are part of the pin (200). As shown in FIG. 24, the active region (101) includes one or more active gate electrode layers (168a), and the active gate electrode layers (168a) are positioned between four dummy gate electrode layers (168d), with at least two on each side.

[0052] In some embodiments, the distance (S1) is between the centerline of the adjacent dummy gate electrode layer (168d) of the adjacent dummy region (210) along the X direction and the centerline of the outermost dummy gate electrode layer (168d), the distance (S1A) is between the outer edge of the adjacent dummy gate electrode layer (168d) of the adjacent dummy region (210) along the X direction and the outer edge of the outermost dummy gate electrode layer (168d), the distance (S2) is between the pin (200) and the pin (212) along the Y direction, and the distance (S2A) is between the adjacent dummy gate electrode layer (168d) of the adjacent dummy gate (210) along the Y direction and the active gate electrode layer (168a). The distance (S1A) may be the length (L9, L10) of the portions of the ILD layer (162) shown in FIG. 21. In some embodiments, the distance (S1) is about 1 / 2 to about 100 times the gate length (L8) (Fig. 19), the distance (S2) is about 1 / 2 to about 100 times the gate length (L8), the distance (S1A) is about 1 / 3 to about 300 times the gate length (L8), and the distance (S2A) is about 1 / 3 to about 100 times the length (L8).

[0053] The present disclosure in various embodiments provides a semiconductor device structure (100) comprising an active region (101) having at least two dummy gate electrode layers (168d) disposed on each side of one or more active gate electrode layers (168a). The gate length of the dummy gate electrode layers (168d) is different from the gate length of the active gate electrode layers (168a). Some embodiments may achieve advantages. For example, due to the active gate electrode layers (168a) having uniform gate lengths, the gate resistance, gate-to-environment total capacitance, and mismatch at the maximum power gain cutoff frequency may be reduced.

[0054] An embodiment is a semiconductor device structure. The structure includes an active region, and the active region includes a pin extending over a substrate, a first dummy gate electrode layer disposed on the pin, a second dummy gate electrode layer adjacent to the first dummy gate electrode layer, a third dummy gate electrode layer disposed on the pin, and a fourth dummy gate electrode layer adjacent to the third dummy gate electrode layer. The second dummy gate electrode layer and the third dummy gate electrode layer are disposed between the first dummy gate electrode layer and the fourth dummy gate electrode layer. The active region further includes an active gate electrode layer disposed on the pin, and the active gate electrode layer is disposed between the second dummy gate electrode layer and the third dummy gate electrode layer.

[0055] Another embodiment is a semiconductor device structure. The structure includes a dielectric layer disposed on a substrate, and the dielectric layer includes a first portion having a first length and a second portion having a second length. The structure further includes an active region located between the first portion and the second portion of the dielectric layer, and the active region includes a pin extending over the substrate, one or more active gate electrode layers disposed on the pin, and a first number of dummy gate electrode layers disposed on a first side of the one or more active gate electrode layers and adjacent to the first portion of the dielectric layer. The first number and the first length have a first positive relationship. The active region includes a second number of dummy gate electrode layers disposed on a second side of the one or more active gate electrode layers opposite the first side and adjacent to the second portion of the dielectric layer.

[0056] An additional embodiment is a method. The method comprises the steps of depositing an interlayer dielectric (ILD) layer on a substrate and removing a first sacrificial gate stack, a second sacrificial gate stack, a third sacrificial gate stack, a fourth sacrificial gate stack, and a fifth sacrificial gate stack to form a first opening, a second opening, a third opening, a fourth opening, and a fifth opening. The first opening is adjacent to the second opening, and the fourth opening is adjacent to the fifth opening. The method further comprises the step of shrinking the first opening, the second opening, the fourth opening, and the fifth opening, wherein the first opening has a greater amount of shrinkage than the second opening, and the fifth opening has a greater amount of shrinkage than the fourth opening. The method further includes the step of depositing a first dummy gate electrode layer in a first opening, a second dummy gate electrode layer in a second opening, an active gate electrode layer in a third opening, a third dummy gate electrode layer in a fourth opening, and a fourth dummy gate electrode layer in a fifth opening. The first dummy gate electrode layer has a first gate length, the second dummy gate electrode layer has a second gate length, the active gate electrode layer has a third gate length, and the first gate length and the second gate length are different from the third gate length.

[0057] The foregoing describes the features of various embodiments to enable those skilled in the art to better understand the aspects of the present disclosure. Those skilled in the art should recognize that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure.

[0058] Examples

[0059] Example 1. In a semiconductor device structure,

[0060] It includes an active region, and the active region is,

[0061] Pin extending over the substrate;

[0062] A first dummy gate electrode layer placed on the above pin;

[0063] A second dummy gate electrode layer adjacent to the first dummy gate electrode layer;

[0064] A third dummy gate electrode layer placed on the above pin;

[0065] A fourth dummy gate electrode layer adjacent to the third dummy gate electrode layer - the second dummy gate electrode layer and the third dummy gate electrode layer are disposed between the first dummy gate electrode layer and the fourth dummy gate electrode layer -; and

[0066] An active gate electrode layer disposed on the above pin - the active gate electrode layer is disposed between the second dummy gate electrode layer and the third dummy gate electrode layer -

[0067] A semiconductor device structure comprising

[0068] Example 2. In Example 1,

[0069] A semiconductor device structure wherein the first dummy gate electrode layer comprises a first material, the second dummy gate electrode layer comprises a second material, the third dummy gate electrode layer comprises a third material, the fourth dummy gate electrode layer comprises a fourth material, and the active gate electrode layer comprises a fifth material.

[0070] Example 3. In Example 2,

[0071] A semiconductor device structure in which the first material, the second material, the third material, the fourth material, and the fifth material include the same material.

[0072] Example 4. In Example 2,

[0073] A semiconductor device structure in which the first material, the second material, the third material, and the fourth material are different from the fifth material.

[0074] Example 5. In Example 2,

[0075] A semiconductor device structure in which the first material is different from the second material, and the second material is different from the fifth material.

[0076] Example 6. In Example 1,

[0077] A semiconductor device structure in which the first dummy gate electrode layer has a first gate length, the second dummy gate electrode layer has a second gate length, and the active gate electrode layer has a third gate length.

[0078] Example 7. In Example 6,

[0079] A semiconductor device structure in which the first gate length is greater than the second gate length, and the third gate length is greater than the second gate length and smaller than the first gate length.

[0080] Example 8. In a semiconductor device structure,

[0081] A dielectric layer disposed on a substrate - said dielectric layer comprises a first portion having a first length and a second portion having a second length -; and

[0082] The above-mentioned genome layer includes an active region located between the first portion and the second portion, and the active region comprises,

[0083] A pin extending over the above substrate;

[0084] One or more active gate electrode layers disposed on the above pin;

[0085] A first number of dummy gate electrode layers disposed on a first side of the one or more active gate electrode layers and adjacent to the first portion of the dielectric layer - the first number and the first length have a first positive relationship -; and

[0086] A second number of dummy gate electrode layers disposed on the second side of the one or more active gate electrode layers opposite the first side and adjacent to the second portion of the dielectric layer

[0087] A semiconductor device structure comprising

[0088] Example 9. In Example 8,

[0089] A semiconductor device structure in which the second number and the second length have a second positive relationship.

[0090] Example 10. In Example 8,

[0091] A semiconductor device structure in which the first length is the same as the second length, and the first number is the same as the second number.

[0092] Example 11. In Example 8,

[0093] A semiconductor device structure in which the first length is different from the second length and the first number is different from the second number.

[0094] Example 12. In Example 11,

[0095] A semiconductor device structure in which the first length is greater than the second length, and the first number is greater than the second number.

[0096] Example 13. In Example 8,

[0097] A semiconductor device structure in which the first number is 2 and the second number is 2.

[0098] Example 14. In Example 8,

[0099] A semiconductor device structure in which the first number is greater than 2 and the second number is greater than 2.

[0100] Example 15. In Example 14,

[0101] A semiconductor device structure in which the dummy gate electrode layers of the first number of dummy gate electrode layers comprise different materials.

[0102] Example 16. In the method,

[0103] A step of depositing an interlayer dielectric (ILD) layer on a substrate;

[0104] Step of removing a first sacrifice gate stack, a second sacrifice gate stack, a third sacrifice gate stack, a fourth sacrifice gate stack and a fifth sacrifice gate stack to form a first opening, a second opening, a third opening, a fourth opening and a fifth opening - wherein the first opening is adjacent to the second opening and the fourth opening is adjacent to the fifth opening -;

[0105] Step of shrinking the first opening, the second opening, the fourth opening and the fifth opening - the first opening has a larger shrinkage amount than the second opening, and the fifth opening has a larger shrinkage amount than the fourth opening -; and

[0106] A step of depositing a first dummy gate electrode layer in the first opening, a second dummy gate electrode layer in the second opening, an active gate electrode layer in the third opening, a third dummy gate electrode layer in the fourth opening, and a fourth dummy gate electrode layer in the fifth opening - wherein the first dummy gate electrode layer has a first gate length, the second dummy gate electrode layer has a second gate length, and the active gate electrode layer has a third gate length, and the first gate length and the second gate length are different from the third gate length -

[0107] A method including

[0108] Example 17. In Example 16,

[0109] A method in which the first gate length is greater than the second gate length, and the third gate length is greater than the second gate length and smaller than the first gate length.

[0110] Example 18. In Example 16,

[0111] A method further comprising the step of depositing a dielectric layer on the first dummy gate electrode layer, the second dummy gate electrode layer, the third dummy gate electrode layer, the fourth dummy gate electrode layer, and the active gate electrode layer.

[0112] Example 19. In Example 18,

[0113] A method further comprising the step of forming a conductive feature penetrating the dielectric layer above the active gate electrode layer, wherein the first dummy gate electrode layer, the second dummy gate electrode layer, the third dummy gate electrode layer and the fourth dummy gate electrode layer are covered by the dielectric layer.

[0114] Example 20. In Example 19,

[0115] A method in which the conductive feature is not formed on the first dummy gate electrode layer, the second dummy gate electrode layer, the third dummy gate electrode layer and the fourth dummy gate electrode layer.

Claims

Claim 1 A semiconductor device structure comprising an active region, wherein the active region comprises: a pin extending over a substrate; a first dummy gate electrode layer disposed over the pin; a second dummy gate electrode layer adjacent to the first dummy gate electrode layer; a third dummy gate electrode layer disposed over the pin; a fourth dummy gate electrode layer adjacent to the third dummy gate electrode layer—wherein the second dummy gate electrode layer and the third dummy gate electrode layer are disposed between the first dummy gate electrode layer and the fourth dummy gate electrode layer—; and an active gate electrode layer disposed over the pin—wherein the active gate electrode layer is disposed between the second dummy gate electrode layer and the third dummy gate electrode layer—the first dummy gate electrode layer and the fourth dummy gate electrode layer are disposed at the edges of the active region, and the second dummy gate electrode layer and the third dummy gate electrode layer are disposed within the active region. Claim 2 A semiconductor device structure according to claim 1, wherein the first dummy gate electrode layer comprises a first material, the second dummy gate electrode layer comprises a second material, the third dummy gate electrode layer comprises a third material, the fourth dummy gate electrode layer comprises a fourth material, and the active gate electrode layer comprises a fifth material. Claim 3 A semiconductor device structure according to claim 1, wherein the first dummy gate electrode layer has a first gate length, the second dummy gate electrode layer has a second gate length, and the active gate electrode layer has a third gate length. Claim 4 A semiconductor device structure comprising: a dielectric layer disposed on a substrate, wherein the dielectric layer comprises a first portion having a first length and a second portion having a second length; and an active region located between the first portion and the second portion of the dielectric layer, wherein the active region comprises: a pin extending over the substrate; one or more active gate electrode layers disposed on the pin; a first number of dummy gate electrode layers disposed on a first side of the one or more active gate electrode layers and adjacent to the first portion of the dielectric layer, wherein the first number and the first length have a first positive proportional relationship; and a second number of dummy gate electrode layers disposed on a second side of the one or more active gate electrode layers opposite to the first side and adjacent to the second portion of the dielectric layer, wherein the second number and the second length have a second positive proportional relationship. Claim 5 A semiconductor device structure according to claim 4, wherein the first length is the same as the second length and the first number is the same as the second number. Claim 6 A semiconductor device structure according to claim 4, wherein the first length is different from the second length and the first number is different from the second number. Claim 7 A semiconductor device structure according to claim 6, wherein the first length is greater than the second length and the first number is greater than the second number. Claim 8 A semiconductor device structure according to claim 4, wherein the first number is 2 and the second number is 2. Claim 9 A semiconductor device structure according to claim 4, wherein the first number is greater than 2 and the second number is greater than 2. Claim 10 A method comprising: a step of depositing an interlayer dielectric (ILD) layer on a substrate; a step of removing a first sacrificial gate stack, a second sacrificial gate stack, a third sacrificial gate stack, a fourth sacrificial gate stack, and a fifth sacrificial gate stack to form a first opening, a second opening, a third opening, a fourth opening, and a fifth opening, wherein the first opening is adjacent to the second opening and the fourth opening is adjacent to the fifth opening; a step of shrinking the first opening, the second opening, the fourth opening, and the fifth opening, wherein the first opening has a greater amount of shrinkage than the second opening and the fifth opening has a greater amount of shrinkage than the fourth opening. A method comprising the step of depositing a first dummy gate electrode layer in the first opening, a second dummy gate electrode layer in the second opening, an active gate electrode layer in the third opening, a third dummy gate electrode layer in the fourth opening, and a fourth dummy gate electrode layer in the fifth opening— wherein the first dummy gate electrode layer has a first gate length, the second dummy gate electrode layer has a second gate length, and the active gate electrode layer has a third gate length, and the first gate length and the second gate length are different from the third gate length.

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