Memory device and semiconductor device

Abstract

One of the objectives of the present invention is to provide a memory device capable of suppressing power consumption and a semiconductor device using the memory device. A transistor utilizing an oxide semiconductor film as an active layer is formed in each memory cell of a memory device as a switching element for holding a charge accumulated in a transistor functioning as a memory element. Additionally, the transistor used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

Description

Technology Field

[0001] The present invention relates to a non-volatile semiconductor memory device, and to the configuration and operation method of a memory cell that holds data. Background Technology

[0003] Semiconductor memory devices (hereinafter simply referred to as memory devices) include volatile memory such as DRAM and SRAM, and non-volatile memory such as mask ROM, EPROM, EEPROM, flash memory, and ferroelectric memory. Most of these memories, formed using a single-crystal semiconductor substrate, have already been commercialized. Among the above semiconductor memories, flash memory is a non-volatile memory that can repeatedly write and erase data and retain data even without a power supply, so it is highly convenient and also resistant to physical shock. Therefore, it is mainly used in portable memory media such as USB memory and memory cards and is widely distributed in the market.

[0004] Flash memory includes NAND type, which has a structure in which multiple memory cells are connected in series, and NOR type, which has a structure in which multiple memory cells are connected in a matrix shape; however, both types of flash memory have a transistor in each memory cell that functions as a memory element. Furthermore, this transistor functioning as a memory element has an electrode for accumulating charge called a floating gate between the gate electrode and the semiconductor film acting as the active layer, and data can be stored by accumulating charge at the floating gate.

[0005] Patent documents 1 and 2 below describe a thin-film transistor having a floating gate formed on a glass substrate. Prior art literature

[0007] Japanese Patent Publication No. Hei 6-021478 and Japanese Patent Publication No. 2005-322899 The problem to be solved

[0008] However, the absolute value of the voltage applied to the memory element during data writing in non-volatile memory is around 20V, which tends to be generally higher than that of volatile memory. In the case of flash memory, which allows for repeated data rewriting, it is necessary to apply a large voltage to the transistor used as the memory element not only during data writing but also during data erasure. Consequently, the power consumed during the operation of flash memory, such as data writing and erasing, is high, and this is one of the factors preventing low power consumption in electronic devices that use flash memory as a storage device. In particular, when flash memory is used in portable electronic devices such as cameras or mobile phones, high power consumption leads to the disadvantage of shortened continuous usage time.

[0009] In addition, although flash memory is a non-volatile memory, data is lost due to leakage of minute charges. Therefore, the data retention period is known to be about 5 to 10 years, so there is a demand for the realization of flash memory capable of securing a longer retention period.

[0010] In addition, although flash memory can repeatedly write and erase data, the gate insulating film is prone to deterioration due to tunnel current when accumulating charge on the floating gate. Therefore, the number of data rewrite cycles in a single memory element is limited to tens of thousands to hundreds of thousands, and there is a demand for the realization of flash memory capable of withstanding a much larger number of rewrite cycles.

[0011] In light of the aforementioned problem, one of the objectives of the present invention is to provide a memory device capable of suppressing power consumption and a semiconductor device using said memory device. Furthermore, one of the objectives of the present invention is to provide a memory device capable of retaining data for a longer period and a semiconductor device using said memory device. Additionally, one of the objectives of the present invention is to provide a memory device capable of increasing the number of data rewrite cycles and a semiconductor device using said memory device. means of solving the problem

[0013] In one embodiment of the present invention, a non-volatile memory device is constructed by using a transistor equipped with a second gate electrode for controlling a threshold voltage in addition to a conventional gate electrode as a memory element. In the memory device, data is written by controlling the potential of the second gate electrode for controlling the threshold voltage of the transistor used as a memory element by a transistor having a very small off-current, rather than injecting a charge at a high voltage into a floating gate surrounded by an insulating film. That is, the memory device according to one embodiment of the present invention is characterized by being composed of at least a transistor whose threshold voltage is controlled by the second gate electrode, a capacitance element for holding the potential of the second gate electrode, and a transistor used as a switching element for controlling the charging and discharging of the capacitance element.

[0014] The amount of shift in the threshold voltage of a transistor used as a memory element is controlled by the height of the potential of the second gate electrode, more specifically, by the potential difference between the source electrode and the second gate electrode. And, the difference in the height of the threshold voltage, or the difference in the resistance value between the source electrode and the drain electrode due to the difference in the height of the threshold voltage, becomes the difference in the data stored by the memory element.

[0015] The transistor used as a memory element is preferably an insulated gate type field-effect transistor, and specifically, has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

[0016] Furthermore, the transistor used as a switching element is characterized by including a semiconductor material in the channel forming region that has a wider band gap than silicon and an intrinsic carrier density lower than silicon. By including a semiconductor material having the characteristics described above in the channel forming region, a transistor with very low off-current can be realized. Examples of such semiconductor materials include oxide semiconductors, silicon carbide, and gallium nitride that have a large band gap of about three times that of silicon.

[0017] Furthermore, oxide semiconductors are metal oxides that exhibit semiconductor properties, combining the high mobility obtained from microcrystalline or polycrystalline silicon with the uniform device characteristics obtained from amorphous silicon. Moreover, a highly purified oxide semiconductor (purified OS), in which impurities such as moisture or hydrogen acting as electron donors are reduced, is Type i (intrinsic semiconductor) or infinitely close to Type i, and a transistor utilizing said oxide semiconductor has the characteristic of having a significantly low off-current. Specifically, by removing impurities such as moisture or hydrogen contained in the oxide semiconductor, the measured value of the hydrogen concentration contained in the oxide semiconductor by Secondary Ion Mass Spectrometry (SIMS) is 5×10 19 / cm 3 Below, preferably 5×10 18 / cm 3Below, more preferably 5×10 17 / cm 3 Below, more preferably 1×10 16 / cm 3 It shall be as follows. In addition, the carrier density of an oxide semiconductor film measurable by Hall effect measurement is 1×10 14 cm －3 Less than, preferably 1×10 12 cm －3 Less than, more preferably less than the measurement limit, 1×10 11 cm －3 It is made less than. That is, the carrier density of the oxide semiconductor film is infinitely close to zero. In addition, the band gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. By using an oxide semiconductor film that has been purified by sufficiently reducing the concentration of impurities such as moisture or hydrogen, the off-current of the transistor can be lowered.

[0018] Here, we will discuss the analysis of hydrogen concentration within oxide semiconductor films and conductive films. Hydrogen concentration in oxide semiconductor films and conductive films is measured using SIMS. It is known that, due to the nature of SIMS, it is difficult to accurately obtain data near the sample surface or near the stacking interface with films of different materials. Therefore, when analyzing the thickness-direction distribution of hydrogen concentration within a film using SIMS, the average value obtained in the region where the target film exists and a nearly constant value is obtained without extreme fluctuations is adopted as the hydrogen concentration. Furthermore, when the thickness of the film being measured is small, it may be impossible to identify a region where a nearly constant value is obtained due to the influence of hydrogen concentration within adjacent films. In this case, the maximum or minimum value of hydrogen concentration in the region where this film exists is adopted as the hydrogen concentration within this film. In addition, in the region where this membrane exists, if there is no mountain-shaped peak with a maximum value or a valley-shaped peak with a minimum value, the value of the inflection point is adopted as the hydrogen concentration.

[0019] In addition, it has been found that oxide semiconductor films formed by sputtering or the like contain a large amount of moisture or hydrogen as impurities. Since moisture or hydrogen is prone to forming donor levels, it is an impurity in the oxide semiconductor itself. Therefore, in one embodiment of the present invention, in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film, a heat treatment is performed on the oxide semiconductor film under an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (argon, helium, etc.). It is preferable to perform the heat treatment in a temperature range of 500°C or higher and 850°C or lower (or below the deformation point of the glass substrate), preferably 550°C or higher and 750°C or lower. Furthermore, this heat treatment is not to exceed the heat resistance temperature of the substrate used. The effect of heat treatment of moisture or hydrogen on desorption has been confirmed by TDS (Thermal Desorption Spectroscopy).

[0020] Heat treatment is performed using heat treatment in a furnace or the RTA method (rapid thermal annealing method). The RTA method includes a method using a lamp light source and a method of moving the substrate through heated gas to perform heat treatment for a short period of time. By using the RTA method, the time required for heat treatment can be reduced to less than 0.1 hours.

[0021] Specifically, a transistor using an oxide semiconductor film purified by the heat treatment described above as an active layer has, for example, a channel width (W) of 1×10 6Even in the case of a device with a diameter of μm and a channel length (L) of 10 μm, when the voltage between the source and drain electrodes (drain voltage) is in the range of 1 V to 10 V, the off-current (drain current when the voltage between the gate and source electrodes is set to 0 V) ​​is below the measurement limit of the semiconductor parameter analyzer, i.e., 1 × 10⁻⁶ －13 A characteristic of A or less can be obtained. Therefore, it can be seen that the off-current density, which is the value obtained by dividing the off-current by the channel width of the transistor, is 100 zA / μm or less. In addition, as a switching element for holding the charge of the retained capacitance, a transistor having a gate insulating film with a thickness of 100 nm and having a high-purity oxide semiconductor film was used to measure the off-current of the transistor from the trend of the charge amount per unit time of the retained capacitance. As a result, it was found that when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even lower off-current, such as 10 zA / μm to 100 zA / μm, is obtained. Therefore, in a memory device according to one embodiment of the present invention, the off-current density of a transistor using a high-purity oxide semiconductor film as an active layer can be 100 zA / μm or less, preferably 10 zA / μm or less, and more preferably 1 zA / μm or less. Therefore, a transistor using a high-purity oxide semiconductor film as an active layer has a significantly lower off-current when the voltage between the gate electrode and the source electrode is 0 or less compared to a transistor using crystalline silicon.

[0022] Furthermore, transistors using high-purity oxide semiconductors exhibit almost no temperature dependence of off-current. This can be attributed to the fact that removing impurities acting as electron donors from the oxide semiconductor purifies it, causing the conductivity type to approach the intrinsic type infinitely, and the Fermi level to be located at the center of the forbidden band. Additionally, this is due to the fact that the energy gap of the oxide semiconductor is greater than 3 eV and the thermally excited carriers are very small. Moreover, the fact that the source and drain electrodes are in a degenerate state is also a factor in the absence of temperature dependence. Since the operation of the transistor relies mostly on carriers injected into the oxide semiconductor from the degenerate source electrode, and carrier density has no temperature dependence, this explains why the temperature dependence of the off-current is not observed.

[0023] In addition, oxide semiconductors may be used such as quaternary metal oxides, In-Sn-Ga-Zn-O oxide semiconductors, ternary metal oxides, In-Sn-Zn-O oxide semiconductors, In-Al-Zn-O oxide semiconductors, Sn-Ga-Zn-O oxide semiconductors, Al-Ga-Zn-O oxide semiconductors, Sn-Al-Zn-O oxide semiconductors, binary metal oxides, In-Zn-O oxide semiconductors, Sn-Zn-O oxide semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg-O oxide semiconductors, In-Mg-O oxide semiconductors, In-Ga-O oxide semiconductors, In-O oxide semiconductors, Sn-O oxide semiconductors, Zn-O oxide semiconductors, etc. In addition, in this specification, for example, an In-Sn-Ga-Zn-O-based oxide semiconductor means a metal oxide having indium (In), tin (Sn), gallium (Ga), and zinc (Zn), and the stoichiometric composition ratio is not particularly required. In addition, the oxide semiconductor may include silicon.

[0024] Alternatively, oxide semiconductors are in the chemical formula InMO3(ZnO) m It can be expressed as (m>0). Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. Effects of the invention

[0026] By utilizing the above-mentioned transistor with low off-current as a switching element for retaining charge accumulated in a memory element, charge leakage from the memory element can be prevented. Accordingly, a memory device capable of retaining data over a long period and a semiconductor device utilizing this memory device can be provided.

[0027] In addition, the voltage required for writing and reading data to and from the memory element is largely determined by the operating voltage of the transistor functioning as a switching element. Therefore, compared to conventional flash memory, the operating voltage can be significantly lowered, thereby enabling the provision of a memory device with suppressed power consumption and a semiconductor device utilizing this memory device.

[0028] In addition, since the degradation of the gate insulating film due to tunnel current can be suppressed compared to conventional flash, a memory device capable of increasing the number of data rewrite cycles and a semiconductor device using this memory device can be provided. Brief explanation of the drawing

[0030] Figure 1 is a diagram showing the configuration of a memory cell. FIG. 2(A) is a diagram illustrating the configuration of a memory element, and FIG. 2(B) is a diagram illustrating the operation thereof. Figure 3 is a diagram showing the configuration of a memory cell. Figure 4 is a diagram showing the configuration of a memory cell. Figure 5 is a diagram showing the configuration of a cell array. Figure 6 is a diagram showing the configuration of a cell array. Figure 7 is a timing chart showing the operation method of a memory device. FIG. 8 is a diagram showing the configuration of a memory device. FIG. 9 is a diagram showing the configuration of a reading circuit. FIG. 10 is a cross-sectional view of a memory cell showing a method of manufacturing a memory device. FIG. 11 is a top view of a memory cell. FIG. 12 is a cross-sectional view of an inverse stagger type transistor using an oxide semiconductor. FIG. 13 is an energy band diagram (schematic) on A–A’ shown in FIG. 12. FIG. 14(A) shows a state in which a positive voltage (VG > 0) is applied to the gate electrode (GE), and FIG. 14(B) shows a state in which a negative voltage (VG < 0) is applied to the gate electrode (GE). Fig. 15 shows the vacuum level and the work function (φ) of the metal. M A diagram showing the relationship between the electron affinity (χ) of oxide semiconductors. FIG. 16 is a diagram showing the configuration of a memory medium. FIG. 17 is a diagram showing the configuration of an electronic device. FIG. 18 is a diagram showing the configuration of a measurement circuit. FIG. 19 is a diagram showing the measurement results (a diagram showing the relationship between elapsed time (Time) and output potential (Vout). FIG. 20 is a diagram showing the measurement results (a diagram showing the relationship between the source-drain voltage (V) and the off-current (I). FIG. 21 is a timing chart showing the operation method of a memory device. Specific details for implementing the invention

[0031] In the following, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description below, and those skilled in the art will readily understand that various changes to its form and details can be made without departing from the spirit and scope of the invention. Accordingly, the present invention is not to be interpreted as being limited to the description of the embodiments shown below.

[0032] Furthermore, all semiconductor devices capable of utilizing integrated circuits such as microprocessors and image processing circuits, or memory devices such as RF tags, memory media, and semiconductor display devices, are included within the scope of the present invention. Additionally, semiconductor display devices include liquid crystal display devices, light-emitting devices with light-emitting elements represented by organic light-emitting diodes (OLEDs) for each pixel, electronic paper, digital micromirror devices (DMDs), plasma display panels (PDPs), and field emission displays (FEDs), which have circuit elements utilizing semiconductor films in the pixel portion or driving circuit.

[0034] (Embodiment 1)

[0035] FIG. 1(A) shows an example of a circuit diagram of a memory cell corresponding to the minimum unit of the memory device of the present invention. The memory cell (100) shown in FIG. 1(A) has a transistor (101) that functions as a memory element and a transistor (102) that functions as a switching element capable of controlling the supply of potential to the second gate electrode of the transistor (101). In addition, the memory cell (100) may have a capacitance element (103) formed therein for holding the potential of the second gate electrode of the transistor (101).

[0036] Additionally, the memory cell (100) may have other circuit elements such as diodes, resistors, and inductors as needed.

[0037] A transistor (101) functioning as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film. Various operations of the memory device can be controlled by the potential applied to the first gate electrode, the second gate electrode, the source electrode, and the drain electrode of the transistor (101).

[0038] The transistor (102) functioning as a switching element includes a semiconductor material having a wider band gap than silicon and a lower intrinsic carrier density than silicon in the channel forming region. This is because the off-current can be sufficiently reduced by using such a semiconductor material in the channel forming region of the transistor (102).

[0039] Examples of semiconductor materials that have a wider band gap than silicon semiconductors and a lower intrinsic carrier density than silicon include compound semiconductors such as silicon carbide (SiC) and gallium nitride (GaN), and oxide semiconductors made of metal oxides such as zinc oxide (ZnO). Among these, oxide semiconductors can be fabricated by sputtering or wet methods (such as printing), and have the advantage of excellent mass production capability. Furthermore, while the process temperature of silicon carbide is approximately 1500°C and that of gallium nitride is approximately 1100°C, the deposition temperature of oxide semiconductors is low at 300–500°C (below the glass transition temperature, with a maximum of about 700°C), allowing for deposition on inexpensive and readily available glass substrates. Additionally, it is possible to stack semiconductor devices made of oxide semiconductors on integrated circuits that do not have resistance to heat treatment at high temperatures of 1500°C to 2000°C. Moreover, it is possible to accommodate larger substrate sizes. Therefore, among the wide-gap semiconductors described above, oxide semiconductors, in particular, have the advantage of high mass production capability. In addition, even when seeking to obtain a crystalline oxide semiconductor to improve the performance of a transistor (e.g., field-effect mobility), a crystalline oxide semiconductor can be easily obtained by heat treatment at 450°C to 800°C.

[0040] In the following description, an example is given of using an oxide semiconductor having the above advantages as the semiconductor film of the second transistor (102).

[0041] Additionally, FIG. 1(A) shows a configuration in which a memory cell (100) has only one transistor (102) that functions as a switching element, but the present invention is not limited to this configuration. In one embodiment of the present invention, at least one transistor that functions as a switching element is installed in each memory cell, and the number of transistors may be multiple. When a memory cell (100) has multiple transistors that function as switching elements, the multiple transistors may be connected in parallel, connected in series, or connected in a combination of series and parallel.

[0042] In addition, the state in which transistors are connected in series means that only one of the source electrode and drain electrode of the first transistor is connected to only one of the source electrode and drain electrode of the second transistor. In addition, the state in which transistors are connected in parallel means that the source electrode of the first transistor is connected to the source electrode of the second transistor, and the drain electrode of the first transistor is connected to the drain electrode of the second transistor.

[0043] In addition, the transistor (102) functioning as a switching element may have a gate electrode existing only on one side of the active layer, unlike the transistor (101) functioning as a memory element. However, the present invention is not limited to this configuration, and the transistor functioning as a switching element may also have a pair of gate electrodes existing with the active layer in between, just like the transistor functioning as a memory element.

[0044] In addition, in one embodiment of the present invention, at least, the transistor (102) functioning as a switching element may have the wide-gap semiconductor material described above in its active layer. Accordingly, an oxide semiconductor film may be used in the active layer of the transistor (101) functioning as a memory element. Alternatively, a semiconductor other than an oxide semiconductor, such as amorphous, microcrystalline, polycrystalline, or single-crystal silicon or germanium, may be used in the active layer of the transistor (101) functioning as a memory element. However, the process can be simplified by using an oxide semiconductor film in the active layer of all transistors in the memory cell (100).

[0045] Next, the connection relationship of the transistor (101), transistor (102), and capacitance element (103) in the memory cell (100) shown in FIG. 1(A) will be explained.

[0046] The gate electrode of the transistor (102) is connected to the writing word line (WL). Also, one of the source electrode and the drain electrode of the transistor (102) is connected to the input data line (Din), and the other is connected to the second gate electrode of the transistor (101). Additionally, the first gate electrode of the transistor (101) is connected to the reading word line (RL). Also, one of the source electrode and the drain electrode of the transistor (101) is connected to the output data line (Dout), and the other is connected to a power line to which a fixed potential, such as ground, is applied.

[0047] Additionally, one of the pair of electrodes of the capacitive element (103) is connected to the second gate electrode of the transistor (101), and the other is connected to a power line to which a fixed potential, such as ground, is applied.

[0048] Furthermore, in this specification, "connection" refers to an electrical connection and corresponds to a state in which current, voltage, or potential can be supplied or transmitted. Accordingly, the state of being connected does not necessarily refer to a state of direct connection, but also includes within its scope a state of indirect connection through circuit elements such as wiring, resistors, diodes, and transistors, so that current, voltage, or potential can be supplied or transmitted.

[0049] Furthermore, even when components that appear independent in the circuit diagram are connected, in reality, a single conductive film may combine the functions of multiple components, such as when a part of the wiring also functions as an electrode. In this specification, the term "connection" includes cases where a single conductive film combines the functions of multiple components.

[0050] In addition, the way the source electrode and drain electrode of a transistor are named changes depending on the polarity of the transistor and the difference in potential applied to each electrode. Generally, in an n-channel type transistor, the electrode to which a low potential is applied is called the source electrode, and the electrode to which a high potential is applied is called the drain electrode. In addition, in a p-channel type transistor, the electrode to which a low potential is applied is called the drain electrode, and the electrode to which a high potential is applied is called the source electrode. In this specification, for convenience, the connection relationship of the transistor is sometimes explained by assuming that the source electrode and the drain electrode are fixed, but in reality, the way the source electrode and the drain electrode are named changes depending on the relationship of the potentials.

[0051] Additionally, FIG. 1(A) illustrates a case where the transistor (102) has a gate electrode on only one side of the active layer. When the transistor (102) has a pair of gate electrodes sandwiched between the active layer, one gate electrode may be connected to a writing word line (WL) and the other gate electrode may be in a floating state where it is electrically insulated, or the potential may be applied from the other side. In the latter case, the same potential may be applied to the pair of electrodes, or a fixed potential, such as ground, may be applied only to the other gate electrode. By controlling the height of the potential applied to the other gate electrode, the threshold voltage of the transistor (102) can be controlled.

[0052] Next, FIG. 1(B) shows an example of a cross-sectional view of a memory cell (100) having the circuit configuration shown in FIG. 1(A). In the memory cell shown in FIG. 1(B), a transistor (101) functioning as a memory element and a transistor (102) functioning as a switching element are formed on a substrate (110) having an insulating surface.

[0053] Specifically, the transistor (101) has a first gate electrode (121) on a substrate (110) having an insulating surface, an insulating film (112) on the first gate electrode (121), an oxide semiconductor film (123) functioning as an active layer that overlaps the first gate electrode (121) with the insulating film (112) in between, a source electrode (124) and a drain electrode (125) on the oxide semiconductor film (123), an insulating film (116) on the oxide semiconductor film (123), the source electrode (124), and the drain electrode (125), and a second gate electrode (126) that overlaps the oxide semiconductor film (123) on the insulating film (116). Additionally, an insulating film (117) is formed on the second gate electrode (126), and the transistor (101) may include the insulating film (117) as a component.

[0054] Additionally, the transistor (102) has a gate electrode (111) on a substrate (110) having an insulating surface, an insulating film (112) on the gate electrode (111), an oxide semiconductor film (113) which functions as an active layer that overlaps the gate electrode (111) with the insulating film (112) in between, and a source electrode (114) and a drain electrode (115) on the oxide semiconductor film (113). An insulating film (116) is formed on the oxide semiconductor film (113), the source electrode (114), and the drain electrode (115), and the transistor (102) may include the insulating film (116) as a component.

[0055] Additionally, the capacitance element (103) is formed in an area where the source electrode (124) of the transistor (101) and the second gate electrode (126) overlap each other with an insulating film (116) in between.

[0056] Next, using FIG. 2, the operation of a transistor functioning as a memory element is explained by taking the case where the transistor (101) is an n-channel type and handles two-value data. In addition, FIG. 2(A) shows a circuit diagram of the transistor (101), and the potential of each electrode of the transistor (101) is indicated as Vcg of the first gate electrode, Vbg of the second gate electrode, Vs of the source electrode, and Vd of the drain electrode.

[0057] First, the operation of the transistor (101) during data writing is explained. During writing, a voltage equal to or lower than the threshold voltage (Vth0) is applied between the first gate electrode and the source electrode of the transistor (101). Additionally, the threshold voltage (Vth0) corresponds to the threshold voltage of the transistor (101) when the potential (Vbg) of the second gate electrode is equal to the potential (Vgnd) of the ground. Specifically, the relationship between the potentials of the first gate electrode and the source electrode during writing is Vcg - Vs ≤ Vth0. Therefore, the transistor (101) is off during writing, and the drain electrode is in a high impedance state.

[0058] And, when writing data, the height of the potential (Vbg) of the second gate electrode is controlled according to the value of the data being written. When handling two values ​​of data, either a high potential (Vdd) or a low potential (Vss) is assigned to the second gate electrode. The relationship between each potential is expressed as Vdd > Vss ≥ Vgnd. For example, when the potential (Vbg) of the second gate electrode is set to a low potential (Vss = Vgnd), the threshold voltage of the transistor (101) remains Vth0. On the other hand, when the potential (Vbg) of the second gate electrode is set to a high potential (Vdd), the threshold voltage of the transistor (101) shifts to the negative side and becomes Vth1.

[0059] In addition, in this embodiment, the case where the low potential (Vss = Vgnd) is used as an example during writing was explained, but the low potential (Vss) does not necessarily have to be the same as the ground potential (Vgnd). For example, Vdd > Vss > Vgnd may be used. However, in this case, the amount of shift in the threshold voltage is made smaller than the amount of shift in the threshold voltage when the potential (Vbg) of the second gate electrode is set to a high potential (Vdd).

[0060] Next, the operation of the transistor (101) when holding data will be explained. When holding data, the transistor (102) that functions as a switching element is off. As described above, since the off current of the transistor (102) is significantly low, the potential (Vbg) of the second gate electrode holds the height set at the time of writing.

[0061] Next, the operation of the transistor (101) during data reading will be described. During reading, the transistor (101) is given a voltage higher than the threshold voltage (Vth1) and lower than the threshold voltage (Vth0) between the first gate electrode and the source electrode.

[0062] And, when the threshold voltage of the transistor (101) is set to Vth1 during the data writing performed immediately prior, the voltage between the first gate electrode and the source electrode becomes higher than the threshold voltage (Vth1), so the transistor (101) turns on, and the resistance value between the source electrode and the drain electrode decreases. Therefore, the potential (Vs) of the source electrode is applied to the drain electrode. On the other hand, when the threshold voltage of the transistor (101) is set to Vth0 during the data writing performed immediately prior, even if the voltage between the first gate electrode and the source electrode becomes higher than the threshold voltage (Vth1), the transistor (101) remains off if it is lower than the threshold voltage (Vth0). Therefore, the resistance value between the source electrode and the drain electrode is high, and the potential (Vd) of the drain electrode of the transistor (101) remains in a high impedance state.

[0063] Accordingly, the potential (Vd) of the drain electrode is linked to the height of the potential applied to the second gate electrode at the time of writing the data immediately preceding it. FIG. 2(B) shows the relationship between the potential (Vcg) of the first gate electrode and the drain current (Id) of the transistor (101) at the time of reading. Line (130) shows the relationship between the potential (Vcg) and the drain current (Id) when the threshold voltage is set to Vth1, and line (131) shows the relationship between the potential (Vcg) and the drain current (Id) when the threshold voltage is set to Vth0. As shown in FIG. 2(B), when the voltage between the first gate electrode and the source electrode is set to a potential (Vread) that is higher than the threshold voltage (Vth1) and lower than the threshold voltage (Vth0), the drain current (Id1) obtained from the line (130) and the line (131) when the threshold voltage is Vth1 becomes higher than the drain current (Id0) obtained when the threshold voltage is Vth0. Therefore, by reading the value of the drain current (Id) or the potential (Vd) of the drain electrode, the value of the written data can be determined.

[0064] In addition, in the present embodiment 1, the case where the voltage between the first gate electrode and the source electrode is higher than the threshold voltage (Vth1) and lower than the threshold voltage (Vth0) during reading was described, but the present invention is not limited to this configuration. The voltage between the first gate electrode and the source electrode during reading does not necessarily have to be lower than the threshold voltage (Vth0). For example, when the threshold voltage of the transistor (101) is set to Vth1 during the data writing performed immediately before, if the voltage between the first gate electrode and the source electrode is higher than the threshold voltage (Vth0) during reading, the transistor (101) turns on, and the resistance value between the source electrode and the drain electrode decreases. At this time, the resistance value between the source electrode and the drain electrode is called Rds0. Meanwhile, when the threshold voltage of the transistor (101) is set to Vth0 during the data writing performed immediately prior to, when the voltage between the first gate electrode and the source electrode is higher than the threshold voltage (Vth0) during reading, the transistor (101) is turned on, and the resistance value between the source electrode and the drain electrode is lowered. At this time, the resistance value between the source electrode and the drain electrode is called Rds1. And, at least when the threshold voltage is set to Vth1, by operating the transistor (101) in the saturation region, even when the transistor (101) is in the ON state during reading at either the threshold voltage setting of Vth1 or Vth0, the resistance value between the source electrode and the drain electrode can be made to have a difference such that Rds0 < Rds1. Specifically, if the voltage between the first gate electrode and the source electrode is Vgs and the voltage between the source electrode and the drain electrode is Vds, it is preferable to operate the transistor (101) in a range satisfying |Vds| > |Vgs-Vth0|.By making the resistance value between the source electrode and the drain electrode different such that Rds0 < Rds1, it is possible to link the potential (Vd) of the drain electrode to the height of the potential applied to the second gate electrode during the data writing performed immediately prior to reading, even if the voltage between the first gate electrode and the source electrode during reading is higher than the threshold voltage (Vth0). For example, as shown in FIG. 2(B), when the voltage between the first gate electrode and the source electrode is set to a potential (Vread') higher than the threshold voltage (Vth0), the drain current (Id1') obtained from line (130) and line (131) when the threshold voltage is Vth1 becomes higher than the drain current (Id0') obtained when the threshold voltage is Vth0. Therefore, by reading the value of the drain current (Id) or the potential (Vd) of the drain electrode, the value of the written data can be determined.

[0065] Next, the operation of the transistor (101) during data erasure will be described. During erasure, the transistor (101) is subjected to a voltage equal to or lower than the threshold voltage (Vth1) between the first gate electrode and the source electrode, just as it is during data writing. Specifically, the relationship between the potentials of the first gate electrode and the source electrode during erasure is Vcg - Vs ≤ Vth1. Therefore, the transistor (101) is off during erasure, and the drain electrode is in a high impedance state. Also, during data erasure, the potential (Vbg) of the second gate electrode is set to a fixed potential such as ground, and the threshold voltage of the transistor (101) is set to Vth0.

[0066] In addition, although the present embodiment 1 describes a method for operating a memory device to erase written data, the present invention is not limited to this configuration. One of the advantages of a memory device according to one aspect of the present invention is that, unlike conventional flash memory, it does not require an erase operation. Therefore, for example, it is possible to write other data to overwrite previously written data.

[0067] Furthermore, in the case of a general flash memory, the floating gate that accumulates charge is in an insulated state covered by an insulating film during data writing. Therefore, in order to accumulate charge on the floating gate using the tunnel effect, it is necessary to apply a high voltage of about 20 V to the memory element. However, in one embodiment of the present invention, data writing and reading can be performed by a transistor using a high-purity oxide semiconductor film as the active layer of the transistor. Accordingly, the voltage required for the operation of the memory device is about a few V, and power consumption can be significantly reduced. In addition, since the structure and driving method of the transistor used as a memory element in a flash memory and the transistor used as a memory element in a memory device according to one embodiment of the present invention are different, it is difficult to accurately determine the difference in power consumption during operation from the potential applied to each electrode of the memory element. However, for example, if we compare power consumption focusing only on data writing, in the memory device according to one embodiment of the present invention, data writing is sufficiently possible if the voltage applied between the second gate electrode and the source electrode is 5 V. Meanwhile, in a conventional flash memory, since data is written by accumulating charge on a floating gate, a voltage of at least 16V is required between the gate electrode and the source electrode. Since the power consumed by a transistor is equivalent to the square of the transistor's gate voltage divided by the transistor's load resistance, it can be seen that the power consumption of a memory device according to one embodiment of the present invention is about 10% of the power consumption of a conventional flash memory. Therefore, it can be seen that the power consumption during operation can be significantly reduced by comparing the power consumption during writing.

[0068] Furthermore, in semiconductor devices using general flash memory, the voltage required for the operation of the flash memory (operating voltage) is high; therefore, the voltage applied to the flash memory is typically increased using a boost circuit or the like. However, in the memory device according to one embodiment of the present invention, the operating voltage of the memory device is suppressed to be low, thereby reducing power consumption. Consequently, the burden on external circuits, such as boost circuits, regarding the operation of the memory device within the semiconductor device can be reduced, and the functionality of the external circuits can be expanded accordingly, thereby realizing high functionality of the semiconductor device. Additionally, since the operating voltage of the memory device is suppressed to be low, a circuit design that requires a long circuit to cover the size of the operating voltage becomes unnecessary, allowing the integration density of the integrated circuit used in the semiconductor device to be increased, thereby enabling high functionality of the semiconductor device.

[0069] In addition, although the present embodiment describes a driving method for handling two-value digital data, the memory device of the present invention can also handle three or more multi-value data. When handling three or more multi-value data, the height of the potential (Vbg) of the second gate electrode can be selected in three or more ways when writing data. Since the value of the threshold voltage is controlled by the potential (Vbg) of the second gate electrode, the height of the threshold voltage can be set in three or more steps according to the height of the potential (Vbg) of the second gate electrode set by the above configuration. Then, reading of multi-value data can be performed by utilizing the difference in drain current caused by the difference in the height of the threshold voltage, or the difference in the resistance value between the source electrode and the drain electrode caused by the difference in the height of the threshold voltage. As another method, a voltage slightly higher than each step is prepared in advance according to each step of the threshold voltage height, and the prepared voltage is applied to the first gate electrode to perform readings corresponding to the step of the threshold voltage height. For example, when reading four values ​​of data, four voltages (Vread0, Vread1, Vread2, Vread3) slightly higher than each step of the four threshold voltages (Vth0, Vth1, Vth2, Vth3) are prepared in advance, and four readings are performed using the four voltages to read four values ​​of data. With the above configuration, the memory capacity of the memory device can be increased while reducing the area.

[0070] In addition, in the case of multi-value data of three or more values, as the values ​​increase to four or five, the difference in threshold voltage between each value decreases. Therefore, if a minute off-current exists, the potential of the second gate electrode changes, making it difficult to maintain data accuracy and causing the retention period to become shorter. However, in one embodiment of the present invention, a transistor with significantly reduced off-current is used as a switching element by utilizing a high-purity oxide semiconductor film, so the effect of blocking off-current is higher than that of a silicon-based transistor. Therefore, the shortening of the retention period due to multi-value can be suppressed.

[0071] In addition, FIG. 1(B) illustrates a case where the transistor (102) functioning as a switching element is a bottom-gate type having an oxide semiconductor film (113) on the gate electrode (111), but the transistor (102) is not limited to a bottom-gate type. The transistor (102) may use an oxide semiconductor film as an active layer, and for example, may be a top-gate type having a gate electrode on the oxide semiconductor film. Furthermore, the transistor (102) is not limited to a top-contact type where the source electrode (114) and the drain electrode (115) are formed on the oxide semiconductor film (113), but may be a bottom-contact type where the oxide semiconductor film (113) is formed on the source electrode (114) and the drain electrode (115). Additionally, the transistor (102) is a channel etch type in which the thickness of the oxide semiconductor film (113) that overlaps with the insulating film (116) between the source electrode (114) and the drain electrode (115) is thinner than other parts, but the present invention is not limited to this configuration. In order to prevent damage caused by plasma during etching for the formation of the source electrode (114) and the drain electrode (115) or film reduction caused by etching, it may be a channel protection type having a channel protection film on the oxide semiconductor film (113) between the source electrode (114) and the drain electrode (115).

[0072] FIG. 3(A) shows an example of a cross-sectional view of a memory cell (100) having the circuit configuration shown in FIG. 1(A). In the memory cell shown in FIG. 3(A), a channel protection type transistor (101) that functions as a memory element and a channel protection type transistor (102) that functions as a switching element are formed on a substrate (140) having an insulating surface.

[0073] Specifically, the transistor (101) has a first gate electrode (151) on a substrate (140) having an insulating surface, an insulating film (142) on the first gate electrode (151), an oxide semiconductor film (153) functioning as an active layer that overlaps the first gate electrode (151) with the insulating film (142) in between, a channel protection film (157) that overlaps the gate electrode (151) on the oxide semiconductor film (153), a source electrode (154) and a drain electrode (155) on the oxide semiconductor film (153), an insulating film (146) on the oxide semiconductor film (153), the channel protection film (157), the source electrode (154) and the drain electrode (155), and a second gate electrode (156) that overlaps the oxide semiconductor film (153) on the insulating film (146). Additionally, an insulating film (147) is formed on the second gate electrode (156), and the transistor (101) may include the insulating film (147) as a component.

[0074] Additionally, the transistor (102) has a gate electrode (141) on a substrate (140) having an insulating surface, an insulating film (142) on the gate electrode (141), an oxide semiconductor film (143) functioning as an active layer that overlaps the gate electrode (141) with the insulating film (142) in between, a channel protection film (148) on the oxide semiconductor film (143), and a source electrode (144) and a drain electrode (145) on the oxide semiconductor film (143). An insulating film (146) is formed on the oxide semiconductor film (143), the channel protection film (148), the source electrode (144), and the drain electrode (145), and the transistor (102) may include the insulating film (146) as a component.

[0075] Additionally, the capacitance element (103) is formed in an area where the source electrode (154) of the transistor (101) and the second gate electrode (156) overlap each other with an insulating film (146) in between.

[0076] Channel protective film (157) and channel protective film (148) can be formed using chemical vapor deposition methods such as plasma CVD or thermal CVD, or sputtering. Additionally, for channel protective film (157) and channel protective film (148), it is preferable to use an inorganic material containing oxygen (silicon oxide, silicon nitride, silicon nitride, etc.). By using an inorganic material containing oxygen for channel protective film (157) and channel protective film (148), even if oxygen deficiency occurs due to heat treatment to reduce moisture or hydrogen in the oxide semiconductor film (153) and oxide semiconductor film (143), it is possible to supply oxygen to the regions of the oxide semiconductor film (153) and oxide semiconductor film (143) that are in contact with the channel protective film (157) and channel protective film (148), respectively, and reduce the oxygen deficiency that becomes a donor, thereby making it possible to achieve a configuration that satisfies the stoichiometric composition ratio. Therefore, the channel formation region can be i-shaped or substantially i-shaped, and the deviation in the electrical characteristics of the transistor caused by oxygen vacancy can be reduced, thereby realizing an improvement in electrical characteristics.

[0077] In addition, the channel formation region corresponds to the region of the semiconductor film that overlaps with the gate electrode with the gate insulating film in between. In the case of a transistor used as a memory device, it corresponds to the region of the semiconductor film that overlaps with the first gate electrode or the second gate electrode with the gate insulating film in between the source electrode and the drain electrode.

[0078] Next, FIG. 3(B) shows an example of a cross-sectional view of a memory cell (100) having the circuit configuration shown in FIG. 1(A). In the memory cell shown in FIG. 3(B), a bottom-contact type transistor (101) functioning as a memory element and a bottom-contact type transistor (102) functioning as a switching element are formed on a substrate (160) having an insulating surface.

[0079] Specifically, the transistor (101) has a first gate electrode (171) on a substrate (160) having an insulating surface, an insulating film (162) on the first gate electrode (171), a source electrode (174) and a drain electrode (175) on the insulating film (162), an oxide semiconductor film (173) functioning as an active layer that overlaps with the first gate electrode (171) and contacts the source electrode (174) and the drain electrode (175) with the insulating film (162) in between, an insulating film (166) on the oxide semiconductor film (173), the source electrode (174), and the drain electrode (175), and a second gate electrode (176) that overlaps with the oxide semiconductor film (173) on the insulating film (166). Additionally, an insulating film (167) is formed on the second gate electrode (176), and the transistor (101) may include the insulating film (167) as a component.

[0080] Additionally, the transistor (102) has a gate electrode (161) on a substrate (160) having an insulating surface, an insulating film (162) on the gate electrode (161), a source electrode (164) and a drain electrode (165) on the insulating film (162), and an oxide semiconductor film (163) that functions as an active layer, which overlaps with the gate electrode (161) with the insulating film (162) in between and is in contact with the source electrode (164) and the drain electrode (165). An insulating film (166) is formed on the oxide semiconductor film (163), the source electrode (164), and the drain electrode (165), and the transistor (102) may include the insulating film (166) as a component.

[0081] Additionally, the capacitance element (103) is formed in an area where the source electrode (174) of the transistor (101) and the second gate electrode (176) overlap each other with an insulating film (166) in between.

[0082] Additionally, FIGS. 1(A), FIGS. 3(A), and FIGS. 3(B) illustrate a case where an oxide semiconductor film is used in the active layer of a transistor (101) that functions as a memory element, but as described above, a semiconductor other than an oxide semiconductor, such as amorphous, microcrystalline, polycrystalline, or single-crystal silicon or germanium, may be used in the active layer of the transistor (101).

[0083] FIG. 4(A) shows a cross-sectional view of a memory cell (100) as an example, in which a semiconductor film containing silicon is used in the active layer of a transistor (101) that functions as a memory element. In the memory cell shown in FIG. 4(A), a transistor (101) that functions as a memory element and a transistor (102) that functions as a switching element are formed on a substrate (200) having an insulating surface.

[0084] Specifically, the transistor (102) has a gate electrode (211) on a substrate (200) having an insulating surface, an insulating film (230) on the gate electrode (211), an oxide semiconductor film (213) which functions as an active layer that overlaps the gate electrode (211) with the insulating film (230) in between, and a source electrode (214) and a drain electrode (215) on the oxide semiconductor film (213). An insulating film (231) is formed on the oxide semiconductor film (213), the source electrode (214), and the drain electrode (215), and the transistor (102) may include the insulating film (231) as a component.

[0085] Additionally, the transistor (101) has a first gate electrode (221) on an insulating film (231) formed on a substrate (200) having an insulating surface, an insulating film (212) on the first gate electrode (221), a semiconductor film (223) functioning as an active layer using silicon that overlaps the first gate electrode (221) with the insulating film (212) in between, a source electrode (224) and a drain electrode (225) on the semiconductor film (223), an insulating film (216) on the semiconductor film (223), the source electrode (224) and the drain electrode (225), and a second gate electrode (226) that overlaps the semiconductor film (223) on the insulating film (216). Additionally, an insulating film (217) is formed on the second gate electrode (226), and the transistor (101) may include the insulating film (217) as a component.

[0086] Additionally, the capacitance element (103) is formed in an area where the drain electrode (225) of the transistor (101) and the second gate electrode (226) overlap each other with an insulating film (216) in between.

[0087] Next, FIG. 4(B) shows a cross-sectional view of a memory cell (100) as an example, in which a semiconductor film containing silicon is used in the active layer of a transistor (101) that functions as a memory element. In the memory cell shown in FIG. 4(B), a transistor (101) that functions as a memory element and a transistor (102) that functions as a switching element are formed on a substrate (270) having an insulating surface.

[0088] Specifically, the transistor (102) has a gate electrode (241) on an insulating film (247) formed on a substrate (270), an insulating film (260) on the gate electrode (241), an oxide semiconductor film (243) functioning as an active layer that overlaps the gate electrode (241) with the insulating film (260) in between, and a source electrode (244) or a drain electrode (245) on the oxide semiconductor film (243). An insulating film (261) is formed on the oxide semiconductor film (243), the source electrode (244), and the drain electrode (245), and the transistor (102) may include the insulating film (261) as a component.

[0089] Additionally, the transistor (101) has a first gate electrode (251) on a substrate (270), an insulating film (242) on the first gate electrode (251), a semiconductor film (253) functioning as an active layer using silicon that overlaps the first gate electrode (251) with the insulating film (242) in between, a source electrode (254) and a drain electrode (255) on the semiconductor film (253), an insulating film (246) on the semiconductor film (253), the source electrode (254), and the drain electrode (255), and a second gate electrode (256) that overlaps the semiconductor film (253) on the insulating film (246). Additionally, an insulating film (247) is formed on the second gate electrode (256), and the transistor (101) may include the insulating film (247) as a component.

[0090] Additionally, the capacitance element (103) is formed in an area where the drain electrode (255) and the second gate electrode (256) of the transistor (101) overlap each other with an insulating film (246) in between.

[0091] Additionally, although the transistor (101) shown in FIG. 4(A) and FIG. 4(B) illustrates a bottom gate type, it may also be a top gate type or a bottom contact type. Also, the transistor (101) is a channel etch type, but it may also be a channel protection type. Additionally, although the transistor (102) shown in FIG. 4(A) and FIG. 4(B) illustrates a bottom gate type, it may also be a top gate type or a bottom contact type. Also, the transistor (102) is a channel etch type, but it may also be a channel protection type.

[0093] (Embodiment 2)

[0094] In this embodiment, an example of the configuration of a memory device having a plurality of memory cells and a method of operating the same is described.

[0095] FIG. 5 shows, as an example, a circuit diagram of a cell array of a NOR-type memory device in which a plurality of memory cells (300) are connected in a matrix shape. Regarding the configuration of each memory cell (300) of the memory device shown in FIG. 5, the configuration of the memory cell (100) described in Embodiment 1 may be taken into consideration.

[0096] Specifically, the memory cell (300) has a transistor (301) that functions as a memory element and a transistor (302) that functions as a switching element capable of controlling the supply of potential to the second gate electrode of the transistor (301). Additionally, the memory cell (300) may have a capacitance element (303) formed therein for holding the potential of the second gate electrode of the transistor (301). The memory cell (300) may further have other circuit elements such as diodes, resistors, and inductors as needed.

[0097] In the cell array shown in FIG. 5, various wirings such as a plurality of input data lines (Din), a plurality of output data lines (Dout), a plurality of writing word lines (WL), and a plurality of reading word lines (RL) are installed, and a signal or power potential from the driving circuit of the cell array is supplied to each memory cell (300) through these wirings. Accordingly, the number of wirings can be determined according to the number and arrangement of memory cells (300).

[0098] Specifically, in the case of the cell array shown in FIG. 5, memory cells of 3 rows × 3 columns are connected in a matrix shape, and at least input data lines (Din1 to Din3), output data lines (Dout1 to Dout3), writing word lines (WL1 to WL3), and reading word lines (RL1 to RL3) are arranged within the cell array.

[0099] Next, regarding the connection structure between the wiring and the circuit element within the memory cell (300), one memory cell (300) connected to the input data line (Din1), output data line (Dout1), write word line (WL1), and read word line (RL1) is described as an example. The gate electrode of the transistor (302) is connected to the write word line (WL1). Also, one of the source electrode and the drain electrode of the transistor (302) is connected to the input data line (Din1), and the other is connected to the second gate electrode of the transistor (301). Additionally, the first gate electrode of the transistor (301) is connected to the read word line (RL1). Also, one of the source electrode and the drain electrode of the transistor (301) is connected to the output data line (Dout1), and the other is connected to a power line (304) to which a fixed potential, such as ground, is applied.

[0100] Additionally, one of the pair of electrodes of the capacitive element (303) is connected to the second gate electrode of the transistor (301), and the other is connected to a power line (304) to which a fixed potential, such as ground, is applied.

[0101] Additionally, FIG. 6 shows, as an example, a circuit diagram of a cell array of a NAND-type memory device in which a plurality of memory cells (300) are connected in series. The configuration of each memory cell of the memory device shown in FIG. 6 is the same as that of FIG. 5, and the configuration of the memory cell (100) described in Embodiment 1 can be taken into consideration.

[0102] In the case of the cell array shown in FIG. 6, an example is provided in which a cell array in which three memory cells are connected in series is arranged in three columns. Specifically, the example provides a cell array having 3×3 memory cells, and in which input data lines (Din1–Din3), output data lines (Dout1–Dout3), writing word lines (WL1–WL3), reading word lines (RL1–RL3), selection signal lines (SEL1–SEL2), and power lines (304) are arranged within the cell array. A signal or power potential from the driving circuit of the cell array is supplied to each memory cell through these wires. Accordingly, the number of wires can be determined by the number of memory cells (300).

[0103] Next, the connection structure between the wiring and the circuit elements within the memory cell (300) will be explained. For example, looking at the memory cell (300) connected to the input data line (Din1), output data line (Dout1), write word line (WL1), and read word line (RL1), the gate electrode of the transistor (302) is connected to the write word line (WL1). Also, one of the source electrode and the drain electrode of the transistor (302) is connected to the input data line (Din1), and the other is connected to the second gate electrode of the transistor (301). Additionally, the first gate electrode of the transistor (301) is connected to the read word line (RL1). Furthermore, adjacent memory cells are connected in series between the output data line (Dout1) and the power line (304) to which a fixed potential, such as ground, is applied.

[0104] Additionally, a pair of electrodes having a capacitive element (303) has one end connected to the second gate electrode of the transistor (301) and the other end connected to a power line (304) to which a fixed potential, such as ground, is applied.

[0105] Next, using the cell array shown in FIG. 6 as an example, the operation of a memory device according to one embodiment of the present invention will be explained using FIG. 21. FIG. 21 is a timing chart showing the time change of the potential of a signal input to each wire, and illustrates a case where the transistor (301) and transistor (302) are of the n-channel type and also handle two values ​​of data.

[0106] First, the operation of the memory device during data writing will be explained. During writing, when a signal having a pulse is input to the writing word line (WL1), the potential of this pulse, specifically a high-level potential, is applied to the gate electrode of the transistor (302). Then, all transistors (302) whose gate electrodes are connected to the writing word line (WL1) are turned on. Meanwhile, when a low-level potential is input to the reading word line (RL1), a low-level potential is applied to the first gate electrode of the transistor (301). Then, all transistors (301) whose first gate electrodes are connected to the reading word line (RL1) are turned off.

[0107] Then, signals containing data as information are sequentially input to the input data lines (Din1 to Din3). FIG. 21 illustrates a case where signals having a high potential are input to the input data lines (Din1) and (Din3), and signals having a low potential are input to the input data line (Din2). Naturally, the potential levels of the signals input to the input data lines (Din1 to Din3) differ depending on the content of the data.

[0108] The potential input to the input data lines (Din1 to Din3) is applied to the second gate electrode of the transistor (301) through the on transistor (302). Then, the amount of shift of the threshold voltage of the transistor (301) is determined according to the potential of the second gate electrode. Specifically, since a signal having a high-level potential is input to the input data lines (Din1) and the input data lines (Din3), the potential of the second gate electrode of the transistor (301) in the memory cell (300) connected to the input data line (Din1) and the memory cell (300) connected to the input data line (Din3) is at a high level. That is, in this memory cell (300), the transistor (301) functioning as a memory element operates according to the line (130) of FIG. 2(B). Meanwhile, since a signal having a low-level potential is input to the input data line (Din2), the potential of the second gate electrode of the transistor (301) in the memory cell (300) connected to the input data line (Din2) is at a low level. That is, in this memory cell (300), the transistor (301) functioning as a memory element operates according to the line (131) of FIG. 2(B).

[0109] When the input of a signal having a pulse to the writing word line (WL1) is terminated, all transistors (302) with gate electrodes connected to the writing word line (WL1) are turned off. Then, signals having pulses are sequentially input to the writing word line (WL2) and the writing word line (WL3), and the operation described above is repeated in the memory cell having the writing word line (WL2) and the memory cell having the writing word line (WL3).

[0110] Next, the operation of the memory device during data retention will be described. During retention, a potential level at which the transistor (302) turns off, specifically a low level potential, is applied to all writing word lines (WL1 to WL3). As described above, since the off current of the transistor (302) is significantly low, the potential of the second gate electrode maintains the level set during writing. Additionally, a low level potential is applied to all reading word lines (RL1 to RL3).

[0111] In the timing chart of Fig. 21, a retention period is provided to explain the operation of holding data. However, in the actual operation of memory, a retention period does not need to be provided.

[0112] Next, the operation of the memory device during data reading will be described. During reading, a potential level at which the transistor (302) is turned off, specifically a low level potential, is applied to all writing word lines (WL1 to WL3), just as during retention.

[0113] In a NAND-type memory device, adjacent memory cells are connected in series between an output data line and a power line to which a fixed potential, such as ground, is applied. When reading data from a memory cell, by controlling a memory cell connected to the same output data line as this memory cell, the two values ​​stored can be distinguished based on whether the output data line to which this memory cell is connected conducts with the power line to which a fixed potential, such as ground, is applied.

[0114] Specifically, focusing on a memory cell (300) connected to an input data line (Din1), an output data line (Dout1), a writing word line (WL1), and a reading word line (RL1), we consider the case of reading high-level data stored in this memory cell (300). To select the output data line (Dout1) to which this memory cell (300) is connected, SEL1 and SEL2 are set to a high-level potential, and the transistor (320) connected to SEL1 and the transistor (321) connected to SEL2 are turned on. Then, the reading word line (RL1) connected to the first gate electrode of the transistor (301) in this memory cell (300) is set to a low level. Additionally, a high-level potential is applied to the reading word lines (RL2 to RL3), and each transistor (301) connected to the reading word lines (RL2 to RL3) is turned on. The transistor (301) of this memory cell (300) has high-level data written to its second gate electrode. That is, according to the operation of the transistor (301) functioning as a memory element as shown in FIG. 2, the threshold voltage shifts to the negative side and becomes Vth1. Therefore, the transistor (301) is turned on. Consequently, all transistors connected to the output data line (Dout1) are turned on, and the output data line (Dout1) conducts with the power line to which ground is applied, and becomes approximately the same potential as ground.

[0115] Next, focusing on a memory cell (300) connected to an input data line (Din2), an output data line (Dout2), a write word line (WL1), and a read word line (RL1), consider the case of reading low-level data stored in this memory cell (300). To select the output data line (Dout2), SEL1 and SEL2 are set to a high-level potential, and the transistor (320) connected to SEL1 and the transistor (321) connected to SEL2 are turned on. Then, the read word line (RL1) connected to the first gate electrode of the transistor (301) in this memory cell (300) is set to a low level. Additionally, a high-level potential is applied to the read word lines (RL2 to RL3), and each transistor (301) connected to the read word lines (RL2 to RL3) is turned on. The transistor (301) of this memory cell (300) has low-level data written to the second gate electrode. That is, according to the operation of the transistor (301) functioning as a memory element as shown in FIG. 2(B), the threshold voltage does not shift and is set to Vth0. Therefore, the transistor (301) is turned off. Consequently, the output data line (Dout2) does not conduct with the power line to which ground is applied, and becomes a high-impedance state.

[0116] In addition, a read circuit is connected to the end of each output data line (Dout), and the output signal of the read circuit becomes the actual output of the memory.

[0117] In addition, in the present embodiment 2, when selecting an output data line during data reading, an example is provided in which two selection signal lines, SEL1 and SEL2, and a transistor with a gate electrode connected to each signal line are used. Since the selection of the output data line during data reading is to select between conduction and non-conduction between the output data line and the reading circuit connected thereto, it is preferable to have at least one selection signal line and a transistor connected to the selection signal line.

[0118] In Embodiment 2, a driving method in which each operation of writing, holding, and reading is performed sequentially in a plurality of memory cells has been described, but the present invention is not limited to this configuration. The above operations may be performed only in the memory cell of a designated address.

[0119] In addition, in the case of the cell array shown in FIG. 6, four wires are connected to each memory cell, including an input data line (Din), an output data line (Dout), a writing word line (WL), and a reading word line (RL). However, in the memory device of the present invention, the number of wires connected to each memory cell is not limited to this. It is possible to supply a signal for controlling the switching of the transistor (301), a signal for controlling the switching of the transistor (302), and a signal for supplying a potential to the second gate electrode of the transistor (301) to the memory cell (300), and also to send a potential containing information such as the drain current of the transistor (301) or the resistance value between the source electrode and the drain electrode to the driving circuit. The number of wires and the connection structure may be appropriately determined.

[0120] In addition, in the timing chart shown in FIG. 21, the diagonal lines of the output data lines (Dout1, Dout2, and Dout3) indicate a state where the data is indeterminate. Furthermore, although the rise of each signal rises vertically and the fall of each signal falls vertically, it is easy for a person skilled in the art to understand that the waveform of each signal becomes dull because the actual signal is affected by the load or noise of the signal line.

[0121] Next, the operation of a memory device according to one embodiment of the present invention will be explained using FIG. 7, with the cell array shown in FIG. 5 as an example. FIG. 7 is a timing chart showing the time change of the potential of a signal input to each wire, and illustrates a case where the transistor (301) and transistor (302) are of the n-channel type and also handle two values ​​of data.

[0122] First, the operation of the memory device during data writing will be explained. During writing, when a signal having a pulse is input to the writing word line (WL1), the potential of this pulse, specifically a high-level potential, is applied to the gate electrode, thereby turning on all transistors (302) whose gate electrodes are connected to the writing word line (WL1). Meanwhile, a signal having a potential lower than Vth1 of FIG. 2(B), which shows the operation of a transistor functioning as a memory element, is input to the reading word line (RL1), and all transistors (301) whose first gate electrodes are connected to the reading word line (RL1) remain off.

[0123] Then, signals containing data as information are input sequentially to the input data lines (Din1 to Din3). Figure 7 illustrates a case where signals having a high-level potential are input to all of the input data lines (Din1 to Din3), but the potential level of the signals input to the input data lines (Din1 to Din3) naturally varies depending on the content of the data. In addition, when handling two-value data, the potential of the signals input to the input data lines (Din1 to Din3) should be two values ​​corresponding to the power supply voltage (e.g., Vdd and Vss), but when handling three or more values ​​of multi-value data, the number of potential levels should be determined according to the number of values ​​used in the data being handled.

[0124] The potential input to the input data lines (Din1 to Din3) can be applied to the second gate electrode of the transistor (301) through the on transistor (302). Then, the amount of shift of the threshold voltage of the transistor (301) is determined according to the potential of the second gate electrode.

[0125] When the input of a signal having a pulse to the writing word line (WL1) is terminated, all transistors (302) with gate electrodes connected to the writing word line (WL1) are turned off. Then, signals having pulses are sequentially input to the writing word line (WL2) and the writing word line (WL3), and the operation is repeated as described above in the memory cell having the writing word line (WL2) and the memory cell having the writing word line (WL3).

[0126] Next, the operation of the memory device during data retention will be described. During retention, a potential level at which the transistor (302) is turned off is applied to all writing word lines (WL1 to WL3), specifically a low level potential. Since the transistor (302) has a significantly low off current as described above, the potential of the second gate electrode is maintained at the level set during writing. Additionally, a potential level at which the transistor (301) is turned off is applied to all reading word lines (RL1 to RL3), specifically a potential lower than Vth1 of FIG. 2(B), which illustrates the operation of the transistor functioning as a memory element.

[0127] In the timing chart of Fig. 7, a retention period is provided to explain the operation of holding data. However, in the actual operation of memory, a retention period does not need to be provided.

[0128] Next, the operation of the memory device during data reading will be described. During reading, all writing word lines (WL1 to WL3) are given a potential level at which the transistor (302) is turned off, specifically a low level potential, just as during retention.

[0129] Meanwhile, during reading, signals having pulses are sequentially input to the reading word lines (RL1 to RL3). Specifically, first, when a signal having pulses is input to the reading word line (RL1), the potential of this pulse, specifically a potential higher than Vth1 and lower than Vth0 in FIG. 2(B) which represents the operation of the transistor functioning as a memory element, or a potential higher than Vth0, is applied to the first gate electrode of the transistor (301). In the transistor (301), when a potential higher than Vth1 and lower than Vth0 in FIG. 2(B) which represents the operation of the transistor functioning as a memory element, or a potential higher than Vth0, is applied to the first gate electrode, the drain current, or the resistance value between the source electrode and the drain electrode, is determined according to the threshold voltage set during the previous writing.

[0130] And, the drain current of the transistor (301), or the resistance value between the source electrode and the drain electrode, is included as information, that is, the potential of the electrode connected to the output data line (Dout1 to Dout3) among the source electrode and the drain electrode of the transistor (301), is supplied to the driving circuit through the output data line (Dout1 to Dout3).

[0131] Additionally, the level of the potential supplied to the output data lines (Dout1 to Dout3) is determined according to the data written in the memory cells. Therefore, ideally, if data of the same value is stored in multiple memory cells, the same level of potential will be supplied to all output data lines connected to these memory cells. However, in reality, since there may be deviations in the characteristics of the transistor (301) or transistor (302) between memory cells, even if the data to be read is of the same value, there may be deviations in the potential supplied to the output data lines, and the distribution may have a range. Therefore, even if some deviation occurs in the potential supplied to the output data lines (Dout1 to Dout3), a reading circuit capable of including the read data as information from the above potential and forming a signal with an amplitude and waveform processed according to the desired specifications is formed in the memory device as a driving circuit.

[0132] In FIG. 9, an example of a read circuit is shown in the circuit diagram. The read circuit shown in FIG. 9 has transistors (310_1 to 310_3) that function as switching elements to control the input of the potential of output data lines (Dout1 to Dout3) to the read circuit, and transistors (311_1 to 311_3) that function as resistors. In addition, the read circuit shown in FIG. 9 has operational amplifiers (312_1 to 312_3).

[0133] Specifically, each transistor (311_1 to 311_3) has its gate electrode and drain electrode connected, and a high-level power supply potential (VDD) is applied to the gate electrode and drain electrode. Additionally, the source electrode of each transistor (311_1 to 311_3) is connected to the non-inverting input terminal (+) of the operational amplifier (312_1 to 312_3). Accordingly, the transistor (311_1 to 311_3) functions as a resistor connected between the node to which the power supply potential (VDD) is applied and the non-inverting input terminal (+) of the operational amplifier (312_1 to 312_3). Furthermore, in FIG. 9, a transistor with its gate electrode and drain electrode connected is used as a resistor, but the present invention is not limited to this, and any device that functions as a resistor can be substituted.

[0134] Additionally, the gate electrodes of the transistors (310_1 to 310_3) functioning as switching elements are respectively connected to the bit lines (BL1 to BL3). Then, depending on the potential of the bit lines (BL1 to BL3), the connection between the output data lines (Dout1 to Dout3) and the source electrodes of the transistors (311_1 to 311_3) is controlled.

[0135] For example, when the transistor (310_1) is turned on, the transistor (301) in the memory cell (300) and the transistor (311_1) in the reading circuit are connected in series, so the potential (Vdata) at the node of this connection is applied to the non-inverting input terminal (+) of the operational amplifier (312_1 to 312_3). And, since the height of the potential (Vdata) is determined by the ratio of the resistance value between the source electrode and the drain electrode of the transistor (301) and the resistance value between the source electrode and the drain electrode of the transistor (311_1), the value of the read data is reflected in the level of the potential (Vdata).

[0136] Meanwhile, a reference potential (Vref) is applied to the inverting input terminal (-) of the operational amplifier (312_1 to 312_3). Then, depending on whether the potential (Vdata) applied to the non-inverting input terminal (+) is higher or lower than the reference potential (Vref), the level of the potential (Vout) of the output terminal can be varied, and thereby, a signal containing data as information can be obtained indirectly.

[0137] Furthermore, even for memory cells storing data of the same value, variations in characteristics between memory cells can cause deviations in the level of the read potential (Vdata), resulting in a range in the distribution. Therefore, the level of the reference potential (Vref) is determined by considering the deviation of the node's potential (Vdata) to accurately read the data value.

[0138] In addition, in FIG. 9, one operational amplifier is used for each output data line for data reading, but the number of operational amplifiers is not limited to this. When handling data of value n (n is a natural number greater than or equal to 2), the number of operational amplifiers used for each output data line is (n-1).

[0139] Next, the operation of the memory device during data erasure will be explained. During erasure, just as during data writing, when a signal having a pulse is input to the writing word line (WL1), the potential of this pulse, specifically a high-level potential, is applied to the gate electrode, thereby turning on all transistors (302) whose gate electrodes are connected to the writing word line (WL1). Meanwhile, a signal having a potential lower than Vth1 of FIG. 2(B), which illustrates the operation of a transistor functioning as a memory element, is input to the reading word line (RL1), and all transistors (301) whose first gate electrodes are connected to the reading word line (RL1) remain off.

[0140] Then, a fixed potential, such as ground, is applied to the input data lines (Din1 to Din3). FIG. 7 illustrates a case where a signal having a low-level potential is input to all of the input data lines (Din1 to Din3). The low-level fixed potential input to the input data lines (Din1 to Din3) is applied to the second gate electrode of the transistor (301) through the on transistor (302). Then, the threshold voltage value of the transistor (301) is reset according to the potential of the second gate electrode.

[0141] When the input of a signal having a pulse to the writing word line (WL1) is terminated, all transistors (302) with gate electrodes connected to the writing word line (WL1) are turned off. Then, signals having pulses to the writing word line (WL2) and the writing word line (WL3) are sequentially input, and the above-described operation is repeated in the memory cell having the writing word line (WL2) and the memory cell having the writing word line (WL3).

[0142] In the timing chart of FIG. 7, an erasure period is provided to explain the operation of erasing data. However, in actual memory operation, an erasure period may not be provided, and in this case, other data may be written so as to overwrite the previously written data. One of the advantages of the memory device according to one embodiment of the present invention is that an erasure period may not be provided.

[0143] In addition, in Embodiment 2, a driving method in which the operations of writing, holding, reading, and erasing are performed sequentially in a plurality of memory cells has been described, but the present invention is not limited to this configuration. The above operations may be performed only in the memory cell of a designated address.

[0144] In addition, in the case of the cell array shown in FIG. 5, four wires are connected to each memory cell: an input data line (Din), an output data line (Dout), a writing word line (WL), and a reading word line (RL). However, in the memory device of the present invention, the number of wires connected to each memory cell is not limited to this. It is possible to supply a signal to control the on / off of the transistor (301), a signal to control the switching of the transistor (302), and a signal to supply potential to the second gate electrode of the transistor (301) to the memory cell (300). Furthermore, the number of wires and the connection structure may be appropriately determined so that the drain current of the transistor (301) or the resistance value between the source electrode and the drain electrode can be sent to the driving circuit as information containing potential.

[0145] Next, the configuration of a driving circuit of a memory device according to one embodiment of the present invention will be described, using a memory device using a cell array shown in FIG. 5 as an example.

[0146] In FIG. 8, the configuration of a memory device according to one embodiment of the present invention is shown as a block diagram as an example. In addition, in the block diagram shown in FIG. 8, circuits within the memory device are classified by function and shown as independent blocks, but in reality, it is difficult to completely separate circuits by function, and a single circuit may be related to multiple functions.

[0147] The memory device shown in FIG. 8 has a cell array (500) in which a plurality of memory cells are connected in a matrix shape, and a driving circuit (501) that controls the driving of the cell array (500). The driving circuit (501) has a reading circuit (502) that generates a signal containing data read from the cell array (500) as information, a word line driving circuit (503) that selects memory cells of the cell array (500) row by row, a data line driving circuit (504) that controls the writing or erasing of data in the selected memory cells, and a control circuit (505) that selects the operation of the reading circuit (502), the word line driving circuit (503), and the data line driving circuit (504). Additionally, the word line driving circuit (503) has a word line decoder (506). Additionally, the data line driving circuit (504) has a data line decoder (508) and a data line selector (509).

[0148] In addition, a memory device according to one embodiment of the present invention may include at least a cell array (500) in its configuration. A memory device according to one embodiment of the present invention includes, in its category, a memory module in which a cell array and a driving circuit, or all of the cell array, are connected. The memory module may be provided with a connection terminal that can be mounted on a printed circuit board, etc., and may also be in a so-called packaged state protected by a resin, etc.

[0149] In addition, all or part of the driving circuit (501) may be formed on a single substrate together with the cell array (500), or may be formed on a different substrate from the cell array (500). When all or part of the driving circuit (501) and the cell array (500) are formed on different substrates, all or part of the driving circuit (501) and the cell array (500) may be connected through a Flexible Printed Circuit (FPC), etc. In this case, a part of the driving circuit (501) may be connected to the FPC using the Chip On Film (COF) method. Additionally, all or part of the driving circuit (501) may be connected to the cell array (500) using the Chip On Glass (COG) method.

[0150] By forming both the cell array (500) and the driving circuit (501) on a single substrate, the number of external circuit components connected to the memory device is reduced, thereby enabling cost reduction through the reduction of assembly and inspection processes. Additionally, since the number of contacts at the connection point between the memory device and the external circuit can be reduced, a decrease in yield caused by connection failures can be prevented, and a decrease in reliability caused by low mechanical strength at the connection point can be prevented. Furthermore, it is possible to form only circuits with a relatively lower driving frequency than other circuits, such as the word line driving circuit (503) and the data line selector (509), on a single substrate together with the cell array (500). In this way, by partially forming the driving circuit (501) on a single substrate together with the cell array (500), benefits such as avoiding the aforementioned decrease in yield caused by connection failures and low mechanical strength at the connection point, and cost reduction through the reduction of assembly and inspection processes can be obtained to some extent. In addition, compared to the case where the cell array (500) and the driving circuit (501) are both formed on a single substrate, the performance of the circuit with a high driving frequency can be further improved.

[0151] When a signal (AD) containing an address (Ax, Ay) as information is input to a memory device, the control circuit (505) sends the address (Ax), which is information regarding the column direction of the address, to the data line driving circuit (504), and sends the address (Ay), which is information regarding the row direction of the address, to the word line driving circuit (503). In addition, the control circuit (505) sends a signal (DATA), which contains data input to the memory device as information, to the data line driving circuit (504).

[0152] The selection of operations to write, read, or erase data is made by signals such as RE (Read enable), WE (Write enable), and EE (Erase enable) supplied to the control circuit (505). Additionally, if a plurality of cell arrays (500) are installed in the memory device, a signal CE (Chip enable) for selecting a cell array may be input to the control circuit (505).

[0153] When the operation of writing is selected by the signal (WE), a signal having a pulse is input to the writing word line (WL) corresponding to the address (Ay) by the word line decoder (506) of the word line driving circuit (503) according to the instruction from the control circuit (505). Meanwhile, when the operation of writing is selected by the signal (WE), a signal controlling the operation of the data line selector (509) is applied to the data line selector (509) from the data line decoder (508) in the data line driving circuit (504) according to the instruction from the control circuit (505). The data line selector (509) samples a signal (DATA) containing data as information according to the signal from the data line decoder (508) and inputs the sampled signal to the input data line (Din) corresponding to the address (Ax).

[0154] When a read operation is selected by a signal (RE), a signal having a pulse is input to a read word line (RL) corresponding to an address (Ay) by a word line decoder (506) of a word line driving circuit (503) according to instructions from a control circuit (505). Meanwhile, when a read operation is selected by a signal (RE), according to instructions from a control circuit (505), the read circuit (502) turns on the transistor corresponding to the address (Ax) among transistors (310_1~310_3) by controlling the potential of the bit line (BL) corresponding to the address (Ax). Then, data stored in the memory cell of the address is read from the potential of the output data line (Dout) corresponding to the address (Ax), and a signal containing this data as information is generated.

[0155] When the erasure operation is selected by the signal (EE), a signal having a pulse is input to the writing word line (WL) of the corresponding address (Ay) by the word line decoder (506) of the word line driving circuit (503) according to the instruction from the control circuit (505). Meanwhile, when the erasure operation is selected by the signal (EE), a signal controlling the operation of the data line selector (509) is applied to the data line selector (509) from the data line decoder (508) in the data line driving circuit (504) according to the instruction from the control circuit (505). The data line selector (509) inputs a signal to erase data to the input data line (Din) of the corresponding address (Ax) according to the signal from the data line decoder (508).

[0156] In addition, in the memory device shown in FIG. 8, the input of a signal to the writing word line (WL) and the input of a signal to the reading word line (RL) are both controlled by the word line driving circuit (503), but the present invention is not limited to this configuration. It is acceptable to provide the memory device with a driving circuit that controls the input of a signal to the writing word line (WL) and a driving circuit that controls the input of a signal to the reading word line (RL), respectively.

[0157] This embodiment can be implemented in appropriate combination with the above embodiment.

[0159] (Embodiment 3)

[0160] A method for manufacturing a memory device according to one embodiment of the present invention is described using a bottom-gate type transistor with a channel etch structure as an example. In addition, Embodiment 3 is described by taking as an example the case where both the transistor functioning as a memory element and the transistor functioning as a switching element utilize an oxide semiconductor film as an active layer.

[0161] As shown in FIG. 10(A), a gate electrode (401) and a gate electrode (402) are formed on a substrate (400).

[0162] There are no major restrictions on the substrate that can be used as the substrate (400) having an insulating surface, but at least, it is necessary to have enough heat resistance to withstand subsequent heat treatment. For example, a glass substrate produced by the fusion method or the float method can be used. As for the glass substrate, if the temperature of the subsequent heat treatment is high, it is preferable to use one with a deformation point of 730°C or higher. In addition, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used as glass substrates. Also, generally, more practical heat-resistant glass can be obtained by including a large amount of barium oxide (BaO) compared to boron oxide. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3.

[0163] In addition, instead of the glass substrate mentioned above, a substrate made of an insulator, such as a ceramic substrate, a quartz substrate, or a sapphire substrate, may be used. Furthermore, crystallized glass may be used. A substrate having an insulating film formed on the surface of a metal substrate, such as a stainless steel alloy, may also be used.

[0164] Additionally, substrates made of flexible synthetic resins such as plastics tend to have a generally low heat resistance temperature, but if they can withstand the processing temperature in subsequent manufacturing processes, they can be used as substrates (400). Examples of plastic substrates include polyester represented by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile butadiene styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, etc.

[0165] An insulating film serving as a base film may be formed between the substrate (400), the gate electrode (401), and the gate electrode (402). As a base film, for example, any one of silicon oxide film, silicon nitride film, silicon nitride film, silicon nitride film, aluminum nitride film, or aluminum nitride film may be used as a single layer or stacked in multiple layers. In particular, by using an insulating film with high barrier properties as the base film, such as a silicon nitride film, silicon nitride film, aluminum nitride film, or aluminum nitride film, impurities in an atmosphere such as moisture or hydrogen, or impurities such as alkali metals or heavy metals contained within the substrate (400), can be prevented from entering the oxide semiconductor film, the gate insulating film, or the interface between the oxide semiconductor film and another insulating film and the vicinity thereof.

[0166] Furthermore, in this specification, the term "nitride oxide" refers to a substance having a higher oxygen content than nitrogen in its composition, and the term "nitride oxide" refers to a substance having a higher nitrogen content than oxygen in its composition.

[0167] The materials for the gate electrode (401) and the gate electrode (402) may be metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium, conductive films using alloy materials with these metal materials as the main components, or nitrides of these metals, used as a single layer or in a stacked manner. Additionally, aluminum and copper may be used as the metal materials if they can withstand the temperature of the heat treatment performed in a subsequent process. Aluminum or copper may be used in combination with high-melting-point metal materials to avoid problems with heat resistance or corrosion. As high-melting-point metal materials, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. may be used.

[0168] For example, as a gate electrode (401) and gate electrode (402) having a two-layer stacked structure, it is preferable to have a two-layer stacked structure in which a molybdenum film is stacked on an aluminum film, a two-layer structure in which a molybdenum film is stacked on a copper film, a two-layer structure in which a titanium nitride film or a tantalum nitride film is stacked on a copper film, or a two-layer structure in which a titanium nitride film and a molybdenum film are stacked. As a gate electrode (401) and gate electrode (402) having a three-layer stacked structure, it is preferable to have a structure in which a tungsten film, a tungsten nitride film, a titanium nitride film, or a titanium film is stacked as upper and lower layers, with an aluminum film, an aluminum-silicon alloy film, an aluminum-titanium alloy film, or an aluminum-neodymium alloy film as an intermediate layer.

[0169] In addition, by using a transparent oxide conductive film such as an indium oxide film, an indium oxide tin oxide alloy film, an indium oxide zinc oxide alloy film, a zinc oxide film, a zinc oxide aluminum film, a zinc oxynitride aluminum film, or a zinc gallium oxide film on the gate electrode (401) and the gate electrode (402), the aperture ratio of the pixel portion can be improved.

[0170] The film thickness of the gate electrode (401) and gate electrode (402) is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment 3, a conductive film for a gate electrode of 150 nm is formed by a sputtering method using a tungsten target, and then the gate electrode (401) and gate electrode (402) are formed by processing (patterning) the conductive film into a desired shape by etching. In addition, if the end of the formed gate electrode has a tapered shape, it is preferable because the coverage of the gate insulating film stacked on top is improved. In addition, the resist mask may be formed by an inkjet method. If the resist mask is formed by an inkjet method, a photomask is not used, so manufacturing costs can be reduced.

[0171] Next, a gate insulating film (403) is formed on the gate electrode (401) and the gate electrode (402). The gate insulating film (403) can be formed by using a plasma CVD method or a sputtering method, etc., to form a silicon oxide film, a silicon nitride film, a silicon oxide nitride film, a silicon nitride nitride film, a silicon nitride nitride film, an aluminum oxide film, an aluminum nitride film, an aluminum oxide nitride film, a hafnium oxide film, or a tantalum oxide film as a single layer or by stacking. It is preferable that the gate insulating film (403) does not contain impurities such as moisture or hydrogen. When forming a silicon oxide film by the sputtering method, a silicon target or a quartz target is used as the target, and oxygen or a mixed gas of oxygen and argon is used as the sputtering gas.

[0172] Since the i-shaped or substantially i-shaped oxide semiconductor (high-purity oxide semiconductor) is very sensitive to interface levels and interface charges by removing impurities, the interface between the high-purity oxide semiconductor and the gate insulating film (403) is important. Therefore, the gate insulating film (GI) in contact with the high-purity oxide semiconductor is required to be of high quality.

[0173] For example, high-density plasma CVD using μ waves (2.45 GHz) is desirable because it can form a high-quality insulating film that is dense and has high dielectric breakdown voltage. This is because the high-purity oxide semiconductor and the high-quality gate insulating film are in close contact, thereby reducing the interface level and making the interface characteristics good.

[0174] Of course, other deposition methods, such as sputtering or plasma CVD, may be applied if it is possible to form a high-quality insulating film as a gate insulating film. Furthermore, it is acceptable for the insulating film to have improved film quality and interface characteristics between the gate insulating film and the oxide semiconductor through heat treatment after deposition. In any case, it is desirable not only to have good film quality as a gate insulating film, but also to be able to form a good interface by reducing the interface level density between the gate insulating film and the oxide semiconductor.

[0175] A gate insulating film (403) may be formed having a structure in which an insulating film using a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon nitride film with a low nitrogen content are stacked. In this case, the insulating film such as the silicon oxide film or the silicon nitride film is formed between the insulating film with high barrier properties and the oxide semiconductor film. Examples of insulating films with high barrier properties include silicon nitride film, silicon nitride film, aluminum nitride film, or aluminum nitride film. By using an insulating film with high barrier properties, impurities in an atmosphere such as moisture or hydrogen, or impurities such as alkali metals or heavy metals contained in the substrate (400), can be prevented from entering the oxide semiconductor film, the gate insulating film (403), or the interface between the oxide semiconductor film and another insulating film and the vicinity thereof. In addition, by forming an insulating film such as a silicon oxide film or a silicon nitride film with a low nitrogen content to come into contact with the oxide semiconductor film, it is possible to prevent the insulating film with high barrier properties from coming into direct contact with the oxide semiconductor film.

[0176] For example, as a first gate insulating film, a silicon nitride film (SiN) with a film thickness of 50 nm or more and 200 nm or less is formed by a sputtering method. y (y>0)) formed, and as a second gate insulating film on the first gate insulating film, a silicon oxide film (SiO₂) with a film thickness of 5 nm or more and 300 nm or less is formed. x(x>0)) may be stacked to form a gate insulating film (403) with a film thickness of 100 nm. The film thickness of the gate insulating film (403) may be appropriately set according to the characteristics required for the transistor, and may be about 350 nm to 400 nm.

[0177] In this embodiment 3, a gate insulating film (403) is formed having a structure in which a silicon oxide film with a thickness of 100 nm formed by sputtering is stacked on a silicon nitride film with a thickness of 50 nm formed by sputtering.

[0178] In addition, in order to ensure that hydrogen, hydroxyl groups, and moisture are not included in the gate insulating film (403) as much as possible, it is preferable to preheat the substrate (400) on which the gate electrode (401) and gate electrode (402) are formed in the preheating chamber of the sputtering device as a pretreatment for film formation, thereby removing and exhausting impurities such as moisture or hydrogen adsorbed on the substrate (400). In addition, the temperature of the preheating is 100°C or higher and 400°C or lower, preferably 150°C or higher and 300°C or lower. In addition, a cryopump is preferred as the exhaust means formed in the preheating chamber. In addition, this preheating treatment may be omitted.

[0179] Next, an oxide semiconductor film (404) with a film thickness of 2 nm or more and 200 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 3 nm or more and 20 nm or less, is formed on the gate insulating film (403). The oxide semiconductor film (404) is formed by sputtering using an oxide semiconductor as a target. Additionally, the oxide semiconductor film (404) can be formed by sputtering under a noble gas (e.g., argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of noble gas (e.g., argon) and oxygen.

[0180] In addition, before forming the oxide semiconductor film (404) by the sputtering method, it is preferable to remove dust attached to the surface of the gate insulating film (403) by performing reverse sputtering, which introduces argon gas and generates plasma. Reverse sputtering is a method of modifying the surface by forming plasma on the substrate by applying voltage to the substrate side using an RF power source under an argon atmosphere without applying voltage to the target side. In addition, nitrogen, helium, etc., may be used instead of an argon atmosphere. In addition, it may be performed in an atmosphere in which oxygen, hydrogen, nitrous oxide, etc., are added to the argon atmosphere. In addition, it may be performed in an atmosphere in which chlorine, carbon tetrafluoride, etc., are added to the argon atmosphere.

[0181] For the oxide semiconductor film (404), an oxide semiconductor as described above may be used.

[0182] In this embodiment, an In-Ga-Zn-O system non-monocrystalline film with a thickness of 30 nm, obtained by a sputtering method using an oxide semiconductor target containing In (indium), Ga (gallium), and Zn (zinc), is used as the oxide semiconductor film (404). Additionally, when using the sputtering method, the film may be formed using a target containing 2 wt% or more and 10 wt% or less of SiO2. Furthermore, the filling rate of the oxide semiconductor target containing In, Ga, and Zn is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using an oxide semiconductor target with a high filling rate, the formed oxide semiconductor film becomes a dense film.

[0183] A substrate is held in a processing chamber maintained in a reduced pressure state, and while removing residual moisture in the processing chamber, a sputtering gas from which hydrogen and moisture have been removed is introduced, and an oxide semiconductor film (404) is deposited on the substrate (400) using a metal oxide as a target. During deposition, the substrate temperature may be set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By depositing while heating the substrate, the concentration of impurities contained in the deposited oxide semiconductor film can be reduced. In addition, damage caused by sputtering is reduced. To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. In addition, as an exhaust means, a turbo pump with a cold trap added may be used. In a deposition chamber evacuated using a cryopump, compounds containing hydrogen atoms, such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms), are evacuated, and thus the concentration of impurities contained in the oxide semiconductor film deposited in this deposition chamber can be reduced.

[0184] As an example of film deposition conditions, a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, a direct current (DC) power supply of 0.5 kW, and an oxygen atmosphere (oxygen flow rate 100%) are applied. In addition, using a pulsed DC power supply is desirable because it can reduce dust, known as particles, generated during film deposition, thereby ensuring a uniform film thickness distribution. The oxide semiconductor film is preferably 5 nm or larger and 30 nm or smaller. Furthermore, the appropriate thickness varies depending on the oxide semiconductor material used, and it is preferable to select the appropriate thickness according to the material.

[0185] In addition, to ensure that hydrogen, hydroxyl groups, and moisture are not included in the oxide semiconductor film (404) as much as possible, it is preferable to preheat the substrate (400) formed up to the gate insulating film (403) in the preheating chamber of the sputtering device as a pretreatment for film formation, thereby removing and exhausting impurities such as moisture or hydrogen adsorbed on the substrate (400). In addition, the temperature of the preheating is 100°C or higher and 400°C or lower, preferably 150°C or higher and 300°C or lower. In addition, a cryo pump is preferred as the exhaust means formed in the preheating chamber. In addition, this preheating treatment may be omitted. In addition, this preheating may be similarly performed on the substrate (400) formed up to the source electrode (407) and drain electrode (408), source electrode (409) and drain electrode (410) before the formation of the insulating film (411).

[0186] Sputtering methods include RF sputtering, which utilizes a high-frequency power supply, and DC sputtering, as well as pulsed DC sputtering, which applies additional bias pulsedly. RF sputtering is primarily used for depositing insulating films, while DC sputtering is primarily used for depositing metal films.

[0187] In addition, there is a multi-stage sputtering device capable of installing multiple targets of different materials. The multi-stage sputtering device can deposit films of different materials in a stacked manner within the same chamber, or deposit films by simultaneously discharging multiple types of materials within the same chamber.

[0188] In addition, there are sputtering devices that utilize the magnetron sputtering method equipped with a magnetic mechanism inside the chamber, or sputtering devices that utilize the ECR sputtering method using plasma generated by microwaves without using glow discharge.

[0189] In addition, as a film deposition method utilizing sputtering, there are reactive sputtering methods in which a target material and a sputtering gas component are chemically reacted during film deposition to form a compound thin film, and bias sputtering methods in which voltage is also applied to the substrate during film deposition.

[0190] The gate insulating film (403) and the oxide semiconductor film (404) may be formed continuously without being exposed to the atmosphere. By forming the film continuously without being exposed to the atmosphere, each stacked interface can be formed without the interface being contaminated by atmospheric components such as water or hydrocarbons or impurity elements floating in the atmosphere, thereby reducing the variation in transistor characteristics.

[0191] Next, as shown in FIG. 10(B), the oxide semiconductor film (404) is processed (patterned) into a desired shape by etching or the like, and an island-shaped oxide semiconductor film (405) and an oxide semiconductor film (406) are formed respectively on the gate insulating film (403) at a position overlapping with the gate electrode (401) and the gate electrode (402).

[0192] A resist mask for forming an island-shaped oxide semiconductor film (405) and an oxide semiconductor film (406) may be formed using an inkjet method. Since a photomask is not used when forming the resist mask using an inkjet method, manufacturing costs can be reduced.

[0193] Additionally, when forming a contact hole in the gate insulating film (403), the process can be performed during the formation of the island-shaped oxide semiconductor film (405) and the oxide semiconductor film (406).

[0194] Additionally, the etching for forming the island-shaped oxide semiconductor film (405) and oxide semiconductor film (406) may be dry etching or wet etching, or both may be used. As for the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, e.g., chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CCl4), etc.) is preferred. Additionally, a gas containing fluorine (fluorine-based gas, e.g., carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr), oxygen (O2), or a gas to which a noble gas such as helium (He) or argon (Ar) is added may be used.

[0195] As a dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. In order to etch into a desired processing shape, etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side, temperature of the electrode on the substrate side, etc.) are appropriately adjusted.

[0196] As an etching solution used for wet etching, a solution mixed with phosphoric acid, acetic acid, and nitric acid may be used. In addition, ITO-07N (manufactured by Kanto Chemical Co., Inc.) may be used. Furthermore, the etching solution after wet etching is removed by cleaning along with the etched material. The waste liquid of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor film from this waste liquid after etching, it is possible to achieve cost reduction by effectively utilizing resources.

[0197] In addition, it is preferable to perform reverse sputtering before forming the conductive film of the next process to remove resist residues attached to the surface of the island-shaped oxide semiconductor film (405), oxide semiconductor film (406), and gate insulating film (403).

[0198] Next, heat treatment is performed on the oxide semiconductor film (405) and oxide semiconductor film (406) under an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (argon, helium, etc.). By performing heat treatment on the oxide semiconductor film (405) and oxide semiconductor film (406), moisture or hydrogen in the oxide semiconductor film (405) and oxide semiconductor film (406) can be removed. Specifically, it is preferable to perform heat treatment at a temperature of 350°C or higher and 850°C or lower (or a temperature below the deformation point of the glass substrate), preferably 550°C or higher and 750°C or lower. For example, it is preferable to perform the treatment at 600°C for 3 minutes or more and 6 minutes or less. Since the RTA method allows for dehydration or dehydrogenation to be performed in a short time, treatment can be performed even at a temperature exceeding the deformation point of the glass substrate. Alternatively, heat treatment may be performed for about 1 hour when the substrate temperature reaches 450℃.

[0199] In the present embodiment 3, using an electric furnace, which is one of the heat treatment devices, heat treatment is performed on the oxide semiconductor film (405) and oxide semiconductor film (406) for 6 minutes under a nitrogen atmosphere with the substrate temperature reaching 600°C. After the heat treatment, the oxide semiconductor film (405) and oxide semiconductor film (406) are kept out of contact with the atmosphere to prevent the re-incorporation of moisture or hydrogen.

[0200] In addition, the heat treatment device is not limited to an electric furnace, and may be equipped with a device that heats the workpiece by heat conduction or thermal radiation from a heating element such as a resistance heating element. For example, Rapid Thermal Anneal (RTA) devices such as Gas Rapid Thermal Anneal (GRTA) devices or Lamp Rapid Thermal Anneal (LRTA) devices may be used. An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. A GRTA device is a device that performs heat treatment using high-temperature gas. For the gas, noble gases such as argon, or inert gases such as nitrogen that do not react with the workpiece during heat treatment are used.

[0201] For example, as a heat treatment, a substrate may be moved into an inert gas heated to a high temperature of 650°C to 700°C, heated for a few minutes, and then moved to perform GRTA, which moves the substrate out of the inert gas heated to a high temperature. Using GRTA makes it possible to perform high-temperature heat treatment in a short time.

[0202] In addition, in the heat treatment, it is desirable that the nitrogen, or noble gas such as helium, neon, or argon, does not contain moisture or hydrogen. Alternatively, it is desirable to have a purity of 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher, of the nitrogen, or noble gas such as helium, neon, or argon introduced into the heat treatment device (i.e., an impurity concentration of 1 ppm or less, preferably 0.1 ppm or less).

[0203] If impurities such as moisture or hydrogen are added to an oxide semiconductor, at 85°C, 2×10⁻⁶ 6In a gate bias thermal stress test (BT test) of V / cm and 12 hours, the number of bonds between impurities and the main components of the oxide semiconductor is cut off by a strong electric field (B: bias) and a high temperature (T: temperature), and the generated number of unpaired bonds causes drift in the threshold voltage (Vth). However, as described above, by improving the interface characteristics between the gate insulating film and the oxide semiconductor film, and by removing impurities in the oxide semiconductor film, especially moisture or hydrogen, to the extreme, a transistor that is stable even in the BT test can be obtained.

[0204] By the above process, the hydrogen concentration in the oxide semiconductor film can be reduced to achieve high purity. This allows for the stabilization of the oxide semiconductor film. Furthermore, by heat treatment below the glass transition temperature, an oxide semiconductor film with extremely low carrier density and a wide band gap can be formed. Consequently, since transistors can be fabricated using large-area substrates, mass production capabilities can be increased. Additionally, by utilizing this oxide semiconductor film with reduced hydrogen concentration and high purity, transistors with high voltage resistance, low short channel effect, and high on / off ratio can be fabricated.

[0205] In addition, when heating an oxide semiconductor film, plate-like crystals may be formed on its surface, although this varies depending on the material of the oxide semiconductor film and the heating conditions. It is preferable that the plate-like crystals be single crystals oriented approximately perpendicularly to the surface of the oxide semiconductor film along the c-axis. Furthermore, even if they are not single crystals, it is preferable that they be polycrystalline, where the ab planes of each crystal coincide in the channel formation region, or where the a-axis or b-axis coincides, and where they are oriented approximately perpendicularly to the surface of the oxide semiconductor film along the c-axis. Additionally, if there are irregularities on the base surface of the oxide semiconductor film, the plate-like crystals become polycrystalline.

[0206] Next, as shown in FIG. 10(C), a conductive film that serves as a source electrode and a drain electrode (including wiring formed in the same layer) is formed on a gate insulating film (403), an oxide semiconductor film (405), and an oxide semiconductor film (406). Then, by patterning the conductive film, a source electrode (407) and a drain electrode (408) are formed on the oxide semiconductor film (405), and a source electrode (409) and a drain electrode (410) are formed on the oxide semiconductor film (406), respectively. It is preferable to form the conductive film by sputtering or vacuum deposition. As a material for the conductive film that serves as a source electrode and a drain electrode (including wiring formed in the same layer), examples include an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy having the above-mentioned elements as components, or an alloy film combining the above-mentioned elements. In addition, it is also acceptable to have a configuration in which a high-melting-point metal film such as Cr, Ta, Ti, Mo, or W is laminated on the lower or upper side of a metal film such as Al or Cu. Furthermore, it is possible to improve heat resistance by using an Al material to which elements such as Si, Ti, Ta, W, Mo, Cr, Nd, Sc, or Y are added to prevent the formation of hillocks or whiskers that occur in the Al film.

[0207] In addition, the conductive film may have a single-layer structure or a stacked structure of two or more layers. Examples include a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on top of an aluminum film, and a three-layer structure in which a Ti film is stacked, an aluminum film is stacked over the Ti film, and a Ti film is deposited thereon.

[0208] In addition, the conductive film serving as the source electrode and drain electrode (including wiring formed in the same layer) may be formed from a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium zinc oxide alloy (In2O3-ZnO), or a metal oxide material containing silicon or silicon oxide may be used.

[0209] When performing a heat treatment after the conductive film, it is desirable to ensure that the conductive film has heat resistance capable of withstanding this heat treatment.

[0210] Then, a resist mask is formed on the conductive film, and selective etching is performed to form the source electrode (407) and drain electrode (408) and the source electrode (409) and drain electrode (410), and then the resist mask is removed.

[0211] Ultraviolet light, KrF laser light, or ArF laser light is used for exposure during the formation of a resist mask in the photolithography process. The channel length (L) of the transistor to be formed later is determined by the gap width between the lower part of the source electrode and the lower part of the drain electrode adjacent to each other on the oxide semiconductor film (405) and the oxide semiconductor film (406). In addition, when performing exposure with a channel length (L) of less than 25 nm, the exposure is performed using extreme ultraviolet light with a very short wavelength of several nm to several tens of nm during the formation of the resist mask in the photolithography process. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is possible to make the channel length (L) of the transistor to be formed later 10 nm or more and 1000 nm or less, the operating speed of the circuit can be accelerated, and since the off-current value is very small, low power consumption can also be achieved.

[0212] In addition, when etching the conductive film, the respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor film (405) and the oxide semiconductor film (406) are not removed as much as possible.

[0213] In the present embodiment 3, a titanium film is used to wet-etch the conductive film using a solution (ammonia peroxide) containing ammonia and hydrogen peroxide, thereby forming a source electrode (407) and a drain electrode (408), and a source electrode (409) and a drain electrode (410). Specifically, the solution containing ammonia peroxide is an aqueous solution in which 31% by weight of hydrogen peroxide, 28% by weight of ammonia, and water are mixed in a volume ratio of 5:2:2. Alternatively, the conductive film may be dry-etched using a gas containing chlorine (Cl2), boron chloride (BCl3), etc.

[0214] When forming the source electrode (407) and drain electrode (408) and the source electrode (409) and drain electrode (410) by the above patterning, the exposed portions of the island-shaped oxide semiconductor film (405) and oxide semiconductor film (406) may be partially etched to form a groove (concave portion). Additionally, a resist mask for forming the source electrode (407) and drain electrode (408) and the source electrode (409) and drain electrode (410) may be formed by an inkjet method. Since a photomask is not used when forming the resist mask by an inkjet method, manufacturing costs can be reduced.

[0215] In addition, to reduce the number of photomasks and process steps used in the photolithography process, an etching process may be performed using a resist mask formed by a multi-gradation mask that provides multi-level intensity to the transmitted light. The resist mask formed using the multi-gradation mask has a shape with multiple film thicknesses, and since the shape can be further modified by etching, it can be used in multiple etching processes to process into different patterns. Therefore, a single multi-gradation mask can form a resist mask corresponding to at least two different patterns. Consequently, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, thereby enabling process simplification.

[0216] Next, plasma treatment is performed using a gas such as N2O, N2, or Ar. This plasma treatment removes adsorbed water and the like attached to the surface of the exposed oxide semiconductor film. Additionally, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0217] Additionally, after performing plasma treatment, an insulating film (411) is formed to cover the source electrode (407) and drain electrode (408), the source electrode (409) and drain electrode (410), the oxide semiconductor film (405), and the oxide semiconductor film (406), as shown in FIG. 10(D). It is preferable that the insulating film (411) does not contain impurities such as moisture or hydrogen, and it may be a single-layer insulating film or composed of a plurality of stacked insulating films. If hydrogen is contained in the insulating film (411), the hydrogen may penetrate into the oxide semiconductor film or extract oxygen from the oxide semiconductor film, causing the back channel portion of the oxide semiconductor film to become low-resistance (n-type) and potentially forming parasitic channels. Therefore, it is important not to use hydrogen in the film formation method so that the insulating film (411) becomes a film that does not contain hydrogen as much as possible. It is preferable to use a material with high barrier properties for the insulating film (411). For example, silicon nitride film, silicon nitride oxide film, aluminum nitride film, or aluminum nitride oxide film can be used as an insulating film with high barrier properties. When using a plurality of stacked insulating films, an insulating film such as a silicon oxide film or a silicon nitride oxide film with a nitrogen content ratio lower than that of the insulating film with high barrier properties is formed on the side closer to the oxide semiconductor film (405) and the oxide semiconductor film (406). Then, an insulating film with high barrier properties is formed by sandwiching the insulating film with a low nitrogen content ratio between it and overlapping with the source electrode (407) and drain electrode (408), the source electrode (409) and drain electrode (410), and the oxide semiconductor film (405) and the oxide semiconductor film (406). By using an insulating film with high barrier properties, it is possible to prevent impurities such as moisture or hydrogen from entering the oxide semiconductor film (405) and oxide semiconductor film (406), the gate insulating film (403), or the interface between the oxide semiconductor film (405) and oxide semiconductor film (406) and another insulating film and its vicinity.In addition, by forming an insulating film such as a silicon oxide film or a silicon nitride film with a low nitrogen ratio to contact the oxide semiconductor film (405) and the oxide semiconductor film (406), it is possible to prevent the insulating film using a material with high barrier properties from directly contacting the oxide semiconductor film (405) and the oxide semiconductor film (406).

[0218] In this embodiment 3, an insulating film (411) having a structure in which a silicon nitride film with a thickness of 100 nm formed by sputtering is laminated on a silicon oxide film with a thickness of 200 nm formed by sputtering. The substrate temperature during film formation should be above room temperature and below 300°C, and in this embodiment 3, it is set to 100°C.

[0219] Additionally, after forming the insulating film (411), a heat treatment may be performed. The heat treatment is performed under an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a noble gas (argon, helium, etc.), preferably at a temperature of 200°C or higher and 400°C or lower, for example, at a temperature of 250°C or higher and 350°C or lower. In the present embodiment 3, for example, a heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. Alternatively, before forming the source electrode (407) and drain electrode (408), and the source electrode (409) and drain electrode (410), a high-temperature, short-time RTA treatment may be performed, similar to the previous heat treatment performed on the oxide semiconductor film. Even if oxygen deficiency has occurred in the oxide semiconductor film (405) and oxide semiconductor film (406) due to the previous heat treatment performed on the oxide semiconductor film, oxygen is supplied to the oxide semiconductor film (405) and oxide semiconductor film (406) by performing a heat treatment after the exposed area of ​​the oxide semiconductor film (405) formed between the source electrode (407) and the drain electrode (408) and the insulating film (411) containing oxygen are formed in contact with each other, or after the exposed area of ​​the oxide semiconductor film (406) formed between the source electrode (409) and the drain electrode (410) and the insulating film (411) containing oxygen are formed in contact with each other. Accordingly, by supplying oxygen to the area in contact with the insulating film (411) of the oxide semiconductor film (405) and the oxide semiconductor film (406), the oxygen deficiency that becomes a donor is reduced, making it possible to achieve a configuration that satisfies the stoichiometric composition ratio. As a result, the oxide semiconductor film (405) and the oxide semiconductor film (406) can be made i-shaped or substantially i-shaped, thereby improving the electrical characteristics of the transistor and reducing deviations in electrical characteristics. The timing of performing this heat treatment is not particularly limited as long as it is after the formation of the insulating film (411).By combining the heat treatment in other processes, for example, the heat treatment during resin film formation or the heat treatment for making the transparent conductive film low-resistance, the oxide semiconductor film (405) and the oxide semiconductor film (406) can be made i-shaped or substantially i-shaped without increasing the number of processes.

[0220] FIG. 11(A) shows a top view of a memory device after the process shown in FIG. 10(D) has been completed. Also, the cross-sectional view along the dashed line A1-A2 in FIG. 11(A) corresponds to FIG. 10(D).

[0221] Next, a contact hole (412) is formed in the insulating film (411) by etching or the like to expose a part of the drain electrode (408). Then, as shown in FIG. 10(E), a conductive film is formed on the insulating film (411), and then the back gate electrode (413) is formed at a position overlapping with the oxide semiconductor film (406) by patterning the conductive film, and then an insulating film (414) is formed to cover the back gate electrode (413). The back gate electrode (413) is connected to the drain electrode (408) at the contact hole (412). The back gate electrode (413) can be formed using materials and structures such as the gate electrode (401), gate electrode (402), source electrode (407) and drain electrode (408), source electrode (409) and drain electrode (410).

[0222] The film thickness of the back gate electrode (413) is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a conductive film having a structure in which a titanium film, an aluminum film, and a titanium film are stacked is formed, then a resist mask is formed by photolithography or the like, unnecessary parts are removed by etching, and the back gate electrode (413) is formed by processing (patterning) the conductive film into a desired shape.

[0223] It is preferable to use a material with high barrier properties for the insulating film (414) that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor. For example, as an insulating film with high barrier properties, silicon nitride film, silicon nitride oxide film, aluminum nitride film, or aluminum nitride oxide film can be formed as a single layer or stacked by plasma CVD or sputtering methods. To obtain a barrier effect, it is preferable to form the insulating film (414) with a film thickness of, for example, 15 nm to 400 nm.

[0224] In this embodiment 3, an insulating film of 300 nm is formed by a plasma CVD method. The film formation conditions are such that the flow rate of silane gas is 4 sccm, the flow rate of dinitrogen monoxide (N2O) is 800 sccm, and the substrate temperature is 400°C.

[0225] By the above process, a transistor (420) functioning as a switching element, a transistor (421) functioning as a memory element, and a capacitance element (430) are formed. FIG. 11(B) shows a top view of the memory cell shown in FIG. 10(E). FIG. 10(E) corresponds to a cross-sectional view along the dashed line A1-A2 in FIG. 11(B).

[0226] The transistor (420) has a gate electrode (401) formed on a substrate (400) having an insulating surface, a gate insulating film (403) on the gate electrode (401), an oxide semiconductor film (405) superimposed on the gate electrode (401) on the gate insulating film (403), and a pair of source electrodes (407) or drain electrodes (408) formed on the oxide semiconductor film (405). Additionally, the transistor (420) may include an insulating film (411) formed on the oxide semiconductor film (405) as a component. The transistor (420) shown in FIG. 10(E) has a channel etch structure in which a portion of the oxide semiconductor film (405) is etched between the source electrode (407) and the drain electrode (408).

[0227] Additionally, although the transistor (420) was described using a single-gate structure transistor, a multi-gate structure transistor having multiple channel forming regions can also be formed by having multiple electrically connected gate electrodes (401) as needed.

[0228] Additionally, the transistor (421) has a gate electrode (402) formed on a substrate (400) having an insulating surface, a gate insulating film (403) on the gate electrode (402), an oxide semiconductor film (406) superimposed on the gate electrode (402) on the gate insulating film (403), a pair of source electrodes (409) or drain electrodes (410) formed on the oxide semiconductor film (406), an insulating film (411) formed on the oxide semiconductor film (406), the source electrode (409), and the drain electrode (410), and a back gate electrode (413) superimposed on the oxide semiconductor film (406) and the gate electrode (402) on the insulating film (411). Additionally, the transistor (421) may include an insulating film (414) formed on the back gate electrode (413) as a component. The transistor (421) shown in FIG. 10(E) is a channel etch structure in which a portion of the oxide semiconductor film (406) is etched between the source electrode (409) and the drain electrode (410).

[0229] Additionally, although the transistor (421) was described using a single-gate structure transistor, a multi-gate structure transistor having multiple channel forming regions can also be formed by having multiple electrically connected gate electrodes (402) as needed.

[0230] Additionally, the capacitance element (430) is formed in an area where the source electrode (409) and the back gate electrode (413) of the transistor (421) overlap each other with an insulating film (411) in between.

[0231] The gate electrode (402) of the transistor (421) functions as a first electrode that can select operations such as writing, reading, retaining, and erasing data as a memory element by controlling its potential. Additionally, the back gate electrode (413) functions as a second gate electrode that can control the threshold voltage value of the transistor (421) used as a memory element by controlling its potential. Furthermore, in this embodiment 3, regarding the transistor (421) used as a memory element, a memory cell is exemplified in which the gate electrode (402) formed before the oxide semiconductor film (406) is used as the first electrode and the back gate electrode (413) formed after the oxide semiconductor film (406) is used as the second electrode, but the present invention is not limited to this configuration. For example, in a transistor (421) used as a memory element, it is possible to operate the gate electrode (402) formed before the oxide semiconductor film (406) as the second electrode and the back gate electrode (413) formed after the oxide semiconductor film (406) as the first electrode. However, in this case, instead of the back gate electrode (413), the gate electrode (402) is connected to the drain electrode (408) of the transistor (420).

[0232] Additionally, FIG. 11(B) illustrates a case where the back gate electrode (413) covers the entire oxide semiconductor film (406), but the present invention is not limited to this configuration. The back gate electrode (413) may overlap at least with a part of the channel forming region of the oxide semiconductor film (406).

[0233] In addition, the band gap of oxide semiconductors is 3.0 to 3.5 eV. Meanwhile, the band gap of silicon carbide is 3.26 eV and the band gap of gallium nitride is 3.39 eV, both having large band gaps that are about three times larger than those of silicon. Therefore, these compound semiconductors, such as silicon carbide and gallium nitride, are similar to oxide semiconductors in that they are wide-gap semiconductors, and the characteristic of having a large band gap is advantageous for improving the breakdown voltage of transistors and reducing power loss.

[0234] Next, the following explains how removing impurities such as moisture or hydrogen contained in the oxide semiconductor film as in Embodiment 3 of this invention to achieve high purity of the oxide semiconductor film affects the characteristics of the transistor.

[0235] FIG. 12 shows a cross-sectional view of an inverse staggered transistor using an oxide semiconductor. An oxide semiconductor film (OS) is formed over a gate electrode (GE) through a gate insulating film (GI), a source electrode (S) and a drain electrode (D) are formed over it, and an insulating film is formed to cover the source electrode (S) and the drain electrode (D).

[0236] FIG. 13 shows the energy band diagram (schematic) on A–A' shown in FIG. 12. Also, in FIG. 13, black circles (●) represent electrons and white circles (○) represent holes, each having charges -q and +q, respectively. A positive voltage (V) is applied to the drain electrode (D). D After applying >0), the dashed line indicates the case where no voltage is applied to the gate electrode (GE) (V G = 0), the solid line represents the positive voltage (V) on the gate electrode (GE). GThis indicates the case where >0) is applied. When no voltage is applied to the gate electrode (GE), carriers (electrons) are not injected from the source electrode (S) to the oxide semiconductor film (OS) side due to the high potential barrier, and an off state is indicated where no current flows. On the other hand, when a positive voltage is applied to the gate electrode (GE), the potential barrier is lowered, and an on state is indicated where current flows.

[0237] FIG. 14 is an energy band diagram (schematic) on B-B' in FIG. 12. FIG. 14(A) is a defined potential (V) at the gate electrode (GE). G It indicates an ON state where a potential >0 is applied and carriers (electrons) flow between the source electrode (S) and the drain electrode (D). Additionally, FIG. 14(B) shows a negative potential (V) at the gate electrode (GE). G <0) indicates the case where it is an authorized state and is off (no minority carriers flow).

[0238] Fig. 15 shows the vacuum level and the work function (φ) of the metal. M It represents the relationship between the electron affinity (χ) of oxide semiconductors.

[0239] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Meanwhile, conventional oxide semiconductors are generally n-type, and in that case, the Fermi level (Ef) is located far from the intrinsic Fermi level (Ei), which is located at the center of the band gap, and is located near the conduction band (Ec). Furthermore, it is known that some of the hydrogen in oxide semiconductors becomes donors, and that this is one of the factors causing the oxide semiconductor to become n-type. It is also known that oxygen vacancies are one of the factors causing it to become n-type.

[0240] In this regard, one aspect of the present invention removes hydrogen, an n-type impurity, from an oxide semiconductor to achieve high purity so that impurities other than the main components of the oxide semiconductor are not included, and furthermore, by removing oxygen vacancies, the oxide semiconductor is brought infinitely close to an intrinsic state. That is, rather than converting the oxide semiconductor to an i-type by adding impurities, the invention is characterized by obtaining an oxide semiconductor that is infinitely close to an i-type (intrinsic semiconductor) or an i-type (intrinsic semiconductor) by achieving high purity through the extreme removal of impurities such as moisture or hydrogen and oxygen vacancies. With the above configuration, as indicated by the arrow, the Fermi level (Ef) can be brought infinitely close to the same level as the intrinsic Fermi level (Ei).

[0241] It is known that the band gap (Eg) of the oxide semiconductor is 3.15 eV and the electron affinity (χ) is 4.3 V. The work function of titanium (Ti) constituting the source and drain electrodes is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, a Schottky-type barrier against electrons is not formed at the metal-oxide semiconductor interface.

[0242] At this time, the electron moves to the energetically stable lowest part on the oxide semiconductor side at the interface between the gate insulating film and the high-purity oxide semiconductor, as shown in FIG. 14(A).

[0243] In addition, in FIG. 14(B), when a negative potential is applied to the gate electrode (GE), the minority carrier, hole, is substantially zero, so the current becomes a value that is infinitely close to zero.

[0244] Next, the intrinsic carrier density in the oxide semiconductor was calculated. The band gap of the In-Ga-Zn-O oxide semiconductor is 3.05 eV, and the intrinsic carrier density is calculated based on this value. It is known that the energy distribution of electrons f(E) in the solid follows Fermi-Dirac statistics as shown in the following equation.

[0245] [Mathematical Formula 1]

[0246]

[0247] In ordinary semiconductors where the carrier density is not significantly high (not degenerate), the following relationship holds.

[0248] [Mathematical Formula 2]

[0249]

[0250] Therefore, the Fermi-Dirac distribution of mathematical formula (1) is approximated by the formula of the Boltzmann distribution, which is expressed by the following formula.

[0251] [Mathematical Formula 3]

[0252]

[0253] Using mathematical formula (3), the intrinsic carrier density (n) of the semiconductor i If you calculate ), you can obtain the following equation.

[0254] [Mathematical Formula 4]

[0255]

[0256] Then, the intrinsic carrier density was calculated by substituting the values ​​of the effective density of states (Nc, Nv) and band gap (Eg) of Si and In-Ga-Zn-O oxide semiconductors into mathematical equation (4). The results are shown in Table 1.

[0257]

[0258] It can be seen that In-Ga-Zn-O oxide semiconductors have an extremely low intrinsic carrier density compared to Si. When 3.05 eV is selected as the band gap for In-Ga-Zn-O oxide semiconductors, assuming that the Fermi-Dirac distribution rule is approximately correct for intrinsic carrier density in Si and In-Ga-Zn-O oxide semiconductors, the carrier density of the former is about 10 times that of the latter. 17 You could say the belly is big.

[0259] Next, the method for measuring the off-current of a transistor having a high-purity oxide semiconductor film and the results thereof will be explained.

[0260] FIG. 18 shows the configuration of a measurement circuit used for actual measurement. The measurement circuit shown in FIG. 18 uses a transistor having a high-purity oxide semiconductor film as a switching element to hold a charge of the holding capacity, and measures the off-current of the transistor from the trend of the charge amount per unit time of the holding capacity.

[0261] Specifically, the measuring circuit shown in FIG. 18 has a configuration in which three measuring systems (801-1) to measuring systems (801-3) for measuring off-current are connected in parallel. In addition, each of the measuring systems (801-1) to measuring systems (801-3) has a capacitive element (802) and a transistor (803) to be measured. Furthermore, each of the measuring systems (801-1) to measuring systems (801-3) has a transistor (804) to a transistor (806).

[0262] In each measurement system, the gate electrode of the transistor (803) is connected to the node where the potential (Vgb) is applied. Additionally, the source electrode of the transistor (803) is connected to the node where the potential (Vb) is applied, and the drain electrode is connected to the node (A). Additionally, the gate electrode of the transistor (804) is connected to the node where the potential (Vga) is applied. Additionally, the source electrode of the transistor (804) is connected to the node (A), and the drain electrode is connected to the node where the potential (Va) is applied. Additionally, the gate electrode and the drain electrode of the transistor (805) are connected to the node where the potential (Va) is applied. Additionally, the gate electrode of the transistor (806) is connected to the node (A), and the source electrode of the transistor (806) is connected to the node where the potential (Vb) is applied. And, the source electrode of the transistor (805) and the drain electrode of the transistor (806) are connected, and the potential of these two electrodes is output from each measuring system as potential (Vout1) to potential (Vout3). One of the pair of electrodes of the capacitive element (802) is connected to node (A), and the other is connected to the node to which potential (Vb) is applied.

[0263] In addition, in the present embodiment 3, the transistor (803) to be measured utilized a high-purity oxide semiconductor film with a thickness of 30 nm and a gate insulating film with a thickness of 100 nm. Furthermore, the channel formation region of the transistor (803) was set to a channel length (L) = 10 μm and a channel width (W) = 50 μm. Additionally, the capacitance values ​​of the capacitance elements (802) of each measurement system were set to 100 fF, 1 pF, and 3 pF, respectively.

[0264] Initialization is performed before measurement. First, the potential (Vgb) is set to a height at which the transistor (803) turns on. By doing so, the transistor (803) turns on, and the potential (Vb), i.e., the low level potential (Vss), is applied to the node (A). Then, the transistor (803) is turned off by setting the potential (Vgb) to a height at which the transistor (803) turns off. Next, the potential (Vga) is set to a height at which the transistor (804) turns on. By doing so, the potential (Va), i.e., the high level potential (VDD), is applied to the node (A), and a potential difference between the low level potential (Vss) and the high level potential (VDD) is applied between the pair of electrodes of the capacitive element (802). After that, by setting the height of the potential (Vga) to a height where the transistor (804) is turned off, the transistor (804) is turned off and the node (A) becomes floating.

[0265] Next, a measurement operation is performed. When performing the measurement, the electric potential (Va) and electric potential (Vb) are set to a height at which charge flows into or out of node (A). In this embodiment 3, the electric potential (Va) and electric potential (Vb) are set to a low level electric potential (Vss). Additionally, at the timing of measuring the electric potential (Vout), the electric potential (Va) is temporarily set to a high level electric potential (VDD), but otherwise, the electric potential (Va) and electric potential (Vb) are maintained at a low level electric potential (Vss).

[0266] Since a small off-current flows through the transistor (803), the amount of charge held at node (A) changes over time. And, as the potential of node (A) changes according to the change in the amount of charge held at node (A), the height of the potential (Vout1 to Vout3) changes according to the value of the off-current of the transistor (803).

[0267] Specifically, in this measurement, the potential (VDD) was set to 5 V and the potential (Vss) to 0 V. Then, during the measurement, the potential (Va) was set to the potential (Vss) as a principle, and every 10 to 300 seconds, the potential (Va) was set to the potential (VDD) for a period of 100 msec, and the potentials (Vout1) to (Vout3) were measured.

[0268] Figure 19 shows the relationship between the elapsed time (Time) and the output potential (Vout) regarding the current measurement. From about 90 hours, the pattern of potential change can be observed.

[0269] In advance, the potential (V) of node (A) A By establishing the relationship between ) and the output potential (Vout), the potential (V) of node (A) from the output potential (Vout) A It is possible to find the potential (V) of node (A). In general, the potential (V) of node (A) A ) can be expressed as a function of output potential (Vout) as shown in the following equation.

[0270] [Mathematical Formula 5]

[0271]

[0272] Also, the charge (Q) of node (A) A ) is the potential (V) of node (A). A ), capacity (C) connected to node (A) A Using ), and an integer (const), it is expressed as follows. Here, the capacity (C) connected to the node (A) A ) is the sum of the capacitance value of the capacitance element (802) and other capacitances (such as the input capacitance of a circuit composed of transistors (805) and transistors (806)).

[0273] [Mathematical Formula 6]

[0274]

[0275] Current (I) at node (A) ASince ) is the time derivative of the charge flowing into node (A) (or the charge flowing out of node (A)), the current (I) at node (A) A ) is expressed as follows.

[0276] [Mathematical Formula 7]

[0277]

[0278] In this way, the capacity (C) connected to the node (A) A From ) and potential (Vout1~Vout3), the current (I) at node (A) A ) can be obtained.

[0279] FIG. 20 shows the off-current calculated by measuring the above current. Δt used to calculate the current (I) flowing through the transistor (803) was set to approximately 30,000 sec. FIG. 20 also shows the relationship between the voltage (V) between the source electrode and the drain electrode and the off-current (I). From FIG. 20, it can be seen that under the condition that the voltage between the source electrode and the drain electrode is 4V, the off-current is approximately 40 zA / μm.

[0280] In this way, by purifying the oxide semiconductor film to a high degree so that impurities such as moisture or hydrogen other than the main components of the oxide semiconductor are not included, the operation of the transistor can be improved.

[0281] This embodiment can be implemented in appropriate combination with the above embodiment.

[0283] (Embodiment 4)

[0284] In this embodiment, an example of a portable memory medium, which is one of the semiconductor devices using a memory device according to one aspect of the present invention, is described.

[0285] FIG. 16(A) illustrates, as an example, the configuration of a memory medium according to one embodiment of the present invention. The memory medium shown in FIG. 16(A) comprises a memory device (701) according to one embodiment of the present invention, a connector (702) that performs electrical connection between a driving device and the memory medium, an interface (703) that performs signal processing according to specifications on various signals input and output through the connector (702), a light-emitting diode (704) that lights up according to the operating state of the memory medium, and a controller (705) that controls the operation of various circuits or semiconductor devices within the memory medium, such as the memory device (701), the interface (703), and the light-emitting diode (704), which are mounted on a printed circuit board (706). In addition, a crystal oscillator used to generate a clock signal for controlling the operation of the controller (705), a regulator for controlling the height of the power supply voltage within the memory medium, etc., may be installed.

[0286] The printed circuit board (706) shown in FIG. 16(A) may be protected by covering it with a cover material (707) made of resin or the like so that the connector (702) and the light-emitting diode (704) are partially exposed as shown in FIG. 16(B).

[0287] A memory device (701) according to one embodiment of the present invention can suppress power consumption during operation to a low level, thereby enabling low power consumption of a memory medium using the memory device (701), and furthermore, low power consumption of a driving device connected to the memory medium. In addition, a memory device (701) according to one embodiment of the present invention can retain data for a long period of time and can increase the number of times data is rewritten, thus increasing the reliability of the memory medium. Furthermore, since data can be retained for a long period of time and can increase the number of times data is rewritten, the constraints on the operating conditions of the memory medium are loosened, thereby increasing the versatility of the memory medium.

[0288] This embodiment can be implemented in appropriate combination with the above embodiment.

[0290] [Example 1]

[0291] By utilizing a semiconductor device according to one embodiment of the present invention, it is possible to provide highly reliable electronic devices, electronic devices with low power consumption, and electronic devices capable of high-speed operation. In particular, for portable electronic devices where it is difficult to receive a constant power supply, adding a semiconductor device with low power consumption according to one embodiment of the present invention to its components provides the advantage of extended continuous usage time.

[0292] In addition, in the semiconductor device of the present invention, since the temperature of the heat treatment during the manufacturing process can be suppressed, it is possible to manufacture a transistor with excellent characteristics and high reliability even on a substrate made of a flexible synthetic resin, such as plastic, which has lower heat resistance than glass. Therefore, by using the manufacturing method according to one embodiment of the present invention, it is possible to provide a semiconductor device that is highly reliable, lightweight, and flexible. Examples of plastic substrates include polyester represented by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile butadiene styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, etc.

[0293] A semiconductor device according to one embodiment of the present invention can be used in a display device, a notebook-type personal computer, and an image playback device equipped with a recording medium (typically, a device having a display capable of displaying an image by playing a recording medium such as a DVD: Digital Versatile Disc). In addition, electronic devices capable of using a semiconductor device according to one embodiment of the present invention include mobile phones, portable game consoles, portable information terminals, electronic books, video cameras, digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), photocopiers, fax machines, printers, multifunction printers, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIG. 17.

[0294] FIG. 17(A) is a portable game console and has a housing (7031), a housing (7032), a display unit (7033), a display unit (7034), a microphone (7035), a speaker (7036), an operation key (7037), a stylus (7038), etc. A semiconductor device according to one embodiment of the present invention can be used in an integrated circuit for controlling the operation of a portable game console. By using a semiconductor device according to one embodiment of the present invention in an integrated circuit for controlling the operation of a portable game console, a portable game console with high reliability, a portable game console with low power consumption, a portable game console with high-speed operation, and a portable game console with high functionality can be provided. In addition, the portable game console shown in FIG. 17(A) has two display units (7033) and a display unit (7034), but the number of display units in the portable game console is not limited to this.

[0295] FIG. 17(B) is a mobile phone and has a housing (7041), a display unit (7042), a voice input unit (7043), a voice output unit (7044), an operation key (7045), a light receiving unit (7046), etc. By converting light received from the light receiving unit (7046) into an electrical signal, an external image can be loaded. A semiconductor device according to one embodiment of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. By using a semiconductor device according to one embodiment of the present invention in an integrated circuit for controlling the operation of a mobile phone, a mobile phone with high reliability, a mobile phone with low power consumption, a mobile phone with high-speed operation, and a mobile phone with high functionality can be provided.

[0296] FIG. 17(C) is a portable information terminal and has a housing (7051), a display unit (7052), an operation key (7053), etc. In the portable information terminal shown in FIG. 17(C), a modem is embedded in the housing (7051). A semiconductor device according to one embodiment of the present invention can be used in an integrated circuit for controlling the operation of a portable information terminal. By using a semiconductor device according to one embodiment of the present invention in an integrated circuit for controlling the operation of a portable information terminal, a portable information terminal with high reliability, a portable information terminal with low power consumption, a portable information terminal with high speed operation, and a portable information terminal with high functionality can be provided.

[0297] This embodiment can be implemented in appropriate combination with the above embodiment.

[0299] The present application is based on Japanese patent application No. 2009-297140, filed with the Japan Patent Office on December 28, 2009, the entire text of which is incorporated herein by reference. Explanation of the symbols

[0301] 100: Memory cell 101: Transistor 102: Transistor 103: Capacitance element 110: Substrate 111: Gate electrode 112: Insulating film 113: Oxide semiconductor film 114: Source electrode 115: Drain electrode 116: Insulating film 117: Insulating film 121: Gate electrode 123: Oxide semiconductor film 124: Source electrode 125: Drain electrode 126: Gate electrode 130: Line 131: Line 140: Substrate 141: Gate electrode 142: Insulating film 143: Oxide semiconductor film 144: Source electrode 145: Drain electrode 146: Insulating film 147: Insulating film 148: Channel protective film 151: Gate electrode 153: Oxide semiconductor film 154: Source electrode 155: Drain electrode 156: Gate electrode 157: Channel shield 160: Substrate 161: Gate electrode 162: Insulating film 163: Oxide semiconductor film 164: Source electrode 165: Drain electrode 166: Insulating film 167: Insulating film 171: Gate electrode 173: Oxide semiconductor film 174: Source electrode 175: Drain electrode 176: Gate electrode 200: Substrate 208: Oxide semiconductor film 211: Gate electrode 212: Insulating film 213: Oxide semiconductor film 214: Source electrode 215: Drain electrode 216: Insulating film 217: Insulating film 221: Gate electrode 223: Semiconductor film 224: Source electrode 225: Drain electrode 226: Gate electrode 230: Insulating film 231: Insulating film 241: Gate electrode 242: Insulating film 243: Oxide semiconductor film 244: Source electrode 245: Drain electrode 246: Insulating film 247: Insulating film 251: Gate electrode 253: Semiconductor film 254: Source electrode 255: Drain electrode 256: Gate electrode 260: Insulating film 261: Insulating film 270: Substrate 300: Memory cell 301: Transistor 302: Transistor 303: Capacitive element 304: Power line 310_1: Transistor 310_2: Transistor 310_3: Transistor 311_1: Transistor 311_2: Transistor 311_3: Transistor 312_1: Operational amplifier 312_2: Operational amplifier 312_3: Operational amplifier 320: Transistor 321: Transistor 400: Substrate 401: Gate electrode 402: Gate electrode 403: Gate insulating film 404: Oxide semiconductor film 405: Oxide semiconductor film 406: Oxide semiconductor film 407: Source electrode 408: Drain electrode 409: Source electrode 410: Drain electrode 411: Insulating film 412: Contact hole 413: Back gate electrode 414: Insulating film 420: Transistor 421: Transistor 430: Capacitive element 500: Cell array 501: Driving circuit 502: Read circuit 503: Word line driving circuit 504: Data line driving circuit 505: Control circuit 506: Decoder for word lines 508: Decoder for data lines 509: Data line selector 701: Memory device 702: Connector 703: Interface 704: Light-emitting diode 705: Controller 706: Printed Wiring Board 707: Cover Material 801-1: Measuring system 801-2: Measuring system 801-3: Measuring system 802: Capacitive element 803: Transistor 804: Transistor 805: Transistor 806: Transistor 7031: Housing 7032: Housing 7033: Display unit 7034: Display unit 7035: Microphone 7036: Speaker 7037: Control Keys 7038: Stylus 7041: Housing 7042: Display 7043: Voice input unit 7044: Voice output unit 7045: Control Key 7046: Light Receiver 7051: Housing 7052: Display unit 7053: Control Keys

Claims

Claim 1 A semiconductor device comprising: a first transistor including a first oxide semiconductor layer; and a second transistor including a second oxide semiconductor layer; The apparatus includes a capacitance element, wherein the first oxide semiconductor layer and the first conductive layer overlap each other, and the first conductive layer includes a region that becomes the first gate of the first transistor, the first oxide semiconductor layer and the second conductive layer overlap each other, and the second conductive layer includes a region that becomes the second gate of the first transistor, and the third conductive layer and the fourth conductive layer each are on the first oxide semiconductor layer and are in contact with the first oxide semiconductor layer, the fifth conductive layer is on the second oxide semiconductor layer and is in contact with the second oxide semiconductor layer, and the second conductive layer is electrically connected to the fifth conductive layer, and the third conductive layer includes a first region that overlaps with the first oxide semiconductor layer and a second region that does not overlap with the first oxide semiconductor layer, and the second conductive layer includes a third region that overlaps with the second region of the third conductive layer, and the third region of the second conductive layer becomes the first electrode of the capacitance element, and the A semiconductor device in which the second region of the third conductive layer becomes the second electrode of the capacitive element, and in the channel length direction of the first transistor, the maximum width of the second region of the third conductive layer is greater than the maximum width of the first region of the third conductive layer, and in the top view, the maximum area of ​​the second region of the third conductive layer is greater than the maximum area of ​​the first region of the third conductive layer, and a signal is supplied to the capacitive element through the second transistor. Claim 2 A semiconductor device comprising: a first transistor including a first oxide semiconductor layer; and a second transistor including a second oxide semiconductor layer; The apparatus includes a first oxide semiconductor layer and a first conductive layer, wherein the first conductive layer includes a region that becomes the first gate of the first transistor, wherein the first oxide semiconductor layer and the second conductive layer overlap each other, wherein the second conductive layer includes a region that becomes the second gate of the first transistor, wherein the third conductive layer and the fourth conductive layer are each on the first oxide semiconductor layer and in contact with the first oxide semiconductor layer, wherein the fifth conductive layer is on the second oxide semiconductor layer and in contact with the second oxide semiconductor layer, wherein the channel length direction of the first transistor is the same as the channel length direction of the second transistor, wherein in the channel length direction of the first transistor, the maximum width of the second conductive layer is greater than the maximum width of the first oxide semiconductor layer, wherein the third conductive layer includes a first region that overlaps with the first oxide semiconductor layer and a second region that does not overlap with the first oxide semiconductor layer, and wherein the second conductive layer is the A semiconductor device comprising a third region that overlaps with a second region, wherein the third region of the second conductive layer becomes the first electrode of the capacitive element and the second region of the third conductive layer becomes the second electrode of the capacitive element, wherein in the channel length direction of the first transistor, the maximum width of the second region of the third conductive layer is greater than the maximum width of the first region of the third conductive layer, and in the top view, the maximum area of ​​the second region of the third conductive layer is greater than the maximum area of ​​the first region of the third conductive layer. Claim 3 A semiconductor device comprising: a first transistor including a first oxide semiconductor layer; and a second transistor including a second oxide semiconductor layer;and includes a capacitance element, wherein the first oxide semiconductor layer and the first conductive layer overlap each other, and the first conductive layer includes a region that becomes the first gate of the first transistor, the first oxide semiconductor layer and the second conductive layer overlap each other, and the second conductive layer includes a region that becomes the second gate of the first transistor, the third conductive layer and the fourth conductive layer each are on the first oxide semiconductor layer and are in contact with the first oxide semiconductor layer, the fifth conductive layer is on the second oxide semiconductor layer and is in contact with the second oxide semiconductor layer, and the second conductive layer is electrically connected to the fifth conductive layer through a contact hole, the channel length direction of the first transistor is the same as the channel length direction of the second transistor, and in the channel length direction of the first transistor, the maximum width of the second conductive layer is greater than the maximum width of the first oxide semiconductor layer, and the third conductive layer includes a first region that overlaps with the first oxide semiconductor layer and the first oxide A semiconductor device comprising a second region that does not overlap with a semiconductor layer, wherein the second conductive layer comprises a third region that overlaps with the second region of the third conductive layer, wherein the third region of the second conductive layer becomes the first electrode of the capacitive element, and the second region of the third conductive layer becomes the second electrode of the capacitive element, wherein in the channel length direction of the first transistor, the maximum width of the second region of the third conductive layer is greater than the maximum width of the first region of the third conductive layer, and in the top view, the maximum area of ​​the second region of the third conductive layer is greater than the maximum area of ​​the first region of the third conductive layer, wherein the second oxide semiconductor layer and the contact hole do not overlap with each other, and a signal is supplied to the capacitive element through the second transistor. Claim 4 A semiconductor device according to any one of claims 1 to 3, wherein the first oxide semiconductor layer comprises indium, gallium, and zinc.

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