Methods and apparatus for decoding received uplink transmissions using log-likelihood ratio (LLR) optimization

Abstract

Methods and apparatuses for decoding received uplink transmissions using log-possible ratio optimization are provided. In one embodiment, the method comprises the steps of soft-demapping resource elements based on soft-demapping parameters as part of a process for generating a log-possible ratio (LLR) value, decoding the LLR to generate decoded data, and identifying a target performance value. The method also comprises the step of determining a performance metric from the decoded data and performing a machine learning algorithm that dynamically adjusts the soft-demapping parameters to shift the performance metric to a target performance value.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] This application claims priority to the U.S. provisional application (Application No. 62 / 975,080) filed in the United States on February 11, 2020, under the title "LOG-LIKELIHOOD RATIO(LLR) OPTIMIZATION FOR 5G BY MACHINE REARNING," the entire contents of which are incorporated herein by reference.

[0003] An exemplary embodiment of the present invention relates to the operation of a communication network. More specifically, an exemplary embodiment of the present invention relates to receiving and processing a data stream using a wireless remote communication network. Background Technology

[0004] With the rapid growth trend of mobile and remote data access through high-speed communication networks such as LTE (Long Term Evolution), 4th generation (4G), and 5th generation (5G) cellular services, it is becoming increasingly difficult to accurately transmit and decode data streams. High-speed communication networks capable of transmitting information include, but are not limited to, wireless networks, cellular networks, wireless personal area networks (WPAN), wireless local area networks (WLAN), and wireless metropolitan area networks ("MAN"). A wireless personal area network ("WPAN") can be Bluetooth or ZigBee, while a wireless local area network (WLAN) can be a Wi-Fi network according to the IEEE 802.11 WLAN standard. The problem to be solved

[0005] In 5G systems, reference signals, data, and uplink control information (UCI) may be included in uplink transmissions from user equipment. Reference signals (RS) are used to estimate channel states or for other purposes. However, reference signals are mixed with data, and therefore, reference signals must be taken into account when data and / or UCI information are processed. For example, when processing received resource elements (REs) in uplink transmissions, special processing may be required to skip resource elements containing reference signals. Even if reference signals are set to zero or are empty, their corresponding resource elements still need to be considered when processing received data. Additionally, it is desirable to provide efficient descrambling, combining, and decoding functions to process received uplink transmissions.

[0006] Therefore, it is desirable to have a system capable of efficiently processing data and UCI information received from uplink transmission. means of solving the problem

[0007] In various exemplary embodiments, a method and device for a decoding system that enables fast and efficient processing of received 4G and / or 5G uplink transmissions are provided. In various exemplary embodiments, a decoder that decodes a received uplink transmission using log-likelihood ratio (LLR) optimization is provided.

[0008] In one embodiment, a resource element identifier indexes and classifies the uplink control information (UCI) of the received uplink symbols into one of three categories. For example, the UCI information includes a hybrid automatic repeat request ("HARQ"), an acknowledgment ("ACK"), first channel status information ("CSI1"), and second channel status information ("CSI2"). For example, Category 0 is data or CSI2 information, Category 1 is ACK information, and Category 2 is CSI1 information. In one embodiment, the classification information is passed to a combiner / extractor that receives the descrambled resource elements. The classification information is used to identify and combine uplink control information from the descrambled resource elements for each symbol. For example, resource elements containing ACK are combined, resource elements containing CSI1 are combined, and resource elements containing CSI2 are combined. Combination is performed for a selected number of received symbols.

[0009] In one embodiment, the provided decoder system includes an LLR preprocessor that splits an LLR stream into individual data and CSI2 LLR streams. Separate decoders decode the streams to generate decoded information. Accordingly, in various exemplary embodiments, the received uplink control information is descrambled, combined, and decoded to obtain UCI information in order to provide efficient processing and enhanced system performance.

[0010] In one embodiment, a method is provided, the method comprising the steps of soft-demapping resource elements based on soft-demapping parameters as part of a process for generating a log-likeness ratio (LLR) value, decoding the LLR to generate decoded data, and identifying a target performance value. The method also comprises the steps of determining a performance metric from the decoded data and performing a machine learning algorithm that dynamically adjusts the soft-demapping parameters to shift the performance metric to a target performance value.

[0011] In one embodiment, an apparatus is provided, the apparatus comprising a soft demapper configured to soft demap resource elements based on soft demapping parameters as part of a process for generating a log similarity ratio (LLR) value, and a decoder configured to decode data from the LLR. The apparatus also comprises a machine learning circuit, the machine learning circuit comprising a machine learning algorithm that identifies a target performance value, determines a performance metric from the decoded data, and dynamically adjusts the soft demapping parameters to shift the performance metric to the target performance value.

[0012] In one embodiment, an apparatus is provided, the apparatus comprising: means for soft-demapping resource elements based on soft-demapping parameters as part of a process for generating log-likeness ratio (LLR) values; means for decoding the LLR to generate decoded data; means for identifying a target performance value; means for determining a performance metric from the decoded data; and means for performing a machine learning algorithm that dynamically adjusts the soft-demapping parameters to shift the performance metric to the target performance value.

[0013] Additional features and advantages of exemplary embodiments of the present invention will become apparent from the detailed description, drawings, and claims described below. Brief explanation of the drawing

[0014] Exemplary aspects of the present invention will be more fully understood from the following detailed description and the accompanying drawings relating to various embodiments of the present invention, but the various embodiments of the present invention should not be construed as limiting the present invention to specific embodiments, and this is for illustrative and illustrative purposes only. FIG. 1 illustrates a block diagram of a communication network in which resource elements received from user equipment in an uplink transmission are descrambled and combined by an exemplary embodiment of a descrambling and combining system. FIG. 2 illustrates an exemplary detailed embodiment of a scrambling and coupling system. FIG. 3 shows a block diagram illustrating a detailed exemplary embodiment of the RE identifier block illustrated in FIG. 2. FIG. 4a shows a block diagram illustrating a detailed exemplary embodiment of the scrambler illustrated in FIG. 2. FIG. 4b illustrates a block diagram illustrating the operation performed by the scrambler shown in FIG. 4a. FIG. 5a illustrates a block diagram illustrating an exemplary embodiment of the combiner / extractor shown in FIG. 2. FIG. 5b illustrates a block diagram illustrating the operation performed by the combiner / extractor shown in FIG. 5a. FIG. 6 illustrates an exemplary method for performing resource element classification according to an exemplary embodiment of a resource element identification system. FIG. 7 illustrates an exemplary method for performing descrambling according to an exemplary embodiment of a descrambling and joining system. FIG. 8 illustrates an exemplary method of performing a combination according to an exemplary embodiment of a scrambling and combination system. FIGS. 9a-b illustrates an exemplary method for performing a combination according to an exemplary embodiment of a scrambling and combination system. FIG. 10a illustrates an exemplary block diagram of a decoder system. FIG. 10b illustrates an exemplary detailed diagram illustrating an example of an LLR stream input to the decoder system illustrated in FIG. 10a. FIG. 11 illustrates an exemplary method for performing decoding according to exemplary embodiments of a decoder system. FIG. 12 illustrates an exemplary embodiment of a part of the scrambling and coupling system illustrated in FIG. 2. FIG. 13 illustrates an exemplary detailed embodiment of the machine learning circuit illustrated in FIG. 12. FIG. 14 shows an exemplary embodiment of the parameter table illustrated in FIG. 13. FIG. 15 illustrates an exemplary embodiment of a soft-demapper circuit for use in an embodiment of the present invention. Figure 16 illustrates an exemplary graph illustrating the operation of the system. FIG. 17 illustrates an exemplary method of performing a machine learning algorithm to optimize performance according to an exemplary embodiment of a decoder system. FIG. 18 illustrates an exemplary method for performing a machine learning algorithm according to an exemplary embodiment of a machine learning circuit. FIG. 19 illustrates a block diagram illustrating a processing system having an exemplary embodiment of a decoder system including a machine learning circuit. Specific details for implementing the invention

[0015] An aspect of the present invention is described below in relation to a method and device for processing uplink information received in wireless transmission.

[0016] The purpose of the following detailed description is to provide an understanding of one or more embodiments of the present invention. Those skilled in the art will recognize that the following detailed description is merely illustrative and is not intended to limit the invention in any way. Other embodiments will be readily apparent to those skilled in the art who benefit from this disclosure and / or description.

[0017] For clarity, not all routine features of the embodiments described herein are illustrated and described. Of course, when developing these actual embodiments, numerous embodiment-specific decisions may be made to achieve specific goals of the developer, such as compliance with application and business-related constraints, and these specific goals may vary from embodiment to embodiment and developer to developer. Furthermore, it will be understood that while such development efforts may be complex and time-consuming, they are nevertheless routine engineering work for those skilled in the art who benefit from the embodiments of this disclosure.

[0018] Various embodiments of the invention illustrated in the drawings may not be drawn to scale. Rather, the dimensions of various features may be expanded or reduced for clarity. Additionally, some drawings may be simplified for clarity. Accordingly, the drawings may not depict all components of a given device (e.g., device) or method. The same reference numbers will be used throughout the drawings to refer to identical or similar parts.

[0019] The terms “system” or “device” are generally used herein to describe any number of components, elements, subsystems, devices, packet switch elements, packet switches, access switches, routers, networks, modems, base stations, eNBs (eNodeBs), computers and / or communication devices or mechanisms, or combinations of components thereof. The term “computer” includes a processor, memory, and a bus capable of executing instructions, wherein “computer” means one or a cluster of a computer, personal computer, workstation, mainframe, or combination of computers.

[0020] An IP communication network, IP network, or communication network refers to any type of network having an access network capable of transmitting data in the form of packets or cells, such as Asynchronous Transfer Mode (ATM), over a transmission medium of the type, for example, TCP / IP or UDP / IP. An ATM cell is the result of the decomposition (or splitting) of a data packet of the IP type, and such a packet (here, an IP packet) consists of an IP header, a header specific to the transmission medium (e.g., UDP or TCP), and payload data. IP networks may include satellite networks, DVB-RCS (Digital Video Broadcasting-Return Channel System) networks or SDMB (Satellite Digital Multimedia Broadcast) networks providing internet access via satellite, terrestrial networks, cable (xDSL) networks or mobile or cellular networks (GPRS / EDGE or UMTS (Multimedia Broadcast / Multimex Multicast Service (MBMS) type, or an evolution of UMTS known as LTE (Long Term Evolution), or DVB-H (Digital Video Broadcasting-Handhelds) is applicable), or hybrid (satellite and terrestrial) networks.

[0021] FIG. 1 illustrates a block diagram of a communication network (100) in which resource elements received from an uplink transmission from user equipment are decoded by an exemplary embodiment of a decoder system (156). The network (100) includes a packet data network gateway ("P-GW") (120), two serving gateways ("S-GW") (121-122), two base stations (or cell sites) (102-104), a server (124), and the Internet (150). The P-GW (120) includes various components (140), such as a billing module (142), a subscribing module (144), and / or a tracking module (146), to facilitate routing activities between a source and a destination. It should be noted that the basic concept of the exemplary embodiment does not change even if one or more blocks (or devices) are added to or removed from the network (100).

[0022] The network (100) may operate as a 4th generation ("4G"), LTE (Long Term Evolution), 5G (Fifth Generation), NR (New Radio), or a combination of 4G and 5G cellular network configurations. In one aspect, a mobility management entity (MME) (126) is connected to a base station (or cell site) and an S-GW that can facilitate data transmission between 4G LTE and 5G. The MME (126) performs various control / management functions, network security, and resource allocation.

[0023] In one example, an S-GW (121 or 122) connected to a P-GW (120), an MME (126), and a base station (102 or 104) can route data packets from the base station (102) or eNodeB to the P-GW (120) and / or the MME (126). The function of the S-GW (121 or 122) is to perform an anchoring function for mobility between 3G and 4G equipment. The S-GW (122) can also perform various network management functions such as path termination, idle UE paging, data storage, information routing, and replica creation.

[0024] A P-GW (120) coupled to an S-GW (121-122) and the Internet (150) can provide network communication between user equipment ("UE") and an IP-based network such as the Internet (150). The P-GW (120) is used for connection, packet filtering, inspection, data usage, billing, or PCRF (policy and billing rule function) enforcement. Additionally, the P-GW (120) also provides an anchoring function for mobility between 4G and 5G packet core networks.

[0025] A base station (102 or 104), also known as a cell site, node B, or eNodeB, includes one or more wireless towers (110 or 112). The wireless towers (110 or 112) are also connected to various UEs, such as cellular phones (106), handheld devices (108), tablets and / or iPads (107), via wireless communications or channels (137-139). The devices (106-108) may be portable devices or mobile devices, such as iPhones (iPhone®), BlackBerrys (BlackBerry®), Androids (Android®), etc. The base station (102) facilitates network communication between mobile devices, such as UEs (106-107), in conjunction with the S-GW (121) via the wireless towers (110). It should be noted that the base station or cell site may include additional wireless towers as well as other ground switching circuits.

[0026] To improve the efficiency and / or processing speed of uplink control information received from user equipment in uplink transmission, a decoder system (156) is provided to decode data and UCI information received in uplink transmission. A more detailed description of the decoder system (156) is provided below.

[0027] FIG. 2 illustrates an exemplary detailed embodiment of an REI system (152). FIG. 2 illustrates a user device ("UE") (224) having an antenna (222) that allows wireless communication with a base station (112) via wireless transmission (226). The UE (224) transmits uplink communication (230) received by a base station front end (FE) (228). In one embodiment, the base station includes a gain normalizer (202), an inverse transform block (IDFT) (204), configuration parameters (222), a processing type detector (208), an RS remover (210), a layer demapper (212), a despreader (214), and an REI system (152). In one embodiment, the REI system (152) includes an RE identifier (232), a soft demapper (216), a SINR calculator (234), and a descrambling and combining system (DCS) (154). In one embodiment, the DCS (154) includes a descrambler (218) and a combiner / extractor (220). In one embodiment, combined data and UCI information output from the DCS (154) are input to a decoder system (156), and the decoder system (156) outputs decoded information. In one embodiment, a machine learning circuit (MLC) (250) is provided, wherein the machine learning circuit (MLC) (250) receives the decoded data / UCI (252) and generates a performance metric, the performance metric is used by a machine learning algorithm to determine updated soft-demapper parameters (256), which are used to perform soft-demapping to achieve selected system performance.

[0028] In one embodiment, the receiver of the uplink transmission processes one symbol at a time, which may come from multiple layers for NR, and the receiver of the uplink transmission processes an entire subframe or slot of a layer for LTE covering a 1 ms transmission time interval (TTI), a 7-OFDM symbol (OS) short(s) TTI, and a 2 / 3-OS sTTI. The modulation order can be derived as follows.

[0029] 1. (π / 2) BPSK for NR

[0030] 2. (π / 2) BPSK for LTE sub-PRB, QPSK, 16QAM, 64QAM, and 256QAM

[0031] Furthermore, demapping rules are applied to constellations as defined in LTE (4G) and / or NR (5G) standards.

[0032] Configuration Parameter (Block 222)

[0033] In one embodiment, the configuration parameter (222) includes a plurality of fields containing parameters used by the plurality of blocks shown in FIG. 2. For example, some of the configuration parameters (222) control the operation of the gain normalizer (202), IDFT (204), REI system (152), and decoder system (156). In one embodiment, the configuration parameter (222) may indicate that the gain normalizer (202) and IDFT (204) are bypassed. In one embodiment, the configuration parameter (222) is used by the soft-demapper (216) to determine when to apply special processing when soft-demapping the received resource element. The configuration parameter (222) is also used to control the operation of the descrambler (218), combiner / extractor (220), and / or SINR calculator (234).

[0034] Gain Normalizer (Block 202)

[0035] In one embodiment, the gain normalizer (202) performs a gain normalization function for the received uplink transmission. For example, the gain normalizer (202) is applicable to LTE and NR DFT-s-OFDM cases. The input samples are normalized per subcarrier per data symbol with a standard (norm) gain value calculated per symbol as follows.

[0036] Gainnorm_out [Ds][sc] =(Gainnorm_in[Ds][sc]) / (Norm_Gain[Ds])

[0037] IDFT(Block 204)

[0038] The IDFT (204) operates to provide an inverse transform to generate a time domain signal. In one embodiment, the IDFT (204) is enabled only for LTE and NR DFT-s-OFDM and LTE sub-PRB. In one embodiment, the input and output are assumed to be 16-bit I and Q values, respectively. The DFT and IDFT operations are defined as follows.

[0039]

[0040]

[0041] Here, am.

[0042] Processing type detector (block 208)

[0043] In an exemplary embodiment, the processing type detector (214) detects the type of processing to be performed by the system. For example, this information may be detected from the configuration parameters (222). In one embodiment, the processing type detector (208) operates to detect one of two processing types covering the operation of the system as follows.

[0044] 1. Type 1 - 5G NR DFT-s-OFDM

[0045] 2. Type 1 - 5G NR CP-OFDM

[0046] 3. Type 2 - 5G NR PUCCH Format 4

[0047] RS Remover (Block 210)

[0048] In one embodiment, the RS remover (210) operates during Type 1 processing to remove RS resource elements from the received data stream to generate a data stream input to a layered demapper. For example, the RE locations of the RS symbols are identified, and the data is rewritten into one or more buffers to remove the RS symbols so as to generate an output containing only data / UCI. In one embodiment, Type 1 processing includes RS / DTX removal, layered demapping using an interleaving structure, soft demapping, and descrambling. Removing the RS RE before layering has the advantage of allowing a single-shot descrambling process to be used continuously and without interruption, without additional buffering.

[0049] Layer Demapper (Block 212)

[0050] In one embodiment, data and signal-to-interference noise ratio (SINR) from multiple layers of a specific subcarrier will be transmitted to a layer demapping circuit (not shown) via a multi-threaded read DMA operation. In this case, each thread will point to memory locations of different layers for a specific symbol. The layer demapper (212) generates demapped data and multiple pSINR reports per layer. In one embodiment, for NR, DMRS / PTRS / DTX RE will be removed from the information stream before soft-demapping for both I / Q and SINR samples.

[0051] Despreader (Block 214)

[0052] In one embodiment, the displayer (214) provides display type 2 processing only for PUCCH format 4. Displaying involves combining conjugates of appropriate spreading sequences and symbols that repeat along the frequency axis when multiplying them. The spreading sequence index and spreading type for combining information in the correct way will be provided by the configuration parameter (222). This process is always performed over a total of 12 REs. The number of REs pushed into subsequent blocks will be reduced by half or 1 / 4 after displaying, depending on the spreading type. The combined result is averaged before soft demapping and stored as 16-bit information.

[0053] REI System (Block 152)

[0054] In one embodiment, the REI system (152) includes an RE identifier (232), a soft demapper (216), a descrambler (218), a combiner / extractor (220), and a SINR calculator (234). During operation, the REI system (152) classifies resource elements and transmits these classified REs to the soft demapper (216) and one or more other blocks of the REI system (152). In one embodiment, the soft demapper (216) uses the classified REs to determine when to apply special processing to the soft demapping process.

[0055] In another embodiment described in more detail below, the RE identifier (232) receives requests for hypothesis index values ​​for resource elements containing data / CSI2 information. The RE identifier (232) processes these requests to determine whether the RE contains data or CSI2 values, and whether the RE contains CSI2 values ​​by providing hypothesis index values ​​associated with the CSI2 values.

[0056] Resource element identifier (block 232)

[0057] In one embodiment, the RE identifier (232) operates to process a received information stream of resource elements to identify, index, and classify each element. The indexing and classification of each element (e.g., RE information 236) are passed to a soft demapper (216) and other blocks of the REI system (152). A more detailed description of the operation of the RE identifier (232) is provided below.

[0058] FIG. 3 is a block diagram illustrating a detailed exemplary embodiment of the RE identifier (232) illustrated in FIG. 2. As illustrated in FIG. 3, the RE identifier (232) includes an RE input interface (302), a parameter receiver (304), a classifier (306), and an RE output interface (308).

[0059] During operation, the uplink transmission is received and processed by the blocks described above to generate an information stream such as the information stream (312). For example, the received uplink transmission is processed by at least one of the processing type detector (208), the layer demapper (212), or the displayer (214). Consequently, the information stream (312) does not contain any reference signal (RS) but contains data or data multiplexed with UCI information, and this stream is input to the RE identifier (232).

[0060] In one embodiment, the information stream (312) includes information or data bits and UCI bits. In one example, UCI bits, such as ACK bits, CSI1 bits, and / or data / CSI2 bits, are distributed throughout the information stream (312). For example, UCI bits are mixed with data bits as illustrated.

[0061] In one embodiment, during 5G operation, the RE identifier (232) accurately identifies the RE indices of the UCI bits for soft demapper special processing, descrambler code modification, and UCI combination / extraction as illustrated in FIG. 2. The RE indices of the UCI bits are used for NR CP-OFDM operation as well as for generating SINR report values ​​for ACK and CSI1.

[0062] In one embodiment, the RE identification process will process two REs per cycle, denoted by 314. For example, resource elements of a received stream (312) are received by an RE input interface (302), and the RE input interface (302) provides the received information to a classifier (306). A parameter receiver (304) receives parameters (310) from a configuration parameter block (222). The classifier (306) uses these parameters to classify the received resource elements (REs), and after classifying the received REs, the classifier (306) stores the classified REs in an array such as an array (316), which indicates an index, RE value, and category. In one embodiment, the identification of RE1 can be obtained based on multiple hypotheses of RE0. Similarly, the identification of RE2 can be derived based on multiple hypotheses of RE0 and RE1. The RE output interface (308) outputs the classified REs to a soft demapper (216), a descrambler (218), a UCI combiner (220), and a SINR calculator (234). In one aspect, the soft demapper (216), the descrambler (218), the UCI combiner (220), and the SINR calculator (234) are interconnected to transmit specific information between these components.

[0063] In an exemplary embodiment, the RE identifier (232) receives a request (318) for a hypothesis index value for an RE containing data / CSI2 information. The request is received from a combiner / extractor (220). In response to the request (318), the RE identifier (232) determines whether the RE contains data or CSI2 information. If the RE contains CSI2 information, a hypothesis index value associated with the CSI2 value is determined. In one embodiment, there are up to 11 hypotheses (0-10) associated with the CSI2 information. The RE identifier (232) outputs the determined hypothesis index value (320) to the combiner / extractor for subsequent processing.

[0064] Refer again to FIG. 2. In various embodiments, a soft demapper (216) provides special processing to the RE based on a specific UCI category. A scrambler (218) may provide scrambled code modification based on a specific UCI category. A UCI combiner / extractor (220) may combine DATA, ACK, CSI1 and / or CSI2 information. A SINR calculator (234) may calculate the DATA / CSI2 SINR as well as other RE-related SINRs, such as ACK SINR and CSI SINR.

[0065] Soft-demapper

[0066] The soft demapping principle is based on calculating the log-likelihood ratio (LLR) of a bit, which quantifies the level of certainty regarding whether it is a logical 0 or 1. The soft demapper (216) processes symbol by symbol and RE by RE within a symbol.

[0067] The soft demapping principle is based on calculating the log-likelihood ratio (LLR) of a bit, which quantifies the level of certainty regarding whether it is a logic 0 or 1. Under the assumption of Gaussian noise, the LLR of the i-th bit is given as follows:

[0068] Mathematical formula 1

[0069] Here, cj and ck are constellation points where the i-th bit takes values ​​of 0 and 1, respectively. For the Gray mapping modulation scheme given in [R1], x can be considered to refer to a single-dimensional I or Q. Computational complexity increases linearly with the modulation order. To reduce computational complexity, the max-log MAP approximation was adopted. This approximation is not necessary for QPSK because the LLR in QPSK has only one term in both the numerator and the denominator.

[0070]

[0071] This approximation is sufficiently accurate, especially in high SNR regions, and simplifies LLR calculations by significantly avoiding complex exponential and logarithmic operations. Given that I and Q are the real and imaginary parts of the input samples, soft LLR is defined as follows for (π / 2) BPSK, QPSK, 16QAM, 64QAM, and 256QAM, respectively.

[0072] In one embodiment, the soft-demapper (216) includes a first minimum function component (MFC), a second MFC, a special treatment component (STC), a subtractor, and / or an LLR generator. The function of the soft-demapper (216) is to demap or verify soft bit information associated with a received symbol or bit stream. For example, the soft-demapper (216) employs a soft demaping principle, which is based on calculating the log-likelihood ratio (LLR) of a bit to quantify the level of certainty regarding whether it is a logic 0 or 1. To reduce noise and interference, the soft-demapper (216) may also discard one or more unused constellation points regarding the frequency of the bit stream from the constellation map.

[0073] In one aspect, the STC is configured to force an infinity value as one input to the first MFC when a bit stream is identified and special processing is required. For example, a predefined control signal having a specific set of encoding categories, such as an ACK having a predefined set of encoding categories, requires special processing. In one aspect, one of the special processings is to force an infinity value as an input to the MFC. For example, the STC forces an infinity value as an input to the first and second MFCs when the bit stream is identified as an ACK or CSI1 having predefined encoding categories. In one example, the STC is configured to determine whether special processing (or special processing function) is required based on the received bit stream or symbols. In one aspect, 1-bit and 2-bit control signals having the predefined encoding categories listed in Table 1 require special processing. It should be noted that Table 1 is exemplary and other configurations are possible.

[0074] number Control signal having encoding categories Renamed categories 1 O ACK = 1 ACK[1] 2 O ACK = 2 ACK[2] 3 O CSI1 = 1 CSI1[1] 4 O CSI1 = 2 CSI1[2]

[0075] SINR Calculator (Block 234)

[0076] The SINR calculator (234) calculates the SINR for each UCI type based on the categories received from the REI block (232).

[0077] Discrambler (Block 218)

[0078] The descrambler (218) is configured to generate a descrambling sequence of bits or bit streams. For example, after generating a sequence based on input values, the descrambler determines whether a descrambling sequence modification is required for specific categories of control information to be descrambled. For example, the descrambler (218) receives RE information (236) classified from the RE identifier (232) and uses this information to determine when a descrambling sequence modification is required. In one embodiment, the descrambler also provides storage of an intermediate linear feedback shift register (LFSR) state to facilitate the generation of a continuous descrambling sequence for multiple symbols. The descrambled resource element (244) of a symbol is passed to a combiner / extractor (220) along with the corresponding descrambling sequence (246). A more detailed description of the descrambler (218) is provided below.

[0079] Combiner / Extractor (Block 220)

[0080] The combiner / extractor (220) provides a combine and extract function that combines descrambled soft bits from the descrambler (218) and extracts uplink control information. In one embodiment, the combiner / extractor (220) modifies its operation based on a category received from the REI block (232). A more detailed description of the combiner / extractor (220) is provided below.

[0081] Decoder system (block 156)

[0082] The decoder system (156) decodes the raw LLR and combined data / UCI information (254) received from the combiner / extractor (220). In one embodiment, the decoder system (156) divides the combined data and CSI2 information into separate LLR streams based on configuration parameters. Then, the decoder system (156) decodes each stream individually to generate the decoded data and CSI2 (UCI) information (252). A more detailed description of the decoder system (156) is provided below.

[0083] Machine Learning Circuit (MLC) (Block 250)

[0084] In one embodiment, a machine learning circuit (250) is provided to receive decoded data / UCI information (252) and determine a performance metric. Based on the determined performance metric, the MLC (250) performs a machine learning algorithm to generate an updated soft demapper parameter (256) that is input to a configuration parameter (222). In one embodiment, the parameter (256) is input to a soft demapper (216) and used to determine a soft demapped RE (242), which is processed into raw LLR and combined data / UCI information (254) that is decoded by a decoder system (156). In one embodiment, the MLC (250) adjusts the soft demapper parameter (256) until a desired performance metric is obtained. A detailed description of the MLC (250) is provided below.

[0085] FIG. 4a illustrates a block diagram illustrating a detailed exemplary embodiment of the descrambler (218) illustrated in FIG. 2. In one embodiment, the descrambler (218) includes a descrambler processor (402), internal memory (404), linear feedback shift registers LFSR0 and LFSR1, and an output interface (406). The descrambler processor (402) also includes a sequence modifier (412) that operates to modify the descrambling sequence for ACK and CSI1 information of a specific category.

[0086] FIG. 4b illustrates a block diagram illustrating an operation performed by the descrambler (218) illustrated in FIG. 4a. During operation, the descrambler processor (402) receives a soft demapped RE (242) from a soft demapper (216). The descrambler processor (402) also receives selected configuration parameters (222), RE information (236), and initialization values ​​(416). In one embodiment, the initialization values ​​(416) are provided by a central processor or other receiver entity and stored as INIT0 (408) and INIT1 (410). The descrambler processor (402) initializes LFSR0 and LFSR1 using the initialization values ​​INIT0 (408) and INIT1 (410), respectively. The shift registers (LFSR0 and LFSR1) output bits used to determine the descramble bits, and the descramble bits are used to descramble the received RE (242). For example, the outputs of the shift registers LFSR0 and LFSR1 are mathematically combined by the descrambler processor (402) to determine the descramble bits to be used to descramble the received RE (242).

[0087] As resource elements of the first symbol are received, the descrambler processor (402) descrambles the received RE (242) using a descrambler bit determined from the output of the shift register. For example, when a resource element of symbol S0 is received, the descrambler processor (402) descrambles the received resource element using a generated descrambler bit. As each RE is descrambled (as indicated by path 418), the descrambled RE is stored in internal memory (404). After the descrambler of all REs of the symbol is completed, the descrambler processor (402) stores the state of the shift register LFSR0 / 1 in external memory (414). For example, at the end of symbol S0, the state of LFSR0 / 1 (422) is stored in external memory (414). In addition, it should be noted that the sequence modifier (412) can be used to modify the descrambling sequence for ACK and CSI1 information of a specific category.

[0088] Before the RE of the next symbol (e.g., S1) is descrambled, the LSFR state (422) is restored from external memory (414) and provided to the descrambler processor (402) as an initial value (416). Thus, the restored state allows the operation of the shift registers to continue from the position where it was interrupted after the descrambled of the previous symbol (e.g., S0) was completed. After descrambled symbol S1, the descrambler processor (402) saves the state of the shift register to external memory (414) (indicated by 424). Before the descrambled symbol S3 begins, the state (424) is restored to the LFSR register of the descrambler processor (402) as described above. This process of saving and restoring the shift register state continues until all REs of all symbols have been descrambled. It should be noted that the RE contains data or UCI information. For example, the S0 symbol contains ACK 420 information illustrated in FIG. 4b. After the REs are descrambled, they are output to the combiner / extractor (220) as descrambled REs (244) by the descrambler output interface (406). In one embodiment, the descrambled sequence (246) used to descramble the REs is also provided to the combiner / extractor (220).

[0089] FIG. 5a illustrates a block diagram illustrating a detailed exemplary embodiment of the combiner / extractor (220) illustrated in FIG. 2. In one embodiment, the combiner / extractor (220) includes a combiner / extractor processor (502) and an internal storage (504). The processor (502) includes a hypothetical processor (516). During operation, the processor (502) receives RE information (236) and a descrambled RE (244) from the descrambler (218). The processor (502) also receives the descrambling sequence (246) that was used to descramble the descrambled RE (244). The processor (502) uses the RE information (236) to determine which RE represents a UCI value. For example, since the RE information (236) includes indexed and classified RE information, the processor (502) can use this information to determine when a selected UCI RE is received.

[0090] At the beginning of the symbol, the processor (502) initializes the ACK (508), CSI1 (510), and 11 (0-10) hypothetical CSI2 (512) values ​​in memory (504). When an RE containing ACK and CSI1 information is received, the processor (502) combines this information with the current values ​​in memory. For example, the processor (502) uses REI information (236) to determine when the ACK information bits are received and combines these bits with the currently stored ACK bits (508). This process continues for ACK (508) and CSI1 (510).

[0091] When CSI2 (512) information is received, the hypothesis processor (516) operates to determine one of the hypotheses (512) to accumulate CSI2 information. A more detailed description of the operation of the hypothesis processor (516) is provided below.

[0092] When all REs of a symbol are received, the combined value is written to external memory (514). Before the next symbol begins, the value in external memory (514) is returned to and restored by the processor (502). Then, the combination of the UCI values ​​of the next symbol is performed. After the UCI information of each symbol is combined, the result is stored in external memory (514). The process continues until the UCI information from a selected number of symbols is combined. When the combination process is completed, the processor (502) outputs the combined result (506) to the decoder.

[0093] FIG. 5b illustrates a block diagram illustrating an operation performed by the combiner / extractor (220) illustrated in FIG. 5a. In one embodiment, a hypothesis processor (516) receives a descrambled RE stream (244) and a descrambled sequence (246) used to descramble the RE of the descrambled stream. The processor (516) drops or erases ACK information from the descrambled stream (416) (indicated by 518) to create a stream containing only CSI1 and data / CSI2 information. Next, the processor (516) drops CSI1 information from the stream (indicated by 520) to create a stream containing only data / CSI2 information. Then, the processor (516) performs a function (522) to identify a hypothesis associated with the data / CSI2 stream. For example, the processor (516) sends a request (318) to the RE identifier (232) to identify a hypothesis index value associated with data / CSI2 information. The RE identifier (232) returns identification information indicating whether the data / CSI2 information contains data or CSI2 information. If the information contains data, the data (524) is output for further processing. If the information contains CSI2, a hypothesis index indicating a hypothesis associated with the CSI2 information is received. The CSI2 information and the hypothesis (526) are further processed.

[0094] The hypothesis processor (516) receives the CSI2 / Hyp (526) and performs additional processing. If the hypothesis is in the range (2-10) as indicated in 530, the CSI2 information is transmitted to be accumulated in memory (504). If the hypothesis is in the range (0-1), the CSI2 value is input into the riskrambling function (532), and the riskrambling function (532) rescrambles the CSI2 information using the received descrambling sequence (246) to recover the CSI2 information (536) prior to descrambling. The descrambling sequence (246) is modified by the modification function (534) to generate a modified descrambling sequence (540). The modified descrambling sequence (540) is used by the descrambling function (542) to descramble the re-scrambed CSI2 information (536) to generate the modified descrambled CSI2 information (544). The modified CSI2 information is transferred to memory (504) for accumulation.

[0095] Combined soft output for UCI

[0096] In an exemplary embodiment, the output for UCI soft coupling can be summarized as follows.

[0097] 1-bit UCI case

[0098] A. A single soft-coupled UCI output with a 16-bit bit width

[0099] B. One soft-coupled 'x' label bit output of 16-bit bit width for ACK and 16QAM, 64QAM, and 256QAM only.

[0100] struct UCI_REPORT_1BIT {

[0101] int16_t uci_soft_combined;

[0102] int16_t uci_x_soft_combined; / / valid only for ACK and 16QAM, 64QAM, 256QAM

[0103] int16_t reserved

[30] ;

[0104] }

[0105] 2-bit UCI case

[0106] A. Three soft-coupled UCI outputs for a 2-bit UCI case with a 16-bit bit width

[0107] B. One soft-coupled 'x' label bit output of 16-bit bit width for ACK and 16QAM, 64QAM, and 256QAM only.

[0108] struct UCI_REPORT_2BIT {

[0109] int16_t uci_soft_combined[3]; / / c0, c1, c2

[0110] int16_t uci_x_soft_combined; / / valid only for ACK and 16QAM, 64QAM, 256QAM

[0111] int16_t reserved

[28] ;

[0112] }

[0113] RM encoding(3 ≤ O UCI ≤ 11) case

[0114] A. One set of 32 soft-coupled UCI outputs with a 16-bit bit width as input to the RM decoder.

[0115] struct UCI_REPORT_RM {

[0116] int16_t uci_soft_combined

[32] ;

[0117] }

[0118] CSI2 case

[0119] In an exemplary embodiment, there will be up to 11 soft-joining results corresponding to each hypothesis. The soft-joining methodology for each hypothesis is fixed and is shown in Table 2 below.

[0120] Table 2: CSI2 soft coupling per hypothesis Hypothesis # Soft bonding method Hypothesis 0 1-bit soft coupling Hypothesis 1 2-bit soft coupling Hypothesis 2 Reed Muller (RM) soft coupling

[0121] It should be noted that LLR modifications may be required for Hypothesis 0 and Hypothesis 1 due to the presence of 'x' and 'y' bits depending on the modulation type and scrambling sequence prior to the soft coupling operation. This is explained in Table 3 below.

[0122] Scrambling seq Hypo0 Hypo1 Hypo2-Hypo10 CSI2 RE llr0 1 1 1 1 llr1 -1 1* -1 -1 llr2 -1 1* 1* -1 llr3 1 1* 1* 1 Stream out along with data 1-bit combiner input 2-bit combiner input RM combiner input llr0 llr0 llr0 llr0 -llr1 llr1 -llr1 -llr1 -llr2 llr2 llr2 -llr2 llr3 llr3 llr3 llr3 * denotes x / y bit modification

[0123] Table 3: An example of CSI2 combination for multiple hypotheses

[0124] FIG. 6 illustrates an exemplary method (600) for performing resource element classification according to an exemplary embodiment of an REI system. For example, the method (600) is suitable for use with the REI system (152) illustrated in FIG. 2.

[0125] In block (602), an uplink transmission is received from a 5G communication network. For example, the uplink transmission is received at the front end (228) shown in FIG. 2.

[0126] In block (604), gain normalization is performed. For example, gain normalization is performed by the gain normalizer (202) shown in FIG. 2.

[0127] In block (606), an inverse Fourier transform is performed to obtain a time domain signal. For example, this process is performed by the IDFT block (204) shown in FIG. 2.

[0128] In block (608), a determination is made regarding the type of processing to be performed. For example, descriptions of two types of processing are provided above. If the first type of processing is performed, the method proceeds to block (610). If the second type of processing is performed, the method proceeds to block (624). For example, this operation is performed by the processing type detector (208) illustrated in FIG. 2.

[0129] In block (624), when the processing type is Type 2, despreading (or despreading) is performed on the received resource element. For example, this operation is performed by the despreader (despreader) (214) shown in FIG. 2. The method then proceeds to block (614).

[0130] If the processing type is type 1, the following action is performed.

[0131] In block (610), reference signals are removed from the received resource elements. For example, resource elements containing RS / DTX are removed. This operation is performed by the RS remover (210) shown in FIG. 2.

[0132] In block (612), hierarchical demapping is performed. For example, resource elements without RS / DTX are hierarchically demapped. This operation is performed by the hierarchical demapper (212).

[0133] In block (614), RE identification and classification are performed. For example, as illustrated in FIG. 3, the RE identifier (232) receives an RE stream, classifies the RE, and then outputs an array (316), in which the RE is indexed and includes classification values.

[0134] In block (616), soft demapping is performed. For example, the soft demapper (216) soft demaps the REs with special processing provided based on the classification of the received REs. The soft demapper (216) generates a soft demapped output, and this output is input to the descrambler (218).

[0135] In block (618), descrambling is performed. For example, the descrambler (218) receives soft demapped bits from the soft demapper (216) and generates descrambled bits. In one embodiment, a descrambler code modified based on the classification of REs is used. In one embodiment, the descrambler (218) operates to store LFSR states between symbols, so that successive descrambling code generation can be provided from symbol to symbol.

[0136] In block (620), the combination and extraction of UCI information are performed. For example, a combiner / extractor (220) receives descrambled bits, combines these bits, and extracts UCI information. For example, the combiner / extractor (220) identifies UCI resource elements using RE classification information and combines these elements into memory (504). The combined UCI values ​​are output at the end of the symbol, and memory is re-initialized for the combination of the UCI of the next symbol.

[0137] In block (622), SINR calculation is performed to calculate the data / CSI2, ACK and CSI1 SINR values.

[0138] Accordingly, the method (600) operates to provide resource element identification and classification according to exemplary embodiments. It should be noted that the operation of the method (600) may be modified, added, deleted, rearranged, or otherwise changed within the scope of the embodiments.

[0139] FIG. 7 illustrates an exemplary method (700) for performing descramming according to an exemplary embodiment of a descramming and coupling system. For example, the method (700) is suitable for use with the DCS (154) illustrated in FIG. 2.

[0140] In block (702), configuration parameters and initialization values ​​are received by the descrambler (218). For example, configuration parameters (222) are received by the descrambler processor (402). Also, initialization values ​​(416) are received by the descrambler processor (402). In one embodiment, the initialization value (416) is received from the central processing entity of the receiver. In another embodiment, the initialization value (416) is LFSR status information received from external memory (414).

[0141] In block (704), one or more linear feedback shift registers are initialized. For example, the processor (402) initializes registers LFSR0 and LFSR1, respectively, with initialization values ​​INIT0 (408) and INIT1 (410).

[0142] In block (706), a resource element of a symbol is received. For example, the processor (402) receives a resource element of symbol S0 as shown in FIG. 4b.

[0143] In block (708), a descrambled code is generated. For example, the processor (402) generates a descrambled code based on the outputs of shift registers LFSR0 and LFSR1.

[0144] In block (710), RE information is accessed by a processor to determine information about the current resource element. For example, the processor (402) accesses information about the current resource element based on RE information (236) and parameters (222).

[0145] In block (712), a decision is made as to whether scrambling code modification is required. For example, the processor (402) determines whether scrambling code modification is required to scramble the current resource element based on RE information (236) and parameters (222). If scrambling code modification is required, the method proceeds to block (714). If modification is not required, the method proceeds to block (716).

[0146] In block (714), the scrambling code is modified by the processor (402) as needed. For example, the sequence modifier (412) modifies the scrambling code for a specific type of ACK and CSI1 information.

[0147] In block (716), RE is descrambled using scrambling code. For example, the processor (402) descrambles RE using the current scrambling code.

[0148] In block (718), a decision is made as to whether there are more REs to descramble in the current symbol. For example, the processor (402) makes this decision based on configuration parameters (222) and / or RE information (236). If there are no more symbols to descramble, the method proceeds to block (720). If there are more symbols to descramble in the current symbol, the method proceeds to block (706).

[0149] In block (720), a decision is made as to whether there are more symbols to descramble. For example, the processor (402) makes this decision based on the configuration parameters (222) and / or RE information (236). If there are no more symbols to descramble, the method terminates. If there are more symbols to descramble, the method proceeds to block (722).

[0150] In block (722), the LFSR state is stored. For example, the processor (402) pushes the current state of registers LFSR0 and LFSR1 to external memory (414), as indicated by, for example, 422.

[0151] In block (724), the LFSR state is restored before descramble the next symbol. For example, the LFSR state stored from memory (414) is provided to the processor (402) as a new set of initialization values ​​(416), which is used to restore the state of registers LFSR0 and LFSR1. Thus, the LFSR generates a descramble sequence based on the restored state. Then, the method proceeds to block (706), where descramble is continued until a desired number of symbols are descrambled.

[0152] Accordingly, the method (700) operates to provide descramming according to an exemplary embodiment of a descramming and combining system. It should be noted that the operation of the method (700) may be modified, added, deleted, rearranged, or otherwise changed within the scope of the embodiment.

[0153] FIG. 8 illustrates an exemplary method (800) for performing a combination according to an exemplary embodiment of a scrambling and combination system. For example, the method (800) is suitable for use with the DCS (154) shown in FIG. 2.

[0154] In block (802), the values ​​of ACK, CSI1, and CSI2 in memory are initialized. For example, in one embodiment, the processor (502) initializes the values ​​of ACK (508), CSI1 (510), and CSI2 (512) in memory (504).

[0155] In block (804), the descrammed RE of the symbol is received. For example, the processor (502) receives the descrammed RE (244).

[0156] In block (806), RE classification information is received. For example, the processor (502) receives RE information (236).

[0157] In block (808), a decision is made as to whether the current RE contains an ACK value. The processor (502) makes this decision from the RE information (236). If the current RE contains an ACK value, the method proceeds to block (810). If the current RE does not contain an ACK value, the method proceeds to block (812).

[0158] In block (810), the ACK value contained in the current RE is combined with the ACK value in memory. For example, the processor (502) combines the current RE value with the stored ACK value (508) and restores the combined value back to memory (504).

[0159] In block (812), a determination is made as to whether the current RE contains the CSI1 value. The processor (502) makes this determination from the RE information (236). If the current RE contains the CSI1 value, the method proceeds to block (814). If the current RE does not contain the CSI1 value, the method proceeds to block (816).

[0160] In block (814), the CSI1 value currently contained in RE is combined with the CSI1 value in memory. For example, the processor (502) combines the current RE value with the stored CSI1 value (510) and restores the combined value back to memory (504).

[0161] In block (816), a determination is made as to whether the current RE contains a CSI2 value. The processor (502) makes this determination from the RE information (236). If the current RE contains a CSI2 value, the method proceeds to block (818). If the current RE does not contain a CSI2 value, the method proceeds to block (820).

[0162] In block (818), the CSI2 value contained in the current RE is combined with the CSI2 value in memory. For example, the processor (502) combines the current RE value with one of the stored hypothetical CSI2 values ​​(512) and restores the combined value back to memory (504). A detailed description of the combination of CSI2 values ​​is provided in relation to FIGS. 9a and 9b.

[0163] In block (820), a decision is made as to whether there are more REs to combine in the current symbol. The processor (502) makes this decision based on the RE information (236). If there are more REs to combine, the method proceeds to block (804). If there are no more REs to combine, the method proceeds to block (822).

[0164] In block (822), the accumulated UCI values ​​are pushed to external memory. For example, the accumulated UCI values ​​are pushed to external memory (514).

[0165] In block (824), a decision is made as to whether there are more symbols to combine. In one embodiment, the processor (502) makes this decision from the REI information (236). If there are no more symbols to combine, the method terminates. If there are more symbols to combine, the method proceeds to block (826).

[0166] In block (826), UCI values ​​stored in external memory are obtained and input to the processor (502) as new initialization values. For example, accumulated UCI values ​​stored in external memory (514) are obtained by the processor (502). Then, the method proceeds to block (802), where the UCI values ​​obtained from external memory are used to initialize the UCI values ​​(508, 510 and 512) of the internal storage (504).

[0167] Accordingly, the method (800) operates to provide a combination according to an exemplary embodiment of a scrambling and combining system. It should be noted that the operation of the method (800) may be modified, added, deleted, rearranged, or otherwise changed within the scope of the embodiment.

[0168] FIGS. 9a-b illustrates an exemplary method (900) for performing a combination according to an exemplary embodiment of a scrambling and combination system. For example, the method (900) is suitable for use with the DCS (154) shown in FIG. 2.

[0169] Now, referring to FIG. 9a, in block (902), initialization is performed on the ACK, CSI1, and 11 hypothetical CSI2 values ​​stored in memory. For example, in one embodiment, the processor (502) initializes the ACK (508), CSI1 (510), and 11 hypothetical CSI2 values ​​(512) in memory (504). In one embodiment, the values ​​used to initialize memory (504) are received from external memory (indicated by D).

[0170] In block (904), the descrammed RE of the symbol is received. For example, the processor (502) receives the descrammed RE (244).

[0171] In block (906), a descrambled sequence is received. For example, the processor (502) receives a descrambled sequence (246).

[0172] In block (908), RE classification information is received. For example, the processor (502) receives RE information (236).

[0173] In block (910), a determination is made as to whether the RE is an ACK value. If the received RE is an ACK value, the method proceeds to block (912). If the received RE is not an ACK value, the method proceeds to block (914).

[0174] In block (912), ACK processing is performed as described in other parts of this document. Then the method proceeds to block (938) (indicated by B).

[0175] In block (914), a decision is made as to whether the RE is a CSI1 value. If the received RE is a CSI1 value, the method proceeds to block (916). If the received RE is not a CSI1 value, the method proceeds to block (918).

[0176] In block (916), CSI1 processing is performed as described in other parts of this document. The method then proceeds to block (938) (indicated by B).

[0177] In block (918), the RE includes data / CSI2, and thus a request for a hypothesis value for the RE is generated. For example, the processor (516) outputs the request (318) to the RE identifier (232) to obtain a hypothesis index value for the data / CSI2 information. In one embodiment, the response (320) generated by the RE identifier (232) indicates that the data / CSI2 information is data. In one embodiment, the response (320) generated by the RE identifier (232) indicates that the data / CSI2 information is CSI2 information associated with a selected hypothesis value (e.g., x).

[0178] In block (920), a determination is made as to whether the data / CSI2 information is data. If the response from the RE identifier (232) indicates that the data / CSI2 information is data, the method proceeds to block (922). Otherwise, the method proceeds to block (924).

[0179] In block (922), the data is processed as described in other parts of this document. The method then proceeds to block (938) (indicated by B).

[0180] In block (924), a decision is made as to whether the hypothesis index associated with the CSI2 information is within the range (2-10). If the hypothesis index is within the range (2-10), the method proceeds to block (926). Otherwise, the method proceeds to block (928) (indicated by A).

[0181] In block (926), as described in other parts of this document, CSI2 information is accumulated in memory (504) along with appropriate CSI2 information based on hypothesis values. The method then proceeds to block (936) (indicated by B).

[0182] Now, referring to FIG. 9b, in block (928), the current CSI2 information is identified as being associated with hypothesis 0 or 1.

[0183] In block (930), the CSI2 RE is re-scrambed using the received descrambling sequence. For example, the processor (516) re-scrambs the received scrambling CSI2 RE (528) using the received descrambling sequence (246) to produce a re-scrambed CSI2 RE (536).

[0184] In block (932), the descramming sequence (246) is modified to generate a modified descramming sequence. The processor (516) performs a modification function (534) to modify the received descramming sequence (246) to generate a modified descramming sequence (540).

[0185] In block (934), the rescrammed RE is descrammed into a modified descramming sequence to produce a modified descrammed RE. For example, the processor (516) performs a descramming function (542) to descrammed the rescrammed CSI2 RE (536) to produce a modified descrammed CSI2 RE (544).

[0186] In block (936), the modified descrambled CSI2 RE (544) is accumulated in memory (504) along with the appropriate hypothesis value.

[0187] In block (938), a decision is made as to whether there are more REs to combine with the current symbol. The processor (502) makes this decision based on the RE information (236). If there are more REs to combine, the method proceeds to block (904) (indicated by C). If there are no more REs to combine, the method proceeds to block (940).

[0188] In block (940), UCI values ​​accumulated in memory (504) are stored in external memory (514).

[0189] In block (942), a determination is made as to whether there are more symbols with UCI information to be combined. If there are more symbols with UCI information to be combined (e.g., in a slot or subframe), the method proceeds to block (902) (indicated by D). In this path, information stored in external memory (514) is used to initialize the value stored in memory (504) before combining information from additional symbols. If there are no more symbols to be combined, the method terminates.

[0190] Accordingly, the method (900) operates to provide a combination according to an exemplary embodiment of a scrambling and combining system. It should be noted that the operation of the method (900) may be modified, added, deleted, rearranged, or otherwise changed within the scope of the embodiment.

[0191] FIG. 10a illustrates an exemplary block diagram of a decoder system (156). In one embodiment, the decoder system (156) includes an LLR preprocessor (1002A-B), a data decoder (1004), and a CSI2 decoder (1006). In one embodiment, FIG. 10a also illustrates a memory (1008). In one embodiment, the memory (1008) receives combined data and UCI information (506) from a combiner / extractor processor (502) illustrated in FIG. 5. For example, the memory (1008) receives combined hypothetical CSI2 values ​​(1010) and outputs these values ​​to the decoder system (156) as an LLR stream (1012).

[0192] In 5G or NR, data and UCI LLRs are multiplexed in both time and frequency. The UCI consists of CSI1 / CSI2 and ACK fields. In one embodiment, the CSI1 and ACK LLRs may be separated and / or removed from the LLR stream. However, the CSI2 LLR cannot be separated before generating the composite output LLR stream (1012) provided as input to the decoder system (156). To extract the necessary LLRs from this composite stream, LLR preprocessors (1002A-B) perform this operation. For example, in some cases, the preprocessor (1002A) extracts the data LLR from the stream (1012) and drops the remaining LLR to form the data LLR stream. In other cases, the preprocessor (1002B) extracts the CSI2 LLR and drops the remaining LLR to form the CSI2 LLR stream.

[0193] In one embodiment, a data decoder (1004) decodes a data LLR stream to produce decoded data. A CSI2 decoder (1006) decodes a CSI2 LLR stream to produce decoded CSI2 information. In another embodiment, a Reed Muller (RM), 1-bit or 2-bit encoded CSI2 LLR (indicated by 1016) is provided directly to the CSI2 decoder (1006).

[0194] FIG. 10b is an exemplary detailed diagram illustrating an example of an LLR stream (1012) input to a decoder system (156) according to an embodiment of the present invention. The LLR stream (1012) includes an LLR for CSI2, an LLR for data, and a padding LLR, which are identified by their respective shading in FIG. 10b. In one embodiment, an LLR preprocessor (1002A-B) performs an algorithm to remove the padding LLR to generate a second stream (1014) containing the LLR for data and CSI2. For example, after the padding LLR is dropped by the preprocessor (1002A-B), the remaining LLR stream follows a pattern as illustrated in stream (1014).

[0195] In one embodiment, up to three CSI2 LLR bursts and up to two data LLR bursts may alternate in each half slot. Each burst of data LLR corresponds to a set of data LLRs within a DMRS symbol. In the case of frequency hopping, since there may be up to two DMRS symbols in each half slot, two bursts of data LLR are possible. Each burst of CSI2 LLR corresponds to a consecutive group of CSI2 LLRs that are not interrupted by data LLRs.

[0196] The burst sizes of the CSI2 LLR are represented by px_a0, px_a1, and px_a2. The burst sizes of the data LLR are represented by px_b0 and p1_b1, respectively. Following these CSI2 and data bursts, there may be periodically alternating CSI2 and data LLRs that repeat "a_k" times. Each period begins with CSI2 of length "px_a_r" LLR and is followed by data of length "px_a_d - px_a_r" LLR. Following this periodic pattern, the remainder will be data LLRs until 'num_rd_dma_word_px' ends. Overall, these bursts are repeated twice. For example, px becomes p0 for Part 0 and p1 for Part 1.

[0197] Configuration

[0198] In one embodiment, for the operation of the LLR preprocessor (1002A-B) to separate data and CSI2 LLR, the following configuration parameters (222) shown in Table 4 below are used. These parameters will be present in the AB_CFG section of the LDPC decoder (LDEC) and polar decoder (PDEC) blocks of the configuration parameters (222). It is not necessary for all of these parameters to be represented as 64-bit words or consecutive words of the same number.

[0199] Table 4: Configuration Parameters Parameter Width Description 1 preproc_mode 1 '0': Pass CSI2 LLRs and drop rest'1': Pass data LLRs and drop rest 2 preproc_p0_csi2_len0 19 CSI2 part 0 - burst 0 size. Range : [0:422399] 3 preproc_p0_csi2_len1 19 CSI2 part 0 - burst 1 size. Range : [0:422399] 4 preproc_p0_csi2_len2 19 CSI2 part 0 - burst 2 size. Range : [0:422399] 5 preproc_p1_csi2_len0 19 CSI2 part 1 - burst 0 size. Range : [0:422399] 6 preproc_p1_csi2_len1 19 CSI2 part 1 - burst 1 size. Range : [0:422399] 7 preproc_p1_csi2_len2 19 CSI2 part 1 - burst 2 size. Range : [0:422399] 8 preproc_p0_data_len0 17 Data part 0 - burst 0 size. Range : [0:105599] 9 preproc_p0_data_len1 17 Data part 0 - burst 1 size. Range : [0:105599] 10 preproc_p1_data_len0 17 Data part 0 - burst 0 size. Range : [0:105599] 11 preproc_p1_data_len1 17 Data part 0 - burst 1 size. Range : [0:105599] 12 preproc_p0_csi2_repeat_period 16 Periodicity of Repeated CSI2 LLRs followed by part 0 (3 bursts of CSI2 and 2 bursts of data) LLRs. Represents number of LLRs of each period. Range : [0:52800] 13 preproc_p1_csi2_repeat_period 16 Periodicity of Repeated CSI2 LLRs followed by part 1 (3 bursts of CSI2 and 2 bursts of data) LLRs. Represents number of LLRs of each period. Range : [0:52800] 14 preproc_csi2_repeat_burst_size 6 Burst size of CSI2 LLRs in each repeat of both part 0 and part 1. Range : {1,2,3,4,6,8,10,12,16,18,20,24,30,32,40} 15 preproc_p0_num_repeat 11 Number of periodic repetitions in part 0. Range: [0:2047] 16 preproc_p1_num_repeat 11 Number of periodic repetitions in part 1. Range: [0:2047] 17 num_rd_dma_words_p0 32 Number of read DMA words for part 0 18 num_rd_dma_words_p1 32 Number of read DMA words for part 1 19 tb_tx_bit_size 24 Number of LLRs to be sent to the decoder core

[0201] LLR preprocessor operation

[0202] In an exemplary embodiment, the following pseudo-code describes the operation of an LLR preprocessor (1002A-B) of a decoding system for separating data and CSI2 LLR to a suitable decoder. For example, the pseudo-code below utilizes the configuration parameters shown in Table 4 to remove padding (e.g., "tagged") LLR and separate data and CSI2 LLR from an input stream to produce a data and CSI2 stream to be passed to a suitable decoder.

[0203] If (preproc_mode == 0)

[0204] target = 'csi2'

[0205] else

[0206] target = 'data'

[0207] end

[0208] csi2_count = 'preproc_p0_csi2_len0'

[0209] data_count = 'preproc_P0_data_len0'

[0210] Step 0:

[0211] Drop all tagged LLRs.

[0212] Step 1: part 0 starts

[0213] Read 'csi2_count' csi2 LLRs.

[0214] If target == 'csi2'

[0215] pass LLRs to CSI2 decoder

[0216] else

[0217] drop them (remove from stream)

[0218] end

[0219] Step 2:

[0220] Read 'data_count' data LLRs.

[0221] If target == 'csi2'

[0222] drop them

[0223] else

[0224] pass remaining to data decoder

[0225] end

[0226] Step 3:

[0227] Repeat steps 1 and 2 one more time with csi2_count = 'preproc_p0_csi2_len1' and data count = 'preproc_p0_data_len1'

[0228] Step 4:

[0229] Read 'preproc_p0_csi2_len2' csi2 LLRs.

[0230] If target == 'csi2'

[0231] pass them to CSI2 decoder

[0232] else

[0233] drop them

[0234] end

[0235] Step 5:

[0236] Read 'preproc_csi2_repeat_burst_size' CSI2 LLRS

[0237] If target == 'csi2'

[0238] pass them to CSI2 decoder

[0239] else

[0240] drop them

[0241] end

[0242] Step 6:

[0243] Read 'preproc_p0_csi2_repeat_period - preproc_p0_csi2_repeat _burst_size' data LLRS

[0244] If target == 'csi2'

[0245] drop them

[0246] else

[0247] pass them to data decoder

[0248] end

[0249] Step 7:

[0250] Repeat steps 5 and 6 'preproc_p0_num_repeat' times

[0251] Step 8: part 0 ends

[0252] Continue reading rest of data LLRs till 'num_rd_dma_words_p0' are read

[0253] If target == 'csi2'

[0254] drop them

[0255] else if (num_rd_data_llrs < 'tb_tx_bit_size')

[0256] / / Number of data LLRs read so far pass them to decoder

[0257] else

[0258] drop them.

[0259] Step 9: Part 1 starts

[0260] Repeats Step 1 to Step 7 by replacing all 'p0' with 'p1'.

[0261] Step 10: part 1 ends

[0262] Continue reading rest of data LLRs till 'num_rd_dma_words_p0 + num_rd_dma_words_p1' are read

[0263] If target == 'csi2'

[0264] drop them

[0265] else

[0266] if (num_rd_data_llrs < 'tb_tx_bit_size')

[0267] / / Number of data LLRs read so far pass them to decoder

[0268] else

[0269] drop them.

[0270] FIG. 11 illustrates an exemplary method (1100) for performing decoding according to an exemplary embodiment of a decoder system. For example, the method (1100) is suitable for use with the decoder system (156) illustrated in FIG. 2.

[0271] In block (1102), a stream of data, CSI2, and padding LLRs is received. For example, in one embodiment, the stream (1012) is received from memory (1008) by a decoder (156). In one embodiment, two LLR preprocessors (1002A-B) receive the stream.

[0272] In block (1104), configuration parameters are received. In one embodiment, configuration parameters (222) are received by the preprocessor (1002A-B).

[0273] In block (1106), padding LLRs are removed from the stream. For example, the preprocessor (1002A-B) removes padding ("tagged") LLRs from the stream they receive.

[0274] In block (1108), data and CSI2 LLR are separated. For example, preprocessors (1102A-B) separate data and CSI2 LLR based on received configuration parameters. For example, each LLR preprocessor (1102A-B) performs the aforementioned algorithm to separate data or CSI2 LLR from the stream they receive.

[0275] In block (1110), the data LLR is decoded. For example, a data decoder (1004) receives and decodes the data LLR.

[0276] In block (1112), the CSI2 LLR is decoded. For example, a CSI2 decoder (1006) receives and decodes the CSI2 LLR.

[0277] Accordingly, the method (1100) operates to provide decoding according to exemplary embodiments. It should be noted that the operation of the method (1100) may be modified, added, deleted, rearranged, or otherwise changed within the scope of the embodiments.

[0278] LLR Optimization Using Machine Learning

[0279] In 5G systems, the quality and range of LLRs generated by an LLR generator are important for achieving optimal physical layer performance. In various embodiments, a machine learning circuit operates to provide parameters to the soft demapping process of the LLR generator to achieve a selected performance objective. In an iterative process, the machine learning algorithm adjusts the soft demapping parameters based on measured performance metrics to shift system performance to a selected target performance until the target performance is achieved. The machine learning circuit includes a parameter table that stores the soft demapping parameters generated after each iteration. The table also provides a repository for soft demapping parameters generated for each of a plurality of decoders operating in a multimodulation coding scheme.

[0280] FIG. 12 illustrates an exemplary embodiment of a part of the scrambling and combining system illustrated in FIG. 2. As illustrated in FIG. 12, the REI system (152) generates raw LLR (254) and includes a soft demapper (216). The REI system (152) receives input from the hierarchical demapper (212) or the displayer (214) and generates raw LLR and combined data / UCI information (254). The REI system (152) receives configuration parameters (222), which are used to control the operation of various function blocks of the REI system (152), including the soft demapper (216).

[0281] In one embodiment, the configuration parameter (222) includes a soft demapping parameter (256) that is passed to the soft demapping agent (216) and used to control the soft demapping process. A more detailed description of the soft demapping parameter (256) is provided below.

[0282] In a 5G system, LLR generated by an LLR generator is fed to one or more decoders. For example, in one embodiment, the decoder (156) includes a turbo decoder (TDEC) block, an LDPC decoder (LDEC) block, and an X decoder (XDEC) block. Any of the decoder blocks may be used to generate the decoded data / UCI output (252). The internal fixed-point implementations of all these decoders may differ for various reasons. To ensure the best possible performance from each of these decoders, the configuration parameters (222) of the LLR generator are carefully selected.

[0283] In one embodiment, the machine learning circuit (250) receives the decoded data / UCI output (252) and determines a performance metric representing the system performance. In one embodiment, the MLC (250) performs a machine learning algorithm to generate updated soft-demapping parameters (256) to be used to adjust the operation of the soft demapper (216) to shift the measured performance to a desired target performance. In one embodiment, the MLC (250) performs a machine learning algorithm based on a reinforcement learning process to generate updated parameters (256) to achieve the desired target performance.

[0284] FIG. 13 illustrates an exemplary detailed embodiment of the machine learning circuit (250) illustrated in FIG. 12. The machine learning circuit (250) includes a processor (1302), a memory (1304), and a performance metric circuit (1306), all of which are combined to communicate via a bus (1312). The memory (1304) includes performance target(s) (1308) and a parameter table (1310).

[0285] Machine Learning Approach

[0286] Machine learning approaches are traditionally divided into broad categories regarding the nature of the "signals" or "feedback" available in the learning system. In an exemplary embodiment, a machine learning algorithm (1314) performs reinforcement learning to interact with a dynamic environment that must perform a specific goal (such as adjusting soft demapper parameters to meet a performance goal). As the algorithm explores the performance space, the algorithm receives feedback (e.g., performance metrics), which is used to adjust the soft demapper parameters (256) to shift the performance metrics toward the performance goal (1308).

[0287] Various types of models have been used and studied to implement machine learning systems. In one embodiment, the machine learning algorithm (1314) is implemented by an artificial neural network that interconnects groups of nodes similar to the vast neural network of the brain. For example, a processor (1302) executes the algorithm (1314) that implements the neural network to perform the operation described herein.

[0288] During operation, the performance measurement circuit (1306) receives the decoded data / UCI (252) and determines one or more performance metrics. For example, the performance metric may include a block error rate (BLER) or other appropriate performance metrics. For example, the performance metric may be the minimum SINR required to achieve a specific BLER that can be defined by the user, such as a BLER of 10%. The processor (1302) executes a machine learning algorithm (1314) that adjusts the parameters of the parameter table (1310) so that the subsequent performance metric moves toward the performance target (1308) until the performance target is reached. Thus, the machine learning algorithm (1314) dynamically adjusts the parameters for the soft demapper (216) to adjust the performance of the system toward the performance target (1308) without manual intervention. In one embodiment, the target performance is a specific performance level or represents a performance range.

[0289] FIG. 14 illustrates an exemplary embodiment of the parameter table (1310) illustrated in FIG. 13. In one embodiment, the parameter table (1310) includes a column for decoder types (1402). Each decoder type (1402) includes parameters for a plurality of modulation coding scheme (MCS) values ​​(1404). The parameters include a modulation (MOD) scale value (1406), a first right shift (RSFT1) value (1408), a second right shift (RSFT1) value (1410), an LLR offset value (1412), and an LLR bit-width value (1414). Based on the decoder types (1402) and MCS values ​​(1404), the machine learning algorithm (1314) adjusts the soft demapper parameters (256) to shift the performance metric to a target performance (1308). For example, the performance metric may be the minimum SINR required to achieve a specific BLER that can be defined by the user, such as 10% BLER. In one embodiment, the parameters of the parameter table (1310) may be initialized to any desired initial value.

[0290] FIG. 15 illustrates an exemplary embodiment of a soft demapper circuit (1500) for use in an embodiment of the present invention. For example, the soft demapper circuit (1500) is suitable for use as at least part of a soft demapper (216). In one embodiment, the soft demapper circuit (1500) includes a minimization (MIN) detector (1502 and 1504), a rounding circuit (1506 and 1508), an LLR offset circuit (1510), and a saturation (SAT) circuit (1512). The circuit (1500) also includes a multiplier (1514, 1516, 1518), an adder (1520), and a subtractor (1522).

[0291] During operation, the received I / Q bits are input to the multiplier (1514). The multiplier (1514) also receives selected constants (e.g., 1, 3, 5, 7, 9, 13, and 15), and the multiplied result is a 20-bit value input to the adder (1520). The adder (1520) also receives a constant (MX_CONSTY) which is an unsigned 18-bit value. The adder (1520) outputs the sum of its inputs as a 21-bit value, which is input to both the minimization circuits (1502 and 1504). Each minimization circuit outputs the minimum value of its inputs. The minimization control circuit (1524) outputs control values ​​to each minimization circuit (1502 and 1504). The control values ​​control which value is output from each minimization circuit. For example, a minimum value is selected for a specific modulation format. The output of the minimization circuit is input to a subtractor (1522), which subtracts the values ​​and generates a 22-bit output that is input to a multiplier (1516). In one embodiment, equation (EQ. 1) is implemented.

[0292] The second multiplier (1518) receives a SINR signal, which is an unsigned 24-bit value, and a modulation scale value, which is an unsigned 16-bit value. The product of these signals is input to a rounding circuit (1508), and the rounding circuit (1508) shifts and rounds the input values ​​based on a first shift value (RSFT1). For example, to generate the RS1 value, the following operation is performed.

[0293] [Input + (2^(RSFT1-1))] >> 2^RSFT1 = 40-bit RS1 value; or

[0294] [Input + (2^(RSFT1-1))] / 2^RSFT1 = 40-bit RS1 value

[0295] The RS1 value is input to a multiplier (1516), which multiplies the inputs to generate a 62-bit value, which is input to a second rounding circuit (1506). The rounding circuit (1506) shifts and rounds the input value based on the second shift value (RSFT2) (1506). For example, to generate the RS2 value, the following operations are performed.

[0296] [Input +(2 ^(RSFT2-1))] / 2 ^ RSFT2 = 40-bit RS2 value

[0297] The LLR offset circuit (1510) receives an RS2 value and an LLR offset value, which is an unsigned (k-1) bit value, and performs an offset operation. The output of the offset circuit (1510) is input to the saturation circuit (1512). The saturation circuit (1512) receives an LLR_bit_width value and determines soft-demapped REs (242) by scaling the input to prevent saturation, which are processed into raw LLR and combined data / UCI information (254) that is decoded by the decoder system (156).

[0298] LLR_bit_width optimization

[0299] Depending on internal implementation details, decoders may behave differently with different LLR bit widths. In the first operation, the optimal bit width at which the selected decoder achieves hard decoding performance is determined. In one embodiment, the following operations are performed by the processor (1302) to determine the optimal LLR bit width to be used during the decoding process.

[0300] 1. Maximize all multipliers and minimize all dividers that saturate LLR. For example, the processor (1302) outputs parameters that saturate LLR (242).

[0301] 2. Adjust the LLR_bit_width value (1414) for a specific decoder / MCS to achieve optimal performance. For example, the processor (1302) adjusts the LLR_bit_width parameter to achieve optimal LLR performance. The LLR_bit_width value is stored in the parameter table (1310).

[0302] Optimization of parameters based on machine learning

[0303] Once the LLR_bit_width parameter is determined, the machine learning algorithm (1314) operates to adjust the remaining soft-demapping parameters to achieve the target performance. In one embodiment, the following operations are performed by the machine learning circuit (250) to adjust the soft-demapping parameters.

[0304] 1. The performance metric is determined by the performance metric circuit (1306).

[0305] 2. Target performance (1308) is obtained from memory (1304).

[0306] 3. The machine learning algorithm (1314) uses the current performance metric and the target performance to adjust the MOD_SCALE (1406), RSF1 (1408), RSFT2 (1410), and LLR_OFFSET (1412) parameters for a specific decoder / MCS to shift the performance metric to the target performance. It should be noted that, as a result of the above operations, each decoder will have a unique set of configuration parameters to achieve the associated target performance. For example, the LLR bit-width parameter (1414) is determined for a specific decoder / MCS. Other parameters are set as initial conditions. The machine learning algorithm (1314) adjusts the MOD_SCALE (1406), RSF1 (1408), RSFT2 (1410), and LLR_OFFSET (1412) parameters for a specific decoder / MCS using the current performance metric and target performance, and moves the performance metric toward the target performance in an iteration process until the target performance is achieved. After each iteration, the updated parameters are stored in the parameter table (1310).

[0307] FIG. 16 illustrates exemplary graphs illustrating the operation of a system for adjusting LLR generation based on SINR received for difference modulation schemes. Graph (1602) shows a plot of the mean of the absolute values ​​of LLR values ​​relative to the signal-to-interference noise ratio (SINR) (e.g., mean(abs(LLR))). Graph (1604) shows a plot of the variance of the absolute values ​​of LLR values ​​relative to the SINR (e.g., var(abs(LLR))). For example, the plots represent LLR ranges generated by the LLR generator for specific fixed configurations for different SINR values. In one embodiment, the LLR_bit_width parameter controls the upper and lower saturation limits of the LLR, while the shift values ​​(RSFT1 and RSFT2) shift the curves along the SINR axis to determine where saturation occurs. For each decoder type, these curves are carefully formed for optimal performance. Because the internal implementations differ, each decoder provided by the LLR generator requires a different set of soft demapping configuration parameters. These optimal configuration parameters for each decoder will be generated by a machine learning algorithm (1314) with minimal or no external intervention. The machine learning algorithm (1314) receives feedback from the decoder in the form of performance metrics to derive an optimization process for achieving target performance.

[0308] FIG. 17 illustrates an exemplary method (1700) that utilizes machine learning to optimize performance according to an exemplary embodiment of a decoder system. For example, the method (1700) is suitable for use with part of the descrambling and combining system illustrated in FIG. 12.

[0309] In block (1702), a stream of data, CSI2, and padding LLRs is received.

[0310] In block (1704), soft demapping is performed using soft demapping parameters as part of LLR processing to generate raw LLR.

[0311] In block (1706), the raw LLR is decoded by a selected decoder.

[0312] In block (1708), performance metrics and target performance are determined. For example, performance metrics are determined by a performance metric circuit (1306) and target performance (1308) is stored in memory (1304).

[0313] In block (1710), a decision is made as to whether the performance metric meets the target performance. If the performance metric meets the performance target, the method ends. If the performance metric does not meet the performance target, the method proceeds to block (1712).

[0314] In block (1712), a machine learning algorithm is performed to adjust soft-demapping parameters to move performance metrics toward performance goals. For example, a machine learning algorithm (1314) is performed.

[0315] In block (1714), the parameter table is updated with the updated soft demapping parameters. For example, the parameter table (1310) is updated with the newly determined soft demapper parameters. Then, the method proceeds to block (1702) to receive and process more of the received stream.

[0316] Accordingly, the method (1700) operates to utilize machine learning to optimize performance according to an exemplary embodiment of the decoder system. It should be noted that the operation of the method (1700) may be modified, added, deleted, combined, rearranged, or otherwise changed within the scope of the embodiment.

[0317] FIG. 18 illustrates an exemplary method (1800) for performing a machine learning algorithm according to an exemplary embodiment of a machine learning circuit. For example, the method (1800) is suitable for use in block (1712) of FIG. 17. In one embodiment, the method (1800) is performed by the machine learning circuit (250) illustrated in FIG. 13.

[0318] In block (1802), a determination is made as to whether this is the first pass through the machine learning process for the selected decoder and MCS. If it is the first pass, the method proceeds to block (1804). If it is not the first pass, the method proceeds to block (1808).

[0319] In block (1804), parameter values ​​are adjusted to obtain LLR saturation for the selected decoder / MCS. For example, to make the LLR saturated for the selected decoder / MCS, parameters are set such that all multipliers in the demapping circuit (1500) are maximized and all dividers are minimized.

[0320] In block (1806), an LLR_bit_width value is determined for the selected decoder / MCS based on the LLR saturation level. A bit width value is selected to avoid saturation.

[0321] In block (1808), the target performance for the selected decoder / MCS is obtained from memory (1304). For example, the target performance (1308) is obtained from memory (1304).

[0322] In block (1810), a performance metric for the selected decoder / MCS is obtained. For example, the performance metric circuit (1306) determines the performance metric for the selected decoder / MCS by analyzing the decoded data (252). In one embodiment, the performance metric is a BLER value.

[0323] In block (1812), a machine learning algorithm is performed to adjust soft-demapping parameters to move performance metrics toward target performance. In one embodiment, the MLC (250) performs a machine learning algorithm (1314) based on a reinforcement learning process to generate updated parameters (256) to achieve the desired target performance. The determined soft-demapper parameters are passed to block (1714), which is stored in the parameter table (1310).

[0324] Accordingly, the method (1800) operates to perform a machine learning algorithm to optimize performance according to an exemplary embodiment of the decoder system. It should be noted that the operation of the method (1800) may be modified, added, deleted, combined, rearranged, or otherwise changed within the scope of the embodiment.

[0325] FIG. 19 shows a block diagram illustrating a processing system (1900) having an exemplary embodiment of a decoder system (1930) comprising a machine learning circuit that adjusts soft-demapping parameters to obtain a performance target for a selected decoder. For example, in one embodiment, the decoder system (1930) includes the machine learning circuit (250) illustrated in FIG. 2. It will be obvious to those skilled in the art that other alternative computer system architectures may also be used.

[0326] The system (1900) includes a processing unit (1901), an interface bus (1912), and an input / output ("IO") unit (1920). The processing unit (1901) includes a processor (1902), main memory (1904), a system bus (1911), a static memory device (1906), a bus control unit (1909), a mass storage memory (1908), and a decoder system (1930). The bus (1911) is used to transfer information between the various components and the processor (1902) for data processing. The processor (1902) is a various general-purpose processor, embedded processor, or ARM® embedded processor, Intel® Core. TM 2 Duo, Core TM 2 Quad, Xeon®, Pentium TM Microprocessors, AMD® family processors, MIPS® embedded processors, or Power PCs TM It could be one of the microprocessors, such as a microprocessor.

[0327] Main memory (1904), which may include multiple levels of cache memory, stores frequently used data and instructions. Main memory (1904) may be RAM (Random Access Memory), MRAM (Magnetic RAM), or flash memory. Static memory (1906) may be ROM (Read-Only Memory) connected to the bus (1911) to store static information and / or instructions. A bus control unit (1909) is connected to the bus (1911-1912) and controls which components, such as the main memory (1904) or the processor (1902), can use the bus. Mass storage memory (1908) may be a magnetic disk, solid-state drive (SSD), optical disk, hard disk drive, floppy disk, CD-ROM, and / or flash memory for storing large amounts of data.

[0328] In one example, the I / O unit (1920) includes a display (1921), a keyboard (1922), a cursor control device (1923), and a communication device (1929). The display device (1921) may be a liquid crystal device, a flat panel monitor, a cathode ray tube (CRT), a touch screen display, or other suitable display device. The display (1921) projects or displays a graphic image or window. The keyboard (1922) may be a conventional alphanumeric input device for communicating information between the computer system (1900) and the computer operator. Other types of user input devices are cursor control devices (1923), such as a mouse, a touch mouse, a trackball, or other types of cursors for communicating information between the system (1900) and the user.

[0329] A communication device (1929) is connected to a bus (1912) to access information from a remote computer or server via a wide area network. The communication device (1929) may include a modem, a router, or a network interface device, or other similar devices that facilitate communication between a computer (1900) and a network. In one aspect, the communication device (1929) is configured to perform wireless functions. Alternatively, the decoder system (1930) and the communication device (1929) perform resource element classification, descrambling and combining, decoding, and machine learning optimization functions according to an embodiment of the present invention.

[0330] In one aspect, the decoder system (1930) is connected to the bus (1911) and is configured to perform decoding, machine learning, and optimization functions on the received uplink communication as described above to improve overall receiver performance. In one embodiment, the decoder system (1930) includes hardware, firmware, or a combination of hardware and firmware.

[0331] In one embodiment, an apparatus is provided that includes means for soft-demapping resource elements based on soft-demapping parameters as part of a process for generating a log-likeness ratio (LLR) value, which includes a soft-demapper (216) in one embodiment. The apparatus also includes means for decoding the LLR to generate decoded data, which includes a decoder system (156) in one embodiment. The apparatus also includes means for identifying a target performance value, means for determining a performance metric from the decoded data, and means for performing a machine learning algorithm that dynamically adjusts the soft-demapping parameters to move the performance metric toward the target performance value, which includes a machine learning circuit (250) in one embodiment.

[0332] Although specific embodiments of the present invention have been illustrated and described, it will be apparent to those skilled in the art that, based on the teachings of this specification, changes and modifications may be made without departing from the exemplary embodiments of the present invention. Accordingly, the appended claims are intended to include within their scope all changes and modifications that fall within the true spirit and scope of these exemplary embodiments of the present invention.

Claims

Claim 1 A method comprising: soft-demapping resource elements based on soft-demapping parameters as part of a process for generating log-likelihood ratio (LLR) values; decoding the LLR to generate decoded data; identifying a target performance value; determining a performance metric from the decoded data; and performing a machine learning algorithm that dynamically adjusts the soft-demapping parameters to shift the performance metric to the target performance value, wherein the soft-demapping parameters include a modulation scale value, a first shift value, a second shift value, or an LLR offset value. Claim 2 A method according to claim 1, characterized in that the resource elements are derived from symbols received in a new radio (NR) uplink transmission. Claim 3 A method according to claim 1, further comprising the step of outputting decoded data. Claim 4 A method according to claim 1, wherein the soft demapping parameters further include LLR bit-width values. Claim 5 A method according to claim 4, wherein the step of performing the machine learning algorithm includes the step of adjusting soft demapping parameters to determine the LLR saturation level. Claim 6 A method according to claim 5, wherein the adjusting step comprises a step of using an LLR saturation level to determine a selected LLR bit-width value. Claim 7 A method according to claim 6, wherein the step of performing the machine learning algorithm comprises the step of performing the machine learning algorithm to update soft demapping parameters based on a selected LLR bit-width value. Claim 8 A method according to claim 7, wherein the step of performing the machine learning algorithm comprises the step of performing the machine learning algorithm in an iterative process to update soft-demapping parameters until a performance metric satisfies the target performance. Claim 9 An apparatus comprising: a soft-demapper configured to soft-demapper resource elements based on soft-demapper parameters as part of a process for generating log-likeness ratio (LLR) values; a decoder configured to decode data from the LLR; and a machine learning circuit, wherein the machine learning circuit is configured to identify a target performance value and determine a performance metric from the decoded data; and to perform a machine learning algorithm that dynamically adjusts the soft-demapper parameters to shift the performance metric to the target performance value, wherein the soft-demapper parameters include a modulation scale value, a first shift value, a second shift value, or an LLR offset value. Claim 10 A device according to claim 9, characterized in that the resource element is derived from symbols received in a new radio (NR) uplink transmission. Claim 11 A device according to claim 9, wherein the decoder outputs decoded data input to a machine learning circuit. Claim 12 A device according to claim 9, characterized in that the soft demapping parameters further include LLR bit-width values. Claim 13 In claim 12, the device is characterized in that the machine learning circuit adjusts soft demapping parameters to determine the LLR saturation level. Claim 14 A device according to claim 13, wherein the machine learning circuit uses an LLR saturation level to determine a selected LLR bit-width value. Claim 15 A device according to claim 14, wherein the machine learning circuit performs a machine learning algorithm to update soft demapping parameters based on a selected LLR bit-width value. Claim 16 A device according to claim 15, wherein the machine learning algorithm performs an iterative process to update soft demapping parameters until a performance metric meets the target performance. Claim 17 An apparatus comprising: means for soft-demapping resource elements based on soft-demapping parameters as part of a process for generating log-likeness ratio (LLR) values; means for decoding LLR to generate decoded data; means for identifying a target performance value; means for determining a performance metric from the decoded data; and means for performing a machine learning algorithm for dynamically adjusting soft-demapping parameters to shift the performance metric to a target performance value, wherein the soft-demapping parameters include a modulation scale value, a first shift value, a second shift value, or an LLR offset value. Claim 18 A device according to claim 17, characterized in that the soft demapping parameters further include LLR bit-width values. Claim 19 In claim 18, the means for performing the machine learning algorithm is characterized by updating soft demapping parameters based on a selected LLR bit-width value. Claim 20 In claim 19, the means for performing the machine learning algorithm is characterized by performing an iterative process of updating soft demapping parameters until a performance metric satisfies the target performance.

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