Method and Apparatus for Controlling Single-Source Dual Inverter

Abstract

A control method and apparatus for a single-power dual inverter are disclosed. A control method for a single-power dual inverter including a first inverter and a second inverter according to one embodiment comprises: a step of determining two reference pulses and four non-reference pulses among six PWM pulses; a step of determining a first offset duty ratio and a second offset duty ratio for clamping two legs among six legs corresponding to the six PWM pulses; a step of applying the first offset duty ratio to each of the two reference pulses and applying the second offset duty ratio to each of the four non-reference pulses; and a step of synchronizing the edges of the four non-reference pulses to which the second offset duty ratio is applied based on the rising edge and falling edge of the two reference pulses to which the first offset duty ratio is applied.

Description

Technology Field

[0001] It relates to the technology for controlling single-power dual inverters. Background Technology

[0002] Recently, as the demand for high-efficiency, high-output power conversion devices has increased in electric vehicles, uninterruptible power supplies (UPS), and industrial drive systems, dual inverter structures that drive a single motor or load using multiple inverters are being widely adopted.

[0003] Among these, the Single-Source Dual Inverter is a structure in which two inverters share a single DC link power source to drive an Open-End Winding PMSM or a three-phase load, and since it does not require a separate isolated power supply, it is possible to achieve miniaturization and high efficiency.

[0004] However, in the case of a single-power dual inverter, the two inverters share the same DC link power, so a zero-sequence voltage (ZSV) is generated due to the difference in common-mode voltage of each inverter, which induces a zero-sequence current (ZSC) to circulate through the motor windings.

[0005] Such zero-sequence currents cause increased power loss, torque ripple, and electromagnetic noise, and lead to a decrease in efficiency, especially in high-speed operation regions.

[0006] Pulse-Shifting PWM (PSPWM) has been proposed as a technique to suppress this; however, while conventional PSPWM is effective in suppressing zero-sequence current, it has the problem of significantly increased switching losses because all switching elements continuously perform switching operations.

[0007] Therefore, a new single-supply dual inverter control technology is required that can suppress zero-sequence current while simultaneously reducing switching losses. The problem to be solved

[0008] The purpose is to provide a control method and apparatus for a single-power dual inverter capable of suppressing zero-sequence current while simultaneously reducing switching losses. means of solving the problem

[0009] A control method for a single-power dual inverter including a first inverter and a second inverter according to one aspect comprises: a step of determining two reference pulses and four non-reference pulses among six PWM pulses; a step of determining a first offset duty ratio and a second offset duty ratio for clamping two legs among six legs corresponding to the six PWM pulses; a step of applying the first offset duty ratio to each of the two reference pulses and applying the second offset duty ratio to each of the four non-reference pulses; and a step of synchronizing the edges of the four non-reference pulses to which the second offset duty ratio is applied based on the rising edge and falling edge of the two reference pulses to which the first offset duty ratio is applied.

[0010] The step of determining the two reference pulses and four non-reference pulses above may determine the PWM pulse with the longest duty cycle and the PWM pulse with the shortest duty cycle among the six PWM pulses as reference pulses, and determine the remaining four PWM pulses as non-reference pulses.

[0011] The step of determining the first offset duty ratio and the second offset duty ratio above can be determined using the following mathematical formula 1.

[0012] [Mathematical Formula 1]

[0013]

[0014] (d offset,SP and d offset,NSPare the first offset duty ratio and the second offset duty ratio, respectively, and d max1 and d max2 are the maximum duty ratios of the first inverter and the second inverter, respectively, and d min1 and d min2 is the minimum duty ratio of the first inverter and the second inverter, respectively, and PRD is a variable that defines the clamping state of the upper switch or the lower switch within the fundamental period.

[0015] The above PRD can alternate between 0 and 1 for every fundamental period.

[0016] The step of synchronizing the edges of the four non-reference pulses to which the second offset duty ratio is applied comprises synchronizing one of the two non-reference pulses of the first inverter to which the second offset duty ratio is applied to the rising edge of the reference pulse of the second inverter to which the first offset duty ratio is applied, synchronizing the other of the two non-reference pulses of the first inverter to which the second offset duty ratio is applied to the falling edge of the reference pulse of the second inverter to which the first offset duty ratio is applied, synchronizing one of the two non-reference pulses of the second inverter to which the second offset duty ratio is applied to the rising edge of the reference pulse of the first inverter to which the first offset duty ratio is applied, and synchronizing the other of the two non-reference pulses of the second inverter to which the second offset duty ratio is applied to the falling edge of the reference pulse of the first inverter to which the first offset duty ratio is applied, provided that the synchronization process of the non-reference pulse having a duty ratio of 0 or 1 among the four non-reference pulses to which the second offset duty ratio is applied may be omitted.

[0017] The step of synchronizing the edges of four non-reference pulses to which the second offset duty ratio is applied may include the step of determining the synchronization duty ratio of each rising edge interval and falling edge interval for each of the reference pulse and the non-reference pulse.

[0018] The step of determining the synchronization duty ratio above can determine the synchronization duty ratio of the rising edge section and the falling edge section by using the following Equation 2 for rising edge synchronization and the following Equation 3 for falling edge synchronization for the non-reference pulse.

[0019] [Mathematical Formula 2]

[0020]

[0021] [Mathematical Formula 3]

[0022]

[0023] (x is an index representing phases a, b, and c, y is an index representing the first inverter and the second inverter, and d xy,Shift,rising and d xy,Shift,falling are the synchronization duty ratios for the rising edge and falling edge periods of the x-phase PWM pulse of the y-inverter, respectively, and d SP,y is the first offset duty ratio (d) of another inverter that is the synchronization target of the non-reference pulse of the y inverter. offset,SP It is the duty ratio of the reference pulse to which ) is applied, and d xy,offset is the second offset duty ratio (d) of the y inverter offset,NSP )This is the duty cycle of the applied x-phase PWM pulse)

[0024] The step of determining the synchronization duty ratio above may determine, for the reference pulse, the duty ratio of the rising edge section and the falling edge section of the reference pulse to which the first offset duty ratio is applied as the synchronization duty ratio of the rising edge section and the falling edge section of the reference pulse.

[0025] The above control method may further include the step of selectively applying a compensation duty to the unclamped leg for each phase to eliminate the third back EMF component.

[0026] The step of applying the compensation duty ratio above involves determining which case corresponds to each phase among a plurality of cases, and selectively applying the compensation duty ratio to the unclamped leg according to the corresponding case for each phase.

[0027] The plurality of cases above includes Case 1, Case 2, Case 3, and Case 4, wherein Case 1 is defined as a case where the corresponding phase of the first inverter is clamped as a result of applying the first offset duty ratio and the second offset duty ratio, Case 2 is defined as a case where the corresponding phase of the first inverter is not clamped as a result of applying the first offset duty ratio and the second offset duty ratio, but the corresponding phase of the second inverter is clamped, Case 3 is defined as a case where neither the corresponding phase of the first inverter nor the second inverter is clamped as a result of applying the first offset duty ratio and the second offset duty ratio, but the rising edge section of the corresponding phase of the first inverter is clamped as a result of edge synchronization, and Case 4 may be defined as a case other than Case 1, Case 2, and Case 3.

[0028] The step of applying the compensation duty ratio may include a step of determining the final duty ratio of each leg to which the compensation duty ratio is selectively applied, using the following mathematical formula 4 for case 1, the following mathematical formula 5 for case 2, the following mathematical formula 6 for case 3, and the following mathematical formula 7 for case 4 for each phase.

[0029] [Mathematical Formula 4]

[0030]

[0031] [Mathematical Formula 5]

[0032]

[0033] [Mathematical Formula 6]

[0034]

[0035] [Mathematical Formula 7]

[0036]

[0037] (d x1,fin,rising and d x1,fin,falling are the final duty ratios of the rising edge and falling edge sections of the x-phase of the first inverter, respectively, and d x2,fin,rising and d x2,fin, falling are the final duty ratios of the rising edge and falling edge sections of the x-phase of the second inverter, respectively, and d x1,Shift,rising and d x1,Shift,falling are the synchronization duty ratios of the rising edge and falling edge sections of the x-phase of the first inverter, respectively, and d x2,Shift,rising and d x2,Shift,falling are the synchronization duty ratios for the rising edge and falling edge periods of the x phase of the second inverter, respectively, and d0 is the compensation duty ratio.

[0038] A control device for a single-power dual inverter including a first inverter and a second inverter according to a different aspect includes: a reference pulse determination unit that determines two reference pulses and four non-reference pulses among six PWM pulses; an offset determination unit that determines a first offset duty ratio and a second offset duty ratio for clamping two legs among six legs corresponding to the six PWM pulses, applies the first offset duty ratio to each of the two reference pulses, and applies the second offset duty ratio to each of the four non-reference pulses; and an edge synchronization unit that synchronizes the edges of the four non-reference pulses to which the second offset duty ratio is applied based on the rising edge and falling edge of the two reference pulses to which the first offset duty ratio is applied.

[0039] The reference pulse determination unit above can determine the PWM pulse with the longest duty cycle and the PWM pulse with the shortest duty cycle among the six PWM pulses as reference pulses, and determine the remaining four PWM pulses as non-reference pulses.

[0040] The above offset determination unit can determine the first offset duty ratio and the second offset duty ratio using the following mathematical formula 1.

[0041] [Mathematical Formula 1]

[0042]

[0043] (d offset,SP and d offset,NSP are the first offset duty ratio and the second offset duty ratio, respectively, and d max1 and d max2 are the maximum duty ratios of the first inverter and the second inverter, respectively, and d min1 and d min2 is the minimum duty ratio of the first inverter and the second inverter, respectively, and PRD is a variable that defines the clamping state of the upper switch or the lower switch within the fundamental period.

[0044] The above PRD can alternate between 0 and 1 for every fundamental period.

[0045] The edge synchronization unit synchronizes one of the two non-reference pulses of the first inverter to which the second offset duty ratio is applied with the rising edge of the reference pulse of the second inverter to which the first offset duty ratio is applied, synchronizes the other of the two non-reference pulses of the first inverter to which the second offset duty ratio is applied with the falling edge of the reference pulse of the second inverter to which the first offset duty ratio is applied, synchronizes one of the two non-reference pulses of the second inverter to which the second offset duty ratio is applied with the rising edge of the reference pulse of the first inverter to which the first offset duty ratio is applied, and synchronizes the other of the two non-reference pulses of the second inverter to which the second offset duty ratio is applied with the falling edge of the reference pulse of the first inverter to which the first offset duty ratio is applied, provided that the synchronization process of the non-reference pulse having a duty ratio of 0 or 1 among the four non-reference pulses to which the second offset duty ratio is applied may be omitted.

[0046] The above edge synchronization unit can determine the synchronization duty ratio of each rising edge section and falling edge section for each of the reference pulse and non-reference pulse.

[0047] The above edge synchronization unit can determine the synchronization duty ratio of the rising edge section and the falling edge section for the above non-reference pulse by using the following Equation 2 for rising edge synchronization and the following Equation 3 for falling edge synchronization.

[0048] [Mathematical Formula 2]

[0049]

[0050] [Mathematical Formula 3]

[0051]

[0052] (x is an index representing phases a, b, and c, y is an index representing the first inverter and the second inverter, and d xy,Shift,rising and d xy,Shift,falling are the synchronization duty ratios for the rising edge and falling edge periods of the x-phase PWM pulse of the y-inverter, respectively, and d SP,y is the first offset duty ratio (d) of another inverter that is the synchronization target of the non-reference pulse of the y inverter. offset,SP It is the duty ratio of the reference pulse to which ) is applied, and d xy,offset is the second offset duty ratio (d) of the y inverter offset,NSP )This is the duty cycle of the applied x-phase PWM pulse)

[0053] The edge synchronization unit above can determine, for the reference pulse, the duty ratio of the rising edge section and the falling edge section of the reference pulse to which the first offset duty ratio is applied as the synchronization duty ratio of the rising edge section and the falling edge section of the reference pulse.

[0054] The control device may further include a third back EMF compensation unit that selectively applies a compensation duty to the unclamped leg for each phase to eliminate the third back EMF component.

[0055] The above third back EMF compensation unit determines which case corresponds to each phase among a plurality of cases, and can selectively apply a compensation duty ratio to the unclamped leg according to the case for each phase.

[0056] The plurality of cases above includes Case 1, Case 2, Case 3, and Case 4, wherein Case 1 is defined as a case where the corresponding phase of the first inverter is clamped as a result of applying the first offset duty ratio and the second offset duty ratio, Case 2 is defined as a case where the corresponding phase of the first inverter is not clamped as a result of applying the first offset duty ratio and the second offset duty ratio, but the corresponding phase of the second inverter is clamped, Case 3 is defined as a case where neither the corresponding phase of the first inverter nor the second inverter is clamped as a result of applying the first offset duty ratio and the second offset duty ratio, but the rising edge section of the corresponding phase of the first inverter is clamped as a result of edge synchronization, and Case 4 may be defined as a case other than Case 1, Case 2, and Case 3.

[0057] The above third back EMF compensation unit can determine the final duty ratio of each leg to which the compensation duty ratio is selectively applied by using the following mathematical formula 4 for case 1, the following mathematical formula 5 for case 2, the following mathematical formula 6 for case 3, and the following mathematical formula 7 for case 4 for each phase.

[0058] [Mathematical Formula 4]

[0059]

[0060] [Mathematical Formula 5]

[0061]

[0062] [Mathematical Formula 6]

[0063]

[0064] [Mathematical Formula 7]

[0065]

[0066] (d x1,fin,rising and d x1,fin,falling are the final duty ratios of the rising edge and falling edge sections of the x-phase of the first inverter, respectively, and d x2,fin,rising and d x2,fin, falling are the final duty ratios of the rising edge and falling edge sections of the x-phase of the second inverter, respectively, and d x1,Shift,rising and d x1,Shift,falling are the synchronization duty ratios of the rising edge and falling edge sections of the x-phase of the first inverter, respectively, and d x2,Shift,rising and d x2,Shift,falling are the synchronization duty ratios for the rising edge and falling edge periods of the x phase of the second inverter, respectively, and d0 is the compensation duty ratio. Effects of the invention

[0067] According to an exemplary embodiment, by clamping two of the six legs and synchronizing the edge of a non-reference pulse with respect to the edge of a reference pulse, the zero-sequence voltage can be eliminated to suppress the generation of zero-sequence current and at the same time reduce switching losses.

[0068] In addition, the upper switch and the lower switch are alternately clamped during every fundamental cycle, so that power loss between the switches can be evenly distributed.

[0069] In addition, by compensating for the generation of zero-sequence current due to the third back EMF, stable current balance and torque ripple reduction effects can be achieved even in high-speed operation regions. Brief explanation of the drawing

[0070] FIG. 1 is a drawing illustrating a single-power dual inverter according to an exemplary embodiment. FIG. 2 is an example diagram illustrating the voltage command of the first inverter, the voltage command of the second inverter, and the total voltage command in a 180° PWM method. Figure 3 is an example diagram illustrating the PWM pulse generated in the 180° PWM method, the common mode voltage of each inverter, and the difference between the common mode voltages. FIG. 4 is a drawing illustrating a control device of a single-power dual inverter according to an exemplary embodiment. Figure 5 is a diagram illustrating the sector, the first fundamental period, and the second fundamental period. Figure 6 is an example diagram illustrating the implementation of rising edge synchronization. Figure 7 is an example diagram illustrating the implementation of falling edge synchronization. FIGS. 8 to 10 are exemplary diagrams for explaining 2-leg clamping and edge synchronization in the first fundamental period (PRD=0). FIGS. 11 to 13 are exemplary diagrams for explaining 2-leg clamping and edge synchronization in the second fundamental period (PRD=1). FIG. 14 is a diagram illustrating a control method of a single-power dual inverter according to an exemplary embodiment. FIG. 15 is a block diagram illustrating a computing environment including a computing device according to one embodiment. Specific details for implementing the invention

[0071] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the attached drawings. It should be noted that in assigning reference numerals to the components of each drawing, the same components are given the same reference numeral whenever possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known functions or configurations could unnecessarily obscure the essence of the present disclosure, such detailed description will be omitted.

[0072] The terms described below are defined in consideration of their functions in this disclosure and may vary depending on the intentions or practices of the user or operator. Therefore, their definitions should be based on the content throughout this specification.

[0073] Terms such as "first," "second," etc., may be used to describe various components, but components should not be limited by these terms. Terms are used solely for the purpose of distinguishing one component from another. A singular expression includes a plural expression unless the context clearly indicates otherwise, and terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0074] Furthermore, the classification of components in this specification is merely based on the primary function each component is responsible for. That is, two or more components may be combined into a single component, or a single component may be divided into two or more components based on more subdivided functions. Additionally, each component may perform some or all of the functions responsible for other components in addition to its primary function, and some of the primary functions responsible for each component may be exclusively performed by other components. Each component may be implemented in hardware or software, or as a combination of hardware and software.

[0075] FIG. 1 is a diagram illustrating a single-power dual inverter according to an exemplary embodiment, FIG. 2 is an exemplary diagram illustrating the voltage command of the first inverter, the voltage command of the second inverter, and the total voltage command in a 180° PWM method, and FIG. 3 is an exemplary diagram illustrating the PWM pulse generated in a 180° PWM method, the common mode voltage of each inverter, and the difference between the common mode voltages.

[0076] Referring to FIG. 1, a single-power dual inverter (100) according to an exemplary embodiment may include a first inverter (110a), a second inverter (110b), and a control unit (120).

[0077] The first inverter (110a) and the second inverter (110b) are connected to a single DC link power source (101), and a DC voltage (U) is obtained from the DC link power source (101). dc Can be supplied with ).

[0078] The first inverter (110a) and the second inverter (110b) are respectively connected to one end and the opposite end of the motor (102) (e.g., an open-end winding permanent magnet synchronous motor (OEW-PMSM)) to apply AC voltage to the motor (102).

[0079] The first inverter (110a) and the second inverter (110b) may each be three-phase inverters comprising six switches (111). For example, the first inverter (110a) may have three upper switches (S a1p , S b1p , S c1p ) and 3 bottom switches (S a1n , S b1n , S c1n It includes ), and the second inverter (110b) has three upper switches (S a2p , S b2p , S c2p ) and 3 bottom switches (S a2n , S b2n , S c2nIt may include ). Each top switch (e.g., S a1p ) and each top switch (e.g., S a1p The bottom switch corresponding to ) (e.g., S a1n ) can form a single leg. The first inverter (110a) and the second inverter (110b) may each include three legs (a-phase leg, b-phase leg and c-phase leg).

[0080] The control unit (120) can control the overall operation of the single-power dual inverter (100). The control unit (120) can generate a Pulse Width Modulation (PWM) signal to control each switch (111) of the first inverter (110a) and the second inverter (110b). According to one embodiment, the control unit (120) can control the first inverter (110a) and the second inverter (110b) using a 180° PWM method.

[0081] The control unit (120) generates an overall voltage command based on the voltage command of each inverter (110a, 110b), which can be expressed as Equation 1. At this time, the overall voltage command can be defined as a fundamental wave (sine wave).

[0082]

[0083] Here, x is an index representing the phase (phase a, phase b, phase c), and u x * is the total voltage command for the x-phase, and u x1 * and u x2 * Each may be an x-phase voltage command of the first inverter (110a) and the second inverter (110b).

[0084] By having the first inverter (110a) and the second inverter (110b) share the same DC link power supply (101), a zero-sequence current (ZSC) path (103) can be formed in the single-power dual inverter (100). Specifically, a zero-sequence voltage (ZSV) is induced by the difference between the common mode voltage of the first inverter (110a) and the common mode voltage of the second inverter (110b) that occurs during the switching operation of the first inverter (110a) and the second inverter (110b), and a zero-sequence current can flow along the path (103) by this zero-sequence voltage. At this time, the zero-sequence current does not contribute to the generation of motor torque of the motor (102), but can cause an increase in Total Harmonic Distortion (THD) and torque ripple.

[0085] The zero-sequence voltage can be composed of the common-mode voltage generated in a PWM manner at each inverter (110a, 110b) and the third back EMF of the motor (102). This can be expressed mathematically as Equation 2.

[0086]

[0087] Here u ZSV is the zero-sequence voltage, and u cmv1 and u cmv2 is the common mode voltage of the first inverter (110a) and the second inverter (110b), respectively, and E 3rd It can be a third-order back electromotive force.

[0088] The common mode voltage of each inverter (110a, 110b) can be expressed by Equation 3.

[0089]

[0090] Here, y is an index representing the inverter (first inverter and second inverter), and u cmvy is the common mode voltage of the y inverter, and u ay , u by and u cyEach of these can be the a-phase, b-phase, and c-phase voltage commands of the y inverter.

[0091] In the case of the 180° PWM method, there is a phase difference of 180° between the common-phase voltage commands of each inverter. For example, as shown in FIG. 2, the x-phase voltage command (U) of the first inverter (110a) x1 * ) and the x-phase voltage command (U) of the second inverter (110b) x2 * A phase difference of 180° can occur between ).

[0092] x-phase voltage command (U) of the first inverter (110a) in the 180° PWM method x1 * ) and the x-phase voltage command (U) of the second inverter (110b) x2 * ) is expressed by mathematical formula 4, and the duty ratio characteristic based on each voltage command relationship can be expressed by mathematical formula 5.

[0093]

[0094]

[0095] Here, x is an index representing the phase (phase a, phase b, phase c), y is an index representing the inverter (first inverter and second inverter), and d ay , d by and d cy are the duty ratios of phases a, b, and c of the y-th inverter, respectively, and d x1 and d x2 are the x-phase duty ratios of the first inverter and the second inverter, respectively, and d xy is the x-phase duty ratio of the y-inverter, and u xy * is the x-phase voltage command of the y-inverter, and U dc It can be a DC voltage.

[0096] In the case of the 180° PWM method, as shown in FIG. 3, the common mode voltage (u) of the first inverter (110a) cmv1The common mode voltage (u) of the ) and the second inverter (110b) cmv2 ) difference(u cmv1 - u cmv2 Since the instantaneous output level of ) is not 0, the switching period (T s A zero-sequence voltage may occur within ). In Fig. 3, S a1 , S b1 , S c1 , S a2 , S b2 , S c2 are respectively d a1 , d b1 , d c1 , d a2 , d b2 , d c2 It can be a PWM pulse corresponding to.

[0097] FIG. 4 is a diagram illustrating a control device of a single-power dual inverter according to an exemplary embodiment, FIG. 5 is a diagram for explaining sectors, a first fundamental period and a second fundamental period, FIG. 6 is an exemplary diagram for explaining the implementation of rising edge synchronization, and FIG. 7 is an exemplary diagram for explaining the implementation of falling edge synchronization.

[0098] The control device (400) of Fig. 4 may be a component of the control unit (120) of Fig. 1.

[0099] Referring to FIGS. 1 and FIGS. 4, a control device (400) according to an exemplary embodiment may include a reference pulse determination unit (410), an offset determination unit (420), and an edge synchronization unit (430).

[0100] The reference pulse determination unit (410) can determine two reference PWM pulses (hereinafter, reference pulses) and four non-reference PWM pulses (hereinafter, non-reference pulses) among six PWM pulses of the single-power dual inverter (100).

[0101] According to one embodiment, a single-power dual inverter (100) can generate three PWM pulses (a-phase PWM pulse, b-phase PWM pulse, and c-phase PWM pulse) of the first inverter (110a) and three PWM pulses (a-phase PWM pulse, b-phase PWM pulse, and c-phase PWM pulse) of the second inverter (110b) based on three phases (a-phase, b-phase, and c-phase). The reference pulse determination unit (410) can determine that among these six PWM pulses, the PWM pulse with the longest duty cycle and the PWM pulse with the shortest duty cycle within one switching cycle are reference pulses, and the remaining four PWM pulses are non-reference pulses. According to Equation 5, since the sum of the phase duty cycles of the first inverter (110a) and the second inverter (110b) is 1, two reference pulses may exist in the phase of each inverter.

[0102] The offset determination unit (420) determines a first offset duty ratio and a second offset duty ratio for clamping two legs among six legs corresponding to six PWM pulses, applies the first offset duty ratio to two reference pulses, and applies the second offset duty ratio to four non-reference pulses.

[0103] According to an exemplary embodiment, the offset determination unit (420) can determine a first offset duty ratio for clamping one of two legs corresponding to two reference pulses and a second offset duty ratio for clamping one of four legs corresponding to four non-reference pulses. For example, the offset determination unit (420) can determine the first offset duty ratio and the second offset duty ratio using Equation 6.

[0104]

[0105] Here, d offset,SP is the first offset duty cycle, and d offset,NSP is the second offset duty cycle, and d max1 and d max2 are the maximum duty ratios of the first inverter and the second inverter, respectively, and d min1and d min2 can be the minimum duty ratio of the first inverter and the second inverter, respectively. Additionally, PRD is a variable that defines the clamping state of the upper switch or the lower switch within the fundamental period. When PRD is 0, the upper switch is clamped during the first fundamental period, and when PRD is 1, the lower switch is clamped during the second fundamental period. Since PRD alternates between 0 and 1 for every fundamental period, and the upper switch is clamped during the first fundamental period (PRD=0) and the lower switch is clamped during the second fundamental period (PRD=1), power loss between the switches can be evenly distributed.

[0106] Referring to Fig. 5, the three-phase total voltage command (u a * , u b * , u c * ) is defined as the fundamental wave (sine wave), and based on the polarity and magnitude relationship of the total three-phase voltage command, one cycle of the fundamental wave can be divided into 12 sectors (sectors 1 to 12). As previously mentioned, since the two reference pulses exist in phase of each inverter, one of the three phases in each sector can be designated as the reference pulse, and the remaining two phases can be designated as non-reference pulses. According to Figure 5 and Equation 6, the relationship of the three-phase offset duty ratio according to each sector can be shown in Table 1.

[0107] sector 12, 1, 6, 7 4, 5, 10, 11 2, 3, 8, 9 d offset,a d offset,SP d offset,NSP d offset,NSP d offset,b d offset,NSP d offset,SP d offset,NSP d offset,c d offset,NSP d offset,NSP d offset,SP

[0108] As shown in Table 1, in sectors 12, 1, 6, and 7, phase a is designated as the reference pulse, and the first offset duty (d offset,SP ) is applied, and phases b and c are designated as non-reference pulses, and the second offset duty (d offset,NSP ) can be applied. In sectors 4, 5, 10, and 11, phase b is designated as the reference pulse, and the first offset duty (d offset,SP ) is applied, and phases a and c are designated as non-reference pulses, and the second offset duty (doffset,NSP ) can be applied. In sectors 2, 3, 8, and 9, phase c is designated as the reference pulse, and the first offset duty (d offset,SP ) is applied, and phases a and b are designated as non-reference pulses, and the second offset duty (d offset,NSP ) can be applied.

[0109] When the offset determination unit (420) determines the first offset duty ratio and the second offset duty ratio, it can apply the first offset duty ratio to two reference pulses and apply the second offset duty ratio to four non-reference pulses. For example, the offset determination unit (420) can determine the duty ratio of each PWM pulse to which the offset duty ratio (first offset duty ratio and second offset duty ratio) is applied using Equation 7.

[0110]

[0111] Here, d xy,offset is the duty cycle of the x-phase PWM pulse of the y-interverter with the offset duty cycle applied, and d xy is the duty ratio of the x-phase PWM pulse of the y-inverter, and d offset,SP and d offset,NSP can be the first offset duty and the second offset duty, respectively.

[0112] The edge synchronization unit (430) can synchronize the edges of four non-reference pulses (hereinafter offset-applied non-reference pulses) to which the second offset duty ratio is applied based on the rising edge and falling edge of two reference pulses (hereinafter offset-applied reference pulses) to which the first offset duty ratio is applied. Specifically, the edge synchronization unit (430) can synchronize (align) one of the two offset-applied non-reference pulses of the first inverter (110a) with the rising edge of the offset-applied reference pulse of the second inverter (110b), and the other one with the falling edge of the offset-applied reference pulse of the second inverter (110b). Additionally, the edge synchronization unit (430) can synchronize (align) one of the two offset-applied non-reference pulses of the second inverter (110b) with the falling edge of the offset-applied reference pulse of the first inverter (110a), and the other one with the rising edge of the offset-applied reference pulse of the first inverter (110a). At this time, as a result of applying the second offset duty cycle, one of the four non-reference pulses may have a duty cycle of 0 or 1. In this case, the synchronization (alignment) process of the offset-applied non-reference pulse may be omitted.

[0113] For example, when a reference pulse exists in phase a and, as a result of applying an offset duty cycle (a first offset duty cycle and a second offset duty cycle), the phase a leg of the first inverter (110a) and the phase c leg of the second inverter (110b) are clamped (when the offset-applied phase a PWM pulse of the first inverter (110a) and the offset-applied phase c PWM pulse of the second inverter (110b) have a duty cycle of 0 or 1, the edge synchronization unit (430) synchronizes the rising edge (or falling edge) of the offset-applied phase b PWM pulse (offset-applied non-reference pulse) of the first inverter (110a) with the rising edge (or falling edge) of the offset-applied phase a PWM pulse (offset-applied reference pulse) of the second inverter (110b), and the falling edge (or rising edge) of the offset-applied phase c PWM pulse (offset-applied non-reference pulse) of the first inverter (110a) with the offset-applied phase c of the second inverter (110b). The falling edge (or rising edge) of the a-phase PWM pulse (offset applied reference pulse) can be synchronized with the falling edge (or rising edge) of the offset applied b-phase PWM pulse (offset applied non-reference pulse) of the second inverter (110b), and the falling edge (or rising edge) of the offset applied a-phase PWM pulse (offset applied reference pulse) of the first inverter (110a) can be synchronized with the falling edge (or rising edge) of the offset applied a-phase PWM pulse (offset applied reference pulse).

[0114] According to an exemplary embodiment, the edge synchronization unit (430) can determine the synchronization duty ratio of the reference pulse and the non-reference pulse in each of the up-slope and down-slope sections of the carrier waveform for edge synchronization. Here, as shown in FIGS. 6 and 7, the down edge of the PWM pulse may be formed in the up-slope section of the carrier waveform, and the up edge of the PWM pulse may be formed in the down-slope section of the carrier waveform. Accordingly, the down-slope section of the carrier waveform may be referred to as the up edge section, and the up-slope section of the carrier waveform may be referred to as the down edge section. As illustrated in FIGS. 6 and 7, the edge synchronization unit (430) determines the synchronization duty ratio of the rising edge section and the falling edge section using Equation 8 for rising edge synchronization and Equation 9 for falling edge synchronization for non-reference pulses, and for reference pulses, determines the duty ratio of the rising edge section and the falling edge section of the offset-applied reference pulse as the synchronization duty ratio of the rising edge section and the falling edge section of the reference pulse.

[0115]

[0116]

[0117] Here, x is an index representing the phase (phase a, phase b, phase c), y is an index representing the inverter (first inverter and second inverter), and d xy,Shift,rising and d xy,Shift,falling are the synchronization duty ratios for the rising edge and falling edge periods of the x-phase PWM pulse (non-reference pulse) of the y-inverter, respectively, and d SP,y is the duty ratio of the offset-applied reference pulse of another inverter that is the synchronization target of the non-reference pulse of the y-inverter, and d xy,offset can be the duty cycle of the offset-applied x-phase PWM pulse (offset-applied non-reference pulse) of the y-inverter. d according to each sector SP,y This can be represented in Table 2.

[0118] sector 12, 1, 6, 7 4, 5, 10, 11 2, 3, 8, 9 d SP,1 d a2,offset d b2,offset d c2,offset d SP,2 d a1,offset d b1,offset d c1,offset

[0119] FIGS. 8 to 10 are exemplary diagrams for explaining 2-leg clamping and edge synchronization in the first fundamental period (PRD=0).

[0120] Referring to FIG. 8, the reference pulse determination unit (410) determines the a-phase, b-phase, and c-phase PWM pulses (S) of the first inverter. a1 , S b1 , S c1 ) and the a-phase, b-phase, and c-phase PWM pulses (S) of the second inverter a2 , S b2 , S c2 The PWM pulse (S) with the longest duty cycle within one switching period among ) a1 ) and the shortest PWM pulse (S a2 ) as the reference pulse, and the remaining 4 PWM pulses (S b1 , S c1 , S b2 , S c2 ) can be determined as a non-reference pulse. The offset determination unit (420) can determine the first offset duty cycle (810) and the second offset duty cycle (820) using the aforementioned mathematical formula 6 (when PRD=0).

[0121] Referring to FIG. 9, the offset determination unit (420) determines the first offset duty ratio (810) as a reference pulse (S a1 , S a2 Apply to ) and the second offset duty cycle (820) to the non-reference pulse (S b1 , S c1 , S b2 , S c2 It can be applied to ). At this time, the offset determination unit (420) can determine the duty ratio of each PWM pulse to which the offset duty ratio (first offset duty ratio and second offset duty ratio) is applied using mathematical formula 7.

[0122] In Fig. 9, S a1,offset and S a2,offset represents the offset-applied a-phase PWM pulse of the first inverter and the second inverter, respectively, and Sb1,offset and S b2,offset represents the offset-applied b-phase PWM pulses of the first inverter and the second inverter, respectively, and S c1,offset and S c2,offset can represent the offset-applied c-phase PWM pulse of the first inverter and the second inverter, respectively. In this case, the offset-applied a-phase PWM pulse (S) of the first inverter a1,offset ) and the c-phase PWM pulse (S) with offset applied to the second inverter c2,offset The duty cycle of ) becomes 1, so that the a-phase leg of the first inverter and the c-phase leg of the second inverter can be clamped.

[0123] Referring to FIG. 10, the edge synchronization unit (430) applies the offset-applied b-phase PWM pulse (S) of the first inverter. b1,offset The falling edge of the )(offset-applied non-reference pulse) is the offset-applied a-phase PWM pulse (S) of the second inverter. a2,offset Synchronized with the falling edge of the )(offset applied reference pulse), and the offset applied c-phase PWM pulse (S) of the first inverter c1,offset The rising edge of the )(offset-applied non-reference pulse) is the offset-applied a-phase PWM pulse (S) of the second inverter. a2,offset It can be synchronized with the rising edge of the )(offset applied reference pulse). In addition, the edge synchronization unit (430) can synchronize with the offset applied b-phase PWM pulse (S of the second inverter). b1,offset The rising edge of the )(offset-applied non-reference pulse) is the offset-applied a-phase PWM pulse (S) of the first inverter. a1,offset It can be synchronized with the rising edge of the (offset application reference pulse). At this time, the edge synchronization unit (430) uses the aforementioned mathematical formula 9 to synchronize the synchronization duty ratio (d) of the b-phase PWM pulse of the first inverter in the rising edge section and the falling edge section. b1,Shift,rising and d b1,Shift,falling ) determines, and using the aforementioned mathematical formula 8, the synchronization duty ratio (d) of the c-phase PWM pulse of the first inverter in the rising edge and falling edge sections c1,Shift,rising and d c1,Shift,falling) and the synchronization duty ratio (d) of the b-phase PWM pulse of the second inverter b2,Shift,rising and d b2,Shift,falling Can determine ).

[0124] In Fig. 10, S a1,shift and S a2,shift represents the edge-synchronized a-phase PWM pulses of the first inverter and the second inverter, respectively, and S b1,shift and S b2,shift represents the edge-synchronized b-phase PWM pulses of the first inverter and the second inverter, respectively, and S c1,shift and S c2,shift can represent the edge-synchronized c-phase PWM pulses of the first inverter and the second inverter, respectively. As illustrated, after edge synchronization, the rising edge and falling edge (e.g., S) that were not used for synchronizing the non-reference pulse c1,shift and S b2,shift The falling edge of can be automatically aligned.

[0125] As illustrated in FIG. 10, through 2-leg clamping and edge synchronization according to an exemplary embodiment, the common mode voltage (U) of the first inverter cmv1 ) and the common mode voltage of the second inverter (U cmv1 Since the difference of ) can be made zero, switching losses can be reduced and zero-sequence voltage can be suppressed at the same time.

[0126] FIGS. 11 to 13 are exemplary diagrams for explaining 2-leg clamping and edge synchronization in the second fundamental period (PRD=1).

[0127] Referring to FIG. 11, the reference pulse determination unit (410) determines the a-phase, b-phase, and c-phase PWM pulses (S) of the first inverter. a1 , S b1 , S c1 ) and the a-phase, b-phase, and c-phase PWM pulses (S) of the second inverter a2 , S b2 , S c2 The PWM pulse (S) with the longest duty cycle within one switching period among ) a1) and the shortest PWM pulse (S a2 ) as the reference pulse, and the remaining 4 PWM pulses (S b1 , S c1 , S b2 , S c2 ) can be determined as a non-reference pulse. The offset determination unit (420) can determine the first offset duty cycle (1110) and the second offset duty cycle (1120) using the aforementioned mathematical formula 6 (when PRD=1).

[0128] Referring to FIG. 12, the offset determination unit (420) determines the first offset duty ratio (1110) as a reference pulse (S a1 , S a2 Apply to ) and the second offset duty ratio (1120) to the non-reference pulse (S b1 , S c1 , S b2 , S c2 It can be applied to ). At this time, the offset determination unit (420) can determine the duty ratio of each PWM pulse to which the offset duty ratio (first offset duty ratio and second offset duty ratio) is applied using mathematical formula 7.

[0129] In Fig. 12, S a1,offset and S a2,offset represents the offset-applied a-phase PWM pulse of the first inverter and the second inverter, respectively, and S b1,offset and S b2,offset represents the offset-applied b-phase PWM pulses of the first inverter and the second inverter, respectively, and S c1,offset and S c2,offset can represent the offset-applied c-phase PWM pulse of the first inverter and the second inverter, respectively. In this case, the offset-applied c-phase PWM pulse (S) of the first inverter c1,offset ) and the offset-applied a-phase PWM pulse (S) of the second inverter a2,offset The duty cycle of ) becomes 0, so the c-phase leg of the first inverter and the a-phase leg of the second inverter can be clamped.

[0130] Referring to FIG. 13, the edge synchronization unit (430) applies the offset-applied b-phase PWM pulse (S) of the first inverter. b1,offset The rising edge of the (offset-applied non-reference pulse) is the middle of the switching cycle (1310) (the middle of the switching cycle is the offset-applied a-phase PWM pulse (S) of the second inverter a2,offset It can be synchronized with the rising edge and falling edge of the offset-applied reference pulse. In addition, the edge synchronization unit (430) can be synchronized with the offset-applied b-phase PWM pulse (S of the second inverter). b2,offset The falling edge of the )(offset-applied non-reference pulse) is the offset-applied a-phase PWM pulse (S) of the first inverter. a1,offset Synchronized with the falling edge of the )(offset applied reference pulse), and the offset applied c-phase PWM pulse (S) of the second inverter c2,offset The rising edge of the )(offset-applied non-reference pulse) is the offset-applied a-phase PWM pulse (S) of the first inverter. a1,offset It can be synchronized with the rising edge of the (offset application reference pulse). At this time, the edge synchronization unit (430) uses the aforementioned mathematical formula 8 to synchronize the synchronization duty (d) of the b-phase PWM pulse of the first inverter in the rising edge section and the falling edge section. b1,Shift,rising and d b1,Shift,falling ) and the synchronization duty of the c-phase PWM pulse of the second inverter (d c2,Shift,rising and d c2,Shift,falling ) determines, and using the aforementioned mathematical formula 9, the synchronization duty (d) of the b-phase PWM pulse of the second inverter in the rising edge and falling edge sections b2,Shift,rising and d b2,Shift,falling Can determine ).

[0131] In Fig. 13, S a1,shift and S a2,shift represents the edge-synchronized a-phase PWM pulses of the first inverter and the second inverter, respectively, and S b1,shift and S b2,shift represents the edge-synchronized b-phase PWM pulses of the first inverter and the second inverter, respectively, and S c1,shift and S c2,shiftcan represent the edge-synchronized c-phase PWM pulses of the first inverter and the second inverter, respectively. As illustrated, after edge synchronization, the rising edge and falling edge (e.g., S) that were not used for synchronizing the non-reference pulse b1,shift and S c2,shift The falling edge of can be automatically aligned.

[0132] As illustrated in FIG. 13, through 2-leg clamping and edge synchronization according to an exemplary embodiment, the common mode voltage (U) of the first inverter cmv1 ) and the common mode voltage of the second inverter (U cmv1 Since the difference of ) can be made zero, switching losses can be reduced and zero-sequence voltage can be suppressed at the same time.

[0133] Referring to FIG. 4, the control device (400) according to an exemplary embodiment may further include a third back EMF compensation unit (440).

[0134] During motor operation, a third-order back EMF having a third-order harmonic component may be generated depending on the electromagnetic characteristics of the winding. In a structure where the first inverter (110a) and the second inverter (110b) share the same DC link power, this third-order back EMF is a common-mode voltage (u cmv1 , u cmv2 It is possible to induce a zero-sequence voltage by disrupting the balance of ).

[0135] The third back EMF compensation unit (440) can selectively apply a compensation duty cycle to the unclamped leg for each phase to eliminate the third back EMF component. That is, since the switching operation is fixed in the clamped leg and duty cycle correction is impossible, the third back EMF compensation unit (440) can compensate the voltage corresponding to the third back EMF by selectively adding or subtracting the compensation duty cycle to the duty cycle of the unclamped leg. At this time, the compensation duty cycle can be obtained from the output of the PR controller (Proportional-Resonant Controller).

[0136] According to an exemplary embodiment, a plurality of cases may be defined based on whether the corresponding phase (leg of the corresponding phase) of the first inverter is clamped as a result of applying the offset duty (first offset duty and second offset duty), whether the corresponding phase (leg of the corresponding phase) of the second inverter is clamped as a result of applying the offset duty (first offset duty and second offset duty), and whether the rising edge section of the corresponding phase of the first inverter is clamped as a result of edge synchronization. The third back EMF compensation unit (440) determines the case corresponding to each phase and may apply a compensation duty to the leg that is not clamped according to the case for each phase.

[0137] For example, each case can be defined as follows.

[0138] - Case 1: When the corresponding phase (corresponding phase leg) of the first inverter is clamped as a result of applying the offset duty cycle

[0139] - Case 2: As a result of applying the offset duty cycle, the corresponding phase (corresponding phase leg) of the first inverter is not clamped, but the corresponding phase (corresponding phase leg) of the second inverter is clamped.

[0140] - Case 3: As a result of applying the offset duty cycle, the corresponding phases (corresponding phase legs) of both the first and second inverters are not clamped, but as a result of edge synchronization, the rising edge section of the corresponding phase of the first inverter is clamped.

[0141] - Case 4: Cases other than Cases 1–3

[0142] The third back EMF compensation unit (440) can determine the final duty ratio of each leg (each phase of each inverter) to which the compensation duty ratio is selectively applied, by using Equation 10 for Case 1, Equation 11 for Case 2, Equation 12 for Case 3, and Equation 13 for Case 4 for each phase. At this time, the third back EMF compensation unit (440) can determine the final duty ratio of each leg (each phase of each inverter) by distinguishing between the rising edge section and the falling edge section.

[0143]

[0144]

[0145]

[0146]

[0147] Here, d x1,fin,rising and d x1,fin,falling are the final duty ratios of the rising edge and falling edge sections of the x-phase of the first inverter, respectively, and d x2,fin,rising and d x2,fin, falling are the final duty ratios of the rising edge and falling edge sections of the x-phase of the second inverter, respectively, and d x1,Shift,rising and d x1,Shift,falling are the synchronization duty ratios of the rising edge and falling edge sections of the x-phase of the first inverter, respectively, and d x2,Shift,rising and d x2,Shift,falling is the synchronization duty ratio of the rising edge and falling edge sections of the x-phase of the second inverter, respectively, and d0 may be the compensation duty ratio.

[0148] For example, in the examples of FIGS. 9 and 10, in the case of phase a, the phase a leg of the first inverter is clamped as a result of applying the offset duty cycle, so it may correspond to Case 1. In the case of phase b, the phase b leg of the first inverter and the second inverter is not clamped as a result of applying the offset duty cycle, but the phase b of the first inverter is clamped in the rising edge section as a result of edge synchronization, so it may correspond to Case 3. In the case of phase c, the phase c leg of the first inverter is not clamped as a result of applying the offset duty cycle, but the phase c leg of the second inverter is clamped, so it may correspond to Case 2. Accordingly, the third back EMF compensation unit (440) can determine the final duty cycle of the rising edge section and the falling edge section of each leg by using Equation 10 for phase a, Equation 12 for phase b, and Equation 11 for phase c, respectively.

[0149] FIG. 14 is a diagram illustrating a control method of a single-power dual inverter according to an exemplary embodiment. The control method of FIG. 14 can be performed by the control device (400) of FIG. 4. Although the control method is described in the illustrated flowchart as being divided into multiple steps, at least some of the steps may be performed in a different order, combined with other steps and performed together, omitted, divided into detailed steps, or one or more steps not illustrated may be added and performed.

[0150] Referring to FIG. 14, in step 1410, the control device can determine two reference pulses and four non-reference pulses among the six PWM pulses of the single-power dual inverter. For example, the control device can determine the PWM pulse with the longest duty cycle and the PWM pulse with the shortest duty cycle within one switching cycle among the six PWM pulses as reference pulses, and the remaining four PWM pulses as non-reference pulses.

[0151] In step 1420, the control device can determine a first offset duty ratio and a second offset duty ratio for clamping two legs. For example, the offset determination unit (420) can determine a first offset duty ratio for clamping one of two legs corresponding to two reference pulses and a second offset duty ratio for clamping one of four legs corresponding to four non-reference pulses using Equation 6.

[0152] In step 1430, when the first offset duty ratio and the second offset duty ratio are determined, the control device may apply the first offset duty ratio to two reference pulses and apply the second offset duty ratio to four non-reference pulses. For example, the control device may determine the duty ratio of the offset-applied PWM pulses using Equation 7.

[0153] In step 1440, the control device can synchronize the edges of four offset-applied non-reference pulses based on the rising and falling edges of two offset-applied reference pulses. Specifically, the control device can synchronize (align) one of the two offset-applied non-reference pulses of the first inverter with the rising edge of the offset-applied reference pulse of the second inverter, and the other with the falling edge of the offset-applied reference pulse of the second inverter. Additionally, the control device can synchronize (align) one of the two offset-applied non-reference pulses of the second inverter with the falling edge of the offset-applied reference pulse of the first inverter, and the other with the rising edge of the offset-applied reference pulse of the first inverter. At this time, as a result of applying the second offset duty cycle, one of the four offset-applied non-reference pulses may have a duty cycle of 0 or 1. In this case, the alignment process of the corresponding offset-applied non-reference pulse may be omitted.

[0154] According to an exemplary embodiment, the control device can determine the synchronization duty ratio of a reference pulse and a non-reference pulse in each of the rising edge interval and the falling edge interval for edge synchronization. For example, for the non-reference pulse, the control device can determine the synchronization duty ratio of the rising edge interval and the falling edge interval by using Equation 8 for rising edge synchronization and Equation 9 for falling edge synchronization, and for the reference pulse, determine the duty ratio to which the first offset duty ratio is applied as the synchronization duty ratio.

[0155] In step 1450, the control device may optionally apply a compensation duty to the unclamped leg for each phase to eliminate the third back EMF component. At this time, the compensation duty can be obtained from the output of the PR controller (Proportional-Resonant Controller).

[0156] According to an exemplary embodiment, the control device determines the case corresponding to each phase and can apply a compensation duty ratio to the leg that is not clamped according to the case for each phase. For example, for each phase, the control device can determine the final duty ratio of each leg to which the compensation duty ratio is selectively applied by using Equation 10 for Case 1, Equation 11 for Case 2, Equation 12 for Case 3, and Equation 13 for Case 4.

[0157] Each phase determines the corresponding case, and for each phase, a compensation duty can be applied to the unclamped leg according to the corresponding case.

[0158] FIG. 15 is a block diagram illustrating a computing environment including a computing device according to one embodiment. In the illustrated embodiment, each component may have different functions and capabilities in addition to those described below, and may include additional components in addition to those described below.

[0159] The illustrated computing environment (10) includes a computing device (12). The computing device (12) may be one or more components included in a single-power dual inverter (100) or a control device (400) according to one embodiment.

[0160] The computing device (12) includes at least one processor (14), a computer-readable storage medium (16), and a communication bus (18). The processor (14) can cause the computing device (12) to operate according to the exemplary embodiment described above. For example, the processor (14) can execute one or more programs stored in the computer-readable storage medium (16). The one or more programs may include one or more computer-executable instructions, and the computer-executable instructions may be configured to cause the computing device (12) to perform operations according to the exemplary embodiment when executed by the processor (14).

[0161] A computer-readable storage medium (16) is configured to store computer-executable instructions or program code, program data and / or other suitable forms of information. A program (20) stored in the computer-readable storage medium (16) includes a set of instructions executable by a processor (14). In one embodiment, the computer-readable storage medium (16) may be memory (volatile memory such as random access memory, non-volatile memory, or a suitable combination thereof), one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, other forms of storage media that are accessed by a computing device (12) and capable of storing desired information, or a suitable combination thereof.

[0162] The communication bus (18) interconnects various other components of the computing device (12), including the processor (14) and the computer-readable storage medium (16).

[0163] The computing device (12) may also include one or more input / output interfaces (22) and one or more network communication interfaces (26) that provide interfaces for one or more input / output devices (24). The input / output interfaces (22) and network communication interfaces (26) are connected to a communication bus (18). The input / output devices (24) may be connected to other components of the computing device (12) through the input / output interfaces (22). An exemplary input / output device (24) may include an input device such as a pointing device (such as a mouse or trackpad), a keyboard, a touch input device (such as a touchpad or touchscreen), a voice or sound input device, various types of sensor devices and / or imaging devices, and / or an output device such as a display device, a printer, a speaker and / or a network card. An exemplary input / output device (24) may be included inside the computing device (12) as a component constituting the computing device (12), or it may be connected to the computing device (12) as a separate device distinct from the computing device (12).

[0164] The present invention has been described above focusing on its preferred embodiments. Those skilled in the art will understand that the present invention may be implemented in modified forms without departing from the essential characteristics of the invention. Accordingly, the scope of the present invention should not be limited to the aforementioned embodiments but should be interpreted to include various embodiments within the scope equivalent to those described in the claims. Explanation of the symbols

[0165] 100: Single-power dual inverter 110a: First inverter 110b: Second inverter 120: Control unit 101: DC Link Power 102: Motor 400: Control unit 410: Reference pulse judgment unit 420: Offset determination unit 430: Edge synchronization unit 440: 3rd back EMF compensation unit 10: Computing Environment 12: Computing device 14: Processor 16: Computer-readable storage media 18: Communication bus 20: Program 22: Input / Output Interface 24: Input / Output Devices 26: Network communication interface

Claims

Claim 1 A control method for a single-power dual inverter comprising a first inverter and a second inverter, comprising: a step of determining two reference pulses and four non-reference pulses among six PWM pulses; a step of determining a first offset duty ratio and a second offset duty ratio for clamping two legs among six legs corresponding to the six PWM pulses; a step of applying the first offset duty ratio to each of the two reference pulses and applying the second offset duty ratio to each of the four non-reference pulses; and a step of synchronizing the edges of the four non-reference pulses to which the second offset duty ratio is applied based on the rising edge and falling edge of the two reference pulses to which the first offset duty ratio is applied. Claim 2 A control method according to claim 1, wherein the step of determining the two reference pulses and four non-reference pulses comprises determining the PWM pulse with the longest duty cycle and the PWM pulse with the shortest duty cycle among the six PWM pulses as reference pulses, and determining the remaining four PWM pulses as non-reference pulses. Claim 3 The control method according to claim 1, wherein the step of determining the first offset duty ratio and the second offset duty ratio is to determine the first offset duty ratio and the second offset duty ratio using the following Equation 1. [Equation 1] (d offset,SP and d offset,NSP are the first offset duty ratio and the second offset duty ratio, respectively, and d max1 and d max2 are the maximum duty ratios of the first inverter and the second inverter, respectively, and d min1 and d min2 is the minimum duty ratio of the first inverter and the second inverter, respectively, and PRD is a variable that defines the clamping state of the upper switch or the lower switch within the fundamental period. Claim 4 A control method according to claim 3, wherein the PRD alternates between 0 and 1 for every fundamental wave period. Claim 5 A control method according to claim 1, wherein the step of synchronizing the edges of four non-reference pulses to which the second offset duty ratio is applied comprises synchronizing one of the two non-reference pulses of the first inverter to which the second offset duty ratio is applied to the rising edge of the reference pulse of the second inverter to which the first offset duty ratio is applied, synchronizing the other of the two non-reference pulses of the first inverter to which the second offset duty ratio is applied to the falling edge of the reference pulse of the second inverter to which the first offset duty ratio is applied, synchronizing one of the two non-reference pulses of the second inverter to which the second offset duty ratio is applied to the rising edge of the reference pulse of the first inverter to which the first offset duty ratio is applied, and synchronizing the other of the two non-reference pulses of the second inverter to which the second offset duty ratio is applied to the falling edge of the reference pulse of the first inverter to which the first offset duty ratio is applied, wherein the synchronization process of the non-reference pulse having a duty ratio of 0 or 1 among the four non-reference pulses to which the second offset duty ratio is applied is omitted. Claim 6 A control method according to claim 1, wherein the step of synchronizing the edges of four non-reference pulses to which the second offset duty ratio is applied comprises the step of determining the synchronization duty ratio of each rising edge interval and each falling edge interval for each of the reference pulse and the non-reference pulse. Claim 7 A control method according to claim 6, wherein the step of determining the synchronization duty ratio determines the synchronization duty ratio of the rising edge section and the falling edge section for the non-reference pulse by using the following Equation 2 for rising edge synchronization and the following Equation 3 for falling edge synchronization.[Equation 2] [Mathematical Formula 3] (x is an index representing phases a, b, and c, y is an index representing the first inverter and the second inverter, and d xy,Shift,rising and d xy,Shift,falling are the synchronization duty ratios for the rising edge and falling edge periods of the x-phase PWM pulse of the y-inverter, respectively, and d SP,y is the first offset duty ratio (d) of another inverter that is the synchronization target of the non-reference pulse of the y inverter. offset,SP It is the duty ratio of the reference pulse to which ) is applied, and d xy,offset is the second offset duty ratio (d) of the y inverter offset,NSP )This is the duty cycle of the applied x-phase PWM pulse) Claim 8 A control method according to claim 7, wherein the step of determining the synchronization duty ratio is, for the reference pulse, determining the duty ratio of the rising edge section and the falling edge section of the reference pulse to which the first offset duty ratio is applied as the synchronization duty ratio of the rising edge section and the falling edge section of the reference pulse. Claim 9 A control method according to claim 1, further comprising the step of selectively applying a compensation duty to an unclamped leg for each phase to eliminate a third back EMF component. Claim 10 A control method according to claim 9, wherein the step of applying the compensation duty ratio comprises determining a case corresponding to each phase among a plurality of cases, and selectively applying the compensation duty ratio to an unclamped leg according to the corresponding case for each phase. Claim 11 A control method according to claim 10, wherein the plurality of cases includes case 1, case 2, case 3, and case 4, wherein case 1 is defined as a case in which the corresponding phase of the first inverter is clamped as a result of applying the first offset duty ratio and the second offset duty ratio, case 2 is defined as a case in which the corresponding phase of the first inverter is not clamped as a result of applying the first offset duty ratio and the second offset duty ratio, but the corresponding phase of the second inverter is clamped, case 3 is defined as a case in which neither the corresponding phase of the first inverter nor the second inverter is clamped as a result of applying the first offset duty ratio and the second offset duty ratio, but the rising edge section of the corresponding phase of the first inverter is clamped as a result of edge synchronization, and case 4 is defined as a case other than case 1, case 2, and case 3. Claim 12 A control method according to claim 11, wherein the step of applying the compensation duty ratio comprises determining the final duty ratio of each leg to which the compensation duty ratio is selectively applied, using the following mathematical formula 4 for case 1, the following mathematical formula 5 for case 2, the following mathematical formula 6 for case 3, and the following mathematical formula 7 for case 4 for each phase. [Mathematical Formula 4] [Mathematical Formula 5] [Mathematical Formula 6] [Mathematical Formula 7] (d x1,fin,rising and d x1,fin,falling are the final duty ratios of the rising edge and falling edge sections of the x-phase of the first inverter, respectively, and d x2,fin,rising and d x2,fin, falling are the final duty ratios of the rising edge and falling edge sections of the x-phase of the second inverter, respectively, and d x1,Shift,rising and d x1,Shift,falling are the synchronization duty ratios of the rising edge and falling edge sections of the x-phase of the first inverter, respectively, and d x2,Shift,rising and d x2,Shift,falling are the synchronization duty ratios for the rising edge and falling edge periods of the x phase of the second inverter, respectively, and d0 is the compensation duty ratio. Claim 13 A control device for a single-power dual inverter comprising a first inverter and a second inverter, comprising: a reference pulse determination unit for determining two reference pulses and four non-reference pulses among six PWM pulses; an offset determination unit for determining a first offset duty ratio and a second offset duty ratio for clamping two legs among six legs corresponding to the six PWM pulses, applying the first offset duty ratio to each of the two reference pulses, and applying the second offset duty ratio to each of the four non-reference pulses; and an edge synchronization unit for synchronizing the edges of the four non-reference pulses to which the second offset duty ratio is applied based on the rising edge and falling edge of the two reference pulses to which the first offset duty ratio is applied. Claim 14 A control device according to claim 13, wherein the reference pulse determination unit determines the PWM pulse with the longest duty cycle and the PWM pulse with the shortest duty cycle among the six PWM pulses as reference pulses, and determines the remaining four PWM pulses as non-reference pulses. Claim 15 The control device of claim 13, wherein the offset determination unit determines a first offset duty ratio and a second offset duty ratio using the following mathematical formula 1.[Mathematical Formula 1] (d offset,SP and d offset,NSP are the first offset duty ratio and the second offset duty ratio, respectively, and d max1 and d max2 are the maximum duty ratios of the first inverter and the second inverter, respectively, and d min1 and d min2 is the minimum duty ratio of the first inverter and the second inverter, respectively, and PRD is a variable that defines the clamping state of the upper switch or the lower switch within the fundamental period. Claim 16 In claim 15, the PRD is a control device in which 0 and 1 alternate with every fundamental wave period. Claim 17 A control device according to claim 13, wherein the edge synchronization unit synchronizes one of the two non-reference pulses of the first inverter to which the second offset duty ratio is applied with the rising edge of the reference pulse of the second inverter to which the first offset duty ratio is applied, synchronizes the other of the two non-reference pulses of the first inverter to which the second offset duty ratio is applied with the falling edge of the reference pulse of the second inverter to which the first offset duty ratio is applied, synchronizes one of the two non-reference pulses of the second inverter to which the second offset duty ratio is applied with the rising edge of the reference pulse of the first inverter to which the first offset duty ratio is applied, and synchronizes the other of the two non-reference pulses of the second inverter to which the second offset duty ratio is applied with the falling edge of the reference pulse of the first inverter to which the first offset duty ratio is applied, wherein the synchronization process of the non-reference pulse having a duty ratio of 0 or 1 among the four non-reference pulses to which the second offset duty ratio is applied is omitted. Claim 18 In claim 13, the edge synchronization unit is a control device that determines the synchronization duty ratio of each rising edge section and each falling edge section for each of the reference pulse and the non-reference pulse. Claim 19 A control device according to claim 18, wherein the edge synchronization unit determines the synchronization duty ratio of the rising edge section and the falling edge section for the non-reference pulse by using the following Equation 2 for rising edge synchronization and the following Equation 3 for falling edge synchronization.[Equation 2] [Mathematical Formula 3] (x is an index representing phases a, b, and c, y is an index representing the first inverter and the second inverter, and d xy,Shift,rising and d xy,Shift,falling are the synchronization duty ratios for the rising edge and falling edge periods of the x-phase PWM pulse of the y-inverter, respectively, and d SP,y is the first offset duty ratio (d) of another inverter that is the synchronization target of the non-reference pulse of the y inverter. offset,SP It is the duty ratio of the reference pulse to which ) is applied, and d xy,offset is the second offset duty ratio (d) of the y inverter offset,NSP )This is the duty cycle of the applied x-phase PWM pulse) Claim 20 A control device according to claim 19, wherein the edge synchronization unit determines, for the reference pulse, the duty ratio of the rising edge section and the falling edge section of the reference pulse to which the first offset duty ratio is applied as the synchronization duty ratio of the rising edge section and the falling edge section of the reference pulse. Claim 21 A control device according to claim 13, further comprising a third back EMF compensation unit that selectively applies a compensation duty ratio to an unclamped leg for each phase to eliminate a third back EMF component. Claim 22 A control device according to claim 21, wherein the third back EMF compensation unit determines a case corresponding to each phase among a plurality of cases, and selectively applies a compensation duty ratio to an unclamped leg according to the corresponding case for each phase. Claim 23 A control device according to claim 22, wherein the plurality of cases includes case 1, case 2, case 3, and case 4, wherein case 1 is defined as a case in which the corresponding phase of the first inverter is clamped as a result of applying the first offset duty ratio and the second offset duty ratio, case 2 is defined as a case in which the corresponding phase of the first inverter is not clamped as a result of applying the first offset duty ratio and the second offset duty ratio, but the corresponding phase of the second inverter is clamped, case 3 is defined as a case in which neither the corresponding phase of the first inverter nor the second inverter is clamped as a result of applying the first offset duty ratio and the second offset duty ratio, but the rising edge section of the corresponding phase of the first inverter is clamped as a result of edge synchronization, and case 4 is defined as a case other than case 1, case 2, and case 3. Claim 24 A control device according to claim 23, wherein the third back EMF compensation unit determines the final duty ratio of each leg to which the compensation duty ratio is selectively applied by using the following mathematical formula 4 for case 1, the following mathematical formula 5 for case 2, the following mathematical formula 6 for case 3, and the following mathematical formula 7 for case 4 for each phase. [Mathematical Formula 4] [Mathematical Formula 5] [Mathematical Formula 6] [Mathematical Formula 7] (d x1,fin,rising and d x1,fin,falling are the final duty ratios of the rising edge and falling edge sections of the x-phase of the first inverter, respectively, and d x2,fin,rising and d x2,fin, falling are the final duty ratios of the rising edge and falling edge sections of the x-phase of the second inverter, respectively, and d x1,Shift,rising and d x1,Shift,falling are the synchronization duty ratios of the rising edge and falling edge sections of the x-phase of the first inverter, respectively, and d x2,Shift,rising and d x2,Shift,falling are the synchronization duty ratios for the rising edge and falling edge periods of the x phase of the second inverter, respectively, and d0 is the compensation duty ratio.

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