Display device

Abstract

The display device includes a display panel. The display panel includes pixels connected to gate lines and data lines. A sensor is positioned overlapping the display panel. A gate driver provides a gate signal to the display panel. In a first mode, the gate driver provides the gate signal to the gate lines in an interlaced scanning manner. In a second mode, the gate driver provides the gate signal in a progressive scanning manner, wherein the sensor operates in a section allocated between the sections where the first interlaced scan and the second interlaced scan are performed within a single frame section.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] With the advancement of information technology, the importance of display devices, which serve as a medium connecting users and information, is being highlighted. In response to this, the use of display devices such as Liquid Crystal Displays (LCDs) and Organic Light Emitting Displays (OLEDs) is increasing.

[0003] The display device may include a display unit for displaying an image and a sensor unit for sensing a touch position. The problem to be solved

[0004] In order to express touch input results (e.g., handwriting using a stylus pen) more naturally in real time, the sensing cycle of the sensor unit must be shortened.

[0005] If the sensing cycle of the sensor unit is shorter than the image refresh cycle of the display unit, in particular, if the sensor unit performs a sensing operation while an image is being displayed on the display unit, interference may occur with the image due to the sensing operation of the sensor unit, and the display quality may be degraded.

[0006] One objective of the present invention is to provide a display device capable of detecting touch input without degrading display quality. means of solving the problem

[0007] To achieve one objective of the present invention, a display device according to embodiments of the present invention comprises: a display panel including pixels connected to gate lines and data lines; a sensor disposed in overlap with the display panel; and a gate driver that provides a gate signal to the gate lines. In a first mode, the gate driver provides the gate signal to the gate lines in an interlaced scanning manner. In a second mode, the gate driver provides the gate signal in a progressive scanning manner, wherein the sensor operates in a section allocated between the sections where the first interlaced scan and the second interlaced scan are performed within a single frame section.

[0008] The above gate lines include first gate lines and second gate lines, wherein the first gate lines and second gate lines are arranged alternately, and the gate driving unit includes a first gate driving unit that sequentially provides a first gate signal to the first gate lines in response to a first start signal; and a second gate driving unit that sequentially provides a second gate signal to the second gate lines in response to a second start signal, wherein the first gate signal is sequentially provided to the first gate lines in a first section of the second mode, and the second gate signal is sequentially provided to the second gate lines in a second section of the second mode after the first section.

[0009] The first gate lines mentioned above may be odd-numbered gate lines, and the second gate lines may be even-numbered gate lines.

[0010] In the above second mode, the pulse of the first start signal and the pulse of the second start signal may occur in mutually different intervals among the first to fourth intervals.

[0011] In the first mode, the pulse of the first start signal and the pulse of the second start signal may occur in mutually identical intervals among the first to fourth intervals.

[0012] When the sensor detects a touch input, the gate driver operates in the second mode, and when the sensor does not detect the touch input, the gate driver can operate in the first mode.

[0013] When the input device linked to the sensor is activated, the gate driver operates in the second mode, and when the input device is deactivated, the gate driver can operate in the first mode.

[0014] The frame interval of the second mode above includes a first interval, a second interval, a third interval, and a fourth interval arranged sequentially, the first interlaced scan is performed in the first interval, the second interlaced scan is performed in the third interval, and the sensor can operate in the second interval and the fourth interval.

[0015] In the second mode, the second driving cycle of the sensor may be different from the first driving cycle of the sensor in the first mode.

[0016] The gate driving unit generates the gate signal based on a clock signal, wherein the second frequency of the clock signal in the second mode may be different from the first frequency of the clock signal in the first mode.

[0017] In the second mode, the second frequency of the clock signal may be greater than the first frequency of the clock signal in the first mode.

[0018] In the second mode, the pulse width of the clock signal may be the same as the pulse width of the clock signal in the first mode.

[0019] In the second mode, the pulse width of the clock signal may be different from the pulse width of the clock signal in the first mode.

[0020] The refresh rate of the image displayed through the above display panel may be the same in the first mode and the second mode.

[0021] To achieve one objective of the present invention, a display device according to embodiments of the present invention comprises: a display panel including pixels connected to gate lines and data lines; a sensor disposed in overlap with the display panel; and a gate driver that provides a gate signal to the gate lines. The gate lines are divided into first gate lines disposed in a first area of ​​the display panel and second gate lines disposed in a second area of ​​the display panel. In a first mode, the gate driver provides a gate signal to the gate lines during a single continuous section within a frame interval, and the sensor does not operate during the single continuous section. In a second mode, the gate driver provides the gate signal to the first gate lines in a first section within a frame interval and provides the gate signal to the second gate lines in a second section within a frame interval, and the sensor operates in a third section between the first section and the second section.

[0022] When the sensor detects a touch input, the gate driver operates in the second mode, and when the sensor does not detect the touch input, the gate driver can operate in the first mode.

[0023] When the input device linked to the sensor is activated, the gate driver operates in the second mode, and when the input device is deactivated, the gate driver can operate in the first mode.

[0024] The frame interval of the second mode above includes the first interval, the second interval, the third interval, and the fourth interval arranged sequentially, and a scanning operation is performed in the first interval and the third interval, and the sensor can operate in the second interval and the fourth interval.

[0025] In the second mode, the second driving cycle of the sensor may be different from the first driving cycle of the sensor in the first mode.

[0026] The refresh rate of the image displayed through the above display panel may be the same in the first mode and the second mode. Effects of the invention

[0027] A display device according to embodiments of the present invention performs mode switching between a first mode and a second mode based on whether it interacts with an external input device or whether a touch input occurs, and can vary the number of blank sections within a single frame (i.e., sections where a touch scan operation can be performed). Accordingly, the display device detects the touch input at a higher driving frequency and can display the touch input result more quickly and naturally.

[0028] In addition, a display device according to one embodiment of the present invention may operate in a sequential scanning manner in a first mode in which no touch input is detected, and in an interlaced scanning manner in a second mode in which a touch input is detected. Accordingly, degradation of display quality may be prevented or mitigated. Brief explanation of the drawing

[0029] FIG. 1 is a drawing showing a display device according to embodiments of the present invention. FIG. 2 is a cross-sectional view showing one embodiment of the display device of FIG. 1. FIG. 3 is a drawing showing one embodiment of the display device of FIG. 1. FIGS. 4 and FIGS. 5 are drawings illustrating an embodiment of the display device of FIGS. 3. FIG. 6 is a drawing showing an embodiment of a gate driving unit included in the display device of FIG. 4. FIG. 7 is a diagram illustrating the operation of the display device of FIG. 4 in the first mode. FIGS. 8 and 9 are drawings illustrating the operation of the first and second gate drivers of FIG. 4 in the first mode. FIG. 10 is a diagram illustrating the operation of the display device of FIG. 4 in the second mode. FIG. 11 is a diagram illustrating the operation of the first and second gate drivers of FIG. 4 in the second mode. FIG. 12 is a drawing illustrating an embodiment of the operation of the display device of FIG. 1. FIG. 13 is a drawing showing embodiments of an image displayed on the display device of FIG. 1. FIG. 14 is a circuit diagram showing an example of a pixel included in the display device of FIG. 1. FIG. 15 is a drawing showing one embodiment of the gate driving unit of FIG. 3. FIG. 16 is a drawing showing another embodiment of the display device of FIG. 3. FIG. 17 is a diagram illustrating the operation of the display device of FIG. 16 in the first mode. FIG. 18 is a diagram illustrating the operation of the display device of FIG. 16 in the second mode. FIG. 19 is a drawing illustrating another embodiment of the operation of the display device of FIG. 1. FIG. 20 is a drawing showing embodiments of an image displayed on the display device of FIG. 1. Specific details for implementing the invention

[0030] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0031] To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are assigned to identical or similar components throughout the specification. Accordingly, the reference numerals described above may also be used in other drawings.

[0032] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thickness may be exaggerated in the drawings to clearly represent various layers and regions.

[0033] Furthermore, the expression "identical" in the explanation may mean "substantially identical." In other words, it may be an identicality to the extent that a person with ordinary knowledge would accept it as identical. Other expressions may also be those in which "substantially" has been omitted.

[0034] Some embodiments are described in the attached drawings in relation to functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by logic circuits, individual components, microprocessors, hardwired circuits, memory elements, wiring connections, and other electronic circuits. These may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units, and / or modules implemented by microprocessors or other similar hardware, they may be programmed and controlled using software to perform the various functions discussed in the present invention, and may optionally be driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware, or by a combination of dedicated hardware performing some functions and a processor performing other functions (e.g., one or more programmed microprocessors and associated circuits). Furthermore, in some embodiments, blocks, units, and / or modules may be physically separated into two or more individual blocks, units, and / or modules that interact within the scope of the concept of the present invention without departing from the scope of the present invention. Additionally, in some embodiments, blocks, units, and / or modules may be combined into physically more complex blocks, units, and / or modules within the scope of the concept of the present invention.

[0035] FIG. 1 is a drawing showing a display device according to embodiments of the present invention.

[0036] Referring to FIG. 1, the display device (1) may include a panel (10) and a driving circuit (20) for driving the panel (10). Additionally, the display device (1) may further include an application processor (30) or be connected to the application processor (30).

[0037] The panel (10) may include a display unit (110) (or, display panel, display layer) for displaying an image and a sensor unit (120) (or, sensor panel, sensor layer, sensor) for sensing touch, pressure, fingerprint, hovering, etc. For example, the panel (10) may include a pixel (PX) and sensors (SC) positioned overlapping at least some of the pixels (PX) in a third direction (DR3). In one embodiment, the sensors (SC) may include first sensors (TX) (or, driving electrode) and second sensors (RX) (or, sensing electrode). In another embodiment (e.g., magnetic capacitance method), the sensors (SC) may be composed of one type of sensor without distinction between the first and second sensors (TX, RX).

[0038] The driving circuit unit (20) may include a display driving unit (210) for driving the display unit (110) and a sensor driving unit (220) for driving the sensor unit (120). For example, a pixel (PX) may display an image in units of a display frame period. For example, sensors (SC) may sense user input in units of a sensing frame period. The sensing frame period and the display frame period may be independent of each other and may be different from each other. The sensing frame period and the display frame period may be synchronized with each other or may be asynchronous.

[0039] According to an embodiment, the display unit (110) and the sensor unit (120) may be manufactured separately from each other and then arranged and / or combined so that at least one area overlaps each other. Alternatively, in another embodiment, the display unit (110) and the sensor unit (120) may be manufactured as a single unit. For example, the sensor unit (120) may be formed directly on at least one substrate constituting the display unit (110) (e.g., an upper and / or lower substrate of a display panel, or a thin film encapsulation layer), or on other insulating layers or various functional films (e.g., an optical layer or a protective layer).

[0040] Meanwhile, in FIG. 1, the sensor unit (120) is shown positioned on the front side of the display unit (110) (e.g., the upper surface where the image is displayed), but the position of the sensor unit (120) is not limited thereto. For example, in other embodiments, the sensor unit (120) may be positioned on the back or both sides of the display unit (110). In yet another embodiment, the sensor unit (120) may be positioned in at least one edge area of ​​the display unit (110).

[0041] The display unit (110) may include a display substrate (111) and a plurality of pixels (PX) formed on the display substrate (111). The pixels (PX) may be placed in a display area (DA) of the display substrate (111).

[0042] The display substrate (111) may include a display area (DA) where an image is displayed and a non-display area (NDA) on the outer edge of the display area (DA). According to an embodiment, the display area (DA) may be placed in the central area of ​​the display unit (110), and the non-display area (NDA) may be placed in the edge area of ​​the display unit (110) to surround the display area (DA).

[0043] The display substrate (111) may be a rigid substrate or a flexible substrate, and its material or physical properties are not particularly limited. For example, the display substrate (111) may be a rigid substrate composed of glass or reinforced glass, or a flexible substrate composed of a thin film made of plastic or metal.

[0044] In the display area (DA), a gate line (GL) and a data line (DL) are arranged, and a pixel (PX) connected to the gate line (GL) and the data line (DL) is arranged. The pixel (PX) is selected by a gate signal of a turn-on level supplied from the gate line (GL), receives a data signal from the data line (DL), and emits light of a luminance corresponding to the data signal. Accordingly, an image corresponding to the data signal is displayed in the display area (DA). In the present invention, the structure and driving method of the pixel (PX) are not particularly limited. For example, the pixel (PX) can be implemented as a pixel employing various structures and driving methods currently known.

[0045] Various wiring and / or embedded circuits connected to pixels (PX) of the display area (DA) may be disposed in the non-display area (NDA). For example, a number of wirings for supplying various power and control signals to the display area (DA) may be disposed in the non-display area (NDA), and additionally, a scan driver, etc., may be disposed therein.

[0046] In the present invention, the type of display unit (110) is not particularly limited. For example, the display unit (110) may be implemented as a self-emissive type display panel, such as an organic light-emitting display panel. However, when the display unit (110) is implemented as a self-emissive type, the pixel (PX) is not necessarily limited to only including organic light-emitting elements. For example, the light-emitting element of the pixel (PX) may be composed of an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot / well light-emitting diode, etc. A plurality of light-emitting elements may be provided in the pixel (PX). In this case, the plurality of light-emitting elements may be connected in series, parallel, series-parallel, etc. Alternatively, the display unit (110) may be implemented as a non-emissive type display panel, such as a liquid crystal display panel. When the display unit (110) is implemented as a non-luminous type, the display device (1) may additionally be provided with a light source such as a backlight unit.

[0047] The sensor unit (120) includes a sensor substrate (121) and a plurality of sensors (SC) formed on the sensor substrate (121). The sensors (SC) may be placed in a sensing area (SA) on the sensor substrate (121).

[0048] The sensor substrate (121) may include a sensing area (SA) capable of sensing touch input, etc., and a peripheral area (NSA) outside the sensing area (SA). According to an embodiment, the sensing area (SA) may be arranged to overlap with at least one area of ​​the display area (DA). For example, the sensing area (SA) may be set as an area corresponding to the display area (DA) (e.g., an area overlapping with the display area (DA)), and the peripheral area (NSA) may be set as an area corresponding to the non-display area (NDA) (e.g., an area overlapping with the non-display area (NDA)). In this case, when touch input, etc. is provided on the display area (DA), the touch input can be detected through the sensor unit (120).

[0049] The sensor substrate (121) may be a rigid or flexible substrate, and may also be composed of at least one insulating film. Additionally, the sensor substrate (121) may be a transparent or translucent light-transmitting substrate, but is not limited thereto. That is, the material and physical properties of the sensor substrate (121) in the present invention are not particularly limited. For example, the sensor substrate (121) may be a rigid substrate composed of glass or reinforced glass, or a flexible substrate composed of a thin film made of plastic or metal. Additionally, depending on the embodiment, at least one substrate constituting the display unit (110) (e.g., a display substrate (111), an encapsulation substrate and / or a thin film encapsulation layer), or at least one insulating film or functional film disposed on the inside and / or outside surface of the display unit (110) may be used as the sensor substrate (121).

[0050] The sensing area (SA) is set as an area capable of responding to touch input (i.e., an active area of ​​the sensor). To this end, sensors (SC) for sensing touch input, etc., may be placed in the sensing area (SA). According to an embodiment, the sensors (SC) may include first sensors (TX) and second sensors (RX).

[0051] For example, each first sensor (TX) may be extended in a first direction (DR1). The first sensors (TX) may be arranged in a second direction (DR2). The second direction (DR2) may be different from the first direction (DR1). For example, the second direction (DR2) may be a direction orthogonal to the first direction (DR1). In other embodiments, the extension direction and arrangement direction of the first sensors (TX) may follow other conventional configurations. Each first sensor (TX) may be in the form of first cells (or driving electrodes) with a relatively large area and first bridges with a relatively small area connected to each other. Although each first cell is illustrated in the shape of a diamond in FIG. 1, it may be configured in various conventional shapes such as a circle, square, triangle, or mesh form. For example, the first bridges may be integrally formed on the same layer as the first cells. In another embodiment, the first bridges are formed in a different layer from the first cells and can electrically connect adjacent first cells.

[0052] For example, each second sensor (RX) may be extended in a second direction (DR2). The second sensors (RX) may be arranged in a first direction (DR1). In other embodiments, the extension direction and arrangement direction of the second sensors (RX) may follow other conventional configurations. Each second sensor (RX) may be in the form of second cells (or sensing electrodes) with a relatively large area and second bridges with a relatively small area connected to them. Although each second cell is illustrated in the shape of a diamond in FIG. 1, it may be configured in various conventional shapes such as a circle, square, triangle, or mesh. For example, the second bridges may be formed integrally on the same layer as the second cells. In other embodiments, the second bridges may be formed on a different layer from the second cells to electrically connect adjacent second cells.

[0053] According to an embodiment, each of the first sensors (TX) and the second sensors (RX) may have conductivity by including at least one of a metallic material, a transparent conductive material, and various other conductive materials. For example, the first sensors (TX) and the second sensors (RX) may include at least one of various metallic materials, such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), platinum (Pt), etc., or an alloy thereof. In this case, the first sensors (TX) and the second sensors (RX) may be configured in a mesh form. Additionally, the first sensors (TX) and the second sensors (RX) may include at least one of various transparent conductive materials, including silver nanowires (AgNW), ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), IGZO (Indium Gallium Zinc Oxide), AZO (Antimony Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), SnO2 (Tin Oxide), carbon nanotubes, graphene, etc. Furthermore, the first sensors (TX) and the second sensors (RX) may possess conductivity by including at least one of various conductive materials. Additionally, each of the first sensors (TX) and the second sensors (RX) may be composed of a single layer or multiple layers, and their cross-sectional structure is not particularly limited.

[0054] Meanwhile, sensor lines for electrically connecting the first and second sensors (TX, RX) to the sensor driving unit (220), etc., may be concentrated in the peripheral area (NSA) of the sensor unit (120).

[0055] The driving circuit section (20) may include a display driving section (210) for driving the display section (110) and a sensor driving section (220) for driving the sensor section (120). In one embodiment, the display driving section (210) and the sensor driving section (220) may be composed of separate ICs (integrated chips). In another embodiment, at least a portion of the display driving section (210) and the sensor driving section (220) may be integrated together within a single IC.

[0056] The display driving unit (210) is electrically connected to the display unit (110) to drive the pixel (PX). For example, the display driving unit (210) may include a data driving unit and a timing control unit, and the scan driving unit may be separately mounted in the non-display area (NDA) of the display unit (110). In another embodiment, the display driving unit (210) may include all or at least part of the data driving unit, the timing control unit, and the scan driving unit. The display driving unit (210) will be described later with reference to FIG. 3.

[0057] The sensor driving unit (220) is electrically connected to the sensor unit (120) to drive the sensor unit (120). The sensor driving unit (220) may include a sensor transmitting unit and a sensor receiving unit. According to an embodiment, the sensor transmitting unit and the sensor receiving unit may be integrated within a single IC, but are not limited thereto.

[0058] The application processor (30) is electrically connected to the display driver (210) and can provide the display driver (210) with gradations and timing signals for the display frame period. Additionally, the application processor (30) is electrically connected to the sensor driver (220) and can receive a sensing signal from the sensor driver (220). The application processor (30) can detect touch, pressure, fingerprint, hovering, etc. based on the sensing signal. The application processor (30) may correspond to at least one of a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), an AP (Application Processor), etc.

[0059] In one embodiment, the application processor (30) is connected to an external input device (e.g., a stylus pen, e.g., an active electrostatic (AES) pen), and can control the operation of the display driver (210) and the sensor driver (220) depending on whether it is connected to the input device. For example, if the application processor (30) (or the display device (1)) is not connected to the external input device or the input device is not activated (or deactivated), the application processor (30) operates the display driver (210) and the sensor driver (220) in a first mode (or normal mode), and if the application processor (30) (or the display device (1)) is connected to the external input device or the input device is activated, the application processor (30) can operate the display driver (210) and the sensor driver (220) in a second mode (or touch mode). The first mode and the second mode will be described later with reference to FIG. 7 and FIG. 10.

[0060] In another embodiment, the application processor (30) can control the operation of the display driver (210) and the sensor driver (220) depending on whether a touch input occurs. For example, if no touch input is detected, the application processor (30) can operate the display driver (210) and the sensor driver (220) in a first mode, and if a touch input is detected through the sensor unit (120), the application processor (30) can operate the display driver (210) and the sensor driver (220) in a second mode.

[0061] FIG. 2 is a cross-sectional view showing one embodiment of the display device of FIG. 1.

[0062] Referring to FIGS. 1 and 2, a sensor unit (120) may be stacked on top of a display unit (110). Additionally, a window (WIN) may be stacked on top of the sensor unit (120).

[0063] The display unit (110) may include a display substrate (111), a circuit element layer (BPL) formed on the display substrate (111), and a light-emitting element (LD) formed on the circuit element layer (BPL). The circuit element layer (BPL) may include pixel circuits (e.g., transistors and capacitors) for driving the light-emitting element (LD) of the pixel (PX), as well as a gate line (GL), a data line (DL), etc.

[0064] The sensor portion (120) may include a sensor substrate (121), sensors (SC) formed on the sensor substrate (121), and a protective film (122) covering the sensors (SC). In the embodiment of FIG. 2, the sensor substrate (121) is shown in the form of a sealing film covering a pixel (PX). In another embodiment, the sensor substrate (121) may exist separately from the sealing film covering the pixel (PX).

[0065] A window (WIN) is a protective member placed at the top of a module of a display device (1) and may be a substantially transparent light-transmitting substrate. Such a window (WIN) may have a multilayer structure selected from a glass substrate, a plastic film, or a plastic substrate. The window (WIN) may include a rigid or flexible substrate, and the constituent material of the window (WIN) is not particularly limited.

[0066] Although not shown, the display device (1) may further include a polarizing plate (or another type of anti-reflection layer) for preventing external light reflection between the window (WIN) and the sensor unit (120).

[0067] FIG. 3 is a drawing showing an embodiment of the display device of FIG. 1. FIG. 3 briefly illustrates a display device (1) centered on a configuration for displaying an image (i.e., a configuration corresponding to the display unit (110) and the display driving unit (210) of FIG. 1).

[0068] Referring to FIGS. 1 and FIGS. 3, the display device (1) may include a display panel (310), a gate driver (320) (or, gate driver, scan driver), a data driver (330) (or, data driver, source driver), and a timing controller (340) (or, timing controller). The display panel (310) is substantially the same as the display unit (110) of FIG. 1, and at least one of the gate driver (320), the data driver (330), and the timing controller (340) may be included in the display driver (210) of FIG. 1.

[0069] The display panel (310) may include gate lines (GL1 to GLn, where n is a positive integer), data lines (DL1 to DLm, where m is a positive integer), and pixels (PX).

[0070] A pixel (PX) can be placed in an area (e.g., a pixel area) partitioned by gate lines (GL1~GLn) and data lines (DL1~DLm).

[0071] A pixel (PX) may be connected to gate lines (GL1–GLn) and data lines (DL1–DLm). In describing embodiments of the present invention, the term "connection" may comprehensively refer to electrical and / or physical connections. For example, a pixel (PX) placed in the i-th pixel row and the j-th pixel column may be connected to the i-th gate line (GLi) and the j-th data line (DLj). Here, i is a positive integer less than or equal to n, and j is a positive integer less than or equal to m.

[0072] A pixel (PX) can emit light with a brightness corresponding to a data signal provided through data lines (DL1~DLm) in response to a gate signal provided through gate lines (GL1~GLn).

[0073] The gate driver (320) can generate a gate signal (e.g., a gate signal of the turn-on level) based on a gate control signal (GCS) (or scan control signal) and sequentially provide the gate signal to gate lines (GL1~GLn). The gate control signal (GCS) includes a start signal and a clock signal, etc., and may be provided from the timing control unit (340). For example, the gate driver (320) may include a shift register (or stage) that sequentially outputs a pulse-shaped gate signal corresponding to the start signal using a clock signal.

[0074] The data driving unit (330) can generate data signals based on image data (DATA2) and a data control signal (DCS) provided by the timing control unit (340), and provide the data signals to the display panel (310) (or pixel (PX)). Here, the data control signal (DCS) is a signal that controls the operation of the data driving unit (330) and may include a load signal (or data enable signal) indicating the output of an effective data signal, a vertical synchronization signal, a horizontal synchronization signal, etc.

[0075] The timing control unit (340) receives input image data (DATA1) and a control signal (CS) from an external source (e.g., an application processor (30, see FIG. 1)), generates a gate control signal (GCS) and a data control signal (DCS) based on the control signal (CS), and can convert the input image data (DATA1) to generate image data (DATA2). For example, the timing control unit (340) can convert input image data (DATA1) in RGB format into image data (DATA2) in RGBG format that corresponds to the pixel array within the display panel (310).

[0076] Meanwhile, at least one of the gate driver (320), data driver (330), and timing control unit (340) may be formed on the display panel (310) or implemented as an integrated circuit (IC) and connected to the display panel (310) through a flexible circuit board. Additionally, at least two of the gate driver (320), data driver (330), and timing control unit (340) may be implemented as a single IC.

[0077] In the embodiments, the gate driver (320) in the first mode provides a gate signal to the gate lines (GL1~GLn) in an interlaced scanning manner in the first mode, and can provide a gate signal to the gate lines (GL1~GLn) in a progressive scanning manner in the second mode. The specific configuration of the gate driver (320) for this purpose will be described with reference to FIGS. 4 and 5.

[0078] FIGS. 4 and FIGS. 5 are drawings illustrating an embodiment of the display device of FIGS. 3.

[0079] Referring to FIGS. 3 through 5, the display device (1) of FIGS. 4 and FIG. 5 may be substantially the same or similar as the display device (1) of FIG. 3, except for the gate driving unit (320) of FIG. 3. Therefore, redundant descriptions will not be repeated.

[0080] The gate lines (GL1~GLn) of FIG. 3 may include first gate lines (GL11~GL1k, where k is a positive integer less than or equal to n) and second gate lines (GL21~GL2k). The first gate lines (GL11~GL1k) and the second gate lines (GL21~GL2k) may be arranged alternately along the scanning direction (or along the extension direction of the data lines (DL1~DLm). For example, the first gate lines (GL11~GL1k) may be odd-numbered gate lines connected to pixels (PX) arranged in odd-numbered pixel rows, and the second gate lines (GL21~GL2k) may be even-numbered gate lines connected to pixels (PX) arranged in even-numbered pixel rows. In this case, k may be n / 2.

[0081] The gate driving unit (320) of FIG. 3 may include a first gate driving unit (421) and a second gate driving unit (422).

[0082] The first gate driver (421) can generate a first gate signal (e.g., a gate signal of the turn-on level) based on a first gate control signal (GCS1) (or, a first scan control signal) and sequentially provide the first gate signal to the first gate lines (GL11~GL1k). For example, the first gate driver (421) can provide the first gate signal to the pixel (PX) through the first i gate line (GL1i). The first gate control signal (GCS1) includes a first start signal and a first clock signal, etc., and may be provided from the timing control unit (340). The first gate driver (421) may include a shift register (or, stage) that sequentially outputs a first gate signal in the form of a pulse corresponding to the first start signal using the first clock signal.

[0083] Similarly, the second gate driver (422) can generate a second gate signal (e.g., a gate signal at the turn-on level) based on the second gate control signal (GCS2) (or, the second scan control signal) and sequentially provide the second gate signal to the second gate lines (GL21 to GL2k). For example, the second gate driver (422) can provide the second gate signal to the pixel (PX) through the secondi gate line (GL2i). The second gate control signal (GCS2) includes a second start signal and a second clock signal, etc., and may be provided from the timing control unit (340). The second gate driver (422) may include a shift register (or, stage) that sequentially outputs a second gate signal in the form of a pulse corresponding to the second start signal using the second clock signal.

[0084] In one embodiment, the gate driver (320) of FIG. 3 may further include a third gate driver (423) and a fourth gate driver (424).

[0085] As illustrated in FIG. 5, the first gate driving unit (421) and the second gate driving unit (422) may be positioned adjacent to one side of the display unit (110), and the third gate driving unit (423) and the fourth gate driving unit (424) may be positioned adjacent to the other side of the display unit (110). However, this is not limited thereto.

[0086] The third gate driver (423) can generate a third gate signal based on the third gate control signal (GCS3) and sequentially provide the third gate signal to the first gate lines (GL11~GL1k). Except for the placement location, the third gate driver (423) may be substantially identical or similar to the first gate driver (421). The third gate control signal (GCS3) and the third gate signal may be substantially identical to the first gate control signal (GCS1) and the first gate signal, respectively. When the mutually substantially identical first gate signal and third gate signal are provided to the left and right ends of the first gate lines (GL11~GL1k), the signal delay of the first gate signal and the third gate signal may be mitigated.

[0087] Similarly, the fourth gate driver (424) can generate a fourth gate signal based on the fourth gate control signal (GCS4) and sequentially provide the fourth gate signal to the second gate lines (GL21–GL2k). Except for the placement location, the fourth gate driver (424) may be substantially identical or similar to the second gate driver (422). The fourth gate control signal (GCS4) and the fourth gate signal may be substantially identical to the second gate control signal (GCS2) and the second gate signal, respectively.

[0088] In one embodiment, in a first mode, while the first gate driver (421) (and the third gate driver (423)) provides a first gate signal to the first gate lines (GL11–GL1k), the second gate driver (422) (and the fourth gate driver (424)) may provide a second gate signal to the second gate lines (GL11–GL1k). For example, the first gate driver (421) and the second gate driver (422) may alternately output the first gate signal and the second gate signal. Accordingly, the display panel (310) may be driven in a sequential scanning manner.

[0089] In one embodiment, in a second mode, a first gate driver (421) (and a third gate driver (423)) may provide a first gate signal to the first gate lines (GL11 to GL1k), and thereafter, a second gate driver (422) (and a fourth gate driver (424)) may provide a second gate signal to the second gate lines (GL11 to GL1k). For example, after the first gate driver (421) provides the first gate signal to the first-k gate line (GL1k), the second gate driver (422) may provide the second gate signal to the second-1 gate line (GL21). Accordingly, the display panel (310) may be driven in an interlaced scanning manner.

[0090] FIG. 6 is a drawing showing an embodiment of a gate driver included in the display device of FIG. 4. Since the gate drivers (421–424) are substantially identical or similar to one another, for convenience of explanation, the first gate driver (421) is shown in FIG. 6. The common features of the gate drivers (421–424) of FIG. 4 and FIG. 5 will be explained with a focus on the first gate driver (421).

[0091] Referring to FIGS. 4, 5, and 6, the first gate driver (421) may include stages (ST1 to STk). The stages (ST1 to STk) may each provide first gate signals to the first gate lines (GL11 to GL1k).

[0092] Each of the stages (ST1~STk) may include an input terminal (IN0), a first clock input terminal (IN1), a second clock input terminal (IN2), and an output terminal (OUT). Each of the stages (ST1~STk) includes at least one transistor and a capacitor, and the internal circuit configurations of the stages (ST1~STk) may be substantially identical to one another.

[0093] Each of the stages (ST1~STk) of the first gate driver (421) can be connected to a first clock signal line (CLKL1) and a second clock signal line (CLKL2). Clock signals from a timing control unit (340, see FIG. 4) can be applied to the first clock signal line (CLKL1) and the second clock signal line (CLKL2). As will be described later with reference to FIG. 8, the second clock signal applied to the second clock signal line (CLKL2) has a delayed phase compared to the first clock signal applied to the first clock signal line (CLKL1); for example, the second clock signal may have a phase delayed by 180 degrees compared to the first clock signal (or an inverted phase). Meanwhile, a first start signal (or a first start pulse) from a timing control unit (340, see FIG. 4) can be applied to the first start signal line (FLML1).

[0094] For example, in the first stage (ST1) (or odd-numbered stage) of the first gate driver (421), the first clock input terminal (IN1) may be connected to the first clock signal line (CLKL1), and the second clock input terminal (IN2) may be connected to the second clock signal line (CLKL2). In the second stage (ST2) (or the k-th stage (STk), even-numbered stage) of the first gate driver (421), the first clock input terminal (IN1) may be connected to the second clock signal line (CLKL2), and the second clock input terminal (IN2) may be connected to the first clock signal line (CLKL1).

[0095] Each of the stages (ST1~STk) of the first gate driving unit (421) is connected to the first start signal line (FLML1) or the output terminal (OUT) of the previous stage, and can generate a first gate signal corresponding to the first start signal provided through the first start signal line (FLML1) and the previous gate signal of the previous stage.

[0096] For example, the input terminal (IN0) of the first stage (ST1) of the first gate driver (421) may be connected to the first start signal line (FLML1). The first stage (ST1) of the first gate driver (421) may generate a first gate signal corresponding to the start signal applied to the first start signal line (FLML1) (for example, the first start signal is delayed by half a cycle of the first clock signal). For example, the input terminal (IN0) of the second stage (ST2) may be connected to the output terminal (OUT) (or the first gate line (GL1)) of the first stage (ST1). Similarly, the input terminal (IN0) of the nth stage (STn) may be connected to the output terminal (or the nth gate line) of the n-1st stage.

[0097] That is, the stages (ST1~STk) of the first gate driving unit (421) can sequentially generate first gate signals corresponding to the first start signal.

[0098] Similarly, the second gate driver (422) may include stages (ST1 to STk). The stages (ST1 to STk) may each provide second gate signals to the second gate lines (GL21 to GL2k).

[0099] Each of the stages (ST1~STk) of the second gate driver (422) can be connected to the third clock signal line (CLKL3) and the fourth clock signal line (CLKL4). As will be described later with reference to FIG. 8, the fourth clock signal applied to the fourth clock signal line (CLKL4) has a delayed phase compared to the third clock signal applied to the third clock signal line (CLKL3). For example, the fourth clock signal may have a phase delayed by 180 degrees compared to the third clock signal (or an inverted phase). Meanwhile, a second start signal (or a second start pulse) may be applied to the second start signal line (FLML2) from the timing control unit (340, see FIG. 4).

[0100] The connection configuration between the stages (ST1~STk) of the second gate driver (422) and the third and fourth clock signal lines (CLK3, CLK4) may be substantially the same or similar to the connection configuration between the stages (ST1~STk) of the first gate driver (421) and the first and second clock signal lines (CLK1, CLK2).

[0101] Each of the stages (ST1~STk) of the second gate driving unit (422) is connected to the second start signal line (FLML2) or the output terminal (OUT) of the previous stage, and can generate a second gate signal corresponding to the start signal provided through the second start signal line (FLML2) and the previous gate signal of the previous stage.

[0102] For example, the input terminal (IN0) of the first stage (ST1) of the second gate driver (422) can be connected to the second start signal line (FLML2). The first stage (ST1) of the second gate driver (422) can generate a second gate signal corresponding to the start signal applied to the second start signal line (FLML2).

[0103] That is, the stages (ST1~STk) of the second gate driving unit (422) can sequentially generate second gate signals corresponding to the second start signal.

[0104] FIG. 7 is a diagram illustrating the operation of the display device of FIG. 4 in the first mode.

[0105] Referring to FIGS. 1 through 7, a first start signal (FLM1) is provided to a first start signal line (FLML1, see FIG. 6), a second start signal (FLM2) is provided to a second start signal line (FLML2, see FIG. 6), and a data signal (DATA) (or data voltage) may be provided to data lines (DL1 to DLm).

[0106] In the first mode, a frame (or frame period) may include an active period and a blank period (or porch period). A frame may be a period for displaying a single frame image. In the active period, a data signal (DATA) has a valid value and may be provided to or written to a pixel (PX, see FIG. 4). A blank period is a period allocated between the active period and the active period of a subsequent frame, in which the data signal (DATA) is not provided or does not have a valid value.

[0107] In the first mode, the first start signal (FLM1) and the second start signal (FLM2) can have turn-on pulses substantially simultaneously, for example, with only a difference of about one horizontal time. Accordingly, in the active period, the first gate driver (421) can sequentially provide the first gate signal to the first gate lines (GL11~GL1k, see FIG. 4), and simultaneously with the sequential provision of the first gate signal, the second gate driver (422) can sequentially provide the second gate signal to the second gate lines (GL21~GL2k, see FIG. 4). That is, gate signals can be sequentially provided to the gate lines (GL1~GLn).

[0108] Meanwhile, in the blank section (BLANK), the sensor unit (120, see FIG. 1) (and sensor driving unit (220), see FIG. 1) is driven and can detect touch input. For example, in the blank section (BLANK), the sensor driving unit (220) can receive or sample a sensing signal output through the sensor unit (120). As previously explained, when the sensor unit (120) (and sensor driving unit (220)) is driven to detect touch input in the active section (ACTIVE), interference may occur in the display unit (110, see FIG. 1), and the display quality may be degraded due to said interference. Therefore, the detection operation for touch input is not performed in the active section (ACTIVE), and the detection operation for touch input may be performed in the blank section (BLANK).

[0109] FIGS. 8 and 9 are drawings illustrating the operation of the first and second gate drivers of FIG. 4 in the first mode. FIGS. 8 and 9 illustrate mutually different embodiments of clock signals (CLK1 to CLK4).

[0110] Referring to FIGS. 1 through 9, a first clock signal (CLK1) may be provided to a first clock signal line (CLKL1, see FIG. 6), a second clock signal (CLK2) may be provided to a second clock signal line (CLKL2, see FIG. 6), a third clock signal (CLK3) may be provided to a third clock signal line (CLKL3, see FIG. 6), and a fourth clock signal (CLK4) may be provided to a fourth clock signal line (CLKL4, see FIG. 6). As illustrated in FIGS. 8 and 9, the clock signals (CLK1 to CLK4) may have mutually different phases. The second clock signal (CLK2) has a waveform that is delayed by half of the first period (CC1) of the first clock signal (CLK1) (or delayed by 180 degrees), and the fourth clock signal (CLK4) may have a waveform that is delayed by half of the first period (CC1) of the third clock signal (CLK3). The third clock signal (CLK3) may have a waveform that is delayed by a quarter of the first period (CC1) of the first clock signal (CLK1) (or delayed by 90 degrees). As illustrated in FIG. 8, the width of the turn-on pulse of the clock signals (CLK1–CLK4) (i.e., the first pulse width (PW1)) may be half of the first period (CC1) of the clock signals (CLK1–CLK4) (or 2 horizontal times). In this case, the gate signals of the gate lines (GL1–GLn) may partially overlap. However, it is not limited to this. For example, as illustrated in FIG. 9, the width of the turn-on pulse of the clock signals (CLK1 to CLK4) (i.e., the first pulse width (PW1)) may be less than 1 / 2 of the first period (CC1) of the clock signals (CLK1 to CLK4), or less than or equal to 1 / 4 (or 1 horizontal time). In this case, the gate signals of the gate lines (GL1 to GLn) may be non-overlapping.

[0111] At the first reference point (TP01), the first start signal (FLM1) can transition from a turn-off level to a turn-on level. In FIG. 8, the turn-on level is shown as a high level and the turn-off level as a low level, but this is an example based on an n-type transistor and is not limited thereto. For example, based on a p-type transistor, the turn-on level may be a low level and the turn-off level may be a high level.

[0112] In this case, depending on the operation of the first gate driver (421, see FIG. 6) based on the first start signal (FLM1) and the first and second clock signals (CLK1, CLK2), a gate signal (or pulse) of a turn-on level may be sequentially provided to the first gate lines (GL11~GL1k) (or odd-numbered gate lines, i.e., the first gate line (GL1), the third gate line (GL3), ..., the n-1 gate line (GLn-1)) during the active period (ACTIVE). For example, a gate signal may be applied to the first gate line (GL1) (or the eleventh gate line (GL11)) at the first time point (TP1), and a gate signal may be applied to the third gate line (GL3) (or the twelfth gate line (GL12)) at the third time point (TP3).

[0113] At the second reference point (TP02), the second start signal (FLM2) may transition from a turn-off level to a turn-on level. The second reference point (TP02) may be a point within half of the first period (CC1) of the clock signals (CLK1~CLK4) from the first reference point (TP01) (e.g., a point after 1 horizontal time). The second reference point (TP02) may be included in the same interval as the first reference point (TP01) (e.g., the active interval).

[0114] In this case, depending on the operation of the second gate driver (422, see FIG. 6) based on the second start signal (FLM2) and the third and fourth clock signals (CLK3, CLK4), a gate signal (or pulse) of a turn-on level may be sequentially provided to the second gate lines (GL21~GL2k) (or even gate lines, i.e., the second gate line (GL2), the fourth gate line (GL4), ..., the nth gate line (GLn)). For example, a gate signal may be applied to the second gate line (GL2) (or the 21st gate line (GL21)) at the second time point (TP2), and a gate signal may be applied to the fourth gate line (GL4) (or the 22nd gate line (GL22)) at the fourth time point (TP4).

[0115] Meanwhile, a touch scan operation can be performed in the blank section (BLANK). As described with reference to FIG. 7, the sensor unit (120, see FIG. 1) (and sensor driving unit (220, see FIG. 1)) is driven in the blank section (BLANK) and can detect a touch input.

[0116] FIG. 10 is a diagram illustrating the operation of the display device of FIG. 4 in the second mode.

[0117] Referring to FIGS. 1 through 10, in the second mode, a frame may include a first active section (ACTIVE1) (or, first section), a first blank section (BLANK1) (or, second section), a second active section (ACTIVE2) (or, third section), and a second blank section (BLANK2) (or, fourth section) arranged sequentially. The first active section (ACTIVE1), the first blank section (BLANK1), the second active section (ACTIVE2), and the second blank section (BLANK2) may not overlap each other. The size (or time) of the frame in the second mode may be substantially the same as the size of the frame in the first mode. For example, the frame in the first mode may be 1 / 120th of a second, and likewise, the frame in the second mode may also be 1 / 120th of a second. That is, the refresh rate of the video in the second mode may be the same as the refresh rate of the video in the first mode. However, this is not limited thereto, and for example, the size of the frame in the second mode may be smaller than the size of the frame in the first mode.

[0118] Each of the first active section (ACTIVE1) and the second active section (ACTIVE2) is similar to the active section (ACTIVE) of FIG. 7, and the total time of the first active section (ACTIVE1) and the second active section (ACTIVE2) may be substantially the same as the time of the active section (ACTIVE) of FIG. 7. The first blank section (BLANK1) and the second blank section (BLANK2) are similar to the blank section (BLANK) of FIG. 7, and the total time of the first blank section (BLANK1) and the second blank section (BLANK2) may be substantially the same as the time of the blank section (BLANK) of FIG. 7.

[0119] In the first active section (ACTIVE1), a first interlaced scan operation (e.g., a scan operation for odd-numbered gate lines) is performed, and in the second active section (ACTIVE2), a second interlaced scan (e.g., a scan operation for even-numbered gate lines) can be performed.

[0120] To this end, in the second mode, the first start signal (FLM1) and the second start signal (FLM2) may have turn-on pulses at mutually different intervals. For example, the first start signal (FLM1) may have a turn-on pulse at the start of the first active interval (ACTIVE1) or at the end of the second blank interval (BLANK2), and the second start signal (FLM2) may have a turn-on pulse at the start of the second active interval (ACTIVE2) or at the end of the first blank interval (BLANK1).

[0121] Accordingly, in the first active section (ACTIVE1), the first gate driver (421) can sequentially provide the first gate signal to the first gate lines (GL11~GL1k, see FIG. 4), and in the second active section (ACTIVE2), the second gate driver (422) can sequentially provide the second gate signal to the second gate lines (GL21~GL2k, see FIG. 4).

[0122] Meanwhile, a detection operation for touch input can be performed in each of the first blank section (BLANK1) and the second blank section (BLANK2). For example, in each of the first blank section (BLANK1) and the second blank section (BLANK2), a sensor unit (120, see FIG. 1) (and a sensor driving unit (220), see FIG. 1) is driven and can detect touch input. That is, the driving cycle of the sensor unit (120, see FIG. 1) (and the sensor driving unit (220), see FIG. 1) in the second mode may be different from the driving cycle in the first mode. For example, the driving cycle in the second mode may be shorter than the driving cycle in the first mode, and the number of touch input detections (or, report rate) in the second mode may be greater than the number of touch input detections in the first mode.

[0123] Accordingly, the display device (1, see FIG. 1) can perform a detection operation for touch input at a higher driving frequency while maintaining the refresh rate of the image and avoiding interference with the display unit (110, see FIG. 1) (and the resulting degradation of display quality). In addition, unlike the sequential scanning method in the first mode, an interlaced scanning method is used in the second mode, so the degradation of display quality (see FIG. 13) that occurs when a sequential scanning method is applied to the second mode can be prevented.

[0124] FIG. 11 is a diagram illustrating the operation of the first and second gate drivers of FIG. 4 in the second mode.

[0125] Referring to FIGS. 1 to 11, the first clock signal (CLK1) and the second clock signal (CLK2) have pulses in the first active interval (ACTIVE1), and may or may not have pulses in the remaining intervals (e.g., the first blank interval (BLANK1), the second active interval (ACTIVE2), and the second blank interval (BLANK2)). For example, in the first blank interval (BLANK1), the second active interval (ACTIVE2), and the second blank interval (BLANK2), the first clock signal (CLK1) and the second clock signal (CLK2) may be maintained at a turn-off level or a turn-on level to reduce power consumption.

[0126] Similarly, the third clock signal (CLK3) and the fourth clock signal (CLK4) have pulses in the second active interval (ACTIVE2), and may or may not have pulses in the remaining intervals (e.g., the first active interval (ACTIVE1), the first blank interval (BLANK1), and the second blank interval (BLANK2)). For example, in the first active interval (ACTIVE1), the first blank interval (BLANK1), and the second blank interval (BLANK2), the third clock signal (CLK3) and the fourth clock signal (CLK4) may be maintained at a turn-off level or a turn-on level to reduce power consumption.

[0127] In the second mode, the second period (CC2) (or second frequency) of the clock signals (CLK1~CLK4) may be different from the first period (CC1) (or first frequency) of the clock signals (CLK1~CLK4) in the first mode. For example, the second period (CC2) of the clock signals (CLK1~CLK4) in the second mode may be half the first period (CC1) of the clock signals (CLK1~CLK4) in the first mode, or the second frequency of the clock signals (CLK1~CLK4) in the second mode may be twice the first frequency of the clock signals (CLK1~CLK4) in the first mode. However, it is not limited thereto. Additionally, the width of the turn-on pulse of the clock signals (CLK1~CLK4) in the second mode (i.e., the second pulse width (PW2)) may be smaller than or equal to the first pulse width (PW1) of the clock signals (CLK1~CLK4) in the first mode. For example, the second pulse width (PW2) may be smaller than the first pulse width (PW1) of FIG. 8 or equal to the first pulse width (PW1) of FIG. 9.

[0128] At the 10th time point (TP10) (or, the 1st reference time point), the 1st start signal (FLM1) may transition from a turn-off level to a turn-on level. The 10th time point (TP10) may be included in the 1st active interval (ACTIVE1), but is not limited thereto.

[0129] In this case, depending on the operation of the first gate driver (421, see FIG. 6) based on the first start signal (FLM1) and the first and second clock signals (CLK1, CLK2), a gate signal (or pulse) of a turn-on level may be sequentially provided to the first gate lines (GL11~GL1k) (or odd-numbered gate lines, i.e., the first gate line (GL1), the third gate line (GL3), ..., the n-1 gate line (GLn-1)) in the first active period (ACTIVE1). For example, a gate signal may be applied to the first gate line (GL1) (or the first gate line (GL11)) at the 11th time point (TP11), and a gate signal may be applied to the third gate line (GL3) (or the 12th gate line (GL12)) at the 12th time point (TP12).

[0130] Subsequently, at the 20th time point (TP20) (or, the 2nd reference time point), the 2nd start signal (FLM2) may transition from a turn-off level to a turn-on level. The 20th time point (TP20) is included in a different interval from the 10th time point (TP10), for example, it may be included in the 2nd active interval (ACTIVE2).

[0131] In this case, depending on the operation of the second gate driver (422, see FIG. 6) based on the second start signal (FLM2) and the third and fourth clock signals (CLK3, CLK4), a gate signal (or pulse) of a turn-on level may be sequentially provided to the second gate lines (GL21~GL2k) (or even gate lines, i.e., the second gate line (GL2), the fourth gate line (GL4), ..., the nth gate line (GLn)) in the second active period (ACTIVE2). For example, a gate signal may be applied to the second gate line (GL2) (or the 21st gate line (GL21)) at the 21st time point (TP21), and a gate signal may be applied to the fourth gate line (GL4) (or the 22nd gate line (GL22)) at the 22nd time point (TP22).

[0132] Meanwhile, a touch scan operation can be performed in the first blank section (BLANK1) and the second blank section (BLANK2). As described with reference to FIG. 10, the sensor unit (120, see FIG. 1) (and sensor driving unit (220, see FIG. 1)) is driven in the first blank section (BLANK1) and the second blank section (BLANK2) and can detect a touch input.

[0133] FIG. 12 is a diagram illustrating an embodiment of the operation of the display device of FIG. 1. FIG. 12 shows some signals centered on the mode switching between the first mode and the second mode of the display device (1) of FIG. 1.

[0134] Referring to FIGS. 1 to 12, a touch signal (TS) may indicate whether there is interaction between a display device (1, see FIG. 1) (or an application processor (30, see FIG. 1)) and an external input device (e.g., a stylus pen, e.g., an active electrostatic (AES) pen) or whether touch input is detected. For example, a high-level touch signal (TS) may indicate or indicate that the display device (1) is interacting with or is activated with an external input device, and a low-level touch signal (TS) may indicate or indicate that the display device (1) is not interacting with or is deactivated with an external input device. As another example, a high-level touch signal (TS) may indicate or indicate that touch input is detected through a sensor unit (120, see FIG. 1), and a low-level touch signal (TS) may indicate or indicate that touch input is not detected through a sensor unit (120).

[0135] When the touch signal (TS) has a low level or is maintained, the display device (1, see FIG. 1) may perform a mode switch from the second mode to the first mode or maintain the first mode. When the touch signal (TS) changes from a high level to a low level, the display device (1) may perform a mode switch from the second mode to the first mode in a subsequent frame.

[0136] As described with reference to FIGS. 7 through 9, in the first mode, the display device (1) can operate in a sequential scanning manner. To this end, the first start signal (FLM1) and the second start signal (FLM2) may have turn-on pulses substantially simultaneously, for example, with only a difference of about one horizontal time. Corresponding to the sequential scanning method, during the frame, the data signal (DATA) may sequentially have voltages corresponding to the order of pixel rows (for example, a first voltage corresponding to the first pixel row, a second voltage corresponding to the second pixel row, a third voltage corresponding to the third pixel row, and a fourth voltage corresponding to the fourth pixel row).

[0137] In the first mode, the frame includes a blank section, and a touch scan operation can be performed in the blank section.

[0138] When the touch signal (TS) has a high level or is maintained, the display device (1) may perform a mode switch from the first mode to the second mode or maintain the second mode. When the touch signal (TS) changes from a low level to a high level, the display device (1) may perform a mode switch from the first mode to the second mode in the subsequent frame.

[0139] As described with reference to FIGS. 10 and FIGS. 11, in the second mode, the display device (1) may operate in an interlaced scanning manner. To this end, at a time when about half of the frame has elapsed from the time when the first start signal (FLM1) has a turn-on pulse, the second start signal (FLM2) may have a turn-on pulse. In accordance with the interlaced scanning method, the data signal (DATA) may sequentially have voltages corresponding to odd-numbered pixel rows (e.g., voltages corresponding to the first, third, fifth, and seventh pixel rows) during the first half of the frame, and sequentially have voltages corresponding to even-numbered pixel rows (e.g., voltages corresponding to the second, fourth, sixth, and eighth pixel rows) during the second half of the frame. For interlaced scanning, the period of the clock signal (CLK) in the second mode (i.e., the clock signals (CLK1 to CLK4, see FIG. 8, FIG. 9, FIG. 11)) can be shorter than the period of the clock signal (CLK) in the first mode.

[0140] In the second mode, the frame includes two blank sections, and a touch scan operation can be performed in the blank sections.

[0141] As described above, the display device (1) performs mode switching between a first mode and a second mode based on whether it interacts with an external input device or whether a touch input occurs, and can vary the number of blank sections (i.e., sections where a touch scan operation can be performed) within a single frame. Accordingly, the display device (1) can detect touch input at a higher driving frequency and display the touch input results more quickly and naturally. In addition, the display device (1) can operate in a sequential scanning method in the first mode and an interlaced scanning method in the second mode by changing the position of the second start signal (FLM2) and the period of the clock signal (CLK) according to the first mode and the second mode. Accordingly, a degradation of display quality can be prevented.

[0142] FIG. 13 is a drawing showing embodiments of an image displayed on the display device of FIG. 1.

[0143] Referring to FIGS. 1 to 13, the first image (IMAGE1) schematically represents an image displayed on a display device according to a comparative embodiment, and the second image (IMAGE2) may represent an image displayed on the display device (1) of FIG. 1.

[0144] The display device according to the comparative embodiment is assumed to operate only in the second mode described with reference to FIG. 10. As described with reference to FIG. 10, a first blank section (BLANK1) may be inserted between the first active section (ACTIVE1) and the second active section (ACTIVE2). When the display device displays an image (e.g., a video) with many frame-to-frame transitions, horizontal lines may be visible along the horizontal direction in the first image (IMAGE1) of the first mode due to the latency corresponding to the interlaced scan (and the first blank section (BLANK1)).

[0145] The display device (1) according to the embodiments of the present invention operates in a sequential scanning method rather than an interlaced scanning method in the first mode, so that horizontal lines can be prevented from being visible, as in the second image (IMAGE2). In addition, when touch input (especially handwriting using a stylus pen) occurs, a still image rather than a video is generally displayed, so horizontal lines may not be visible in the second mode either.

[0146] FIG. 14 is a circuit diagram showing an example of a pixel included in the display device of FIG. 1. For convenience of explanation, FIG. 14 shows a pixel (PXnm) located on the nth horizontal line (or nth pixel row) and connected to the mth data line (Dm).

[0147] Referring to FIGS. 1 and 2, a pixel (PXnm) may be electrically connected to a write gate line (GWLn), an initialization gate line (GILn), a compensation gate line (GCLn), light emission control lines (EMLn) (or, light emission gate line), and a bias control line (GBLn) (or, bias gate line, bypass control line). Each of the write gate line (GWLn), the initialization gate line (GILn), the compensation gate line (GCLn), the light emission control lines (EMLn), and the bias control line (GBLn) may correspond to the gate line (GL) of FIG. 1. The write gate line (GWLn), the initialization gate line (GILn), the compensation gate line (GCLn), the light emission control lines (EMLn), and the bias control line (GBLn) are named to distinguish them from one another according to the use of the signal (or, gate signal), and all of the lines may be substantially identical or similar signal transmission lines.

[0148] The pixel (PXnm) may include transistors (M1~M8), a storage capacitor (Cst), and a light-emitting element (LD).

[0149] The first electrode of the first transistor (M1) is connected to the second node (N2), the second electrode of the first transistor (M1) is connected to the third node (N3), and the gate electrode of the first transistor (M1) can be connected to the first node (N1). The first transistor (M1) may be named a driving transistor. The first transistor (M1) can control the amount of current flowing from the first power supply line (VDD) to the second power supply line (VSS) via the light-emitting element (LD) in response to the voltage of the first node (N1).

[0150] The first electrode of the second transistor (M2) is connected to the data line (DLm), the second electrode of the second transistor (M2) is connected to the first electrode (or second node (N2)) of the first transistor (M1), and the gate electrode of the second transistor (M2) can be connected to the write gate line (GWLn). The second transistor (M2) can be named a switching transistor. The second transistor (M2) can be turned on when a write gate signal is supplied to the write gate line (GWLn) to electrically connect the data line (DLm) and the first electrode of the first transistor (M1).

[0151] The first electrode of the third transistor (M3) is connected to the gate electrode (or, the first node (N1)) of the first transistor (M1), the second electrode of the third transistor (M3) is connected to the second electrode (or, the third node (N3)) of the first transistor (M1), and the gate electrode of the third transistor (M3) can be connected to the compensation gate line (GCLn). The third transistor (M3) may be named a compensation transistor. The third transistor (M3) can be turned on when a compensation gate signal is supplied to the compensation gate line (GCLn) to electrically connect the first node (N1) and the third node (N3). Thus, when the third transistor (M3) is turned on, the first transistor (M1) can be connected in the form of a diode.

[0152] The first electrode of the fourth transistor (M4) is connected to the gate electrode (or the first node (N1)) of the first transistor (M1), the second electrode of the fourth transistor (M4) is connected to the first initialization line (VINTL1) (or the third power line), and the gate electrode of the fourth transistor (M4) can be connected to the initialization gate line (GILn). The fourth transistor (M4) may be named the initialization transistor. The fourth transistor (M4) can be turned on when an initialization gate signal is supplied to the initialization gate line (GILn) to connect the first node (N1) to the first initialization line (VINTL1).

[0153] The first electrode of the fifth transistor (M5) is connected to the first power supply line (VDD), the second electrode of the fifth transistor (M5) is connected to the first electrode (or the second node (N2)) of the first transistor (M1), and the gate electrode of the fifth transistor (M5) can be connected to the light-emitting gate line (EMLn). The fifth transistor (M5) can be named the first light-emitting transistor.

[0154] The first electrode of the sixth transistor (M6) is connected to the second electrode (or third node (N3)) of the first transistor (M1), the second electrode of the sixth transistor (M6) is connected to the first electrode (or anode electrode) of the light-emitting element (LD), and the gate electrode of the sixth transistor (M6) can be connected to the light-emitting gate line (EMLn). The sixth transistor (M6) can be named the second light-emitting transistor.

[0155] The fifth transistor (M5) and the sixth transistor (M6) can be turned off when a light-emitting gate signal of the turn-off level is supplied to the light-emitting gate line (EMLn), and can be turned on when a light-emitting gate signal of the turn-on level is supplied to the light-emitting gate line (EMLn).

[0156] The first electrode of the seventh transistor (M7) is connected to the first electrode of the light-emitting element (LD), the second electrode of the seventh transistor (M7) is connected to the second initialization line (VINTL2) (or the fourth power line), and the gate electrode of the seventh transistor (M7) can be connected to the bias control line (GBLn). The seventh transistor (M7) may be named a bias transistor. The seventh transistor (M7) can be turned on when a bias gate signal is supplied to the bias control line (GBLn) to connect the first electrode of the light-emitting element (LD) to the second initialization line (VINTL2).

[0157] The first electrode of the eighth transistor (M8) is connected to the second node (N2), the second electrode of the eighth transistor (M8) is connected to the bias power line (VBIAS), and the gate electrode of the eighth transistor (M8) can be connected to the bias control line (GBLn). The eighth transistor (M8) can be turned on when a bias gate signal is supplied to the bias gate line (GBLn) to connect the second node (N2) to the bias power line (VBIAS). When the voltage of the bias power line (VBIAS) is periodically applied to the second node (N2) (or the first electrode of the first transistor (M1)), the first transistor (M1) can continuously maintain a specific on-bias state and control the amount of driving current flowing to the light-emitting element (LD) to be substantially constant. Depending on the operation of the eighth transistor (M8), the pixel (PXnm) emits light with a constant brightness regardless of the driving frequency (or refresh rate) of the display device (1, see FIG. 1), and the pixel (PXnm) can also operate at a high frequency.

[0158] A storage capacitor (Cst) may be formed or connected between a first power supply line (VDD) and the gate electrode (or, a first node (N1)) of a first transistor (M1). For example, the first electrode of the storage capacitor (Cst) may be connected to the first power supply line (VDD), and the second electrode of the storage capacitor (Cst) may be connected to the gate electrode of the first transistor (M1). The storage capacitor (Cst) may store a voltage corresponding to a data voltage and a threshold voltage of the first transistor (M1) (for example, a voltage in which the threshold voltage of the first transistor (M1) is reflected in the data voltage).

[0159] The first electrode of the light-emitting element (LD) is connected to the second electrode of the sixth transistor (M6), and the second electrode (or cathode electrode) of the light-emitting element (LD) can be connected to the second power supply line (VSS). The light-emitting element (LD) can generate light of a predetermined brightness in response to the current supplied from the first transistor (M1).

[0160] The light-emitting element (LD) may be composed of an organic light-emitting diode or an inorganic light-emitting diode such as a micro LED or a quantum dot light-emitting diode. Additionally, the light-emitting element (LD) may be a light-emitting element composed of a combination of organic and inorganic materials. Although FIG. 3 illustrates a pixel (PXnm) comprising a single light-emitting element (LD), in other embodiments, the pixel (PXnm) may comprise a plurality of light-emitting elements, and the plurality of light-emitting elements may be connected to each other in series, parallel, or series-parallel.

[0161] The voltage applied to the first power supply line (VDD) can be set to be greater than the voltages applied to the first initialization line (VINTL1), the second initialization line (VINTL2), and the second power supply line (VSS).

[0162] The first, second, fifth, sixth, seventh, and eighth transistors (M1, M2, M5, M6, M7, M8) may be P-type transistors. The channels of the first, second, fifth, sixth, seventh, and eighth transistors (M1, M2, M5, M6, M7, M8) may be composed of polysilicon. The polysilicon transistors may be LTPS (low temperature polysilicon) transistors. The polysilicon transistors have high electron mobility and consequently fast driving characteristics.

[0163] The third and fourth transistors (M3, M4) may be N-type transistors. The channels of the third and fourth transistors (M3, M4) may be composed of oxide semiconductors. Oxide semiconductor transistors have lower charge mobility compared to polysilicon. Therefore, the amount of leakage current occurring in the turn-off state of oxide semiconductor transistors is smaller than that of polysilicon transistors.

[0164] FIG. 15 is a drawing showing an embodiment of the gate driving unit of FIG. 3. For convenience of explanation, a display panel (310) is additionally shown in FIG. 15 in addition to the gate driving unit.

[0165] Referring to FIGS. 1 through 6 and FIG. 15, to drive the pixel (PXnm) of FIG. 14, the gate driver (320, see FIG. 3) may include first gate drivers (521 to 525). Additionally, as described with reference to FIG. 4 and FIG. 5, the gate driver (320, see FIG. 3) may further include second gate drivers (621 to 625).

[0166] The first gate driving units (521 to 525) are arranged adjacent to one side of the display panel (310), and each of the first gate driving units (521 to 525) may include the first gate driving unit (421) and the second gate driving unit (422) of FIG. 5.

[0167] The second gate driving units (621 to 625) are arranged adjacent to the other side of the display unit (110), and each of the second gate driving units (621 to 625) may include the third gate driving unit (423) and the fourth gate driving unit (424) of FIG. 5.

[0168] Each of the first write gate driver (521) and the second write gate driver (621) can generate a write gate signal as described with reference to FIG. 14 based on the first write start signal (GW_FLM1) and the second write start signal (GW_FLM2).

[0169] Each of the first initialization gate driver (522) and the second initialization gate driver (622) can generate an initialization gate signal as described with reference to FIG. 14 based on the first initialization start signal (GI_FLM1) and the second initialization start signal (GI_FLM2).

[0170] Each of the first compensation gate driver (523) and the second compensation gate driver (623) can generate a compensation gate signal as described with reference to FIG. 14 based on the first compensation start signal (GC_FLM1) and the second compensation start signal (GC_FLM2).

[0171] Each of the first bias gate driver (524) and the second bias gate driver (624) can generate a bias gate signal as described with reference to FIG. 14 based on the first bias start signal (GB_FLM1) and the second bias start signal (GB_FLM2).

[0172] Each of the first light-emitting gate driver (525) and the second light-emitting gate driver (625) can generate a light-emitting gate signal as described with reference to FIG. 14 based on the first light-emitting start signal (EM_FLM1) and the second light-emitting start signal (EM_FLM2).

[0173] As described above, the gate driver includes first gate drivers (521 to 525), and in order to selectively use a sequential scanning method and an interlaced scanning method, each of the first gate drivers (521 to 525) may be implemented by including the first gate driver (421) and the second gate driver (422) of FIG. 5.

[0174] FIG. 16 is a drawing showing another embodiment of the display device of FIG. 3.

[0175] Referring to FIGS. 1, FIGS. 3, FIGS. 4, and FIGS. 16, the display device (1) of FIG. 16 may be substantially the same or similar to the display device (1) of FIG. 4, except for the first and second gate drivers (421_1, 422_1). Therefore, redundant descriptions will not be repeated.

[0176] The display panel (310) may include a first display area (DA1) (or, first area) and a second display area (DA2) (or, second area). The first display area (DA1) and the second display area (DA2) may be separated from each other along the scanning direction (or along the extension direction of the data lines (DL1~DLm)).

[0177] The gate lines (GL1~GLn) of FIG. 3 may include third gate lines (GL1~GLk, where k is a positive integer less than or equal to n) and fourth gate lines (GLk+1~GLn) corresponding to the first display area (DA1) and the second display area (DA2). In one embodiment, k may be n / 2. However, k is not limited thereto.

[0178] For example, the third gate lines (GL1~GLk) may include a first gate line (GL1), an i-th gate line (GLi), and a k-th gate line (GLk) arranged sequentially in correspondence with the first display area (DA1). The third gate lines (GL1~GLk) may be connected to a pixel (PX) of the first display area (DA1).

[0179] The fourth gate lines (GLk+1 to GLn) may include the k+1 gate line (GLk+1), the k+i gate line (GLk+i), and the n gate line (GLn) arranged sequentially in correspondence with the second display area (DA2). The fourth gate lines (GLk+1 to GLn) may be connected to a pixel (PX) of the second display area (DA2).

[0180] The gate driving unit (320) of FIG. 3 may include a first gate driving unit (421_1) and a second gate driving unit (422_1).

[0181] The first gate driver (421_1) can generate a first gate signal (e.g., a gate signal at the turn-on level) based on a first gate control signal (GCS1) (or, a first scan control signal) and sequentially provide the first gate signal to the third gate lines (GL1~GLk). The first gate control signal (GCS1) includes a first start signal and a first clock signal, etc., and may be provided from the timing control unit (340). The first gate driver (421_1) may include a shift register (or, stage) that sequentially outputs a first gate signal in the form of a pulse corresponding to the first start signal using the first clock signal (see FIG. 6).

[0182] Similarly, the second gate driver (422_1) can generate a second gate signal (e.g., a gate signal at the turn-on level) based on a second gate control signal (GCS2) (or, a second scan control signal) and sequentially provide the second gate signal to the fourth gate lines (GLk+1 to GLn). The second gate control signal (GCS2) may include a second start signal and a second clock signal, etc., and may be provided from the timing control unit (340). The second gate driver (422) may include a shift register (or, stage) that sequentially outputs a second gate signal in the form of a pulse corresponding to the second start signal using the second clock signal (see FIG. 6).

[0183] According to the embodiment, the embodiment of FIG. 5 may be applied to the embodiment of FIG. 16. For example, the gate driver (320) of FIG. 3 may further include a third gate driver and a fourth gate driver located on the other side of the display panel (310) (i.e., the side opposite to the one side of the display panel (310) where the first gate driver (421_1) and the second gate driver (422_1) are located). In this case, the third gate driver and the fourth gate driver can perform the same function as the first gate driver (421_1) and the second gate driver (422_1), respectively.

[0184] In one embodiment, in a first mode, the first gate driver (421_1) and the second gate driver (422_1) can continuously provide gate signals to the gate lines (GL1~GLn).

[0185] In one embodiment, in a second mode, the first gate driver (421_1) and the second gate driver (422_1) may provide gate signals discontinuously to the gate lines (GL1 to GLn). For example, the first gate driver (421_1) may provide a first gate signal to the third gate lines (GL1 to GLk), and after a certain amount of time has elapsed, the second gate driver (422_1) may provide a second gate signal to the fourth gate lines (GLk+1 to GLn).

[0186] FIG. 17 is a diagram illustrating the operation of the display device of FIG. 16 in the first mode.

[0187] Referring to FIGS. 1, FIGS. 7, FIGS. 16, and FIGS. 17, the first start signal (FLM1), the second start signal (FLM2), and the data signal (DATA) may be substantially identical or similar to the first start signal (FLM1), the second start signal (FLM2), and the data signal (DATA) of FIG. 7, respectively. Therefore, redundant descriptions will not be repeated.

[0188] In the first mode, the frame may include a first active section (ACTIVE1), a second active section (ACTIVE2), and a blank section (BLANK). In the first mode, the first active section (ACTIVE1) and the second active section (ACTIVE2) are adjacent, and no separate section (e.g., a blank section (BLANK)) is allocated between the first active section (ACTIVE1) and the second active section (ACTIVE2).

[0189] In the first active section (ACTIVE1), the first start signal (FLM1) has a turn-on pulse, and the first gate driver (421_1) can sequentially provide the first gate signal to the third gate lines (GL1~GLk, see FIG. 16).

[0190] In the second active period (ACTIVE2), the second start signal (FLM2) has a turn-on pulse, and the second gate driver (422_1) can sequentially provide the second gate signal to the fourth gate lines (GLk+1 to GLn, see FIG. 16). In particular, at the end of the first active period (ACTIVE1), the second start signal (FLM2) has a turn-on pulse, and accordingly, the gate signal can be provided to the gate lines (GL1 to GLn) substantially without interruption (or continuously).

[0191] Meanwhile, in the blank section (BLANK), the sensor unit (120, see FIG. 1) (and the sensor driving unit (220), see FIG. 1) is driven and can detect touch input. For example, in the blank section (BLANK), the sensor driving unit (220) can receive or sample a sensing signal output through the sensor unit (120).

[0192] FIG. 18 is a diagram illustrating the operation of the display device of FIG. 16 in the second mode.

[0193] Referring to FIGS. 1, FIG. 10, and FIGS. 16 through 18, in the second mode, a FRAME may include a first active section (ACTIVE1) (or, first section), a first blank section (BLANK1) (or, second section), a second active section (ACTIVE2) (or, third section), and a second blank section (BLANK2) (or, fourth section) arranged sequentially. Since the first active section (ACTIVE1), the first blank section (BLANK1), the second active section (ACTIVE2), and the second blank section (BLANK2) of FIG. 18 are substantially identical or similar to the first active section (ACTIVE1), the first blank section (BLANK1), the second active section (ACTIVE2), and the second blank section (BLANK2) of FIG. 10, redundant descriptions will not be repeated.

[0194] The first start signal (FLM1) may have a turn-on pulse at the start of the first active period (ACTIVE1) or at the end of the second blank period (BLANK2).

[0195] In order to prevent a display operation from being performed during the first blank period (BLANK1), the second start signal (FLM2) may have a turn-on pulse after a certain amount of time has elapsed from the end of the first active period (ACTIVE1), rather than at the end of the first active period (ACTIVE1). For example, the second start signal (FLM2) may have a turn-on pulse after the first blank period (BLANK1) has elapsed from the end of the first active period (ACTIVE1), that is, at the start of the second active period (ACTIVE2) or at the end of the first blank period (BLANK1).

[0196] A detection operation for touch input can be performed in each of the first blank section (BLANK1) and the second blank section (BLANK2). For example, in each of the first blank section (BLANK1) and the second blank section (BLANK2), a sensor unit (120, see FIG. 1) (and a sensor driving unit (220), see FIG. 1) is driven and can detect touch input. That is, the driving cycle of the sensor unit (120, see FIG. 1) (and the sensor driving unit (220), see FIG. 1) in the second mode may be different from the driving cycle in the first mode. For example, the driving cycle in the second mode may be shorter than the driving cycle in the first mode, and the number of touch input detections (or, report rate) in the second mode may be greater than the number of touch input detections in the first mode.

[0197] Accordingly, the display device (1, see FIG. 1) can perform a detection operation for touch input at a higher driving frequency while maintaining the refresh rate of the image and also avoiding interference with the display unit (110, see FIG. 1) (and the resulting degradation of display quality).

[0198] FIG. 19 is a drawing illustrating another embodiment of the operation of the display device of FIG. 1. FIG. 19 shows some signals centered on the mode switching between the first mode and the second mode of the display device (1) of FIG. 1.

[0199] Referring to FIGS. 1, FIGS. 12, and FIGS. 16 through 19, the touch signal (TS), the first start signal (FLM1), the second start signal (FLM2), and the data signal (DATA) of FIG. 19 are substantially identical or similar to the touch signal (TS), the first start signal (FLM1), the second start signal (FLM2), and the data signal (DATA) of FIG. 12, respectively, so redundant descriptions will not be repeated.

[0200] When the touch signal (TS) has a low level or is maintained, the display device (1, see FIG. 1) can perform a mode switch from the second mode to the first mode or maintain the first mode.

[0201] As described with reference to FIG. 17, in the first mode, the display device (1) can continuously output a gate signal. To this end, the first start signal (FLM1) and the second start signal (FLM2) may have a turn-on pulse in one interval (or one continuous active interval).

[0202] In the first mode, the frame includes a blank section, and a touch scan operation can be performed in the blank section.

[0203] When the touch signal (TS) has a high level or is maintained, the display device (1) can perform a mode switch from the first mode to the second mode or maintain the second mode.

[0204] As described with reference to FIG. 18, in the second mode, the display device (1) can output a gate signal discontinuously. To this end, at a time when about half of the frame has elapsed from the time when the first start signal (FLM1) has a turn-on pulse, the second start signal (FLM2) can have a turn-on pulse.

[0205] In the second mode, the frame includes two blank sections, and a touch scan operation can be performed in the blank sections.

[0206] The size (or time) of a frame in the second mode may be substantially the same as the size of a frame in the first mode. For example, a frame in the first mode may be 1 / 120th of a second, and likewise, a frame in the second mode may also be 1 / 120th of a second. That is, the refresh rate of the video in the second mode may be the same as the refresh rate of the video in the first mode.

[0207] As described above, the display device (1) performs mode switching between a first mode and a second mode based on whether it interacts with an external input device or whether a touch input occurs, and can vary the number of blank sections (i.e., sections where a touch scan operation can be performed) within a single frame. Accordingly, the display device (1) detects the touch input at a higher driving frequency and can display the touch input result more quickly and naturally.

[0208] FIG. 20 is a drawing showing embodiments of an image displayed on the display device of FIG. 1.

[0209] Referring to FIGS. 1, FIGS. 13, FIGS. 16 to 20, the third image (IMAGE3) schematically represents an image displayed on a display device according to a comparative embodiment, and the second image (IMAGE2) may represent an image displayed on the display device (1) of FIG. 1.

[0210] The display device according to the comparative embodiment is assumed to operate only in the second mode described with reference to FIG. 18. As described with reference to FIG. 18, a first blank section (BLANK1) may be inserted between the first active section (ACTIVE1) and the second active section (ACTIVE2). When the display device displays an image (e.g., a video) with many frame transitions, the third image (IMAGE3) of the first mode may be displayed discontinuously due to the latency corresponding to the first blank section (BLANK1).

[0211] The display device (1) according to the embodiments of the present invention performs a continuous scanning operation in the first mode, so it can resolve problems such as discontinuity of images, such as the second image (IMAGE2).

[0212] The drawings and detailed description of the invention referenced so far are merely exemplary of the invention and are used only for the purpose of explaining the invention, not to limit the meaning or the scope of the invention as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0213] 1: Display device 10: Panel 20: Driving circuit section 30: Application processor 110: Display unit 111: Display board 120: Sensor section 121: Sensor board 210: Display drive unit 220: Sensor drive unit 310: Display panel 320: Gate drive unit 330: Data driver 340: Timing control unit 421~424: Gate drivers 521~525: First gate drivers 621~625: Second gate drivers GL: Gate line PX: Pixel SC: Sensors

Claims

Claim 1 A display device comprising: a display panel including pixels connected to gate lines and data lines; a sensor disposed in overlap with the display panel; and a gate driver that provides a gate signal to the gate lines, wherein in a first mode, the gate driver provides the gate signal to the gate lines in an interlaced scanning manner, and in a second mode, the gate driver provides the gate signal in a progressive scanning manner, wherein the sensor operates in a section allocated between sections where the first interlaced scanning and the second interlaced scanning are performed within a single frame section, and when an input device linked to the sensor is activated, the gate driver operates in the second mode, and when the input device is deactivated, the gate driver operates in the first mode. Claim 2 A display device according to claim 1, wherein the gate lines include first gate lines and second gate lines, wherein the first gate lines and second gate lines are arranged alternately, and the gate driving unit includes: a first gate driving unit that sequentially provides a first gate signal to the first gate lines in response to a first start signal; and a second gate driving unit that sequentially provides a second gate signal to the second gate lines in response to a second start signal, wherein the first gate signal is sequentially provided to the first gate lines in a first section of a second mode, and the second gate signal is sequentially provided to the second gate lines in a second section of the second mode after the first section. Claim 3 A display device according to claim 2, wherein the first gate lines are odd-numbered gate lines and the second gate lines are even-numbered gate lines. Claim 4 A display device according to claim 2, wherein in the second mode, the pulse of the first start signal and the pulse of the second start signal occur in mutually different sections among the first to fourth sections. Claim 5 A display device according to claim 4, wherein in the first mode, the pulse of the first start signal and the pulse of the second start signal occur in mutually identical sections among the first to fourth sections. Claim 6 A display device according to claim 1, wherein when the sensor detects a touch input, the gate driving unit operates in the second mode, and when the sensor does not detect the touch input, the gate driving unit operates in the first mode. Claim 7 delete Claim 8 A display device according to claim 1, wherein the frame interval of the second mode includes a sequentially arranged first interval, second interval, third interval, and fourth interval, wherein the first interlaced scan is performed in the first interval, the second interlaced scan is performed in the third interval, and the sensor is operated in the second interval and the fourth interval. Claim 9 In claim 8, a display device wherein the second driving cycle of the sensor in the second mode is different from the first driving cycle of the sensor in the first mode. Claim 10 A display device according to claim 1, wherein the gate driving unit generates the gate signal based on a clock signal, and in the second mode, the second frequency of the clock signal is different from the first frequency of the clock signal in the first mode. Claim 11 A display device according to claim 10, wherein the second frequency of the clock signal in the second mode is greater than the first frequency of the clock signal in the first mode. Claim 12 A display device according to claim 11, wherein the pulse width of the clock signal in the second mode is the same as the pulse width of the clock signal in the first mode. Claim 13 A display device according to claim 11, wherein the pulse width of the clock signal in the second mode is different from the pulse width of the clock signal in the first mode. Claim 14 A display device according to claim 1, wherein the refresh rate of the image displayed through the display panel is the same in the first mode and the second mode. Claim 15 A display device comprising: a display panel including pixels connected to gate lines and data lines; a sensor disposed in overlap with the display panel; and a gate driver that provides a gate signal to the gate lines, wherein the gate lines are divided into first gate lines disposed in a first area of ​​the display panel and second gate lines disposed in a second area of ​​the display panel, wherein in a first mode, the gate driver provides a gate signal to the gate lines during a continuous section within a frame section, and the sensor does not operate during the continuous section, wherein in a second mode, the gate driver provides the gate signal to the first gate lines in a first section within a frame section and provides the gate signal to the second gate lines in a second section within a frame section, and the sensor operates in a third section between the first section and the second section, wherein when an input device linked to the sensor is activated, the gate driver operates in the second mode, and when the input device is deactivated, the gate driver operates in the first mode. Claim 16 A display device according to claim 15, wherein when the sensor detects a touch input, the gate driving unit operates in the second mode, and when the sensor does not detect the touch input, the gate driving unit operates in the first mode. Claim 17 delete Claim 18 A display device according to claim 15, wherein the frame interval of the second mode comprises the first interval, the second interval, the third interval, and the fourth interval arranged in sequence, wherein a scanning operation is performed in the first interval and the third interval, and the sensor operates in the second interval and the fourth interval. Claim 19 In claim 18, a display device wherein the second driving cycle of the sensor in the second mode is different from the first driving cycle of the sensor in the first mode. Claim 20 In claim 15, a display device in which the refresh rate of the image displayed through the display panel is the same in the first mode and the second mode.

Images