Semiconductor package and method of fabricating the same

Abstract

A method for manufacturing a semiconductor package is provided. The semiconductor package manufacturing method comprises placing a preliminary semiconductor package on a stage, the pre-packaging semiconductor package including a substrate having a pad portion attached, an interposer on the substrate, and a semiconductor chip between the substrate and the interposer, placing a bonding tool on the interposer such that a first surface facing the interposer includes a first region and a second region outside the first region, and arranging the bonding tool so that the second region corresponds to the pad portion to bond the interposer and the substrate.

Description

Technology Field

[0001] The present invention relates to a semiconductor package manufactured using a semiconductor substrate bonding device and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor package including an interposer and a method for manufacturing the same. Background Technology

[0002] Due to the development of the electronics industry, there is an increasing demand for high functionality, high speed, and miniaturization of electronic components. In response to this trend, methods may be utilized to mount multiple semiconductor chips by stacking them on a single package wiring structure, or to stack packages on top of each other. In this case, an interposer may be included between the upper package and the lower package to facilitate their electrical connection. The interposer facilitates the connection between the upper and lower packages and can prevent warpage between them.

[0003] To connect such an interposer and a lower package, the solder between the interposer and the lower package can be joined by TC bonding (Thermal Compression Bonding) by using a bonding tool to heat-compress.

[0004] Conventionally, in manufacturing such semiconductor packages, copper core balls may be used to connect and support the interposer and the underlying package. In this case, since separate processes are required to attach the copper core balls and solder to the interposer, there is an inefficiency due to an increase in the number of process steps. Additionally, there is a problem where component reliability is reduced as cracks occur in the copper core balls due to thermal compression. The problem to be solved

[0005] The technical problem to be solved by the present invention is to provide a method for manufacturing a semiconductor package that can bond an interposer and a substrate without using a copper core ball by arranging a protrusion formed in the outer region of a bonding tool and a pad formed on a lower package substrate so as to correspond to each other.

[0006] The technical problem to be solved by the present invention is to provide a semiconductor substrate bonding device capable of bonding an interposer and a substrate without using copper core balls by arranging a protrusion formed in the outer region of a bonding tool and a pad formed on a lower package substrate to correspond to each other.

[0007] The technical problem to be solved by the present invention is to provide a semiconductor package and a method for manufacturing the same that can minimize thermal deformation by forming a metallic pad portion on a lower package substrate.

[0008] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0009] A method for manufacturing a semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises placing a preliminary semiconductor package on a stage, the package including a substrate having a pad portion attached, an interposer on the substrate, and a semiconductor chip between the substrate and the interposer, placing a bonding tool on the interposer such that a first surface facing the interposer includes a first region and a second region outside the first region, and arranging the bonding tool so that the second region corresponds to the pad portion to bond the interposer and the substrate.

[0010] In addition, a semiconductor package manufacturing method according to some embodiments of the present invention for achieving the above technical problem comprises placing a preliminary semiconductor package on a stage, the pre-packaging of a substrate having a recess formed therein, an interposer on the substrate, and a semiconductor chip between the substrate and the interposer, placing a bonding tool on the interposer such that a first surface facing the interposer includes a first region and a second region outside the first region, and arranging the bonding tool so that the second region corresponds to the recess to bond the interposer and the substrate.

[0011] In addition, a semiconductor substrate bonding device according to some embodiments of the present invention for achieving the above technical problem comprises a substrate having a pad portion attached, a stage on which a preliminary semiconductor package including an interposer on the substrate and a semiconductor chip between the substrate and the interposer is loaded, and a bonding tool on the stage, wherein a first surface facing the interposer includes a first region and a second region outside the first region, and a protrusion protruding from the second region of the first surface, wherein the protrusion is spaced apart from the outer surface of the bonding tool.

[0012] In addition, a semiconductor substrate bonding device according to some embodiments of the present invention for achieving the above technical problem comprises a substrate having a pad portion attached, a stage on which a preliminary semiconductor package including an interposer on the substrate and a semiconductor chip between the substrate and the interposer is loaded, and a bonding tool extending on the stage in first and second directions intersecting each other, wherein a first surface facing the interposer includes a first region and a second region outside the first region, wherein the bonding tool includes a pair of first protrusions formed in the second region and facing each other in the first direction and a pair of second protrusions facing each other in the second direction.

[0013] The height of the first pair of protrusions and the height of the second pair of protrusions are different from each other.

[0014] Additionally, a semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises: a substrate having a recess formed at an edge that exposes at least one side, a pad portion disposed in the recess, and a first wiring layer spaced apart from the pad portion; an interposer disposed on the substrate and having a second wiring layer; a semiconductor chip disposed between the substrate and the interposer; and a connecting member electrically connecting the substrate and the interposer.

[0015] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0016] FIG. 1 is a schematic diagram showing a semiconductor substrate bonding apparatus used in the manufacture of a semiconductor package according to some embodiments of the present invention. FIG. 2 is a diagram for showing the positional relationship between a bonding unit constituting a semiconductor substrate bonding device and a substrate constituting a semiconductor package according to some embodiments of the present invention. FIG. 3 is a diagram illustrating the bonding relationship between a bonding unit constituting a semiconductor substrate bonding device and a substrate constituting a semiconductor package according to some embodiments of the present invention. FIG. 4 is a top view of the upper surface of a bonding tool constituting a semiconductor substrate bonding device according to some embodiments of the present invention. FIG. 5 is a drawing of the lower surface of a bonding tool constituting a semiconductor substrate bonding device according to some embodiments of the present invention, viewed from below. FIG. 6 is a drawing showing the lower surface of a bonding tool constituting a semiconductor substrate bonding device according to some embodiments of the present invention. FIG. 7 is a drawing showing the lower surface of a bonding tool constituting a semiconductor substrate bonding device according to some embodiments of the present invention. FIG. 8 is a drawing showing the lower surface of a bonding tool constituting a semiconductor substrate bonding device according to some embodiments of the present invention. FIG. 9 is a drawing showing the lower surface of a bonding tool constituting a semiconductor substrate bonding device according to some embodiments of the present invention. FIG. 10 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 11 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 12 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 13 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 14 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 15 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 16 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 17 is a schematic diagram showing the structure of a semiconductor package according to some embodiments of the present invention. FIG. 18 is a flowchart schematically illustrating a method for manufacturing a semiconductor package using a semiconductor substrate bonding device according to some embodiments of the present invention. Specific details for implementing the invention

[0017] Hereinafter, with reference to FIGS. 1 to 5, a semiconductor package according to several embodiments will be described.

[0018] FIG. 1 is a schematic diagram showing a semiconductor substrate bonding device used in the manufacture of a semiconductor package according to some embodiments of the present invention. FIG. 2 is a diagram showing the positional relationship between a bonding unit constituting a semiconductor substrate bonding device according to some embodiments of the present invention and a substrate constituting a semiconductor package. FIG. 3 is a diagram showing the coupling relationship between a bonding unit constituting a semiconductor substrate bonding device according to some embodiments of the present invention and a substrate constituting a semiconductor package. FIG. 4 is a top view of the upper surface of a bonding tool constituting a semiconductor substrate bonding device according to some embodiments of the present invention. FIG. 5 is a bottom view of the lower surface of a bonding tool constituting a semiconductor substrate bonding device according to some embodiments of the present invention.

[0019] According to FIG. 1, a semiconductor substrate bonding device (1000B) includes a bonding unit (700) and a vacuum unit (800). The bonding unit (700) may include a stage (710), a bonding tool (720), and a bonding head (730).

[0020] The semiconductor substrate bonding device (1000B) can be used to bond the solder between the interposer (200) and the substrate (100) by TC bonding (Thermal Compression Bonding) in order to connect the interposer (200) and the substrate (100) in the process of manufacturing a semiconductor package (1000A).

[0021] The semiconductor substrate bonding device (1000B) can be used when manufacturing a SiP (System in Package), for example, when manufacturing a HBM (High Bandwidth Memory) with a stack structure in which a TSV (Through Silicon Via) is applied.

[0022] The bonding head (730) can provide heat and pressure for thermal compression bonding. The bonding head (730) is installed at the top level of the semiconductor substrate bonding device (1000B) and can provide heat and pressure in a downward direction (a direction parallel to the third direction (Z)) to bond the interposer (200) located below it and the substrate (100).

[0023] The stage (710) is installed at the lowest level of the semiconductor substrate bonding device (1000B) and can support the bonding head (730) and bonding tool (720) installed on the upper part thereof. The stage (710) may be manufactured using a material capable of thermal conductivity and excellent heat resistance (e.g., ceramic), and may be formed to have a wider width in a first direction (X) or a second direction (Y) intersecting therefrom than the bonding head (730) and bonding tool (720).

[0024] The bonding tool (720) can press a preliminary semiconductor package (1000a) on the interposer (200) to bond the interposer (200) and the substrate (100). The bonding tool (720) can press the interposer (200) and the semiconductor chip (300) according to the heat and pressure applied from the upper bonding head (730).

[0025] The bonding tool (720) includes a flat plate (760) that extends in a first direction (X) and a second direction (Y), respectively. The flat plate (760) includes a first surface (760_1) facing the bonding head (730) and a second surface (760_2) facing the first surface (760_1). The first surface (760_1) may contact the bonding head (730), and the second surface (760_2) may contact the interposer (200).

[0026] The second surface (760_2) includes a first area (A1) that presses an area adjacent to the center of the interposer (200) and a second area (A2) that presses an edge area of ​​the interposer (200). To this end, the second area (A2) may be positioned to surround the first area (A1) at the periphery of the first area (A1).

[0027] The bonding tool (720) includes a plurality of holes (740) penetrating the bonding tool (720). The plurality of holes (740) may be vacuum holes that adsorb the interposer (200). The plurality of holes (740) may include a first hole (740_1) that adsorbs an area adjacent to the center of the interposer (200) and a second hole (740_2) that adsorbs an area adjacent to the edge of the interposer (200). The second hole (740_2) may be positioned in the bonding tool (720) to surround the first hole (740_1) at the periphery of the first hole (740_1). Through this, the plurality of holes (740) can stably adsorb the interposer (200).

[0028] Multiple holes (740) can be formed on the first surface (760_1) and the second surface (760_2) of the bonding tool (720) so as to correspond to each other in the third direction (Z). The multiple holes (740) can adsorb the interposer (200) through the first vacuum line (741) formed on the first surface (760_1) of the bonding tool (720) and the second vacuum line (742) formed on the second surface (760_2) of the bonding tool (720).

[0029] Multiple holes (740) can adsorb the interposer (200) together with the hole (731) formed in the bonding head (730). The multiple holes (740) and the hole (731) of the bonding head (730) can be connected to a vacuum unit (800). The vacuum unit (800) can control the process of the bonding unit (700) adsorbing the pre-semiconductor package (1000a).

[0030] The bonding tool (720) includes a protrusion (750) formed in the second area (A2) and protruding from the second surface (760_2) of the flat plate (760). Referring to FIG. 10, the thickness (T) of the protrusion (750) may be equal to the distance between the first surface (100_1) of the substrate (100) and the second surface (760_2) of the flat plate (760).

[0031] The protrusion (750) may include a pair of first protrusions (751_1, 751_2) facing each other in a first direction (X) and a pair of second protrusions (752_1, 752_2) facing each other in a second direction (Y). Each of the pair of first protrusions (751_1, 751_2) may extend along the second direction (Y), and each of the pair of second protrusions (752_1, 752_2) may extend along the first direction (X). The length of each of the pair of second protrusions (752_1, 752_2) extending along the first direction (X) may be smaller than the length of the bonding tool (720) extending along the first direction (X). However, this is not limited thereto, and the length of each of the pair of second protrusions (752_1, 752_2) extending along the first direction (X) may be the same as the length of the bonding tool (720) extending along the first direction (X).

[0032] The thickness of a pair of first protrusions (751_1, 751_2) may each be the same, and the thickness of a pair of second protrusions (752_1, 752_2) may each be the same. On the other hand, the thickness of a pair of first protrusions (751_1, 751_2) and the thickness of a pair of second protrusions (752_1, 752_2) may be different from each other.

[0033] The protrusion (750) of the bonding tool (720) may be formed integrally with the flat portion (760). The flat portion (760) and the protrusion (750) of the bonding tool (720) may be manufactured using a material capable of heat conduction and excellent heat resistance, similar to the bonding head (730). For example, the bonding tool (720) may include aluminum nitride (AlN) or silicon carbide (SiC). However, it is not limited thereto.

[0034] Hereinafter, a semiconductor substrate bonding apparatus according to several embodiments of the present invention will be described with reference to FIGS. 6 to 9. For convenience of explanation, the description will focus on the differences from the semiconductor substrate bonding apparatus illustrated in FIGS. 1 to 5.

[0035] FIG. 6 is a drawing showing the lower surface of a bonding tool constituting a semiconductor substrate bonding device according to some embodiment of the present invention. FIG. 7 is a drawing showing the lower surface of a bonding tool constituting a semiconductor substrate bonding device according to some embodiment of the present invention. FIG. 8 is a drawing showing the lower surface of a bonding tool constituting a semiconductor substrate bonding device according to some embodiment of the present invention. FIG. 9 is a drawing showing the lower surface of a bonding tool constituting a semiconductor substrate bonding device according to some embodiment of the present invention.

[0036] Referring to FIG. 6, a pair of first protrusions (751_1, 751_2) may be less than 1 / 3 of the length of the bonding tool (720). Specifically, the length (L1) of the pair of first protrusions (751_1, 751_2) extending along the second direction (Y) may be less than 1 / 3 of the length (L2) of the bonding tool (720) extending along the second direction (Y). In this case, electrical interference caused by the pair of first protrusions (751_1, 751_2) and the substrate (100) adjacent in the first direction (X) can be minimized.

[0037] Referring to FIG. 7, a pair of first protrusions (751_1, 751_2) may be spaced apart from the outer surface of the bonding tool (720). Specifically, a pair of first protrusions (751_1, 751_2) may be spaced apart by a predetermined distance (d) along a first direction (X) from the outer surface of the bonding tool (720). In this case, electrical interference caused by a substrate (100) adjacent to the pair of first protrusions (751_1, 751_2) in the first direction (X) can be minimized.

[0038] Referring to FIG. 8, a pair of first protrusions (751_1, 751_2) and a pair of second protrusions (752_1, 752_2) may be arranged to extend to the outer surface of the bonding tool (720). In this case, the protrusions (750) may be arranged in a second area (A2) to surround the second surface (760_2) of the bonding tool (720). The protrusions (750) may form a closed loop shape on the second surface (760_2).

[0039] However, this is not limited thereto, and each of the pair of first protrusions (751_1, 751_2) and the pair of second protrusions (752_1, 752_2) may be formed spaced apart from each other in the corner area of ​​the second surface (760_2). Additionally, the pair of first protrusions (751_1, 751_2) may be spaced apart by a predetermined distance (d) along the first direction (X) from the outer surface of the bonding tool (720), and the pair of second protrusions (752_1, 752_2) may be extended to reach the pair of first protrusions (751_1, 751_2) of the bonding tool (720). In this case, the pair of second protrusions (752_1, 752_2) may not reach the corner area of ​​the second surface (760_2).

[0040] Referring to FIG. 9, the length of a pair of first protrusions (751_1, 751_2) extending along the second direction (Y) is less than or equal to 1 / 3 of the length of a bonding tool (720) extending along the second direction (Y), and at the same time, the pair of first protrusions (751_1, 751_2) may be spaced apart from the outer circumference of the second surface (760_2). In this case, electrical interference caused by the pair of first protrusions (751_1, 751_2) and a substrate (100) adjacent in the first direction (X) can be minimized.

[0041] Hereinafter, a semiconductor substrate bonding apparatus according to several embodiments of the present invention will be described with reference to FIGS. 10 to 16. For convenience of explanation, the description will focus on the differences from the semiconductor substrate bonding apparatus and semiconductor package illustrated in FIGS. 1 to 5.

[0042] FIG. 10 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 11 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 12 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 13 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 14 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 15 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention. FIG. 16 is a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments of the present invention.

[0043] FIGS. 10 to 16 are drawings corresponding to a schematic diagram showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments cut along I-I' of FIG. 2.

[0044] Referring to FIG. 10, a preliminary semiconductor package (1000a) includes a substrate (100) to which a pad portion (130) is attached, an interposer (200) on the substrate (100), and a semiconductor chip (300) between the substrate (100) and the interposer (200). Additionally, the preliminary semiconductor package (1000a) may further include preliminary connection members (410, 420) that electrically connect the substrate (100) and the interposer (200).

[0045] The substrate (100) includes a first surface (100_1) facing the interposer (200) on which a semiconductor chip (300) is mounted, and a second surface (100_2) facing the first surface (100_1).

[0046] The pad portion (130) may be positioned to correspond to the second area (A2) of the bonding tool (720). Additionally, the protrusion (750) and the pad portion (130) may come into direct contact with each other. In some embodiments, corresponding means being positioned in a straight line along a direction parallel to the third direction (Z). However, in some embodiments, being positioned in a straight line does not mean only being positioned in a physical or mathematical straight line, but may include cases where alignment errors occur due to partial protrusion in the first direction (X) or the second direction (Y). However, even in such cases, the protrusion (750) and the pad portion (130) may each be positioned in an area that overlaps with the second area (A2).

[0047] A pad portion (130) is disposed in a recess (R1) formed at the edge of a substrate (100) to expose at least a portion of the inner surface of the substrate (100). Referring to FIG. 2, the recess (R1) includes a side wall (R1_S) that exposes at least a portion of the inner surface of the substrate (100) in the edge region of the substrate (100), and a bottom surface (R1_B) connected to the side wall (R1_S). The pad portion (130) may be disposed on the side wall (R1_S) and the bottom surface (R1_B) of the recess. The width of the pad portion (130) may be the same as the width of the recess (R1) of the substrate (100).

[0048] In some embodiments, the edge region of the substrate (100) may mean a region corresponding to the second region (A2) of the bonding tool (720). That is, the edge region of the substrate (100) may be a region that overlaps with the second region (A2) of the bonding tool (720).

[0049] The pad portion (130) includes a pair of first pad portions (131_1, 131_2) facing each other in a first direction (X) and a pair of second pad portions (132_1, 132_2) facing each other in a second direction (Y). A pair of first pad portions (131_1, 131_2) correspond to a pair of first protrusions (751_1, 751_2), and a pair of second pad portions (132_1, 132_2) may correspond to a pair of second protrusions (752_1, 752_2).

[0050] In this case, the thickness of a pair of first pad portions (131_1, 131_2) may be the same, and the thickness of a pair of second pad portions (132_1, 132_2) may be the same. Additionally, the thickness of a pair of first pad portions (131_1, 131_2) and the thickness of a pair of second pad portions (132_1, 132_2) may be different from each other. That is, the protrusions (750) and pad portions (130) facing each other in a first direction (X) or a second direction (Y) may have the same thickness and width.

[0051] The upper surface of the pad portion (130) may be positioned on the same surface as the first surface (100_1) of the substrate (100). Additionally, the upper surface of the pad portion (130) may be positioned at a lower height than the first surface (100_1) of the substrate (100). For example, the pad portion (130) may be formed with a thickness (t1) of 200 μm or less from the first surface (100_1) of the substrate (100). However, it is not limited thereto.

[0052] The pad portion (130) may include a metallic material. For example, the pad portion (130) may include copper (Cu) or non-ferrous metals other than copper. However, it is not limited thereto. If the pad portion (130) includes a metallic material, deformation of the substrate (100) due to heat and pressure during TC bonding can be minimized.

[0053] Although not specifically illustrated, the pad portion (130) may be formed by exposing and / or developing the substrate (100) using a mask formed on the substrate (100). However, the method of forming the pad portion (130) is not limited thereto.

[0054] Referring to FIG. 11, a pair of first protrusions (751_1, 751_2) may be spaced apart from the outer surface of the bonding tool (720). That is, the pair of first protrusions (751_1, 751_2) may be positioned inward by a predetermined distance (d) from the outer surface of the bonding tool (720) along the first direction (X). In this case, electrical interference caused by the pair of first protrusions (751_1, 751_2) and the substrate (100) adjacent in the first direction (X) can be minimized.

[0055] Referring to FIG. 12, the pad portion (130) includes at least one bend portion. The pad portion (130) includes a recess (R2) having a bottom surface (R2_B) in contact with a pair of first protrusions (751_1, 751_2) and a side wall (R2_S) connected to the bottom surface (R2_B). The bend portion may be formed on the recess (R2). In this case, as the thickness of the pad portion (130) decreases, the thickness of the pair of first protrusions (751_1, 751_2) may increase compared to FIG. 10.

[0056] Referring to FIG. 13, the pad portion (130) includes at least one bend portion. In this case, a multi-stage recess (R3) is formed in the substrate (100), and the bend portion may be disposed on the multi-stage recess (R3).

[0057] Referring to FIG. 14, the thickness (t1) of the pad portion (130) may be smaller than the thickness (t2) of the substrate (100). That is, the upper surface of the pad portion (130) may be positioned lower than the upper surface of the substrate (100). In this case, as the thickness of the pad portion (100) decreases, the thickness of the first protrusions (751_1, 751_2) may increase compared to FIG. 10.

[0058] Referring to FIG. 15, the pad portion (130) may not be positioned at the bottom of the first protrusion (751_1, 751_2) but may be positioned on the side of the first protrusion (751_1, 751_2). That is, the pad portion (130) may not be in contact with the bottom surface of the first protrusion (751_1, 751_2) but may be in contact with the side of the first protrusion (751_1, 751_2).

[0059] The width (W1) of the pad portion (130) may be smaller than the width (W2) of the recess of the substrate (100). In this case, the first protrusion (751_1, 751_2) may come into contact with one side of the substrate (100) exposed by the recess of the substrate (100).

[0060] A preliminary semiconductor package (1000a), which is a large-area product, is formed by the semiconductor substrate bonding device (1000B) described above. Below, a preliminary semiconductor package (1000b), which is a small-area product, formed by the semiconductor substrate bonding device (1000B) will be described.

[0061] Referring to FIG. 16, a preliminary semiconductor package (1000b) and a plurality of pad portions (130a, 130b, 130c, 130d, 130e) may be disposed on a substrate (100). The preliminary semiconductor package (1000b) includes a substrate (100) to which a plurality of pad portions (130a, 130b, 130c, 130d, 130e) are attached, an interposer (200) on the substrate (100), and a plurality of semiconductor chips (300a, 300b, 300c, 300d, 300e) between the substrate (100) and the interposer (200). Additionally, the preliminary semiconductor package (1000b) may further include a plurality of preliminary connection members (400a, 400b, 400c, 400d, 400e) that electrically connect the substrate (100) and the interposer (200). Each of the plurality of pad portions (130a, 130b, 130c, 130d, 130e) may be disposed between a plurality of semiconductor chips (300a, 300b, 300c, 300d, 300e).

[0062] In this case, after the substrate (100) and the interposer (200) are bonded by TC bonding, the preliminary semiconductor package (1000b) can be divided into a plurality of semiconductor packages. Except for the fact that each divided semiconductor package is a small-area product, the description of the semiconductor package (1000A) of FIG. 17 described later can be applied in the same way.

[0063] Meanwhile, FIGS. 10 to 16 may be drawings corresponding to schematic diagrams showing the structure of a semiconductor substrate bonding device and a preliminary semiconductor package according to some embodiments cut along II-II' of FIG. 2. In this case, the description of FIGS. 10 to 16 described above may be applied in the same way.

[0064] Referring to FIG. 17, a semiconductor package (1000A) manufactured using a semiconductor substrate bonding device according to some embodiment includes a substrate (100), an interposer (200), a semiconductor chip (300), a connection member (400), and further includes a mold layer (500).

[0065] Referring to FIG. 3 and FIG. 17 together, a recess (R1) is formed at the edge of the substrate (100) to expose at least one side, and a pad portion (130) is disposed in the recess (R1). The description of the recess (R1) and the pad portion (130) can be likewise applied to the description of the recess (R1) and the pad portion (130) of the preliminary semiconductor package (1000a) of FIG. 1 to 16.

[0066] The substrate (100) includes a first insulating layer (110), a pad portion (130), and a first wiring layer (120) spaced apart from the pad portion (130).

[0067] The first insulating layer (110) may include an insulating film (111) and a passivation film (112) disposed below the insulating film (111). The insulating film (111) may be, for example, a printed circuit board (PCB) or a ceramic substrate. However, the technical concept of the present invention is not limited thereto.

[0068] The first wiring layer (120) may include a lower pad (122) exposed by a passivation film (112) and a plurality of wiring pads (121) electrically connected to the lower pad (122).

[0069] When the insulating film (111) is a printed circuit board, the insulating film (111) may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, the insulating film (111) may include at least one material selected from FR-4, tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, BT (bismaleimide triazine), thermount, cyanate ester, polyimide, and liquid crystal polymer.

[0070] The surface of the insulating film (111) may be covered by a solder resist. That is, the passivation film (112) formed on the surface of the insulating film (111) may be a solder resist. In this case, the passivation film (112) may include a photosensitive insulating material. However, it is not limited thereto.

[0071] A connection terminal (140) may be formed on the lower surface of the first insulating layer (110). The connection terminal (140) may be attached to the lower pad (122). The connection terminal (140) may be, for example, spherical or elliptical, but is not limited thereto. The connection terminal (140) may include, for example, at least one of tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations thereof, but is not limited thereto.

[0072] The connection terminal (140) can electrically connect the substrate (100) to an external device. Accordingly, the connection terminal (140) can provide an electrical signal to the substrate (100) or provide an electrical signal provided from the substrate (100) to the external device.

[0073] A semiconductor chip (300) may be placed on a substrate (100). For example, the semiconductor chip (300) may be mounted on the upper surface of the substrate (100). The semiconductor chip (300) may include an integrated circuit (IC) in which hundreds to millions or more semiconductor elements are integrated into a single chip. For example, the semiconductor chip (300) may be an application processor (AP) such as a CPU (Central Processing Unit), GPU (Graphic Processing Unit), FPGA (Field-Programmable Gate Array), digital signal processor, encryption processor, microprocessor, or microcontroller, but is not limited thereto. For example, the semiconductor chip (300) may be a logic chip such as an ADC (Analog-Digital Converter) or an ASIC (Application-Specific IC), or a memory chip such as volatile memory (e.g., DRAM) or non-volatile memory (e.g., ROM or flash memory). In addition, it goes without saying that the semiconductor chips (300) may be composed of a combination of these.

[0074] Although it is illustrated that only one semiconductor chip (300) is formed on the substrate (100), this is merely for convenience of explanation. For example, multiple semiconductor chips (300) may be formed side by side on the substrate (100), or multiple semiconductor chips (300) may be stacked sequentially on the substrate (100).

[0075] In this case, the semiconductor chip (300) may include a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip may include a first substrate on which a first semiconductor element is placed. The second semiconductor chip may include a second substrate on which a second semiconductor element is placed.

[0076] The second semiconductor chip and the first semiconductor chip can be electrically connected by a conductive structure penetrating the first substrate. For example, the conductive structure may be in the form of a copper-filled pillar (Cu post). However, the shape of the conductive structure is not limited to this.

[0077] Specifically, an insulating material is formed between the lower surface of the second substrate and the upper surface of the first substrate, and at least one coupling pad may be formed within the insulating material. The coupling pad can be coupled with a conductive structure to electrically connect the first semiconductor chip and the second semiconductor chip.

[0078] The semiconductor chip (300) can be mounted on the substrate (100) by a flip chip bonding method. For example, a bump (310) can be formed between the upper surface of the substrate (100) and the lower surface of the semiconductor chip (300). The bump (310) can electrically connect the substrate (100) and the semiconductor chip (300).

[0079] The bump (310) may include, for example, a pillar layer (312) and a solder layer (311).

[0080] The pillar layer (312) may protrude from the lower surface of the semiconductor chip (300). The pillar layer (312) may include, for example, copper (Cu), copper alloy, nickel (Ni), palladium (Pd), platinum (Pt), gold (Au), cobalt (Co), and combinations thereof, but is not limited thereto.

[0081] The solder layer (311) can connect the pillar layer (312) and the substrate (100). Although not specifically illustrated, the solder layer (311) may be electrically connected to some of the wiring layers (120). The solder layer (311) may be, for example, spherical or elliptical, but is not limited thereto. The solder layer (311) may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof, but is not limited thereto.

[0082] The interposer (200) may be placed on the upper surface of the substrate (100) and the semiconductor chip (300). The interposer (200) may be spaced apart from the substrate (100) and the semiconductor chip (300).

[0083] The interposer (200) includes a second insulating layer (210) and a second wiring layer (220). Although not specifically illustrated, the second insulating layer (210) may include an insulating film which is a printed circuit board (PCB) or a ceramic substrate. However, the technical concept of the present invention is not limited thereto. In some embodiments, the interposer (200) may include silicon (Si).

[0084] The second insulating layer (210) may include an insulating film and a passivation film disposed on the upper and lower portions of the insulating film. The passivation film formed on the surface of the insulating film may be a solder resist. The second wiring layer (220) may include a plurality of wiring pads disposed inside the second insulating layer (210).

[0085] The interposer (200) may include a plurality of protruding patterns (230). The protruding patterns (230) may function to maintain a constant distance between the interposer (200) and the semiconductor chip (300).

[0086] A connecting member (400) may be interposed between a substrate (100) and an interposer (200). The connecting member (400) may come into contact with the upper surface of the substrate (100) and the lower surface of the interposer (200). For example, the connecting member (400) may be electrically connected to the first wiring layer (120) of the substrate (100). Accordingly, the connecting member (400) may electrically connect the substrate (100) and the interposer (200).

[0087] The connecting member (400) may be, for example, spherical or elliptical, but is not limited thereto. The connecting member (400) may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof, but is not limited thereto.

[0088] A mold layer (500) can be formed on a substrate (100). The mold layer (500) can fill the space between the substrate (100) and the interposer (200). Accordingly, the mold layer (500) can cover and protect at least a portion of the substrate (100) and the semiconductor chip (300).

[0089] The mold layer (500) may include, for example, an insulating polymer material such as EMC (epoxy molding compound). The mold layer (500) may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin containing reinforcing materials such as fillers, for example, ABF, FR-4, BT resin, etc.

[0090] The filler may use at least one selected from the group consisting of silica (SiO2), alumina (Al2O3), silicon carbide (SiC), barium sulfate (BaSO4), talc, clay, mica powder, aluminum hydroxide (Al(OH)3), magnesium hydroxide (Mg(OH)2), calcium carbonate (CaCO3), magnesium carbonate (MgCO3), magnesium oxide (MgO), boron nitride (BN), aluminum borate (AlBO3), barium titanate (BaTiO3), and calcium zirconate (CaZrO3). However, the material of the filler is not limited thereto.

[0091] The underfill material (320) can cover the side of the bump (310). The underfill material (320) can prevent the semiconductor chip (300) from breaking by fixing the semiconductor chip (300) on the substrate (100). The underfill material (320) may include, for example, an insulating polymer material such as EMC (epoxy molding compound). However, it is not limited thereto, and the material of the underfill material (320) may include a material different from that of the mold layer (500).

[0092] FIG. 18 is a flowchart schematically illustrating a method for manufacturing a semiconductor package using a semiconductor substrate bonding apparatus according to some embodiments of the present invention. For convenience of explanation, the explanation will focus on the differences from the semiconductor substrate bonding apparatus, preliminary semiconductor package, and semiconductor package illustrated in FIGS. 1 to 17.

[0093] Referring to FIG. 1 and FIG. 18 together, a preliminary semiconductor package (1000a, 1000b) comprising a substrate (100) with a pad portion (130) attached, an interposer (200) on the substrate (100), and a semiconductor chip (300) between the substrate (100) and the interposer (200) is placed on a stage (710) (S1).

[0094] A bonding tool (720) is placed on the interposer (200), wherein the second surface (760_2) facing the interposer (200) includes a first region (A1) and a second region (A2) outside the first region (A1) (S2). The bonding tool (720) further includes a plurality of holes (740) penetrating the bonding tool (720), and the bonding tool (720) can adsorb the interposer (200) through the plurality of holes (740).

[0095] The second region (A2) of the bonding tool (720) is positioned to correspond to the pad portion (130) to bond the interposer (200) and the substrate (100) (S3). Here, bonding the interposer (200) and the substrate (100) can be performed by bonding the first preliminary connection member (410) formed on the substrate (100) and the second preliminary connection member (420) formed on the interposer (200) to each other using a TC bonding process.

[0096] The bonding tool (720) further includes a protrusion (750) formed in a second area (A2) and protruding from a second surface (760_2) of the bonding tool (720). In a planar view, the bonding tool (720) extends in a first direction (X) and a second direction (Y) intersecting the first direction (X), respectively, and the protrusion (750) includes a pair of first protrusions (751_1, 751_2) facing each other in the first direction (X) and a pair of second protrusions (752_1, 752_2) facing each other in the second direction (Y). The thickness of the pair of first protrusions (751_1, 751_2) may be the same, and the thickness of the pair of second protrusions (752_1, 752_2) may be the same. Referring to FIG. 7 and FIG. 11 together, with respect to the first direction (X), a pair of first protrusions (751_1, 751_2) may be spaced apart from the outer surface of the bonding tool (720).

[0097] The protrusion (750) contacts the pad portion (130). The thickness (T) of the protrusion (750) may be equal to the distance between the surface of the substrate (100) and the second surface (760_2).

[0098] The pad portion (130) includes a pair of first pad portions (131_1, 131_2) facing each other in a first direction (X) and a pair of second pad portions (132_1, 132_2) facing each other in a second direction (Y). A pair of first pad portions (131_1, 131_2) correspond to a pair of first protrusions (751_1, 751_2), and a pair of second pad portions (132_1, 132_2) may correspond to a pair of second protrusions (752_1, 752_2). The thickness of a pair of first pad portions (131_1, 131_2) and a pair of second pad portions (132_1, 132_2) may be different from each other. That is, a pair of first pad portions (131_1, 131_2) and a pair of second pad portions (132_1, 132_2) may be formed asymmetrically with respect to each other on the second surface (760_2) of the bonding tool (720) shown in FIGS. 5 to 9. However, even in this case, the pair of first pad portions (131_1, 131_2) and / or the pair of second pad portions (132_1, 132_2) may be formed symmetrically with respect to each other.

[0099] The pad portion (130) is placed in a recess (R1) formed at the edge of the substrate (100). That is, the second region (A2) of the bonding tool (720) may be placed to correspond to the recess (R1). In this case, the pad portion (130) may be formed with a thickness of 200 μm or less from the surface of the substrate (100). Referring to FIG. 12 and FIG. 13 together, the pad portion (130) may include at least one bend. The pad portion (130) may include a metallic material.

[0100] After separating the preliminary semiconductor packages (1000a, 1000b) from the bonding unit (700), the preliminary semiconductor packages (1000a, 1000b) are divided into semiconductor packages (1000A), each having a unit structure (S4). After removing all residual contaminants or cleaning materials for removing contaminants around the connection member (400), a mold layer (500) can be filled between the substrate (100) of the preliminary semiconductor packages (1000a, 1000b) and the interposer (200).

[0101] Dividing the preliminary semiconductor packages (1000a, 1000b) into semiconductor packages (1000A) may include dicing each semiconductor package (1000A) along the first direction (X) or second direction (Y) of the second vacuum line (742) shown in FIG. 5. In this case, at least a portion of the second vacuum line (742) may function as a dicing line.

[0102] By arranging the protrusion (750) formed in the outer region (A2) of the bonding tool (720) and the pad portion (130) formed on the substrate (100) so as to correspond to each other, the interposer (200) and the substrate (100) can be bonded without using copper core balls. As a result, the process of attaching copper core balls and solder balls to the interposer can be simplified. In addition, the problem of reduced reliability of the component due to cracks occurring in the copper core balls caused by thermal compression can be prevented. Furthermore, by forming a metallic pad portion (130) on the substrate (100), thermal deformation of the component can be minimized. This allows the gap between the substrate (100) and the interposer (200) to be maintained appropriately.

[0103] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0104] 100: Substrate 110: First insulating layer 120: 1st wiring layer 130: Pad section 200: Interposer 210: Second insulating layer 220: Second wiring layer 300: Semiconductor chip 310: Bump 320: Underfill material 400: Connection member 500: Mold layer 700: Bonding Unit 710: Stage 720: Bonding tool 730: Bonding head 740: Hole 750: Protrusion 760: Reputation Department 1000A: Semiconductor package 1000B: Semiconductor substrate bonding device

Claims

Claim 1 A method for manufacturing a semiconductor package comprising a substrate having a pad portion attached, an interposer on the substrate, and a semiconductor chip between the substrate and the interposer, wherein a pre-semiconductor package is placed on a stage, wherein a bonding tool is placed on the interposer such that a first surface facing the interposer includes a first region and a second region outside the first region, wherein the second region of the bonding tool is positioned to correspond to the pad portion to bond the interposer and the substrate, wherein a recess is formed at the edge of the substrate to expose at least a portion of the inner surface of the substrate, and wherein the pad portion is placed in the recess. Claim 2 A method for manufacturing a semiconductor package according to claim 1, wherein the bonding tool further comprises a protrusion formed in the second region and protruding from the first surface of the bonding tool, and the protrusion contacts the pad portion. Claim 3 A method for manufacturing a semiconductor package according to claim 1, wherein the bonding tool further comprises a plurality of holes penetrating the bonding tool, and the bonding tool adsorbs the interposer through the plurality of holes. Claim 4 delete Claim 5 A method for manufacturing a semiconductor package according to claim 1, wherein the pad portion comprises at least one bend portion. Claim 6 A method for manufacturing a semiconductor package according to claim 1, wherein the pad portion is formed with a thickness of 200 μm or less from the surface of the substrate. Claim 7 A method for manufacturing a semiconductor package according to claim 1, wherein the pad portion comprises a metal material. Claim 8 A semiconductor package manufacturing method according to claim 2, wherein the thickness of the protrusion is equal to the distance between the surface of the substrate and the first surface of the bonding tool. Claim 9 A method for manufacturing a semiconductor package according to claim 2, wherein, from a planar perspective, the bonding tool extends in a first direction and a second direction intersecting the first direction, respectively, and the protrusions include a pair of first protrusions facing each other in the first direction and a pair of second protrusions facing each other in the second direction, wherein the heights of the pair of first protrusions are each the same and the heights of the pair of second protrusions are each the same. Claim 10 A semiconductor package manufacturing method according to claim 9, wherein, with respect to the first direction, the pair of first protrusions are spaced apart from the outer surface of the bonding tool. Claim 11 A method for manufacturing a semiconductor package according to claim 9, wherein the pad portion comprises a pair of first pad portions facing each other in the first direction and a pair of second pad portions facing each other in the second direction, wherein the pair of first pad portions correspond to the pair of first protrusions and the pair of second pad portions correspond to the pair of second protrusions. Claim 12 A semiconductor package manufacturing method according to claim 11, wherein the height of the first pair of pad portions is different from the height of the second pair of pad portions. Claim 13 A method for manufacturing a semiconductor package, comprising a substrate having a recess formed therein, an interposer on the substrate, and a semiconductor chip between the substrate and the interposer, wherein a pre-semiconductor package is placed on a stage, a bonding tool is placed on the interposer such that a first surface facing the interposer includes a first region and a second region outside the first region, and the second region of the bonding tool is positioned to correspond to the recess to bond the interposer and the substrate. Claim 14 A method for manufacturing a semiconductor package according to claim 13, wherein the bonding tool further comprises a protrusion disposed to protrude from a first surface of the bonding tool and surround the first region. Claim 15 A method for manufacturing a semiconductor package according to claim 13, wherein the bonding tool further comprises a protrusion formed in the second region and protruding from the first surface of the bonding tool, and the substrate further comprises a pad portion formed in the recess. Claim 16 A method for manufacturing a semiconductor package according to claim 15, wherein, in a planar view, the bonding tool extends in a first direction and in a second direction intersecting the first direction, respectively, and the protrusions include a pair of first protrusions facing each other in the first direction and a pair of second protrusions facing each other in the second direction, wherein the heights of the pair of first protrusions are each the same and the heights of the pair of second protrusions are each the same. Claim 17 A semiconductor package manufacturing method according to claim 16, wherein, with respect to the first direction, the pair of first protrusions are spaced apart from the outer surface of the bonding tool. Claim 18 delete Claim 19 delete Claim 20 delete

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