Image sensor

Abstract

An image sensor according to the present invention comprises a semiconductor substrate including first to fourth pixel regions, wherein each of the first to fourth pixel regions includes first to fourth photoelectric conversion regions; and a pixel separation structure disposed within the semiconductor substrate and defining the first to fourth pixel regions, wherein the second pixel region is spaced apart from the first pixel region in a first direction, and the fourth pixel region is spaced apart from the first pixel region in a second direction intersecting the first direction, and the semiconductor substrate includes first impurity regions disposed in the central portions of the first to fourth pixel regions; and a second impurity region disposed between the second pixel region and the fourth pixel region, wherein the impurity doped in the first impurity regions may have a different conductivity type from the impurity doped in the second impurity region.

Description

Technology Field

[0001] The present invention relates to an image sensor, and more specifically, to an image sensor capable of auto-focusing (AF) operation. Background Technology

[0002] Image sensors convert optical images into electrical signals. Recently, with the development of the computer and telecommunications industries, there has been an increasing demand for high-performance image sensors in various fields, such as smartphones, wearable devices, digital cameras, PCS (Personal Communication System), gaming devices, security cameras, and medical micro cameras.

[0003] Image sensors include Charge Coupled Devices (CCDs) and CMOS image sensors. Among these, CMOS image sensors offer a simple driving method and allow for the integration of signal processing circuits onto a single chip, enabling product miniaturization. CMOS image sensors also consume very little power, making them suitable for applications with limited battery capacity. Consequently, the use of CMOS image sensors is rapidly increasing as technological advancements enable the realization of high resolutions. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide an image sensor having improved optical and electrical characteristics.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] To achieve the above-mentioned problem, an image sensor according to embodiments of the present invention comprises: a semiconductor substrate including first to fourth pixel regions, wherein each of the first to fourth pixel regions includes first to fourth photoelectric conversion regions; and a pixel separation structure disposed within the semiconductor substrate and defining the first to fourth pixel regions, wherein the second pixel region is spaced apart from the first pixel region in a first direction, and the fourth pixel region is spaced apart from the first pixel region in a second direction intersecting the first direction, and the semiconductor substrate includes first impurity regions disposed in the central portions of the first to fourth pixel regions; and a second impurity region disposed between the second pixel region and the fourth pixel region, wherein the impurity doped in the first impurity regions may have a different conductivity type from the impurity doped in the second impurity region.

[0007] To achieve the above-mentioned problem, an image sensor according to embodiments of the present invention comprises: a semiconductor substrate including first to fourth pixel regions, wherein each of the first to fourth pixel regions includes first to fourth photoelectric conversion regions; a pixel separation structure disposed within the semiconductor substrate and defining the first to fourth pixel regions; and auxiliary pixel separation structures provided within the semiconductor substrate and disposed at the center of each of the first to fourth pixel regions, wherein the second pixel region is spaced apart from the first pixel region in a first direction, and the fourth pixel region is spaced apart from the first pixel region in a second direction intersecting the first direction, and the semiconductor substrate includes first impurity regions disposed at the central portions of the first to fourth pixel regions; and a second impurity region disposed between the second pixel region and the fourth pixel region, wherein the auxiliary pixel separation structures are spaced apart from the pixel separation structures and may overlap perpendicularly with the first impurity regions.

[0008] To achieve the above-mentioned problem, an image sensor according to embodiments of the present invention comprises: a semiconductor substrate including first to fourth pixel regions, wherein the semiconductor substrate includes a first surface and a second surface facing each other; each of the first to fourth pixel regions includes first to fourth photoelectric conversion regions; a pixel separation structure disposed within the semiconductor substrate and defining the first to fourth pixel regions; gate electrodes and wiring provided on the first surface; and first to fourth microlenses provided on the second surface and respectively provided on the first to fourth pixel regions; wherein the second pixel region is spaced apart from the first pixel region in a first direction, and the fourth pixel region is spaced apart from the first pixel region in a second direction intersecting the first direction, and the semiconductor substrate comprises first impurity regions respectively disposed in the central portions of the first to fourth pixel regions; and a second impurity region disposed between the second pixel region and the fourth pixel region. The pixel separation structure includes third impurity regions that electrically connect the first to fourth photoelectric conversion regions, and the pixel separation structure includes first pixel separation portions that are spaced apart from each other and extend in a first direction; second pixel separation portions that are spaced apart from each other and extend in a second direction across the first pixel separation portions; and protrusions that protrude from the center of each of the first pixel separation portions and the second pixel separation portions toward the center of each of the first to fourth pixel regions, wherein the impurity doped in the first impurity region may be different from the impurity doped in the second impurity region. Effects of the invention

[0009] According to embodiments of the present invention, a pixel region group comprising first to fourth pixel regions may include a ground region at its center. The ground region may be shared by the first to fourth pixel regions. Each of the first to fourth pixel regions may include a floating diffusion region at its center. According to the arrangement of the ground region and the floating diffusion region according to embodiments of the present invention, the efficiency of spatial arrangement is maximized, and accordingly, the operating characteristics of the image sensor can be improved. Brief explanation of the drawing

[0010] FIG. 1 is a circuit diagram of an image sensor according to embodiments of the present invention. FIG. 2 is a schematic plan view of an image sensor according to embodiments of the present invention. Figure 3 is a cross-section taken along the line I-I' of Figure 2. Figure 4 is a plan view showing an enlarged view of area A of Figure 2. FIG. 5 is a plan view illustrating an image sensor according to embodiments of the present invention, with the gate electrodes and microlenses omitted from FIG. 4. Figure 6 is a cross-section taken along the line II-II' of Figure 4. Figure 7 is a cross-section taken along the line III-III' of Figure 4. FIG. 8 is a plan view of an image sensor according to embodiments of the present invention, corresponding to area A of FIG. 2. FIG. 9 is a plan view illustrating an image sensor according to embodiments of the present invention, in which the gate electrodes and microlenses shown in FIG. 8 are omitted. Figure 10 is a cross-section taken along the line IV-IV' of Figure 8. Figure 11 is a cross-section taken along the line V-V' of Figure 8. FIGS. 12 to 16 are cross-sectional views for explaining a method of manufacturing an image sensor according to embodiments of the present invention, corresponding to a cross-section cut along line II-II' of FIG. 4. Specific details for implementing the invention

[0011] Hereinafter, an image sensor according to embodiments of the present invention will be described in detail with reference to the drawings.

[0012] FIG. 1 is a circuit diagram of an image sensor according to embodiments of the present invention. More specifically, FIG. 1 is a circuit diagram of a pixel area group (PG) according to an embodiment of the present invention.

[0013] Referring to FIG. 1, the pixel region group (PG) may include, for example, first to fourth pixel regions (PX1, PX2, PX3, PX4). The pixel region group (PG) may include photoelectric conversion regions (PD1 to PD16), first to fourth floating diffusion regions (FD1, FD2, FD3, FD4), transfer transistors (TX1 to TX16), source follower transistors (SX), reset transistors (RX), and select transistors (AX). The transfer transistors (TX1 to TX16), source follower transistors (SX), reset transistors (RX), and select transistors (AX) may each include transfer gates (TG1 to TG16), source follower gates (SF), reset gates (RG), and select gates (SEL).

[0014] For example, the first pixel area (PX1) may include first to fourth photoelectric conversion areas (PD1, PD2, PD3, PD4), a first floating diffusion area (FD1), and first to fourth transfer transistors (TX1 to TX4); the second pixel area (PX2) may include fifth to eighth photoelectric conversion areas (PD5, PD6, PD7, PD8), a second floating diffusion area (FD2), and fifth to eighth transfer transistors (TX5, TX6, TX7, TX8); the third pixel area (PX3) may include ninth to twelfth photoelectric conversion areas (PD9, PD10, PD11, PD12), a third floating diffusion area (FD3), and ninth to twelfth transfer transistors (TX9, TX10, TX11, TX12); and the fourth pixel area (PX4) may include thirteenth to sixteenth photoelectric conversion areas (PD13, It may include PD14, PD15, PD16), a fourth floating diffusion region (FD4), and 13 to 16 transfer transistors (TX13, TX14, TX15, TX16).

[0015] The photoelectric conversion regions (PD1 to PD16) may be photodiodes comprising an n-type impurity region and a p-type impurity region. The first to fourth floating diffusion regions (FD1 to FD4) may function as drains of transfer transistors (TX1 to TX16). The first to fourth floating diffusion regions (FD1 to FD4) may be electrically connected to each other. For example, the first floating diffusion region (FD1) may function as a drain of the first to fourth transfer transistors (TX1 to TX4), the second floating diffusion region (FD2) may function as a drain of the fifth to eighth transfer transistors (TX5 to TX8), the third floating diffusion region (FD3) may function as a drain of the ninth to twelfth transfer transistors (TX9 to TX12), and the fourth floating diffusion region (FD4) may function as a drain of the thirteenth to sixteenth transfer transistors (TX13 to TX16).

[0016] The first to fourth floating diffusion regions (FD1 to FD4) can function as sources for a source follower transistor (SX) and a reset transistor (RX). The first to fourth floating diffusion regions (FD1 to FD4) can be electrically connected to the source follower gate (SF) of the source follower transistor (SX) and the reset gate (RG) of the reset transistor (RX). The source follower transistor (SX) can be connected to a selection transistor (AX).

[0017] The operation of the image sensor is explained with reference to FIG. 1 as follows. First, in a state where light is blocked, a power supply voltage (V) is applied to the drain of the reset transistor (RX) and the drain of the source follower transistor (SX). DD ) is applied and the reset transistor (RX) is turned on to release the charges remaining in the first to fourth floating diffusion regions (FD1 to FD4). Then, the reset transistor (RX) is turned off and external light is incident on the photoelectric conversion regions (PD1 to PD16), and electron-hole pairs are generated in each of the photoelectric conversion regions (PD1 to PD16). Holes move to the P-type impurity region of each of the photoelectric conversion regions (PD1 to PD16), and electrons move to the n-type impurity region and accumulate. When the transfer transistors (TX1 to TX16) are turned on, charges such as these electrons and holes are transferred to and accumulated in the first to fourth floating diffusion regions (FD1 to FD4). The gate bias of the source follower transistor (SX) changes in proportion to the amount of accumulated charge, causing a change in the source potential of the source follower transistor (SX). At this time, when the selector transistor (AX) is turned ON, a signal due to charge is read through the column line.

[0018] The wiring line may be electrically connected to at least one of the transmission gate (TG), source follower gate (SF), reset gate (RG), and select gate (SEL). The wiring line is connected to the drain of the reset transistor (RX) or the drain of the source follower transistor (SX) with a power supply voltage (V DD It can be configured to apply ). The wiring line may include a column line connected to a select transistor (AX). The wiring line may be the wirings described below.

[0019] Although FIG. 1 illustrates a configuration in which four photoelectric conversion regions electrically share a single floating diffusion region (FD), embodiments of the present invention are not limited thereto and can be modified in various ways. Accordingly, the integration density of the image sensor can be improved.

[0020] FIG. 2 is a schematic plan view of an image sensor according to embodiments of the present invention. FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 2.

[0021] Referring to FIGS. 2 and 3, an image sensor according to embodiments may include a sensor chip (1000) and a circuit chip (2000). The sensor chip (1000) may include a photoelectric conversion layer (10), a first wiring layer (20), and an upper layer (30). The photoelectric conversion layer (10) may include a first substrate (100), a pixel separation structure (150), and gate electrodes (171, 173).

[0022] The first substrate (100) may include a pixel array region (AR), an optical black region (OB), and a pad region (PAD). The pixel array region (AR) may be positioned in the center portion of the first substrate (100) in a planar view. The pixel array region (AR) may include a plurality of pixel region groups (PG). Each of the pixel region groups (PG) may include a plurality of pixel regions (PX). For example, each of the pixel region groups (PG) may include four pixel regions (PX) arranged in a 2x2 arrangement. The pixel regions (PX) may output a photoelectric signal from incident light. The pixel regions (PX) may form columns and rows and may be arranged two-dimensionally. The rows may be parallel to the first direction (D1). The columns may be parallel to the second direction (D2). In the present specification, the first direction (D1) may be parallel to the first surface (100a) of the first substrate (100), and the second direction (D2) may be parallel to the first surface (100a) of the first substrate (100) and intersect with the first direction (D1). For example, the second direction (D2) may be substantially perpendicular to the first direction (D1). The third direction (D3) may be perpendicular to the first direction (D1) and the second direction (D3), respectively.

[0023] A pad area (PAD) is provided at the edge portion of the substrate (100) and can surround a pixel array area (AR) in a planar view. An optical black area (OB) can be placed between the pixel array area (AR) and the pad area (PAD) of the substrate (100). The optical black area (OB) can surround the pixel array area (AR) in a planar view. Below, the pixel array area (AR) of the image sensor will be described in more detail, and the optical black area (OB), the pad area (PAD), and the circuit chip (2000) will be described later.

[0024] FIG. 4 is a plan view showing an enlarged view of area A of FIG. 2. FIG. 5 is a plan view illustrating an image sensor according to embodiments of the present invention, in which the gate electrodes and microlenses shown in FIG. 4 are omitted. FIG. 6 is a cross-section taken along line II-II' of FIG. 4. FIG. 7 is a cross-section taken along line III-III' of FIG. 4.

[0025] Referring to FIG. 4 together with FIG. 2, the first substrate (100) may have a first surface (100a) and a second surface (100b) facing each other. Light may be incident on the second surface (100b) of the first substrate (100). A first wiring layer (20) may be disposed on the first surface (100a) of the first substrate (100), and an upper layer (30) may be disposed on the second surface (100b) of the first substrate (100). The first substrate (100) may be a semiconductor substrate or an SOI (Silicon on Insulator). The first substrate (100) may include, for example, a silicon first substrate, a germanium substrate, or a silicon-germanium substrate. The first substrate (100) may include impurities of a first conductivity type. For example, the first type of impurity may include p-type impurities such as aluminum (Al), boron (B), indium (In) and / or gallium (Ga).

[0026] In the pixel array area (AR), the first substrate (100) may include a plurality of pixel area groups (PG). Each of the pixel area groups (PG) may be arranged in a repetitive matrix form along a first direction (D1) and a second direction (D2) that intersect each other. Each of the pixel area groups (PG) may include a plurality of pixel areas (PX1, PX2, PX3, PX4) defined by a pixel separation structure (150). For example, the plurality of pixel areas (PX1, PX2, PX3, PX4) may include first to fourth pixel areas (PX1, PX2, PX3, PX4). Hereinafter, for convenience of explanation, the description is based on a single pixel area group (PG).

[0027] As shown in FIG. 4, the first to fourth pixel regions (PX1, PX2, PX3, PX4) may be spaced apart from each other with a pixel separation structure (150) in between. The first to fourth pixel regions (PX1, PX2, PX3, PX4) may have a 2x2 arrangement in a planar view. For example, the first pixel region (PX1) and the second pixel region (PX2) may be aligned in a first direction (D1), and the first pixel region (PX1) and the fourth pixel region (PX4) may be aligned in a second direction (D2). The third pixel region (PX3) may not be aligned with the first pixel region (PX1) in the first direction (D1) and the second direction (D2). The second pixel area (PX2) and the third pixel area (PX3) can be aligned in the second direction (D2), and the third pixel area (PX3) and the fourth pixel area (PX4) can be aligned in the first direction (D1). The width of each of the plurality of first to fourth pixel areas (PX1, PX2, PX3, PX4) in the first direction (D1) may be 1 μm or more and 1.4 μm or less.

[0028] Each of the first to fourth pixel regions (PX1, PX2, PX3, PX4) may include first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d). In each of the first to fourth pixel regions (PX1, PX2, PX3, PX4), the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) may be spaced apart from each other with a pixel separation structure (150) in between. The first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) may have a 2x2 array in a planar view. For example, the first photoelectric conversion region (110a) and the second photoelectric conversion region (110b) may be aligned in a first direction (D1), and the first photoelectric conversion region (110a) and the fourth photoelectric conversion region (110d) may be aligned in a second direction (D2). The third photoelectric conversion region (110c) may not be aligned with the first photoelectric conversion region (110a) in the first direction (D1) and the second direction (D2). The second photoelectric conversion region (110b) and the third photoelectric conversion region (110c) may be aligned in a second direction (D2), and the third photoelectric conversion region (110c) and the fourth photoelectric conversion region (110d) may be aligned in a first direction (D1).

[0029] The first and second photoelectric conversion regions (110a, 110b) can detect the phase difference of light incident differently depending on the first direction (D1). The third and fourth photoelectric conversion regions (110c, 110d) can detect the phase difference of light incident differently depending on the first direction (D1). An autofocus signal for adjusting the position of the lens can be calculated by comparing the signals output from the first and second photoelectric conversion regions (110a, 110b) or by comparing the signals output from the third and fourth photoelectric conversion regions (110c, 110d). The first and fourth photoelectric conversion regions (110a, 110d) can detect the phase difference of light incident differently depending on the second direction (D2). The second and third photoelectric conversion regions (110b, 110c) can detect the phase difference of light incident differently depending on the second direction (D2). An autofocus signal for adjusting the position of the lens can be calculated by comparing signals output from the first and fourth photoelectric conversion regions (110a, 110d) or signals output from the second and third photoelectric conversion regions (110b, 110c).

[0030] The first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) may be regions doped with second conductivity type impurities within the first substrate (100). The second conductivity type impurities may have a conductivity type opposite to that of the first conductivity type impurities. The second conductivity type impurities may include n-type impurities such as phosphorus, arsenic, bismuth, and / or antimony. The first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) may be adjacent to the first surface (100a) of the first substrate (100). More specifically, the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) may be positioned closer to the first surface (100a) than to the second surface (100b). For example, each photoelectric conversion region (110) may include a first region adjacent to a first surface (100a) and a second region adjacent to a second surface (100b). There may be a difference in impurity concentration between the first region and the second region of the photoelectric conversion region (110). Accordingly, the photoelectric conversion region (110) may have a potential gradient between the first surface (100a) and the second surface (100b) of the first substrate (100). As another example, the photoelectric conversion region (110) may not have a potential gradient between the first surface (100a) and the second surface (100b) of the first substrate (100).

[0031] The first substrate (100) and the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) can form a photodiode. That is, the photodiode can be formed by a pn junction of the first substrate (100) of the first conductivity type and the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) of the second conductivity type. The first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) forming the photodiode can generate and accumulate photocharges in proportion to the intensity of incident light.

[0033] Referring to FIG. 5, a pixel separation structure (150) may be provided inside a first substrate (100). In a planar view, the pixel separation structure (150) may include first pixel separation portions (150a) extending in a first direction (D1), second pixel separation portions (150b) extending in a second direction (D2), and protrusions (150c). The pixel separation structure (150) may define first to fourth pixel regions (PX1, PX2, PX3, PX4) and may separate first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) of each of the first to fourth pixel regions (PX1, PX2, PX3, PX4) from each other. More specifically, a pair of first pixel separation units (150a) and a pair of second pixel separation units (150b) can define a pixel region.

[0034] The first pixel separation portions (150a) may be portions extending in the first direction (D1) from the pixel separation structure (150). More specifically, the first pixel separation portions (150a) may extend in the first direction (D1) across the second pixel separation portions (150b). The first pixel separation portions (150a) may be spaced apart from each other in the second direction (D2). The first pixel separation portions (150a) may be placed on the edge regions of each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). The first pixel separation portions (150a) may be connected to adjacent second pixel separation portions (150b) and protrusions (150c). Each of the first pixel separation portions (150a) may be interposed between adjacent pixel regions in the second direction (D2) to separate the pixel regions.

[0035] The second pixel separation portions (150b) may be portions extending in the second direction (D2) from the pixel separation structure (150). More specifically, the second pixel separation portions (150b) may extend in the second direction (D2) across the first pixel separation portions (150a). The second pixel separation portions (150b) may be spaced apart from each other in the first direction (D1). The second pixel separation portions (150b) may be placed on the edge regions of each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). The second pixel separation portions (150a) may be connected to adjacent first pixel separation portions (150a) and protrusions (150c). Each of the second pixel separation portions (150b) may be interposed between adjacent pixel regions in the first direction (D1) to separate the pixel regions.

[0036] Four protrusions (150c) may be provided on each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). For example, the four protrusions (150c) of the first pixel region (PX1) may extend from the center of each of the pair of first pixel separators (150a) and the pair of second pixel separators (150b) surrounding the first pixel region (PX1) toward the center of the first pixel region (PX1). However, the four protrusions (150c) may not be provided at the center of the first pixel region (PX1). The four protrusions (150c) may be connected to the adjacent first pixel separators (150a) and second pixel separators (150b). One pair of opposing protrusions (150c) may extend in a first direction (D1), and the other pair of opposing protrusions (150c) may extend in a second direction (D2). The four protrusions (150c) may be spaced apart from each other. The four protrusions (150c) on each of the second pixel area (PX2), the third pixel area (PX3), and the fourth pixel area (PX4) may have the same structure as the four protrusions (150c) of the first pixel area (PX1).

[0037] From a planar perspective, the first pixel separation portions (150a) and the second pixel separation portions (150b) can be integrally connected to each other to form a grid structure. Accordingly, the first pixel separation portions (150a) and the second pixel separation portions (150b) can define the first to fourth pixel regions (PX1, PX2, PX3, PX4). The protrusions (150c) can be interposed between the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) of each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). The first pixel separation portions (150a), the second pixel separation portions (150b), and the protrusions (150c) can surround each of the first to fourth pixel regions (PX1, PX2, PX3, PX4).

[0038] In a pixel area group (PG), the first pixel separation parts (150a) and the second pixel separation parts (150b) may not be provided at the center of the pixel area group (PG). For example, among the first pixel separation parts (150a), the first pixel separation part (150a) extending in a first direction (D1) toward the center of the pixel area group (PG) may be disconnected at the center of the pixel area group (PG). Among the second pixel separation parts (150b), the second pixel separation part (150b) extending in a second direction (D2) toward the center of the pixel area group (PG) may be disconnected at the center of the pixel area group (PG). Accordingly, the first pixel separation part (150a) and the second pixel separation part (150b) may not be provided at the center of the pixel area group (PG). More specifically, one end (150a_1, 150a_2) of a pair of first pixel separation parts (150a) adjacent to the center of the pixel area group (PG) may face each other. One end of a pair of second pixel separation parts (150b) adjacent to the center of the pixel area group (PG) may face each other.

[0039] In the embodiments, the center of the first to fourth pixel regions (PX1, PX2, PX3, PX4) means a point located at an equal distance from each of the first and second pixel separation parts (150a, 150b) surrounding the first to fourth pixel regions (PX1, PX2, PX3, PX4). The center of the pixel region group (PG) means a point located at an equal distance from each of the first and second pixel separation parts (150a, 150b) surrounding the pixel region group (PG).

[0040] Referring to FIG. 6, a pixel isolation structure (150) may be provided inside a first substrate (100). The pixel isolation structure (150) may be provided within a first trench (TR1), and the first trench (TR1) may be recessed from a first surface (100a) of the first substrate (100). The pixel isolation structure (150) may extend from the first surface (100a) of the first substrate (100) to a second surface (100b) and penetrate the first substrate (100). For example, the width (W1) of the pixel isolation structure (150) may gradually decrease from the first surface (100a) of the first substrate (100) to the second surface (100b). The pixel isolation structure (150) may be a deep trench isolation. The vertical height of the pixel separation structure (150) may be substantially the same as the vertical thickness of the first substrate (100).

[0041] The pixel isolation structure (150) may include an insulating pattern (151), a semiconductor pattern (153), and a capping pattern (155). The pixel isolation structure (150) may include an insulating pattern (151), a semiconductor pattern (153), and a capping pattern (155). The insulating pattern (151) may be provided along the sidewall of the first trench (TR1). The insulating pattern (151) may, for example, include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high dielectric material (e.g., hafnium oxide and / or aluminum oxide). For another example, the insulating pattern (151) may include a plurality of layers, and said layers may include different materials. The insulating pattern (151) may have a lower refractive index than the first substrate (100). Accordingly, crosstalk phenomena between the first to fourth pixel regions (PX1, PX2, PX3, PX4) of the first substrate (100) can be prevented or reduced.

[0042] A semiconductor pattern (153) may be provided inside the first trench (TR1). The semiconductor pattern (153) may fill the interior of the first trench (TR1). The sidewalls of the semiconductor pattern (153) may be surrounded by an insulating pattern (151). An insulating pattern (151) may be interposed between the semiconductor pattern (153) and the first substrate (100). Accordingly, the semiconductor pattern (153) may be spaced apart from the first substrate (100) by the insulating pattern (151). When the image sensor is in operation, the semiconductor pattern (153) may be electrically separated from the first substrate (100) by the insulating pattern (151). The semiconductor pattern (153) may include, for example, silicon oxide, silicon nitride, silicon oxynitride, polycrystalline silicon containing impurities, polycrystalline silicon without impurities, amorphous silicon, and / or metallic materials. For example, if the semiconductor pattern (153) is silicon containing impurities, the impurities may include n-type or p-type impurities. For another example, if the semiconductor pattern (153) contains a metal material, the metal material may include tungsten.

[0043] A capping pattern (155) may be provided on the upper surface of a semiconductor pattern (153). The capping pattern (155) may be disposed adjacent to a first surface (100a) of a first substrate (100). The upper surface of the capping pattern (155) may be coplanar with the first surface (100a) of the first substrate (100). The lower surface of the capping pattern (155) may be in contact with the upper surface of the semiconductor pattern (153). The capping pattern (155) may include a non-conductive material. For example, the capping pattern (155) may include a silicon-based insulating material (e.g., silicon nitride, silicon oxide, and / or silicon oxynitride) and / or a high dielectric material (e.g., hafnium oxide and / or aluminum oxide). Accordingly, the pixel separation structure (150) can prevent photocharges generated by incident light incident on each of the unit pixel regions (PX) from being incident on adjacent first to fourth pixel regions (PX1, PX2, PX3, PX4) by random drift. That is, the pixel separation structure (150) can prevent crosstalk between the first to fourth pixel regions (PX1, PX2, PX3, PX4).

[0044] Referring to FIGS. 5 through 7, the first substrate (100) may include first impurity regions (111) and second impurity regions (112) within it. The first impurity regions (111) and the second impurity regions (112) may be disposed adjacent to the first surface (100a) of the first substrate (100). The bottom surface of each of the first impurity regions (111) and the second impurity region (112) may be spaced apart from the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d).

[0045] As shown in FIG. 5, in a planar view, the first impurity regions (111) may be provided at the center of each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). Each of the first impurity regions (111) may be positioned between a pair of opposing protrusions (150c) among adjacent protrusions (150c). The first impurity regions (111) may be positioned adjacent to the first gate electrodes (171). The first impurity regions (111) may be regions doped with an impurity of a second conductivity type. The impurity of the second conductivity type may have a conductivity type opposite to that of the impurity of the first conductivity type. The impurity of the second conductivity type may include n-type impurities such as phosphorus (P), arsenic (As), bismuth (Bi), and / or antimony (Sb).

[0046] Each of the first to fourth pixel regions (PX1, PX2, PX3, PX4) may include a singular first impurity region (111). Accordingly, a pixel region group (PG) may include four first impurity regions (111). Each of the first impurity regions (111) may be X-shaped in a planar view. More specifically, each of the first impurity regions (111) may extend diagonally toward each of the adjacent first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) in a planar view. Each of the first impurity regions (111) may overlap perpendicularly with a portion of each of the adjacent first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d). The first impurity regions (111) may correspond to the first to fourth floating diffusion regions (FD1, FD2, FD3, FD4) of FIG. 1.

[0047] From a planar perspective, a second impurity region (112) may be provided at the center of a pixel region group (PG). The second impurity region (112) may be positioned between a pair of first pixel separation units (150a) spaced apart in a first direction (D1) at the center of the pixel region group (PG). More specifically, it may be positioned between one end (150a_1) of one of the adjacent first pixel separation units (150a) and the other end (150a_2) of the first pixel separation units (150a) at the center of the pixel region group (PG). The second impurity region (112) may be a region doped with an impurity of the first conductivity type. For example, the impurity of the first conductivity type may include p-type impurities such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga). The second impurity region (112) may be a ground region. The second impurity region (112) may contain impurities of the same conductivity type as the first substrate (100) and impurities of a different conductivity type from the first impurity region (111). The impurity concentration doped in the second impurity region (112) may be greater than the impurity concentration doped in the first substrate (100).

[0048] A single pixel area group (PG) may include a singular second impurity area (112). The second impurity area (112) may be X-shaped in a planar view. More specifically, the second impurity area (112) may extend diagonally toward each of the adjacent first to fourth pixel areas (PX1, PX2, PX3, PX4) in a planar view. For example, the second impurity area (112) may be perpendicularly superimposed on a portion of the third photoelectric conversion area (110c) of the first pixel area (PX1), a portion of the fourth photoelectric conversion area (110d) of the second pixel area (PX2), a portion of the first photoelectric conversion area (110a) of the third pixel area (PX3), and a portion of the second photoelectric conversion area (110b) of the fourth pixel area (PX4). As another example, the second impurity region (112) may not overlap vertically with the first to fourth pixel regions (PX1, PX2, PX3, PX4).

[0049] Referring to FIGS. 4, 6, and 7, the first substrate (100) of the image sensor according to the embodiments may further include third impurity regions (113). The third impurity regions (113) may overlap perpendicularly with the first impurity regions (111), respectively. For example, the third impurity regions (113) may be provided at the center of each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). Accordingly, each of the first to fourth pixel regions (PX1, PX2, PX3, PX4) may include a singular third impurity region (113), and a pixel region group (PG) may include four third impurity regions (113). Each of the third impurity regions (113) may overlap with adjacent first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d). More specifically, each of the third impurity regions (113) may be provided at a level between the lowest and highest parts of each of the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) in a vertical view.

[0050] Each of the third impurity regions (113) can electrically connect the adjacent first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d). Each of the third impurity regions (113) may be a region doped with an impurity of the second conductivity type. The impurity of the second conductivity type may have a conductivity type opposite to that of the impurity of the first conductivity type. The impurity of the second conductivity type may include n-type impurities such as phosphorus (P), arsenic (As), bismuth (Bi), and / or antimony (Sb). The concentration of the impurity doped in the third impurity regions (113) may be equal to or different from the concentration of the impurity doped in the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d). The third impurity regions (113) can serve as a channel that allows electrons accumulated in any one of the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) to move to another of the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d). Accordingly, electrons are evenly distributed and accumulated in the adjacent first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d), thereby increasing the number of electrons (Full Well Capacity; FWC) that each of the first to fourth pixel regions (PX1, PX2, PX3, PX4) can hold. Accordingly, an image sensor with improved operating characteristics can be provided.

[0051] Referring again to FIGS. 6 and FIGS. 7, the first substrate (100) of the image sensor according to the embodiments may further include fourth impurity regions (114). The fourth impurity regions (114) may be provided between the first gate electrode (171) and the second gate electrode (173). The fourth impurity regions (114) may be disposed adjacent to the first surface (100a) of the first substrate (100). In a planar view, each of the fourth impurity regions (114) may extend along a first direction (D1) between the first gate electrode (171) and the second gate electrode (173). The fourth impurity regions (114) may be regions doped with an impurity of a first conductivity type. For example, the impurity of the first conductivity type may include p-type impurities such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga). The fourth impurity regions (114) may contain the same impurities as the first substrate (100). The impurity concentration doped in the fourth impurity regions (114) may be greater than the impurity concentration doped in the first substrate (100). The fourth impurity regions (114) can improve insulation by preventing current leakage between the second conductivity type doped regions placed around the first gate electrode (171) and the second conductivity type doped regions placed around the second gate electrode (173). Additionally, the image sensor according to the embodiments may include the fourth impurity regions (114) to omit the formation of a shallow device isolation (STI) film. If multiple shallow device isolation films are present, the dark current of the image sensor may increase, thereby degrading operating characteristics. Therefore, the image sensor according to the embodiments may further include the fourth impurity regions (114) to reduce the dark current and improve operating characteristics.

[0052] Referring again to FIGS. 6 and 7, a first wiring layer (20) may be provided on a first surface (100a) of a first substrate (100). The first wiring layer (20) may include insulating layers (221, 223) and a conductive structure (210, 220). The insulating layers (221, 223) may include a first insulating layer (221) and second insulating layers (223). The first insulating layer (221) may cover the first surface (100a) of the first substrate (100). The first insulating layer (221) may be provided on the first surface (100a) of the first substrate (100) to cover gate electrodes (171, 173). The second insulating layers (223) may be laminated on the first insulating layer (221). The first and second insulating layers (212, 223) may comprise a non-conductive material. For example, the first and second insulating layers (212, 223) may comprise a silicon-based insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. A conductive structure (210, 220) may be provided within the insulating layers (221, 223). The conductive structure (210, 220) may include a contact plug portion (210) and a wiring portion (220). More specifically, the wiring portion (220) may include a wiring pattern and a via pattern. The contact plug portion (210) is provided within the first insulating layer (221) and may be electrically connected to any one of the gate electrodes (171, 173), the first impurity regions (111), and the second impurity regions (112). The wiring portion (220) of the conductive structure (210, 220) may be interposed between two adjacent insulating layers (221, 223). The wiring portion (220) may be connected to a contact plug portion. The via pattern of the conductive structure (210, 220) penetrates at least one of the second insulating layers (223) and may be connected to the wiring pattern. The contact plug portion (210) of the conductive structure (210, 220) may include a material different from the wiring pattern and the via pattern.The wiring pattern and via pattern may include a metallic material, for example, copper (Cu), and the contact plug portion (210) may include tungsten.

[0053] A light receiving unit (300) may be provided on a second surface (100b) of a first substrate (100). More specifically, the light receiving unit (300) may be disposed on a pixel array area (AR) of the first substrate (100). The light receiving unit (300) may include a first rear insulating layer (310), an anti-reflection film (315), color filters (320), a second rear insulating layer (330), micro lenses (340), and a lens coating layer (350). The light receiving unit (300) may collect and filter light incident from the outside and provide the light to a photoelectric conversion layer (10).

[0054] Specifically, color filters (320) and micro lenses (340) may be provided on the second surface (100b) of the first substrate (100). The color filters (320) may be placed on the first to fourth pixel regions (PX1, PX2, PX3, PX4). Micro lenses (340) may be placed on each of the color filters (320). An anti-reflection film (315) may be provided between the second surface (100b) of the first substrate (100) and the color filters (320). The anti-reflection film (315) may prevent reflection of light so that light incident on the second surface (100b) of the first substrate (100) can smoothly reach the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d). A first rear insulating layer (310) may be provided between the second surface (100b) of the first substrate (100) and the anti-reflection film (315), and a second rear insulating layer (330) may be provided between the color filters (320) and the micro lenses (340). The second rear insulating layer (330) may include at least one of a fixed charge layer, an adhesive layer, and a protective layer. The second rear insulating layer (310) may include a plurality of layers as not illustrated and may include a metal oxide (e.g., aluminum oxide or hafnium oxide) or a silicon-based insulating material (e.g., silicon oxide or silicon nitride).

[0055] The color filters (320) may include primary color filters. The color filters (320) may include first to third color filters that transmit different colors. For example, the first to third color filters may each transmit green, red, and blue light. The first to third color filters may be arranged in a Bayer pattern. For another example, the first to third color filters may transmit other colors such as cyan, magenta, or yellow.

[0056] Color filters (320) may be placed corresponding to each of a plurality of pixel area groups (PG). More specifically, any one of the first to third color filters may be placed on one pixel area group (PG). For example, any one of the first to third color filters may be provided on the first to fourth pixel areas (PX1, PX2, PX3, PX4) of the pixel area group (PG) of FIG. 4. That is, any one of the first to third color filters may cover all of the first to fourth pixel areas (PX1, PX2, PX3, PX4). Accordingly, the first to fourth pixel areas (PX1, PX2, PX3, PX4) may output a signal for any one of green, red, and blue light.

[0057] Micro-lenses (340) may be placed on color filters (320). Four micro-lenses (340) may be placed on any one of the color filters (320). Micro-lenses (340) may be vertically overlapped with each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). Micro-lenses (340) may be connected to each other. Micro-lenses (340) may be transparent so as to transmit light. Micro-lenses (340) may have a convex shape so as to concentrate light incident on each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). Micro-lenses (340) may include organic materials. For example, micro-lenses (340) may include a photoresist material or a thermosetting resin.

[0058] A lens coating layer (350) may be provided on the surface of the micro-lenses (340). The lens coating layer (350) may conformally cover the convex surface of the micro-lenses (340). The lens coating layer (350) may include an insulating material and may be transparent. The lens coating layer (350) may protect the micro-lenses (340).

[0059] FIG. 8 is a plan view of an image sensor according to embodiments of the present invention, corresponding to area A in FIG. 2. FIG. 9 is a plan view illustrating an image sensor according to embodiments of the present invention, in which the gate electrodes and microlenses are omitted from FIG. 8. FIG. 10 is a cross-section taken along line IV-IV' of FIG. 8. FIG. 11 is a cross-section taken along line V-V' of FIG. 8. Hereinafter, details overlapping with the above description are omitted, and the differences are explained in more detail.

[0060] Referring to FIGS. 8 to 10, the image sensor according to the embodiments may further include auxiliary pixel separation structures (160).

[0061] Auxiliary pixel separation structures (160) may be provided within the first substrate (100). The auxiliary pixel separation structures (160) may extend from the second surface (100b) of the first substrate (100) toward the first surface (100a). The width of the auxiliary pixel separation structures (160) may decrease as it goes from the second surface (100b) of the first substrate (100) toward the first surface (100a). The height (H2) of each of the auxiliary pixel separation structures (160) may be smaller than the height (H1) of the pixel separation structure (150). More specifically, the upper surface of each of the auxiliary pixel separation structures (160) may be provided at a level between the first surface (100a) and the second surface (100b) of the first substrate (100). The lower surface of each of the auxiliary pixel separation structures (160) can form a co-plane with the second surface (100b) of the first substrate (100).

[0062] Each of the auxiliary pixel separation structures (160) may overlap perpendicularly with the first impurity regions (111). In a planar view, the auxiliary pixel separation structures (160) may be in the shape of a cross. The auxiliary pixel separation structures (160) may be spaced apart from the pixel separation structure (150). The auxiliary pixel separation structures (160) may include an insulating material. For example, the pixel separation structures (160) may include a silicon-based insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0063] Hereinafter, the configurations on the optical black region (OB) of the first substrate (100) are described.

[0064] In the optical black region (OB), the first substrate (100) may include a first reference pixel region (RPX1) and a second reference pixel region (RPX2) defined by a pixel separation structure (150). The first reference pixel region (RPX1) may be positioned between the second reference pixel region (RPX2) and the pixel array region (AR). First to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) may be provided within the first reference pixel region (RPX1). The first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) within the first reference pixel region (RPX1) may have the same planar area and volume as the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) of each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). The first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) may not be provided within the second reference pixel region (RPX2). Impurity regions and gate electrodes (171, 173) may be disposed on the first and second reference pixel regions (RPX1, RPX2), respectively. The impurity regions and gate electrodes (171, 173) may be the same as those described in the pixel array region (AR).

[0065] An anti-reflection film (315) may be provided on the second surface (100b) of the optical black region (OB) of the first substrate (100). The anti-reflection film (315) may extend horizontally from the pixel array region (AR) to the optical black region (OB) to cover the first substrate (100) and the pixel separation structure (150).

[0066] A first through-structure (70) may be provided within an optical black region (OB) of a first substrate (100). The first through-structure (70) may include a first conductive pattern (71), a first through-insulating layer (73), a first embedded pattern (75), and a first capping pattern (77).

[0067] A first through hole may be formed on a second surface (100b) of a first substrate (100), and a first conductive pattern (71) may be provided within the first through hole. The first through hole may be positioned on a first side of a contact pad (91). The first through hole may be positioned between the contact pad (91) and a pixel separation structure (150). The first through hole may penetrate at least a portion of the first substrate (100), the first wiring layer (20), and the second wiring layer (50). The first through hole may have a first bottom surface and a second bottom surface. The first bottom surface of the first through hole may expose a wiring pattern of a conductive structure (210, 220). The second bottom surface of the first through hole may expose lower wirings (55) within the second wiring layer (50).

[0068] The first conductive pattern (71) may cover a portion of the upper surface of the anti-reflective film (315) on the second surface (100b) of the first substrate (100), and may conformally cover the inner wall and bottom surface of the first through hole. The first conductive pattern (71) may penetrate at least a portion of the first substrate (100), the first wiring layer (20), and the second wiring layer (50). More specifically, the first conductive pattern (71) may be electrically connected by contacting the wiring pattern of the conductive structure (210, 220) within the first wiring layer (20). The first conductive pattern (71) may be electrically connected by contacting the lower wiring (55) within the second wiring layer (50). The first conductive pattern (71) may include a metallic material, for example, copper, tungsten, or aluminum.

[0069] The first conductive pattern (71) can extend onto the second surface (100b) of the first substrate (100) of the optical black region (OB) and function as a light-blocking film. More specifically, the first conductive pattern (71) can extend onto the anti-reflection film (315). The first conductive pattern (71) can be in contact with the side of the color filters (320) on the pixel array region (AR) horizontally. Light may not be incident on the photoelectric conversion region (110) within the optical black region (OB) by the first conductive pattern (71). The pixels of the first and second reference pixel regions (RPX1, RPX2) of the optical black region (OB) may not output a photoelectric signal but may output a noise signal. The noise signal may be generated by electrons produced by heat generation or dark current, etc. The first conductive pattern (71) does not cover the pixel array region (AR), so that light can be incident on the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) within the pixel array region (AR). The noise signal can be removed from the photoelectric signal output from the first to fourth pixel regions (PX1, PX2, PX3, PX4). The first conductive pattern (71) may include a metal such as, for example, tungsten, copper, aluminum, or an alloy thereof.

[0070] A first through-insulating layer (73) may be provided on a first conductive pattern (71). The first through-insulating layer (73) may extend vertically or horizontally to cover the inner wall of the first through-hole. The first through-insulating layer (73) may extend onto a second surface (100b) of the first substrate (100) to cover a portion of the bias application pad (92) and the second conductive pattern (81). The first through-insulating layer (73) may come into contact with the side of the color filters (320). The first through-insulating layer (73) may include an insulating material, for example, silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, silicon oxynitride.

[0071] A first embedded pattern (75) may be provided on the first through-insulating layer (73) to fill the remaining portion inside the first through-hole. The first embedded pattern (75) may not extend onto the second surface (100b) of the first substrate (100). The first embedded pattern (75) may include a low-refractive index material and may have insulating properties. The upper surface of the first embedded pattern (75) may have a recess. For example, the center portion of the upper surface of the first embedded pattern (75) may be placed at a lower level than the edge portion.

[0072] A first capping pattern (77) may be placed on the upper surface of the first embedding pattern (75) to fill the recess. The upper surface of the first capping pattern (77) may be substantially flat. The first capping pattern (77) may include an insulating polymer such as a photoresist material.

[0073] A bulk color filter (93) may cover the first through-insulation layer (73) and the first capping pattern (77). The bulk color filter (93) may be, for example, a blue color filter. The bulk color filter (93) may be vertically overlapped with the light-blocking film (60).

[0074] Hereinafter, the configurations on the pad area (PAD) of the first substrate (100) are described.

[0075] A contact pad trench is formed on the second surface (100b) of the pad area (PAD) of the first substrate (100), and a contact pad (91) may be provided within the contact pad trench. The contact pad (91) may include a metallic material, for example, aluminum. The contact pad (91) may serve as an electrical connection path between the image sensor and the outside when the image sensor is in operation. More specifically, the contact pad (91) may output electrical signals generated in the first to fourth pixel areas (PX1, PX2, PX3, PX4) to the outside.

[0076] A second through-structure (80) may be provided within a pad area (PAD) of the first substrate (100). The second through-structure (80) may include a second conductive pattern (81), a second through-insulating layer (83), a second embedded pattern (85), and a second capping pattern (87).

[0077] A second through hole may be formed on a second surface (100b) of the first substrate (100), and a second conductive pattern (81) may be provided within the second through hole. The second through hole may be positioned on a second side of the contact pad (91). The second side of the contact pad (91) may be different from the first side. The second through hole may penetrate at least a portion of the first substrate (100), the first wiring layer (20), and the second wiring layer (50). The bottom surface of the second through hole may expose the lower wiring (55) within the second wiring layer (50).

[0078] A second conductive pattern (81) may be provided on the first surface (100a) of the first substrate (100) at the pad area (PAD) of the first substrate (100). The second conductive pattern (81) may conformally cover the inner wall and bottom surface of the contact pad trench. The second conductive pattern (81) may extend further into the interior of the second through hole to conformally cover the inner wall and bottom surface of the second through hole. The second conductive pattern (81) may be electrically connected to the contact pad (91). The second conductive pattern (81) may penetrate at least a portion of the first substrate (100), the first wiring layer (20), and the second wiring layer (50). More specifically, the second conductive pattern (81) may be electrically connected by contacting the lower wiring (55) within the second wiring layer (50). The second conductive pattern (81) may include a metallic material, for example, copper, tungsten, or aluminum.

[0079] A second through-insulating layer (83) may be provided on the second conductive pattern (81). The second through-insulating layer (83) may extend vertically or horizontally to cover the inner wall of the through-hole. The second through-insulating layer (83) may extend onto the second surface (100b) of the first substrate (100). The second through-insulating layer (83) may not cover the upper surface of the contact pad (91). The second through-insulating layer (83) may include an insulating material, for example, silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, silicon oxynitride.

[0080] A second embedded pattern (85) may be provided on the second through-insulating layer (83) to fill the remaining portion inside the second through-hole. The second embedded pattern (85) may not extend onto the second surface (100b) of the first substrate (100). The second embedded pattern (85) may contain the same material as the first embedded pattern (75). The upper surface of the second embedded pattern (85) may have a recess. For example, the center portion of the upper surface of the second embedded pattern (75) may be placed at a lower level than the edge portion.

[0081] A second capping pattern (87) may be placed on the upper surface of the second filling pattern (85) to fill the recess. The upper surface of the first capping pattern (87) may be substantially flat. The second capping pattern (87) may include an insulating polymer such as a photoresist material.

[0082] An organic film (95) may be provided on the second surface (100b) of the optical black region (OB) and pad region (PAD) of the first substrate (100). The organic film (95) may cover the upper surface of the first through-insulating layer (73) and the upper surface of the bulk color filter (93) in the optical black region (OB), and cover the second through-insulating layer (83) and the second capping pattern (87) in the pad region (PAD), but may not cover the upper surface of the contact pad (91). Accordingly, the upper surface of the contact pad (91) may be exposed to the outside. The organic film (95) may be transparent. The upper surface of the organic film (95) may be substantially flat. The organic film (95) may include, for example, a polymer. The organic film (95) may have insulating properties. Unlike what is illustrated, the organic film (95) may be connected to microlenses (340). The organic film (95) may contain the same material as the microlenses (340).

[0083] A coating layer (97) may be provided on an organic film (95). The coating layer (97) may conformally cover the upper surface of the organic film (95). The coating layer (97) may include an insulating material and may be transparent. The coating layer (97) may include the same material as the lens coating layer (350).

[0084] Referring again to FIG. 3, the image sensor may include a circuit chip (2000). The circuit chip (2000) may be laminated on the sensor chip (1000). The circuit chip (2000) may include a second wiring layer (50) and a second substrate (40). The second wiring layer (50) may be interposed between the first wiring layer (20) and the second substrate (40). Integrated circuits (TR) may be disposed on the upper surface of the second substrate (40) or within the second substrate (40). The integrated circuits (TR) may include logic circuits, memory circuits, or a combination thereof. The integrated circuits (TR) may include, for example, transistors. The second wiring layer (50) may include lower insulating layers and lower wiring (55). The lower wiring (55) may be provided between the lower insulating layers or within the lower insulating layers. The lower wiring (55) can be electrically connected to the integrated circuits (TR) and can be connected to the first through-structure (70) and the second through-structure (80).

[0086] FIGS. 12 to 16 are cross-sectional views for explaining a method of manufacturing an image sensor according to embodiments of the present invention, corresponding to a cross-section cut along line II-II' of FIG. 4.

[0087] Referring to FIG. 12, a first substrate (100) having a first surface (100a) and a second surface (100b) facing each other may be prepared. The first substrate (100) may contain impurities of a first conductivity type (e.g., p-type). In one example, the first substrate (100) may be a substrate in which a first conductivity type epitaxial layer is formed on a first conductivity type bulk silicon substrate. In another example, the first substrate (100) may be a bulk substrate including wells of the first conductivity type.

[0088] A first trench (TR1) can be formed on a first surface (100a) of a first substrate (100). Forming the first trench (TR1) may include forming a first mask pattern on the first surface (100a) of the first substrate (100) and performing an etching process on the first surface (100a) using the first mask pattern.

[0089] After the formation of the first trench (TR1), a preliminary insulating pattern (151p) may be formed to conformally cover the inner wall of the first trench (TR1) and the first surface (100a) of the first substrate (100). The preliminary insulating pattern (151p) may be formed by depositing an insulating material on the first substrate (100) on which the first trench (TR1) is formed. The preliminary insulating pattern (151p) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0090] A preliminary semiconductor pattern (153p) can be formed on a preliminary insulating pattern (151p). The preliminary semiconductor pattern (153p) can be formed by performing a deposition process on a first substrate (100) on which the preliminary insulating pattern (151p) is formed. The preliminary semiconductor pattern (153p) can cover the preliminary insulating pattern (151p) on the inner wall of the first trench (TR1). The second semiconductor pattern (153p) can fill the interior of the first trench (TR1). The preliminary semiconductor pattern (153p) may include, for example, polysilicon.

[0091] Referring to FIG. 13, an etching process can be performed on a preliminary semiconductor pattern (153p). In the etching process, the upper portion of the preliminary semiconductor pattern (153p) can be removed to form a semiconductor pattern (153). Accordingly, a portion of the preliminary insulating pattern (151p) can be exposed to the outside.

[0092] A preliminary capping film (155p) may be formed on a preliminary insulating pattern (151p) and a semiconductor pattern (153). Forming the preliminary capping film (155p) may include performing a deposition process on a first surface (100a) of the first substrate (100). The preliminary capping film (155p) may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0093] Referring to FIG. 14, an insulating pattern (151) and a capping pattern (155) can be formed. Forming the insulating pattern (151) and the capping pattern (155) may include performing a planarization process on a first surface (100a) of a first substrate (100). In the planarization process, the upper portion of the preliminary insulating pattern (151p) and the upper portion of the preliminary capping film (155p) may be removed. Accordingly, the first surface (100a) of the first substrate (100), the upper surface of the capping pattern (155), and the upper surface of the insulating pattern (151) may form a co-surface.

[0094] Referring to FIG. 15, first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) can be formed by doping impurities into each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). Each of the first to fourth photoelectric conversion regions (110a, 110b, 110c, 110d) may have a second conductivity type (e.g., n-type) different from the first conductivity type (e.g., p-type). According to embodiments, third impurity regions (113) can be formed by doping impurities into each of the first to fourth pixel regions (PX1, PX2, PX3, PX4). The third impurity regions (113) may have impurities of the second conductivity type (e.g., n-type).

[0095] The vertical thickness of the first substrate (100) can be reduced by performing a thinning process that removes a portion of the first substrate (100). The thinning process may include grinding or polishing the second surface (100b) of the first substrate (100) and performing anisotropic or isotropic etching. To thin the first substrate (100), the top and bottom of the first substrate (100) may be inverted. A portion of the first substrate (100) may be removed by the grinding or polishing process, and subsequently, anisotropic or isotropic etching process may be performed to remove remaining surface defects of the first substrate (100).

[0096] As a thin film process is performed on the second surface (100b) of the first substrate (100), the lower surfaces of the insulating pattern (151) and the semiconductor pattern (153) may be exposed. The lower surfaces of the insulating pattern (151) and the semiconductor pattern (153) may co-plane with the second surface (100b) of the first substrate (100). Subsequently, transistors may be formed on the first surface (100a) of the first substrate (100). Forming the transistors may include forming gate electrodes (171, 173) and doping impurities on the first surface (100a) of the first substrate (100) to form first impurity regions (111), second impurity regions (112), and fourth impurity regions (114). The first impurity regions (111), the second impurity regions (112), and the fourth impurity regions (114) may contain n-type or p-type impurities.

[0097] A first wiring layer (20) can be formed on a first surface (100a) of a first substrate (100). Forming the first wiring layer (20) may include forming a first insulating layer (221) covering gate electrodes (171, 173) formed on a first surface (100b) of the first substrate (100), forming a contact plug of a conductive structure (210, 220) penetrating the first insulating layer (221), forming a second insulating layer (223) covering the contact plug (210) and the first insulating layer (221), and forming a wiring pattern and a via pattern of a conductive structure (210, 220) disposed inside the second insulating layer (223). The first insulating layer (221) and the second insulating layer (223) can be formed by performing a process of depositing an insulating material on the first surface (100a) of the first substrate (100). The conductive structure (210, 220) can be formed by performing a process of etching the first insulating layer (221) or the second insulating layer (223) and depositing a conductive material.

[0098] Referring again to FIG. 6, a first rear insulating layer (310), an anti-reflective film (315), color filters (320), a second rear insulating layer (330), and micro-lenses (340) can be formed on the second surface (100b) of the first substrate (100). An organic film can be deposited on the micro-lenses (340) to form a lens coating layer (350). Accordingly, an image sensor according to embodiments of the present invention can be manufactured.

[0100] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A semiconductor substrate comprising first to fourth pixel regions, wherein each of the first to fourth pixel regions comprises first to fourth photoelectric conversion regions; and a pixel separation structure disposed within the semiconductor substrate to define the first to fourth pixel regions and penetrating at least a portion of the semiconductor substrate, wherein the second pixel region is spaced apart from the first pixel region in a first direction, and the fourth pixel region is spaced apart from the first pixel region in a second direction intersecting the first direction, and the pixel separation structure is disposed between the first to fourth pixel regions, and the semiconductor substrate comprises: first impurity regions disposed in the central portions of the first to fourth pixel regions; An image sensor comprising a second impurity region disposed between the second pixel region and the fourth pixel region, wherein the impurity doped in the first impurity regions has a different conductivity type from the impurity doped in the second impurity region, and the pixel separation structure comprises first pixel separation portions that are spaced apart from each other and extend in the first direction, wherein, in a planar view, one end of any one of the first pixel separation portions and the other end of the first pixel separation portions are spaced apart in the first direction, and the second impurity region is disposed between one end of any one of the first pixel separation portions and the other end of the first pixel separation portions. Claim 2 An image sensor according to claim 1, wherein the pixel separation structure further comprises second pixel separation parts extending in the second direction, spaced apart from each other and crossing the first pixel separation parts. Claim 3 In claim 1, the image sensor in which the second impurity region is X-shaped from a planar perspective. Claim 4 In claim 2, the pixel separation structure further comprises protrusions that protrude from the center of each of the first pixel separation portions and the second pixel separation portions toward the center of each of the first to fourth pixel regions, wherein, in a planar view, the first impurity regions are positioned between the protrusions facing each other. Claim 5 An image sensor according to claim 4, wherein each of the first to fourth photoelectric conversion regions of each of the first to fourth pixel regions is surrounded by the first pixel separators, the second pixel separators, and the protrusions, and each of the first impurity regions is vertically superimposed with a part of each of the adjacent first to fourth photoelectric conversion regions. Claim 6 In claim 4, the image sensor in which the first impurity regions are X-shaped from a planar perspective. Claim 7 An image sensor according to claim 2, wherein the semiconductor substrate further comprises third impurity regions provided therein, wherein the third impurity regions each overlap perpendicularly with the first impurity regions, and each of the third impurity regions electrically connects the adjacent first to fourth photoelectric conversion regions. Claim 8 An image sensor according to claim 1, further comprising first to fourth microlenses provided on each of the first to fourth pixel regions, wherein each of the first to fourth microlenses is perpendicularly superimposed with the first to fourth photoelectric conversion regions of each of the corresponding first to fourth microlenses. Claim 9 An image sensor according to claim 8, wherein the semiconductor substrate comprises a first surface adjacent to the first to fourth microlenses and a second surface opposite to the first surface, wherein the width of the pixel separation structure decreases as it is adjacent to the first surface. Claim 10 A semiconductor substrate comprising first to fourth pixel regions, wherein each of the first to fourth pixel regions comprises first to fourth photoelectric conversion regions; a pixel separation structure disposed within the semiconductor substrate and defining the first to fourth pixel regions; and auxiliary pixel separation structures provided within the semiconductor substrate and disposed at the center of each of the first to fourth pixel regions, wherein the second pixel region is spaced apart from the first pixel region in a first direction, and the fourth pixel region is spaced apart from the first pixel region in a second direction intersecting the first direction, and the semiconductor substrate comprises: first impurity regions disposed in the central portions of the first to fourth pixel regions; and a second impurity region disposed between the second pixel region and the fourth pixel region, wherein the auxiliary pixel separation structures are spaced apart from the pixel separation structure and overlap perpendicularly with the first impurity regions.

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