Power converter module

Abstract

The present invention relates to a 3-level power semiconductor module. The 3-level power semiconductor module according to the present invention is a 3-level power semiconductor module that converts alternating current into direct current and outputs it, comprising: a first switch unit connected to an input terminal into which alternating current is input and composed of two or more MOSFET dies connected in parallel with each other; and a second switch unit composed of two or more MOSFET dies connected in parallel with each other, wherein one end is connected to a neutral point located between the positive output terminal and the negative output terminal of the power semiconductor module and the other end is connected to the first switch unit in a common source structure, and wherein the sources of the MOSFET dies connected in parallel in each of the first switch unit and the second switch unit are connected to each other through a connecting line. According to the present invention, the difference between the power loop inductance and the signal loop inductance between MOSFET dies connected in parallel can be minimized.

Description

Technology Field

[0001] The present invention relates to a power semiconductor module, and more specifically, to a 3-level power semiconductor module applied to a power converter that converts alternating current (AC) into direct current (DC). Background Technology

[0003] Conventional 2-level 3-phase rectifiers have only two voltage levels, with output terminal voltages of +0.5Vdc or -0.5Vdc. Consequently, the Total Harmonic Distortion (THD) of the voltage is high, requiring a relatively large-capacity input inductor to reduce the THD of the current. Additionally, IGBTs with high voltage ratings are generally used as switching elements in 2-level 3-phase rectifiers; however, when high-speed switching is required, IGBTs have high switching losses, which limits the ability to increase efficiency.

[0004] Accordingly, the application of multi-level power converters is increasing in order to reduce switching losses and lower THD in power semiconductor devices. In particular, among multi-levels, the 3-level topology is recognized as a structure that can secure maximum efficiency at low cost in high-power applications and is widely used in power converters such as PV (Photovoltaic), ESS (Energy Storage System), and DC Fast Charger.

[0005] 3-level topologies can be classified into I-type and T-type structures depending on the circuit diagram and the voltage configuration of the components used. Among 3-level T-type structures, the Vienna rectifier is a structure in which the main switch of a 3-level T-type MNPC rectifier is replaced with a high-speed diode, allowing the application of SiC MOSFETs instead of Si IGBTs as power semiconductor devices. Through this, switching losses can be significantly reduced and material costs can be lowered, enabling the implementation of low-cost and high-efficiency modules.

[0006] FIG. 1 illustrates an example of a T-type 3-level structure rectifier circuit according to the prior art.

[0007] Referring to FIG. 1, two MOSFET devices (MA, MB) are configured in a common source configuration, and the common source is shared as a signal source for the two MOSFET devices. In actual applications, to secure high current, the MOSFET devices (MA, MB) of the circuit diagram according to FIG. 1 are often implemented by connecting multiple MOSFET dies in parallel. However, according to the prior art, the design focuses only on balancing the stray inductance of the parallel-connected MOSFET dies and balancing the stray inductance between the MOSFET devices (MA, MB) of the common source structure.

[0008] As a result, if the two MOSFET devices (MA, MB) are not turned on and off simultaneously, a potential difference may occur between the grounds of each MOSFET device (MA, MB), which may cause gate-source oscillation. Additionally, if the dies connected in parallel have different dynamic characteristics regarding gate-source turn-on voltage, input capacitance, etc., a surge voltage may occur between the gate and source, which may lead to reliability issues with the gate-source of the MOSFET. Prior art literature

[0010] Korean Patent Publication No. 10-1710911 (Registered on Feb. 22, 2017) The problem to be solved

[0011] The present invention was devised to solve the problems of the aforementioned prior art, and aims to provide a MOSFET-based T-type 3-level power semiconductor module capable of minimizing gate-source oscillation of a MOSFET device and reducing surge voltage. means of solving the problem

[0013] The above objective can be achieved by a 3-level power semiconductor module according to one embodiment of the present invention, which converts alternating current into direct current and outputs it, comprising: a first switch unit connected to an input terminal into which alternating current is input and composed of two or more MOSFET dies connected in parallel with each other; and a second switch unit composed of two or more MOSFET dies connected in parallel with each other, wherein one end is connected to a neutral point located between the positive output terminal and the negative output terminal of the power semiconductor module and the other end is connected to the first switch unit in a common source structure, and wherein the sources of the MOSFET dies connected in parallel in each of the first switch unit and the second switch unit are connected to each other through a connecting line.

[0014] Here, the connecting line can be formed through wire bonding.

[0015] Meanwhile, the 3-level power semiconductor module may further include a first rectifier connected between the input terminal and the positive output terminal, comprising three rectifier diodes corresponding to each phase of the three-phase alternating current; and a second rectifier connected between the input terminal and the negative output terminal, comprising three rectifier diodes corresponding to each phase of the three-phase alternating current.

[0016] Additionally, it may further include a first capacitor connected between the positive output terminal and the neutral point; and a second capacitor connected between the neutral point and the negative output terminal.

[0017] And, the drain of each MOSFET die of the first switch unit is connected to the input terminal, and the drain of each MOSFET die of the second switch unit can be connected to the neutral point.

[0018] Meanwhile, the sources of each MOSFET die constituting the first switch unit and the second switch unit can be connected to the same pad area of ​​the DBC (Direct Bonding Copper) substrate. Effects of the invention

[0020] As described above, according to the present invention, the difference between the power loop inductance and the signal loop inductance between MOSFET dies connected in parallel can be reduced. Through this, gate-source oscillation that may be caused by deviations in the actual switching timing between MOSFET devices configured as a common source can be minimized. Brief explanation of the drawing

[0022] FIG. 1 is a circuit diagram of a T-type 3-level structure rectifier according to the prior art; FIG. 2 is a plan view of a 3-level power semiconductor module according to an embodiment of the present invention; FIG. 3 is a schematic circuit diagram of a 3-level power semiconductor module according to FIG. 2; and Figure 4 is a diagram showing the simulation results for comparing the difference between the power supply loop inductance and the signal loop inductance depending on the presence or absence of a connecting line connecting the sources of MOSFET dies connected in parallel in a power semiconductor module according to an embodiment of the present invention. Specific details for implementing the invention

[0023] Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. However, detailed descriptions of known functions or configurations that may obscure the essence of the present invention in the following description and the attached drawings are omitted. Additionally, it should be noted that identical components throughout the drawings are indicated by the same reference numerals whenever possible.

[0024] The 3-level power semiconductor module according to the present invention converts input AC into DC and outputs it. The 3-level power semiconductor module according to the present invention is a converter topology having unidirectional power transfer operation characteristics, and can be designed based on a Vienna rectifier in which some switching elements in a general 3-level converter structure are replaced with diodes.

[0025] FIG. 2 is a plan view of a 3-level power semiconductor module according to an embodiment of the present invention. FIG. 2 shows the power semiconductor module implemented by mounting each component on a DBC substrate. FIG. 3 is a schematic circuit diagram of the 3-level power semiconductor module (hereinafter referred to as the 'power semiconductor module') according to FIG. 2. Three power semiconductor modules (1) according to an embodiment of the present invention can be used to apply to 3-phase AC input conversion.

[0026] Referring to FIGS. 2 and 3, a power semiconductor module (1) according to an embodiment of the present invention includes an input section (10), an output section (20), a first switch section (30), a second switch section (40), a first rectifier section (50), and a second rectifier section (60).

[0027] The input section (10) includes a plurality of input terminals (T1) into which three-phase AC is input from an external AC power source.

[0028] The output section (20) includes a plurality of output terminals (T2) for outputting a DC voltage converted by a power semiconductor module (1), and the output terminals (T2) are divided into a positive output terminal (T2(DC+)) that outputs a + DC voltage and a negative output terminal (T2(DC-)) that outputs a - DC voltage. Here, a neutral point (N) is located between the positive output terminal (T2(DC+)) and the negative output terminal (T2(DC-)).

[0029] Additionally, the output section (20) includes a first capacitor (C1) connected between the positive output terminal (T2(DC+)) and the neutral point (N), and a second capacitor (C2) connected between the neutral point (N) and the negative output terminal (T2(DC-)). The first capacitor (C1) and the second capacitor (C2) perform the function of smoothing the voltage of the output terminal (T2).

[0030] The first switch unit (30) is connected to an input terminal (T1) to which an AC voltage is applied, and is composed of two or more MOSFET dies (M1, M2) connected in parallel with each other. The drain of each MOSFET die (M1, M2) is connected to the input terminal (T1), and the source is connected to the second switch unit (40) as described below.

[0031] Meanwhile, the sources of the MOSFET dies (M1, M2) connected in parallel to each other constituting the first switch unit (30) are connected to each other through a connecting line (33L). As shown in FIG. 2, when implementing a power semiconductor module (1) on a DBC substrate (101), the connecting line (33L) connecting the source of M1 and the source of M2 can be formed through wire bonding.

[0032] The second switch unit (40) is composed of two or more MOSFET dies (M3, M4) connected in parallel with each other, similar to the first switch unit (30). One end of the second switch unit (40) is connected to the neutral point (N) of the power semiconductor module (1), and the other end is connected to the first switch unit (30) in a common source structure. That is, the source of each MOSFET die (M3, M4) constituting the second switch unit (40) and the source of each MOSFET die (M1, M2) constituting the first switch unit (30) are electrically connected to each other in a common source structure, and the above common source is shared as a signal source for the MOSFET dies (M1-M4) of the first switch unit (30) and the second switch unit (40). Accordingly, the sources of each MOSFET die (M1-M4) constituting the first switch unit (30) and the second switch unit (40) are connected to the same pad area (101P) on the DBC substrate (101). For reference, the pad is a pattern of conductive material formed on the surface of the DBC substrate (101) and is provided to electrically connect each component mounted on the DBC substrate (101).

[0033] Meanwhile, the drain of the MOSFET dies (M3, M4) constituting the second switch unit (40) is connected to a neutral point (N) located between the positive output terminal (T2(DC+)) and the negative output terminal (T2(DC-)).

[0034] In addition, as described in the first switch section (30), the sources of the MOSFET dies (M3, M4) connected in parallel in the second switch section (40) are connected to each other through a connecting line (43L). In this case as well, as previously described, the connecting line (43L) connecting the source of M3 and the source of M4 can be formed through wire bonding.

[0035] For reference, FIGS. 2 and FIGS. 3 show an example in which the first and second switch sections (30, 40) are each configured with two MOSFET dies in parallel, but more MOSFET dies may be connected in parallel. Additionally, N-channel type MOSFETs may be applied to the first and second switch sections (30, 40).

[0036] Meanwhile, the power semiconductor module (1) includes a first rectifier (50) on the upper side and a second rectifier (60) on the lower side, corresponding to different current directions of the alternating current. The first rectifier (50) and the second rectifier (60) are each configured to include a total of three rectifier diodes so that one corresponds to each phase of the three-phase alternating current input. That is, the first rectifier (50) is connected between the input terminal (T1) and the positive output terminal (T2 (DC+)) and is configured to include three rectifier diodes D1, D2, and D3, and the second rectifier (60) is connected between the input terminal (T1) and the negative output terminal (T2 (DC-)) and is configured to include three rectifier diodes D4, D5, and D6.

[0037] When examining the operation of the power semiconductor module (1) according to the switching state of the first and second switch sections (30, 40), when both the first and second switch sections (30, 40) are turned off, either the first rectifier section (50) or the second rectifier section (60) operates selectively according to the direction of the alternating current, and +Vdc / 2[V] or -Vdc / 2[V] is output through the positive output terminal (T2(DC+)) or the negative output terminal (T2(DC-)). On the other hand, when both the first and second switch sections (30, 40) are turned on, 0[V] is output.

[0038] As described above, the power semiconductor module (1) according to an embodiment of the present invention can effectively reduce the difference between the power supply loop inductance and the signal loop inductance between MOSFET dies connected in parallel by adding connecting lines (33L, 43L) that connect the sources of MOSFET dies connected in parallel at the first switch unit (30) and the second switch unit (40), namely the sources of M1 and M2 and the sources of M3 and M4.

[0039] FIG. 4 shows simulation results for comparing the difference between the power supply loop inductance and the signal loop inductance depending on the presence or absence of connecting lines (33L, 43L) connecting the sources of MOSFET dies (M1 and M2, M3 and M4) connected in parallel in a power semiconductor module (1) according to an embodiment of the present invention. For reference, FIG. 4(a) shows each simulation current path (indicated in red), and the table in FIG. 4(b) shows the values ​​of the power supply loop inductance (L1) and the signal loop inductance (L2) depending on the presence or absence of connecting lines (33L, 43L) in each current path, and the difference between the values ​​of the loop inductances (L1, L2) depending on the path. Shows ).

[0040] Referring to FIG. 4, when there are no connecting lines (33L, 43L), the difference between the power supply loop inductance (L1) of M1 along the path (T1->S_1) from the input terminal (T1) to the common source pin (S) via M1 and the power supply loop inductance (L1) of M2 along the path (T1->S_2) from the input terminal (T1) to the common source pin (S) via M2 is 0.657 nH, whereas when connecting lines (33L, 43L) are present, the difference is reduced to 0.472 nH. In addition, when there are no connecting lines (33L, 43L), the difference between the signal loop inductance (L2) of M1 along the path (G1->S_1) from the gate pin (G1) connected to the gates of M1 and M2 to the common source pin (S) via M1 and the signal loop inductance (L2) of M2 along the path (G1->S_2) from the gate pin (G1) to the common source pin (S) via M2 is 0.006 nH (absolute value), whereas when connecting lines (33L, 43L) are present, the difference is reduced to 0 nH. For reference, a lead for signal application is connected to the pin.

[0041] In this way, according to the power semiconductor module (1) according to the embodiment of the present invention, by additionally connecting the sources of MOSFET dies (M1 and M2, M3 and M4) connected in parallel at each switch unit (30, 40) through connecting lines (33L, 43L), the difference in power supply and signal loop inductance according to the current path compared to the prior art can be reduced, and accordingly, by allowing the switching of the MOSFETs to be switched simultaneously and rapidly, the gate-source oscillation that may be caused by deviations in the switching timing of each device can be minimized, thereby improving system performance.

[0042] Terms such as "include," "compose," or "have" as described above, unless specifically stated otherwise, mean that the relevant component may be inherent; therefore, they should be interpreted as allowing for the inclusion of additional components rather than excluding them. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0043] Although the configuration and operation of a 3-level power semiconductor module according to one embodiment of the present invention have been described above, this is illustrative and those skilled in the art will understand that it is possible to substitute and modify parts of the aforementioned embodiments without departing from the technical spirit of the present invention.

[0044] Therefore, the scope of protection of the present invention should be understood to extend to the invention described in the patent claims and its equivalents. Explanation of the symbols

[0046] 1: 3-level power semiconductor module 10: Input section 20: Output section 30: 1st switch section 40: Second switch section 50: First rectifier 60: Second rectifier

Claims

Claim 1 A 3-level power semiconductor module that converts alternating current into direct current and outputs it, comprising: a first switch unit connected to an input terminal into which alternating current is input and composed of two or more MOSFET dies connected in parallel; and a second switch unit composed of two or more MOSFET dies connected in parallel, wherein one end is connected to a neutral point located between the positive output terminal and the negative output terminal of the power semiconductor module and the other end is connected to the first switch unit in a common source structure, wherein the sources of the MOSFET dies connected in parallel in each of the first switch unit and the second switch unit are connected to each other through a connecting line, the drain of each MOSFET die of the first switch unit is connected to the input terminal, and the drain of each MOSFET die of the second switch unit is connected to the neutral point. Claim 2 A 3-level power semiconductor module according to claim 1, characterized in that the connecting line is formed through wire bonding. Claim 3 A 3-level power semiconductor module according to claim 1, further comprising: a first rectifier connected between an input terminal and a positive output terminal, comprising three rectifier diodes corresponding to each phase of a 3-phase alternating current; and a second rectifier connected between an input terminal and a negative output terminal, comprising three rectifier diodes corresponding to each phase of a 3-phase alternating current. Claim 4 A 3-level power semiconductor module according to claim 1, further comprising: a first capacitor connected between the positive output terminal and the neutral point; and a second capacitor connected between the neutral point and the negative output terminal. Claim 5 delete Claim 6 A 3-level power semiconductor module according to claim 1, characterized in that the sources of each MOSFET die constituting the first switch unit and the second switch unit are connected to the same pad area of ​​a DBC (Direct Bonding Copper) substrate.

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