Display device, electronic device including the same

Abstract

A display device of one embodiment includes a first pixel and a second pixel. A light-emitting element and a driving circuit of the second pixel are disposed in a second region. The first pixel includes a silicon transistor and an oxide transistor disposed in the second region. The first pixel includes a first sub-light-emitting element and a second sub-light-emitting element disposed in the first region, and a first sub-pixel circuit and a second sub-pixel circuit disposed in the second region. A first connecting wire connecting the transistor included in the first sub-pixel circuit and the first sub-light-emitting element, and a second connecting wire connecting the transistor included in the second sub-pixel circuit and the second sub-light-emitting element are disposed on different layers and include a transparent conductive oxide.

Description

Technology Field

[0001] The present invention relates to a display device comprising a display area through which a light signal is transmitted, and an electronic device comprising the display device. Background Technology

[0002] The electronic device may include various electronic components, such as a display panel and an electronic module. The electronic module may include a camera, an infrared detection sensor, or a proximity sensor. The electronic module may be placed beneath the display panel. The transmittance of some areas of the display panel may be higher than the transmittance of other areas of the display panel. The electronic module may receive an optical signal or output an optical signal through the area with high transmittance. The problem to be solved

[0003] The present invention aims to provide a display device with a simplified stacked structure.

[0004] The present invention aims to provide an electronic device comprising a display device with a simplified stacked structure. means of solving the problem

[0005] One embodiment includes a display panel comprising a base layer including a first region and a second region adjacent to the first region, and a peripheral region adjacent to the display region, an insulating layer disposed on the base layer, a first pixel disposed on the base layer, and a second pixel, wherein the first pixel includes different first subpixels and second subpixels, the first subpixel includes a first sub-light-emitting element disposed in the first region and a first subpixel circuit electrically connected to the first sub-light-emitting element, the second subpixel includes a second sub-light-emitting element disposed in the first region and a second subpixel circuit electrically connected to the second sub-light-emitting element, and the second pixel includes a second light-emitting element disposed in the second region and a second pixel circuit disposed in the second region that is electrically connected to the second light-emitting element, and the first subpixel circuit includes a first silicon semiconductor pattern including a drain region, an active region, and a source region, and a first gate electrode superimposed on the active region of the first silicon semiconductor pattern, and the second region or the peripheral region A first oxide semiconductor pattern comprising a first silicon transistor disposed therein, a drain region, an active region, and a source region, and a second gate electrode superimposed on the active region of the first oxide semiconductor pattern, wherein the first oxide transistor disposed therein in the second region or the peripheral region, a first upper electrode superimposed on the first gate electrode, and a first connecting wire comprising a transparent conductive oxide that electrically connects the first silicon transistor or the first oxide transistor and the first sub-light-emitting element, superimposed on the first region, disposed on the same layer as the first upper electrode, and electrically connects the first silicon transistor or the first oxide transistor and the first sub-light-emitting element, and superimposed on the first region, disposed on the same layer as the first upper electrode, and wherein the second sub-pixel circuit comprises a drain region, an active region,A display device is provided comprising a second silicon semiconductor pattern including a source region and a third gate electrode overlapping the active region of the second silicon semiconductor pattern, a second silicon transistor disposed in the second region or the peripheral region, a second oxide semiconductor pattern including a drain region, an active region, and a source region, and a fourth gate electrode overlapping the active region of the second oxide semiconductor pattern, a second oxide transistor disposed in the second region or the peripheral region, a second upper electrode overlapping the third gate electrode, and a second connecting wire electrically connecting the second silicon transistor or the second oxide transistor and the second sub-light-emitting element, overlapping the first region, disposed on the same layer as the second oxide semiconductor pattern, and comprising a transparent conductive oxide.

[0006] The insulating layer may include a lower insulating layer disposed below the first upper electrode and the second upper electrode, and an upper insulating layer disposed above the first upper electrode and the second upper electrode.

[0007] The first and second oxide semiconductor patterns and the second connecting wiring may be disposed on the upper insulating layer.

[0008] The upper insulating layer may cover the first connecting wiring, the first upper electrode, and the second upper electrode.

[0009] It may further include insulating patterns disposed respectively between the active region of the first oxide semiconductor pattern and the second gate electrode, and between the active region of the second oxide semiconductor pattern and the fourth gate electrode.

[0010] The insulating layer may further include a cover insulating layer disposed on the upper insulating layer and covering the first and second oxide semiconductor patterns and the second connecting wiring.

[0011] The above cover insulating layer has an opening defined corresponding to the first region, and a part of the second connecting wiring may be exposed by the opening defined in the cover insulating layer.

[0012] The first connecting wire, the second connecting wire, the first and second upper electrodes, and the first and second oxide semiconductor patterns may each include at least one of In, Zn, and Sn.

[0013] The display area further includes a third area adjacent to the second area, and the display panel further includes a third pixel disposed in the third area, wherein the third pixel includes a third light-emitting element disposed in the third area and a third pixel circuit electrically connected to the third light-emitting element and disposed in the third area, and the number of the second light-emitting elements disposed per unit area of ​​the second area is less than the number of the third light-emitting elements disposed per unit area of ​​the third area, and the sum of the number of the first sub-light-emitting elements and the second sub-light-emitting elements disposed per unit area of ​​the first area may be less than the number of the third light-emitting elements disposed per unit area of ​​the third area.

[0014] The electrical conductivity of the second connecting wire may be greater than the electrical conductivity of the active region of the first and second oxide semiconductor patterns.

[0015] One embodiment comprises a display panel including a first region, a second region adjacent to the first region, and a third region adjacent to the second region, a base layer including a peripheral region adjacent to the display region, an insulating layer disposed on the base layer, and first to third pixels disposed on the base layer, wherein the first pixel comprises different first subpixels and second subpixels, the first subpixel comprises a first sub-light-emitting element disposed in the first region and a first subpixel circuit electrically connected to the first sub-light-emitting element, the second subpixel comprises a second sub-light-emitting element disposed in the first region and a second subpixel circuit electrically connected to the second sub-light-emitting element, the second pixel comprises a second light-emitting element disposed in the second region and a second pixel circuit disposed in the second region that is electrically connected to the second light-emitting element, and the third pixel comprises a third light-emitting element disposed in the third region and a third pixel circuit electrically connected to the third light-emitting element, wherein the first region is disposed per unit area The sum of the number of the first sub-luminescent element and the second sub-luminescent element is less than the number of the third luminescent element disposed per unit area in the third region, and the number of the second luminescent element disposed per unit area in the second region is less than the number of the third luminescent element disposed per unit area in the third region, and the first sub-pixel circuit includes a first silicon semiconductor pattern including a drain region, an active region, and a source region, and a first gate electrode overlapping the active region of the first silicon semiconductor pattern, and a first silicon transistor disposed in the second region or the peripheral region, a first oxide semiconductor pattern including a drain region, an active region, and a source region, and a second gate electrode overlapping the active region of the first oxide semiconductor pattern, andA first oxide transistor disposed in the second region or the peripheral region, a first upper electrode overlapping with the first gate electrode, and a first connecting wire comprising a transparent conductive oxide that electrically connects the first silicon transistor or the first oxide transistor and the first sub-luminescent element, overlaps in the first region, is disposed on the same layer as the first upper electrode, and is overlapped in the first region; the second sub-pixel circuit comprises a second silicon semiconductor pattern including a drain region, an active region, and a source region, and a third gate electrode overlapping in the active region of the second silicon semiconductor pattern; a second silicon transistor disposed in the second region or the peripheral region, a second oxide semiconductor pattern including a drain region, an active region, and a source region, and a fourth gate electrode overlapping in the active region of the second oxide semiconductor pattern; a second oxide transistor disposed in the second region or the peripheral region, a second upper electrode overlapping with the third gate electrode, electrically connects the second silicon transistor or the second oxide transistor and the second sub-luminescent element, overlaps in the first region, and the first connecting A display device is provided that includes a second connecting wire disposed on a different layer from the wiring and comprising a transparent conductive oxide.

[0016] The insulating layer may include a lower insulating layer disposed below the first upper electrode and the second upper electrode, and an upper insulating layer disposed above the first upper electrode and the second upper electrode.

[0017] The first and second upper electrodes and the first and second oxide semiconductor patterns may be disposed on the same layer on the lower insulating layer, and the first and second upper electrodes and the first and second oxide semiconductor patterns may be covered by the upper insulating layer.

[0018] It may further include a first insulating pattern disposed respectively between the active region of the first oxide semiconductor pattern and the second gate electrode and between the active region of the second oxide semiconductor pattern and the fourth gate electrode, and a second insulating pattern disposed between the lower insulating layer and the second connecting wire.

[0019] The first connecting wire, the second connecting wire, the first upper electrode, the second upper electrode, the first oxide semiconductor pattern, the second oxide semiconductor pattern, the second gate electrode, and the fourth gate electrode may each include at least one of In, Zn, and Sn.

[0020] Another embodiment includes a sensing area through which an optical signal passes, a display area adjacent to the sensing area, and a peripheral area adjacent to the display area, wherein the sensing area includes a device area in which a first light-emitting element, comprising a first sub-light-emitting element and a second sub-light-emitting element, overlaps, and a transmission area in which the first light-emitting element does not overlap, and an electronic module disposed below the display device, overlapping the sensing area, and receiving the optical signal, wherein the display device includes the first sub-light-emitting element disposed in the device area, a first sub-pixel electrically connected to the first sub-light-emitting element, the second sub-light-emitting element disposed in the device area, and a second sub-pixel electrically connected to the second sub-light-emitting element, and wherein the first sub-pixel circuit includes a first silicon semiconductor pattern comprising a drain area, an active area, and a source area, and a first gate electrode overlapping the active area of ​​the first silicon semiconductor pattern, wherein a first transistor disposed in the display area or the peripheral area, a first oxide semiconductor pattern comprising a drain area, an active area, and a source area, and of the first oxide semiconductor pattern A second gate electrode overlapping the active region, a second transistor disposed in the display region or the peripheral region, a first upper electrode overlapping the first gate electrode, and a first connecting wire electrically connecting the first transistor or the second transistor and the first sub-light-emitting element, overlapping the sensing region, disposed on the same layer as the first upper electrode, and comprising a transparent conductive oxide; wherein the second sub-pixel circuit comprises a second silicon semiconductor pattern including a drain region, an active region, and a source region, and a third gate electrode overlapping the active region of the second silicon semiconductor pattern, and a third transistor disposed in the display region or the peripheral region.An electronic device is provided comprising: a second oxide semiconductor pattern including a drain region, an active region, and a source region; a fourth gate electrode superimposed on the active region of the second oxide semiconductor pattern; a fourth transistor disposed in the display region or the peripheral region; a second upper electrode superimposed on the third gate electrode; and a second connecting wire electrically connecting the third transistor or the fourth transistor and the second sub-luminescent element, superimposed on the sensing region, disposed on the same layer as the second oxide semiconductor pattern, and comprising a transparent conductive oxide.

[0021] The display device further includes a display pixel comprising a second light-emitting element disposed in the display area and a second pixel circuit electrically connected to the second light-emitting element and disposed in the display area, and the sum of the number of the first sub-light-emitting element and the second sub-light-emitting element per unit area disposed in the sensing area may be less than the number of the second light-emitting element disposed per unit area in the display area.

[0022] The above electronic module may include a camera module.

[0023] The electrical conductivity of the second connecting wire may be greater than the electrical conductivity of each of the active region of the first oxide semiconductor pattern and the active region of the second oxide semiconductor pattern.

[0024] The above display device further includes a window, and the window may include a base film and a bezel pattern disposed on the base film and overlapping the surrounding area. Effects of the invention

[0025] A display device of one embodiment can provide a display device with a simplified stacking structure by utilizing one of the metal layers included in the transistors as a transparent electrode in a transparent region. Additionally, the display device with a simplified stacking structure can be manufactured using a relatively simplified process.

[0026] In addition, the display device of one embodiment can efficiently arrange wiring by placing the connecting wiring in a double layer on a different layer in the transparent area.

[0027] An electronic device of one embodiment can be manufactured using a relatively simplified process by including a display device and an electronic module with a simplified stacked structure. Additionally, the electronic device of one embodiment has the effect of efficiently arranging wiring by placing connecting wiring in a dual layer on a transparent area. Brief explanation of the drawing

[0028] FIG. 1 is a perspective view of an electronic device according to one embodiment. FIG. 2 is an exploded perspective view illustrating some components of an electronic device according to one embodiment. FIG. 3 is a cross-sectional view of a display device according to one embodiment. FIG. 4 is an equivalent circuit diagram of a pixel according to one embodiment. FIG. 5a is a plan view of a display panel according to one embodiment. Fig. 5b is an enlarged plan view of a part of Fig. 5a. Fig. 5c is an enlarged plan view of a part of Fig. 5b. Fig. 5d is an enlarged plan view of a part of Fig. 5b. FIG. 5e is a plan view of a display panel according to one embodiment. FIG. 6 is a cross-sectional view corresponding to a third region of a display device according to one embodiment. FIG. 7a is a cross-sectional view corresponding to the first region and the second region of a display device according to one embodiment. FIG. 7b is a cross-sectional view corresponding to the first region and the second region of a display device according to one embodiment. FIG. 8 is a cross-sectional view corresponding to the first region and the second region of a display device according to one embodiment. FIG. 9 is a cross-sectional view corresponding to the first region and the second region of a display device according to one embodiment. Specific details for implementing the invention

[0029] The present invention is capable of various modifications and may take various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the invention to the specific disclosed forms, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0030] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0031] Meanwhile, in the present application, "direct placement" may mean that there are no additional layers, films, regions, plates, etc. added between a part such as a layer, film, region, or plate and another part. For example, "direct placement" may mean that two layers or two members are placed without using additional members such as adhesive members between them.

[0032] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the effective illustration of the technical content.

[0033] "And / or" includes all one or more combinations that the associated configurations can define.

[0034] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0035] Additionally, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components illustrated in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings. In this specification, "placed on" may refer to a case where a component is placed not only on the upper side but also on the lower side.

[0036] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0037] Terms such as "include" or "have" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0038] Hereinafter, a display device according to one embodiment and an electronic device including the same will be described with reference to the drawings.

[0039] FIG. 1 is a perspective view of an electronic device (1000) according to one embodiment.

[0040] Referring to FIG. 1, the electronic device (1000) may include a display device, and in this embodiment, a mobile phone is illustrated as an example. However, it is not limited thereto, and the electronic device (1000) may be a tablet, monitor, television, car navigation system, game console, or wearable device.

[0041] An electronic device (1000) can display an image through a display area (1000A). The display area (1000A) may include a plane defined by a first direction (DR1) and a second direction (DR2). The display area (1000A) may further include curved surfaces bent from at least two sides of the plane. However, the shape of the display area (1000A) is not limited thereto. For example, the display area (1000A) may include only the plane, or the display area (1000A) may further include four curved surfaces bent from at least two, for example, four sides of the plane.

[0042] A portion of the display area (1000A) may be defined as a sensing area (1000SA). In FIG. 1, one sensing area (1000SA) is illustrated as an example, but the number of sensing areas (1000SA) is not limited thereto. The sensing area (1000SA) may be a part of the display area (1000A), but may have a higher light signal transmittance compared to other areas of the display area (1000A). Therefore, an image can be displayed through the sensing area (1000SA), and a light signal can be provided through the sensing area (1000SA).

[0043] The electronic device (1000) may include an electronic module placed in an area overlapping with the sensing area (1000SA). The electronic module may receive an optical signal provided from the outside through the sensing area (1000SA) or output an optical signal through the sensing area (1000SA). For example, the electronic module may be a camera module, a sensor that measures the distance between an object and a mobile phone such as a proximity sensor, a sensor that recognizes a part of the user's body (e.g., fingerprint, iris, or face), or a small lamp that outputs light, but is not particularly limited thereto.

[0044] The thickness direction of the electronic device (1000) may be a third direction (DR3) which is the normal direction of the display area (1000A). The front (or top) and back (or bottom) surfaces of the components constituting the electronic device (1000) may be defined based on the third direction (DR3).

[0045] FIG. 2 is an exploded perspective view illustrating some components of an electronic device (1000) according to one embodiment.

[0046] Referring to FIG. 2, the electronic device (1000) may include a display device (DD) and a camera module (CM). The display device (DD) can generate an image and detect an external input. The camera module (CM) is positioned below the display device (DD). When the display device (DD) is defined as a first electronic module constituting the electronic device (1000), the camera module (CM) may be defined as a second electronic module.

[0047] The display device (DD) may include a display area (100A) and a peripheral area (100N). The display area (100A) may correspond to the display area (1000A) shown in FIG. 1. A portion of the display device (DD) may be defined as a sensing area (100SA), and the sensing area (100SA) may have a higher transmittance than another portion of the display area (100A) (hereinafter referred to as the main display area). Thus, the sensing area (100SA) can provide external natural light to the camera module (CM). Since the sensing area (100SA) is a part of the display area (100A), it can display an image.

[0048] Pixels (PX) are placed in the display area (100A). Light-emitting elements are placed in the display area (100A), and light-emitting elements are not placed in the peripheral area (100N). Pixels (PX) are placed in the sensing area (100SA) and the main display area, respectively. However, the configuration of the pixels (PX) placed in the sensing area (100SA) and the main display area may differ. A detailed explanation regarding this will be provided later.

[0049] FIG. 3 is a cross-sectional view of a display device (DD) according to one embodiment.

[0050] Referring to FIG. 3, the display device (DD) may include a display panel (100), a sensor layer (200), an anti-reflection layer (300), and a window (400). The anti-reflection layer (300) and the window (400) may be joined by an adhesive layer (AD). However, this is merely exemplary and the embodiments are not limited thereto, and the window (400) may be placed directly on the anti-reflection layer (300).

[0051] The display panel (100) may be a configuration that substantially generates an image. The display panel (100) may be a light-emitting display panel, for example, the display panel (100) may be an organic light-emitting display panel, an inorganic light-emitting display panel, a micro LED display panel, or a nano LED display panel. The display panel (100) may also be referred to as a display layer.

[0052] The display panel (100) may include a base layer (110), a circuit layer (120), a light-emitting element layer (130), and an encapsulation layer (140).

[0053] The base layer (110) may be a member that provides a base surface on which the circuit layer (120) is placed. The base layer (110) may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc. The base layer (110) may be a glass substrate, a metal substrate, or a polymer substrate, etc. However, embodiments of the present invention are not limited thereto, and the base layer (110) may be an inorganic layer, an organic layer, or a composite material layer.

[0054] The base layer (110) may have a multilayer structure. For example, the base layer (110) may include a first synthetic resin layer, a multilayer or single-layer inorganic layer, and a second synthetic resin layer disposed on the multilayer or single-layer inorganic layer. Each of the first and second synthetic resin layers may include a polyimide-based resin, and is not particularly limited.

[0055] The circuit layer (120) may be placed on the base layer (110). The circuit layer (120) may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line, etc.

[0056] The light-emitting element layer (130) may be disposed on the circuit layer (120). The light-emitting element layer (130) may include a light-emitting element. For example, the light-emitting element may include an organic light-emitting material, an inorganic light-emitting material, an organic-inorganic light-emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED.

[0057] The encapsulation layer (140) may be placed on the light-emitting element layer (130). The encapsulation layer (140) may protect the light-emitting element layer (130) from foreign substances such as moisture, oxygen, and dust particles. The encapsulation layer (140) may include at least one inorganic layer. The encapsulation layer (140) may include a stacked structure of an inorganic layer / organic layer / inorganic layer.

[0058] The sensor layer (200) may be placed on the display panel (100). The sensor layer (200) may detect external input applied from the outside. The external input may be user input. User input may include various forms of external input such as a part of the user's body, light, heat, a pen, or pressure.

[0059] The sensor layer (200) can be formed on the display panel (100) through a continuous process. In this case, the sensor layer (200) can be placed directly on the display panel (100). Here, "placed directly" may mean that no third component is placed between the sensor layer (200) and the display panel (100). That is, no separate adhesive member may be placed between the sensor layer (200) and the display panel (100).

[0060] The anti-reflection layer (300) can be placed directly on the sensor layer (200). The anti-reflection layer (300) can reduce the reflectivity of external light incident from outside the display device (DD). The anti-reflection layer (300) can be formed on the sensor layer (200) through a continuous process. The anti-reflection layer (300) may include color filters. The color filters may have a predetermined arrangement. For example, the color filters may be arranged considering the light emission colors of the pixels included in the display panel (100). Additionally, the anti-reflection layer (300) may further include a black matrix adjacent to the color filters.

[0061] In one embodiment, the sensor layer (200) may be omitted. In this case, the anti-reflection layer (300) may be placed directly on the display panel (100). In one embodiment, the positions of the sensor layer (200) and the anti-reflection layer (300) may be interchanged.

[0062] Although not illustrated, in one embodiment, the display device (DD) may further include an optical layer disposed on the anti-reflection layer (300). For example, the optical layer may be formed on the anti-reflection layer (300) through a continuous process. The optical layer may improve the front brightness of the display device (DD) by controlling the direction of light incident from the display panel (100). For example, the optical layer may include an organic insulating layer in which openings are defined corresponding to each light-emitting region of the pixels included in the display panel (100), and a high-refractive index layer covering the organic insulating layer and filling the openings. The high-refractive index layer may have a higher refractive index than the organic insulating layer.

[0063] The window (400) may provide the front surface of the electronic device (1000). The window (400) may include a glass film or a synthetic resin film as a base film. The window (400) may further include an anti-reflective layer or an anti-fingerprint layer. The window (400) may include a glass film or a synthetic resin film. The window (400) may further include a bezel pattern (BZ, see FIG. 5e) that overlaps the peripheral area (DP-NA) of the display panel (100).

[0064] FIG. 4 is an equivalent circuit diagram of a pixel (PX) according to one embodiment.

[0065] Referring to FIG. 4, an equivalent circuit diagram of one pixel (PX) among the plurality of pixels (PX) shown in FIG. 2 is illustrated. The pixel (PX) may include a light-emitting element (LD) and a pixel circuit (PC). The light-emitting element (LD) may be a component included in the light-emitting element layer (130) of FIG. 3, and the pixel circuit (PC) may be a component included in the circuit layer (120) of FIG. 3.

[0066] The pixel circuit (PC) may include a plurality of transistors (T1 to T7, or thin-film transistors) and a storage capacitor (Cst). The plurality of transistors (T1 to T7) and the storage capacitor (Cst) may be electrically connected to signal lines (SL1, SL2, SLp, SLn, EL, DL), a first initialization voltage line (VL1), a second initialization voltage line (VL2) (or, an anode initialization voltage line) and a driving voltage line (PL).

[0067] A plurality of transistors (T1 to T7) may include a driving transistor (T1, or the first transistor), a switching transistor (T2, or the second transistor), a compensation transistor (T3, or the third transistor), a first initialization transistor (T4, or the fourth transistor), an operation control transistor (T5, or the fifth transistor), a light emission control transistor (T6, or the sixth transistor), and a second initialization transistor (T7, or the seventh transistor).

[0068] A light-emitting element (LD) may include a first electrode (e.g., an anode electrode or a pixel electrode) and a second electrode (e.g., a cathode electrode or a common electrode). The first electrode of the light-emitting element (LD) may be connected to a driving transistor (T1) via a light-emitting control transistor (T6) to receive a driving current (ILD), and the second electrode may receive a low power supply voltage (ELVSS). The light-emitting element (LD) may generate light of a brightness corresponding to the driving current (ILD).

[0069] Some of the plurality of transistors (T1 to T7) may be NMOS (n-channel MOSFETs) and the rest may be PMOS (p-channel MOSFETs). For example, among the plurality of transistors (T1 to T7), the compensation transistor (T3) and the first initialization transistor (T4) may be NMOS (n-channel MOSFETs) and the rest may be PMOS (p-channel MOSFETs).

[0070] According to one embodiment, among the plurality of transistors (T1 to T7), the compensation transistor (T3), the first initialization transistor (T4), and the second initialization transistor (T7) may be NMOS, and the remainder may be PMOS. According to one embodiment, only one of the plurality of transistors (T1 to T7) may be NMOS, and the remainder may be PMOS. According to one embodiment, all of the plurality of transistors (T1 to T7) may be NMOS, or all of them may be PMOS.

[0071] The signal line may include a first current scan line (SL1) that transmits a first scan signal (Sn), a second current scan line (SL2) that transmits a second scan signal (Sn'), a prior scan line (SLp) that transmits a previous scan signal (Sn-1) to a first initialization transistor (T4), a light emission control line (EL) that transmits a light emission control signal (En) to an operation control transistor (T5) and a light emission control transistor (T6), a next scan line (SLn) that transmits a subsequent scan signal (Sn+1) to a second initialization transistor (T7), and a data line (DL) that intersects with the first current scan line (SL1) and transmits a data signal (Dm).

[0072] The driving voltage line (PL) transmits a driving voltage (ELVDD) to the driving transistor (T1), and the first initialization voltage line (VL1) can transmit an initialization voltage (Vint1) that initializes the driving transistor (T1) and the first electrode of the light-emitting element (LD).

[0073] The gate of the driving transistor (T1) is connected to the storage capacitor (Cst), the source of the driving transistor (T1) is connected to the driving voltage line (PL) via the operation control transistor (T5), and the drain of the driving transistor (T1) can be electrically connected to the first electrode of the light-emitting element (LD) via the light-emitting control transistor (T6). The driving transistor (T1) receives a data signal (Dm) according to the switching operation of the switching transistor (T2) and transmits a driving current (I) to the light-emitting element (LD). LD Can supply ).

[0074] The gate of the switching transistor (T2) is connected to the first current scan line (SL1) that transmits the first scan signal (Sn), the source of the switching transistor (T2) is connected to the data line (DL), and the drain of the switching transistor (T2) is connected to the source of the driving transistor (T1) and can be connected to the driving voltage line (PL) via the operation control transistor (T5). The switching transistor (T2) can perform a switching operation in which it is turned on according to the first scan signal (Sn) received through the first current scan line (SL1) and transmits the data signal (Dm) transmitted to the data line (DL) to the source of the driving transistor (T1).

[0075] The gate of the compensation transistor (T3) is connected to the second current scan line (SL2). The drain of the compensation transistor (T3) is connected to the drain of the driving transistor (T1) and can be connected to the first electrode of the light-emitting element (LD) via the light-emitting control transistor (T6). The source of the compensation transistor (T3) can be connected to the first electrode (CE10) of the storage capacitor (Cst) and the gate of the driving transistor (T1). Additionally, the source of the compensation transistor (T3) can be connected to the drain of the first initialization transistor (T4).

[0076] The compensation transistor (T3) is turned on according to the second scan signal (Sn') received through the second current scan line (SL2) to electrically connect the gate and drain of the driving transistor (T1), thereby allowing the driving transistor (T1) to be diode-connected.

[0077] The gate of the first initialization transistor (T4) can be connected to the previous scan line (SLp). The source of the first initialization transistor (T4) can be connected to the source of the second initialization transistor (T7) and the first initialization voltage line (VL1). The drain of the first initialization transistor (T4) can be connected to the first electrode (CE10) of the storage capacitor (Cst), the source of the compensation transistor (T3), and the gate of the driving transistor (T1). The first initialization transistor (T4) can perform an initialization operation by turning on according to the previous scan signal (Sn-1) received through the previous scan line (SLp) to transmit an initialization voltage (Vint1) to the gate of the driving transistor (T1) and initialize the voltage of the gate of the driving transistor (T1).

[0078] The gate of the operation control transistor (T5) is connected to the light emission control line (EL), the operation control source of the operation control transistor (T5) is connected to the driving voltage line (PL), and the drain of the operation control transistor (T5) can be connected to the source of the driving transistor (T1) and the drain of the switching transistor (T2).

[0079] The gate of the light-emitting control transistor (T6) is connected to the light-emitting control line (EL), and the light-emitting control source of the light-emitting control transistor (T6) is connected to the drain of the driving transistor (T1) and the drain of the compensation transistor (T3), and the drain of the light-emitting control transistor (T6) can be electrically connected to the drain of the second initialization transistor (T7) and the first electrode of the light-emitting element (LD).

[0080] The operation control transistor (T5) and the light emission control transistor (T6) are simultaneously turned on according to the light emission control signal (En) received through the light emission control line (EL), so that the driving voltage (ELVDD) is transmitted to the light emission element (LD) and the driving current (I) to the light emission element (LD) LD Make ) flow.

[0081] The gate of the second initialization transistor (T7) is subsequently connected to the scan line (SLn), the drain of the second initialization transistor (T7) is connected to the drain of the light emission control transistor (T6) and the first electrode of the light-emitting element (LD), and the source of the second initialization transistor (T7) is connected to the second initialization voltage line (VL2) to receive the anode initialization voltage (Vint2). The second initialization transistor (T7) is subsequently turned on according to the scan signal (Sn+1) received through the scan line (SLn) to initialize the first electrode of the light-emitting element (LD).

[0082] In another embodiment, the second initialization transistor (T7) can be connected to the light emission control line (EL) and driven according to the light emission control signal (En). Meanwhile, the positions of the source and drain can be swapped depending on the type of transistor (p-type or n-type).

[0083] The storage capacitor (Cst) may include a first electrode (CE10) and a second electrode (CE20). The first electrode (CE10) of the storage capacitor (Cst) is connected to the gate of the driving transistor (T1), and the second electrode (CE20) of the storage capacitor (Cst) is connected to the driving voltage line (PL). The storage capacitor (Cst) may store a charge corresponding to the difference between the voltage of the gate of the driving transistor (T1) and the driving voltage (ELVDD).

[0084] The boosting capacitor (Cbs) may include a first electrode (CE11) and a second electrode (CE21). The first electrode (CE11) of the boosting capacitor (Cbs) is connected to the first electrode (CE11) of the storage capacitor (Cst), and the second electrode (CE21) of the boosting capacitor (Cbs) may receive a first scan signal (Sn). The boosting capacitor (Cbs) can compensate for a voltage drop in the gate by increasing the voltage in the gate of the driving transistor (T1) at the point when the provision of the first scan signal (Sn) is stopped.

[0085] The specific operation of each pixel (PX) according to one embodiment is as follows.

[0086] During the initialization period, when a previous scan signal (Sn-1) is supplied through the previous scan line (SLp), the first initialization transistor (T4) is turned on in response to the previous scan signal (Sn-1), and the driving transistor (T1) is initialized by the initialization voltage (Vint1) supplied from the first initialization voltage line (VL1).

[0087] During the data programming period, when a first scan signal (Sn) and a second scan signal (Sn') are supplied through the first current scan line (SL1) and the second current scan line (SL2), the switching transistor (T2) and the compensation transistor (T3) are turned on in response to the first scan signal (Sn) and the second scan signal (Sn'). At this time, the driving transistor (T1) is diode-connected by the turned-on compensation transistor (T3) and is forward-biased.

[0088] Then, a compensation voltage (Dm+Vth, where Vth is a negative value) that is reduced by the threshold voltage (Vth) of the driving transistor (T1) from the data signal (Dm) supplied from the data line (DL) is applied to the gate of the driving transistor (T1).

[0089] A driving voltage (ELVDD) and a compensation voltage (Dm+Vth) are applied across the storage capacitor (Cst), and a charge corresponding to the voltage difference across the storage capacitor (Cst) is stored.

[0090] During the light emission period, the operation control transistor (T5) and the light emission control transistor (T6) are turned on by the light emission control signal (En) supplied from the light emission control line (EL). A driving current (ILD) is generated according to the voltage difference between the gate voltage of the driving transistor (T1) and the driving voltage (ELVDD), and the driving current (ILD) is supplied to the light emission element (LD) through the light emission control transistor (T6).

[0091] In this embodiment, at least one of the plurality of transistors (T1 to T7) includes a semiconductor layer containing oxide, and the remainder includes a semiconductor layer containing silicon.

[0092] Specifically, the driving transistor (T1), which directly affects the brightness of the display device, is configured to include a semiconductor layer composed of polycrystalline silicon with high reliability, thereby enabling the implementation of a high-resolution display device.

[0093] Meanwhile, oxide semiconductors possess high carrier mobility and low leakage current, so the voltage drop is not significant even during long driving times. In other words, since the change in image color due to voltage drop is not significant even during low-frequency driving, low-frequency driving is possible.

[0094] As such, since oxide semiconductors have the advantage of low leakage current, at least one of the compensation transistor (T3) connected to the gate of the driving transistor (T1), the first initialization transistor (T4), and the second initialization transistor (T7) is adopted as an oxide semiconductor to prevent leakage current from flowing to the gate and at the same time reduce power consumption.

[0095] FIG. 5a is a plan view of a display panel (DP) according to one embodiment. FIG. 5b is an enlarged plan view of a portion (10A) of FIG. 5a. FIG. 5c is an enlarged plan view of a portion (200A) of FIG. 5b. FIG. 5d is an enlarged plan view of a portion (300A) of FIG. 5b. FIG. 5e is a plan view of a display panel according to one embodiment.

[0096] Referring to FIG. 5a, the display panel (100) may include a display area (DP-A) and a peripheral area (DP-NA). The peripheral area (DP-NA) is adjacent to the display area (DP-A) and may surround at least a portion of the display area (DP-A). The peripheral area (DP-NA) may correspond to the peripheral area (100N) of FIG. 3.

[0097] The display area (DP-A) may include a first area (DP-A1), a second area (DP-A2), and a third area (DP-A3). The first area (DP-A1) may overlap (or correspond) with the sensing area (1000SA) shown in FIG. 1 or the sensing area (100SA) shown in FIG. 2. In this embodiment, the first area (DP-A1) is shown as a circular shape, but it may have various shapes such as a polygon, an ellipse, a shape with at least one curved side, or an irregular shape, and is not limited to any one embodiment.

[0098] A display panel (100) may include a plurality of pixels (PX). The display panel (100) may include a first pixel (PX1) including a light-emitting element placed in a first area (DP-A1), a second pixel (PX2) including a light-emitting element placed in a second area (DP-A2), and a third pixel (PX3) including a light-emitting element placed in a third area (DP-A3). Each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may include a pixel circuit (PC) as illustrated in FIG. 4. The first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) illustrated in FIG. 5a are illustrated based on the location of the corresponding light-emitting element (LD, see FIG. 4). Meanwhile, pixels in which both the light-emitting element and the pixel circuit are placed in the second area (DP-A2), or in which both the light-emitting element and the pixel circuit are placed in the third area (DP-A3), may be referred to as display pixels.

[0099] Each of the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3) may be provided in multiple numbers. In this case, each of the first to third pixels (PX1, PX2, PX3) may include a red pixel, a green pixel, and a blue pixel, and, depending on the embodiment, may further include a white pixel.

[0100] The first region (DP-A1), the second region (DP-A2), and the third region (DP-A3) can be distinguished by light transmittance or resolution. Light transmittance and resolution are measured within a reference area. The first region (DP-A1) may have a higher light transmittance compared to the second region (DP-A2) and the third region (DP-A3). This is because the ratio of the occupied area of ​​the light-shielding structure described below to the first region (DP-A1) is lower compared to the second region (DP-A2) and the third region (DP-A3). The non-occupied area of ​​the light-shielding structure corresponds to the transmission area of ​​the light signal. The light-shielding structure may include the conductive pattern of the circuit layer described below, a pixel defining film, a pixel defining pattern, etc.

[0101] The third region (DP-A3) may have a higher resolution compared to the first region (DP-A1) and the second region (DP-A2). The third region (DP-A3) may have a larger number of light-emitting elements arranged within a reference area (or the same area) compared to the first region (DP-A1) and the second region (DP-A2).

[0102] When classified based on light transmittance, the first region (DP-A1) may be the first transmittance region, and the second region (DP-A2) and the third region (DP-A3) may be different parts of the second transmittance region that are distinct from the first transmittance region. The transmittance of the second region (DP-A2) and the third region (DP-A3) may be substantially the same. Even if the transmittance of the second region (DP-A2) and the third region (DP-A3) is not the same, because the transmittance of the first region (DP-A1) is significantly higher than the transmittance of the second region (DP-A2) and the third region (DP-A3) respectively, when the first region (DP-A1) is defined as the first transmittance region, the second region (DP-A2) and the third region (DP-A3) may be defined as the second transmittance region.

[0103] When classified based on resolution, the first region (DP-A1) may be a first resolution region having a first resolution, and the second region (DP-A2) and the third region (DP-A3) may be second resolution regions having a second resolution. The first resolution of the first resolution region may be lower than the second resolution of the second resolution region. Resolution may be classified by the number of light-emitting elements arranged per reference area. The number of light-emitting elements per reference area of ​​the first region (DP-A1) may be less than the number of light-emitting elements per reference area of ​​the second region (DP-A2). The number of light-emitting elements per reference area of ​​the second region (DP-A2) may be substantially the same as the number of light-emitting elements per reference area of ​​the third region (DP-A3).

[0104] Referring to FIG. 5b, the first pixel (PX1) may include a first light-emitting element (LD1) and a first pixel circuit (PC1) electrically connected to the first light-emitting element (LD1). The second pixel (PX2) may include a second light-emitting element (LD2) and a second pixel circuit (PC2) for driving the second light-emitting element (LD2), and the third pixel (PX3) may include a third light-emitting element (LD3) and a third pixel circuit (PC3) for driving the third light-emitting element (LD3).

[0105] The first light-emitting element (LD1) is placed in the first area (DP-A1), and the first pixel circuit (PC1) is placed in the second area (DP-A2). The second light-emitting element (LD2) and the second pixel circuit (PC2) are placed in the second area (DP-A2). The third light-emitting element (LD3) and the third pixel circuit (PC3) are placed in the third area (DP-A3).

[0106] To increase the light transmittance of the first region (DP-A1), the first pixel circuit (PC1) is moved from the first region (DP-A1) to the second region (DP-A2). By removing light-blocking structures such as transistors, the occupancy of the transmittance area is increased, and as a result, the transmittance of the first region (DP-A1) is improved. The first pixel circuit (PC1) may also be placed in the surrounding region (DP-NA) in addition to the second region (DP-A2).

[0107] Meanwhile, the first pixel (PX1) may include first and second subpixels (SPX1 to SPX2). The first pixel (PX1) may further include a third subpixel (SPX3). The first subpixel (SPX1) includes a first sub-light-emitting element (SLD1) disposed spaced apart from the first subpixel circuit (SPC1) in a first direction (DR1). The second subpixel (PX2) includes a second sub-light-emitting element (SLD2) disposed spaced apart from the second subpixel circuit (SPC2) in a first direction (DR1). The third subpixel (PX3) includes a third sub-light-emitting element (SLD3) disposed spaced apart from the third subpixel circuit (SPC3) in a second direction (DR2).

[0108] Although not shown, the sub-emissive element and sub-pixel circuit included in the sub-pixel positioned to the right of the first region (DP-A1) may have a similar arrangement relationship to the first sub-emissive element (SLD1) and first sub-pixel circuit (SPC1) positioned to the left of the first region (DP-A1). The sub-emissive element and sub-pixel circuit included in the sub-pixel positioned to the lower side of the first region (DP-A1) may have a similar arrangement relationship to the third sub-emissive element (SLD3) and third sub-pixel circuit (SPC3) positioned to the upper side of the first region (DP-A1). In FIG. 5c, the first electrodes (AE1, AE2, AE3) of the light-emitting elements are illustrated to represent the first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3), respectively. To improve the transmittance of the first region (DP-A1), the first light-emitting element (LD1) is positioned less than the third light-emitting element (LD3) within the reference area. For example, the resolution of the first region (DP-A1) may be about 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, 1 / 16, etc. of the resolution of the third region (DP-A3). For example, the resolution of the third region (DP-A3) may be about 400 ppi or higher, and the resolution of the first region (DP-A1) may be about 200 ppi or 100 ppi. However, this is merely an example and is not specifically limited thereto. Meanwhile, to increase the brightness of the first region (DP-A1), the first electrode (AE1) of the first light-emitting element (LD1) may have a larger area than the first electrode (AE3) of the third light-emitting element (LD3).

[0109] At least a portion of the area in the first region (DP-A1) where the first light-emitting element (LD1) is not placed may be defined as a transparent region. For example, at least a portion of the area in the first region (DP-A1) where the first electrode (AE1) of the first light-emitting element (LD1) is not placed may be defined as a transparent region.

[0110] In order to secure an area within the second region (DP-A2) where the first pixel circuit (PC1) is to be placed, the second light-emitting element (LD2) is placed less than the third light-emitting element (LD3) within the reference area. The first pixel circuit (PC1) is placed in the area within the second region (DP-A2) where the second pixel circuit (PC2) is not placed.

[0111] The first light-emitting element (LD1) can be electrically connected to the first pixel circuit (PC1) via a connecting wire (TWL). The connecting wire (TWL) overlaps the first region (DP-A1) and the second region (DP-A2). The connecting wire (TWL) may overlap with a transparent region (TA, see FIG. 8). At least a portion of the connecting wire (TWL) may comprise a transparent conductive material. Within the first region (DP-A1) of FIG. 5c, at least a portion of the region where the first electrode (AE1) is not placed may be substantially a transparent region (TA). The transparent region (TA) is described in detail later in FIG. 8.

[0112] Meanwhile, different first to third sub-emissive elements (SLD1 to SLD3) placed in the first region (DP-A1) can each be electrically connected to different first to third sub-pixel circuits (SPC1 to SPC3). Each of the different first emissive elements (SLD1 to SLD3) can be electrically connected to different first to third sub-pixel circuits (SPC1 to SPC3) through connecting wires (TWL) placed on different layers. By placing the connecting wires (TWL) on different layers, the connecting wires can be efficiently placed within the same area compared to when the connecting wires (TWL) are placed on the same layer.

[0113] The first electrodes (AE1, AE2, AE3) may have curved edges. The first electrodes (AE1, AE2, AE3) having curved edges can minimize light diffraction. In particular, the first electrode (AE1) of the first light-emitting element (LD1) can minimize light diffraction passing through the transmission region.

[0114] The first electrode (AE1) of the first light-emitting element (LD1) may have an elliptical shape in a planar plane. The first electrode (AE1) can secure a light-emitting area while simultaneously securing a connection area of ​​the connecting wire (TWL).

[0115] Referring to FIG. 5d, three first light-emitting elements (LD1) of three colors are illustrated. A first electrode (AE1-R), a first electrode (AE1-G), and a first electrode (AE1-B) are illustrated to represent the first light-emitting element of the first color (LD1), the first light-emitting element of the second color (LD1), and the first light-emitting element of the third color (LD1), respectively. The first color may be red, the second color may be green, and the third color may be blue, but is not limited thereto, and the third color inherent in the first color may be adopted as another primary three color.

[0116] First to fourth rows of light-emitting elements (PXL1 to PXL4) arranged within a first region (DP-A1) are illustrated. In each of the first and third rows of light-emitting elements (PXL1 and PXL3), first electrodes (AE1-G) of a second color may be arranged along a first direction (DR1). In each of the second and fourth rows of light-emitting elements (PXL2 and PXL4), first electrodes (AE1-R) of a first color and first electrodes (AE1-B) of a third color may be arranged alternately along a first direction (DR1). Within the second direction (DR2), the first electrode (AE1-R) of the first color of the second row of light-emitting elements (PXL2) is aligned with the first electrode (AE1-B) of the third color of the fourth row of light-emitting elements (PXL4). The arrangement of these first to fourth light-emitting element rows (PXL1 to PXL4) can be extended to a second region (DP-A2) and a third region (DP-A3).

[0117] The first electrodes (AE1-R, AE1-G, AE1-B) placed in a part area (300A1) correspond to the first electrodes of the first pixel (PX1) placed to the left of the first area (DP-A1) shown in FIG. 5b, and the first electrodes (AE1-R, AE1-G, AE1-B) placed in another part area (300A2) correspond to the first electrodes of the first pixel (PX1) placed to the upper side of the first area (DP-A1) shown in FIG. 5b. Depending on the position of the first electrodes (AE1-R, AE1-G, AE1-B), the extension direction of the connecting wire (TWL) may be different.

[0118] Referring to FIG. 5e, the first pixel circuit (PC1) may be placed in a fourth area other than the first area (DP-A1), the second area (DP-A2), and the third area (DP-A3). For example, as shown in FIG. 5e, the first pixel circuit (PC1) may be placed in the surrounding area (DP-NA). When the first pixel circuit (PC1) is placed in the surrounding area (DP-NA), the connecting wire (TWL) may overlap the first area (DP-A1), the second area (DP-A2), the third area (DP-A3), and the surrounding area (DP-NA).

[0119] FIG. 6 is a cross-sectional view corresponding to a third region (DP-A3) of a display device (DD) according to one embodiment. FIG. 7a is a cross-sectional view corresponding to a first region (DP-A1) and a second region (DP-A2) of a display device according to one embodiment. FIG. 7b is a cross-sectional view corresponding to a first region (DP-A1) and a second region (DP-A2) of a display device according to one embodiment. FIG. 7a illustrates a first sub-light-emitting element (SLD1) connected to a first transistor (S-TFT) through a second connecting wire (TWL2), and FIG. 7b illustrates a second sub-light-emitting element (LD2) shown in FIG. 7a connected to a first transistor (S-TFT) through a first connecting wire (TWL1). The first sub-light-emitting element (SLD1) shown in FIG. 7a and the second sub-light-emitting element (SLD2) shown in FIG. 7b may be different from each other. For example, the first sub-luminescent element (SLD1) shown in FIG. 7a is the first sub-luminescent element (SLD1, FIG. 5b) shown in FIG. 5b, and the second sub-luminescent element (SLD2) shown in FIG. 7b may be the second or third sub-luminescent element (SLD2, SLD3, FIG. 5b). Hereinafter, common contents of FIG. 6 to 7b will be described together, and FIG. 7a and 7b will be distinguished and described only when explaining the relationship between the first luminescent elements (SLD1, SLD2) and the connecting wires (TWL1, TWL2), which is the difference between FIG. 7a and 7b.

[0120] In FIG. 6, silicon transistors (S-TFTs) and oxide transistors (O-TFTs) of the third light-emitting element (LD3) and the third pixel circuit (PC3, see FIG. 5c) are illustrated. In the equivalent circuit illustrated in FIG. 4, the third and fourth transistors (T3, T4) may be oxide transistors (O-TFTs), and the remaining transistors may be silicon transistors (S-TFTs). FIG. 7a and FIG. 7b illustrate parts of the first light-emitting elements (SLD1, SLD2) and the first pixel circuits (SPC1, SPC2), and parts of the second light-emitting element (LD2) and the second pixel circuit (PC2). Specifically, FIG. 7a illustrates the first sub-light-emitting element (SLD1) and the first sub-pixel circuit (SPC1), and FIG. 7b illustrates the second sub-light-emitting element (SLD2) and the second sub-pixel circuit (SPC2). In FIGS. 7a and 7b, the silicon transistor (S-TFT) connected to the light-emitting elements (SPD1, SPD2, LD2) is the sixth transistor (T6) shown in FIG. 4, and the silicon transistor (S-TFT) not connected to the light-emitting elements (SPD1, SPD2, LD2) may be any one of the first, second, fifth, and seventh transistors (T1, T2, T5, T7) shown in FIG. 4. Meanwhile, the silicon transistor (S-TFT) may be referred to as the first silicon transistor when connected to the first sub-light-emitting element (SLD1) and as the second silicon transistor when connected to the second sub-light-emitting element (SLD2). Additionally, the oxide transistor (O-TFT) may be referred to as the first oxide transistor when connected to the first sub-light-emitting element (SLD1) and as the second oxide transistor when connected to the second sub-light-emitting element (SLD2). The buffer layer (10br) may be placed on the base layer (110). The buffer layer (10br) can prevent metal atoms or impurities from the base layer (110) from diffusing into the upper silicon semiconductor pattern (SP1).The silicon semiconductor pattern (SP1) includes an active region (AC1) of a silicon transistor (S-TFT). The buffer layer (10br) can control the rate of heat supply during the crystallization process for forming the silicon semiconductor pattern (SP1) so that the silicon semiconductor pattern (SP1) can be formed uniformly.

[0121] A first back metal layer (BMLa) may be disposed below a silicon transistor (S-TFT), and a second back metal layer (BMLb) may be disposed below an oxide transistor (O-TFT). The first and second back metal layers (BMLa, BMLb) may be disposed overlapping with the first to third pixel circuits (SPC1, SPC2, PC2, PC3). The first and second back metal layers (BMLa, BMLb) may block external light from reaching the first to third pixel circuits (SPC1, SPC2, PC2, PC3).

[0122] The first back metal layer (BMLa) may be positioned to correspond to at least a portion of each of the first to third pixel circuits (SPC1, SPC2, PC2, PC3). The first back metal layer (BMLa) may be positioned to overlap with a driving transistor (T1, see FIG. 4) implemented as a silicon transistor (S-TFT).

[0123] A first back metal layer (BMLa) may be disposed between the base layer (110) and the buffer layer (10br). In one embodiment, an inorganic barrier layer may be further disposed between the first back metal layer (BMLa) and the buffer layer (10br). The first back metal layer (BMLa) may be connected to an electrode or wiring and may receive a static voltage or signal from them. According to one embodiment, the first back metal layer (BMLa) may be a floating electrode in a form isolated from other electrodes or wiring.

[0124] The second back metal layer (BMLb) may be positioned corresponding to the bottom of the oxide transistor (O-TFT). The second back metal layer (BMLb) may be positioned between the second insulating layer (20) and the third insulating layer (30). The second back metal layer (BMLb) may be positioned on the same layer as the second electrode (CE20) of the storage capacitor (Cst). The second back metal layer (BMLb) may be connected to the contact electrode (BML2-C) to receive a constant voltage or signal. The contact electrode (BML2-C) may be positioned on the same layer as the second gate electrode (GT2) of the oxide transistor (O-TFT).

[0125] Each of the first back metal layer (BMLa) and the second back metal layer (BMLb) may include a reflective metal. For example, each of the first back metal layer (BMLa) and the second back metal layer (BMLb) may include silver (Ag), an alloy containing silver (Ag), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), and p+-doped amorphous silicon. The first back metal layer (BMLa) and the second back metal layer (BMLb) may include the same material or different materials.

[0126] Although not separately described, according to one embodiment, the second back metal layer (BMLb) may be omitted. The first back metal layer (BMLa) may extend to the bottom of the oxide transistor (O-TFT) so that the first back metal layer (BMLa) can block light incident on the bottom of the oxide transistor (O-TFT).

[0127] A silicon semiconductor pattern (SP1) can be placed on a buffer layer (10br). The silicon semiconductor pattern (SP1) may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the silicon semiconductor pattern (SP1) may include low-temperature polysilicon.

[0128] FIG. 6 illustrates only a portion of the silicon semiconductor pattern (SP1) placed on the buffer layer (10br), and additional silicon semiconductor patterns (SP1) may be placed in other areas. The silicon semiconductor pattern (SP1) may be arranged according to a specific rule across the pixels. The silicon semiconductor pattern (SP1) may have different electrical properties depending on whether it is doped. The silicon semiconductor pattern (SP1) may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region or a region doped at a lower concentration compared to the first region.

[0129] The conductivity of the first region is greater than the conductivity of the second region, and the first region can substantially function as an electrode or a signal line. The second region can substantially correspond to the active region (or channel) of the transistor. In other words, a part of the silicon semiconductor pattern (SP1) may be the active region of the transistor, another part may be the source or drain of the transistor, and yet another part may be a connecting electrode or a connecting signal line.

[0130] The source region (SE1, or source), active region (AC1, or channel), and drain region (DE1, or drain) of the silicon transistor (S-TFT) can be formed from a silicon semiconductor pattern (SP1). The source region (SE1) and the drain region (DE1) can extend in opposite directions from the active region (AC1) on a cross-section.

[0131] The first insulating layer (10) may be placed on the buffer layer (10br). The first insulating layer (10) may overlap in common with a plurality of pixels and cover a silicon semiconductor pattern (SP1). The first insulating layer (10) may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer (10) may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer (10) may be a single-layer silicon oxide layer. The insulating layer of the circuit layer (120) described below, as well as the first insulating layer (10), may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the materials described above, but is not limited thereto.

[0132] The first gate electrode (GT1) of the silicon transistor (S-TFT) may be placed on the first insulating layer (10). The first gate electrode (GT1) may be part of a metal pattern. The first gate electrode (GT1) may overlap with the active region (AC1). In the process of doping the silicon semiconductor pattern (SP1), the first gate electrode (GT1) may function as a mask. The first gate electrode (GT1) may include titanium (Ti), silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not particularly limited thereto.

[0133] The second insulating layer (20) is placed on the first insulating layer (10) and can cover the first gate electrode (GT1). The third insulating layer (30) can be placed on the second insulating layer (20). The second electrode (CE20) of the storage capacitor (Cst) can be placed between the second insulating layer (20) and the third insulating layer (30). Additionally, the first electrode (CE10) of the storage capacitor (Cst) can be placed between the first insulating layer (10) and the second insulating layer (20). Meanwhile, the first gate electrode (GT1) included in the first subpixel circuit (SPC1) is referred to as the first gate electrode, and the first gate electrode (GT1) included in the second subpixel circuit (SPC1) can be referred to as the third gate electrode.

[0134] The upper electrode (UE) may be disposed on the second insulating layer (20). The upper electrode (UE) may form a storage capacitor (Cst) together with the first gate electrode (GT1). The upper electrode (UE) may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). Meanwhile, the upper electrode (UE) may be referred to as the first upper electrode or the second upper electrode. For example, the upper electrode included in the first subpixel circuit (SPC1, FIG. 5b) may be referred to as the first upper electrode, and the upper electrode included in the second subpixel circuit (SPC2, FIG. 5b) may be referred to as the second upper electrode.

[0135] The oxide semiconductor pattern (SP2) may be placed on the third insulating layer (30). The oxide semiconductor pattern (SP2) may include the active region (AC2) of the oxide transistor (O-TFT) described later. The oxide semiconductor pattern (SP2) may include an oxide semiconductor. The oxide semiconductor pattern (SP2) may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3).

[0136] The oxide semiconductor may include multiple regions distinguished by whether the transparent conductive oxide is reduced. The region where the transparent conductive oxide is reduced (hereinafter, the reduced region) has greater conductivity than the region where it is not reduced (hereinafter, the non-reduced region). The reduced region substantially serves as the source / drain or signal line of the transistor. The non-reduced region substantially corresponds to the semiconductor region (or active region or channel) of the transistor. In other words, some regions of the oxide semiconductor pattern (SP2) may be the semiconductor region of the transistor, some regions may be the source / drain region of the transistor, and yet another part may be the signal transmission region.

[0137] The source region (SE2, or source), active region (AC2, or channel), and drain region (DE2, or drain) of the oxide transistor (O-TFT) can be formed from an oxide semiconductor pattern (SP2). The source region (SE2) and the drain region (DE2) can extend in opposite directions from the active region (AC2) on a cross-section.

[0138] The fourth insulating layer (40) may be placed on the third insulating layer (30). As shown in FIG. 6, the fourth insulating layer (40) may be an insulating pattern that overlaps the second gate electrode (GT2) of the oxide transistor (O-TFT) and exposes the source region (SE2) and drain region (DE2) of the oxide transistor (O-TFT). Although not shown, the fourth insulating layer (40) may overlap in common with a plurality of pixels and cover an oxide semiconductor pattern (SP2).

[0139] As shown in FIG. 6, the second gate electrode (GT2) of the oxide transistor (O-TFT) is placed on the fourth insulating layer (40). The second gate electrode (GT2) of the oxide transistor (O-TFT) may be part of a metal pattern. The second gate electrode (GT2) of the oxide transistor (O-TFT) overlaps the active region (AC2) of the oxide transistor (O-TFT).

[0140] The fifth insulating layer (50) is placed on the fourth insulating layer (40) and can cover the second gate electrode (GT2). The first connecting electrode (CNE1) can be placed on the fifth insulating layer (50). The first connecting electrode (CNE1) can be connected to the drain region (DE1) of the silicon transistor (S-TFT) through a contact hole penetrating the first to fifth insulating layers (10, 20, 30, 40, 50).

[0141] A sixth insulating layer (60) may be placed on top of a fifth insulating layer (50). A second connecting electrode (CNE2) may be placed on top of the sixth insulating layer (60). The second connecting electrode (CNE2) may be connected to a first connecting electrode (CNE1) through a contact hole penetrating the sixth insulating layer (60). A seventh insulating layer (70) is placed on top of the sixth insulating layer (60) and may cover the second connecting electrode (CNE2). An eighth insulating layer (80) may be placed on top of the seventh insulating layer (70).

[0142] Each of the sixth insulating layer (60), the seventh insulating layer (70), and the eighth insulating layer (80) may be an organic layer. For example, each of the sixth insulating layer (60), the seventh insulating layer (70), and the eighth insulating layer (80) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0143] Meanwhile, in FIGS. 7a, 7b, and 8, the first and second insulating layers (10, 20) are referred to as lower insulating layers (10, 20), and the third insulating layer (30) is referred to as upper insulating layer (30). Additionally, the fifth insulating layer (50) is referred to as cover insulating layer (50).

[0144] That is, the insulating layer may include a lower insulating layer (10, 20) and an upper insulating layer (30). The lower insulating layer (10, 20) may be placed below the upper electrode (UE). The upper insulating layer (30) may be placed above the upper electrode (UE). A cover insulating layer (50) may be placed on the upper insulating layer (30). An oxide semiconductor pattern (SP2), a fourth insulating layer (40) which is an insulating pattern, and a second gate electrode (GT2), etc., may be placed between the upper insulating layer (30) and the cover insulating layer (50). Meanwhile, the second gate electrode (GT2) included in the first subpixel circuit (SPC1) may be referred to as the second gate electrode, and the second gate electrode (GT2) included in the second subpixel circuit (SPC2) may be referred to as the fourth gate electrode.

[0145] The third light-emitting element (LD3) may include a first electrode (AE3, or pixel electrode), a light-emitting layer (EL3), and a second electrode (CE, or common electrode). The second electrode (CE) of the first light-emitting element (SLD1, SLD2) and the second light-emitting element (LD2) described below may have an integral shape with the second electrode (CE) of the third light-emitting element (LD3). That is, the second electrode (CE) may be provided in common to the first light-emitting element (SLD1, SLD2), the second light-emitting element (LD2), and the third light-emitting element (LD3).

[0146] The first electrode (AE3) of the third light-emitting element (LD3) may be disposed on the eighth insulating layer (80). The first electrode (AE3) of the third light-emitting element (LD3) may be a (semi)transparent electrode or a reflective electrode. According to one embodiment, each of the first electrodes (AE3) of the third light-emitting element (LD3) may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a transparent or semitransparent electrode layer formed on the reflective layer. The transparent or semitransparent electrode layer may include at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO) or indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode (AE3) of the third light-emitting element (LD3) may include a stacked structure of ITO / Ag / ITO.

[0147] A pixel defining film (PDL) may be placed on the eighth insulating layer (80). The pixel defining film (PDL) may contain the same material and be formed through the same process. The pixel defining film (PDL) may have the property of absorbing light, and for example, the pixel defining film (PDL) may have a black color. The pixel defining film (PDL) may contain a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining film (PDL) may correspond to a light-blocking pattern having light-blocking properties.

[0148] The pixel defining film (PDL) can cover a portion of the first electrode (AE3) of the third light-emitting element (LD3). For example, a second opening (PDL-OP2) that exposes a portion of the first electrode (AE3) of the third light-emitting element (LD3) can be defined in the pixel defining film (PDL). The pixel defining film (PDL) can increase the distance between the edge of the first electrode (AE3) of the third light-emitting element (LD3) and the second electrode (CE). Therefore, the pixel defining film (PDL) can serve to prevent the occurrence of arcs, etc., at the edge of the first electrodes (AE3).

[0149] Although not shown, a hole control layer may be disposed between the first electrode (AE3) and the light-emitting layer (EL3). The hole control layer includes a hole transport layer and may further include a hole injection layer. An electronic control layer may be disposed between the light-emitting layers (EL3) and the second electrode (CE). The electronic control layer includes an electron transport layer and may further include an electron injection layer. The hole control layer and the electronic control layer may be formed in common on a plurality of pixels (PX, see FIG. 5a) using an open mask.

[0150] The encapsulation layer (140) may be disposed on the light-emitting element layer (130). The encapsulation layer (140) may include sequentially stacked inorganic layers (141), organic layers (142), and inorganic layers (143), but the layers constituting the encapsulation layer (140) are not limited thereto.

[0151] Inorganic layers (141, 143) can protect the light-emitting element layer (130) from moisture and oxygen, and organic layer (142) can protect the light-emitting element layer (130) from foreign substances such as dust particles. The inorganic layers (141, 143) may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, etc. The organic layer (142) may include an acrylic-based organic layer, but is not limited thereto.

[0152] The sensor layer (200) may be placed on the display panel (100). The sensor layer (200) may be referred to as a sensor, an input detection layer, or an input detection panel. The sensor layer (200) may include a base layer (210), a first conductive layer (220), a sensing insulating layer (230), and a second conductive layer (240).

[0153] The base layer (210) may be placed directly on the display panel (100). The base layer (210) may be an inorganic layer comprising at least one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the base layer (210) may be an organic layer comprising epoxy resin, acrylic resin, or imide-based resin. The base layer (210) may have a single-layer structure or a multi-layer structure stacked along a third direction (DR3).

[0154] Each of the first conductive layer (220) and the second conductive layer (240) may have a single-layer structure or a multi-layer structure stacked along the third direction (DR3). The first conductive layer (220) and the second conductive layer (240) may include conductive lines defining a mesh-shaped sensing electrode. The conductive lines do not overlap the first aperture (PDL-OP1), the second aperture (PDL-OP2), and the apertures (PDP-OP1, PDP-OP2), and overlap the pixel defining pattern (PDP) and the pixel defining film (PDL). The sensing electrode defined by the first conductive layer (220) and the second conductive layer (240) overlaps at least the third region (DP-A3) shown in FIG. 5a.

[0155] The single-layer conductive layer may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Additionally, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, graphene, etc.

[0156] The conductive layer of the multilayer structure may include metal layers. The metal layers may have a three-layer structure, for example, titanium / aluminum / titanium. The conductive layer of the multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0157] The sensing insulating layer (230) may be disposed between the first conductive layer (220) and the second conductive layer (240). The sensing insulating layer (230) may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0158] Alternatively, the sensing insulating layer (230) may include an organic film. The organic film may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0159] The anti-reflection layer (300) may be placed on the sensor layer (200). The anti-reflection layer (300) may include a dividing layer (310), a first color filter (321), a second color filter (322), a third color filter (323), and a flattening layer (330).

[0160] The material constituting the dividing layer (310) is not particularly limited as long as it is a light-absorbing material. The dividing layer (310) is a layer having a black color, and in one embodiment, the dividing layer (310) may include a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include carbon black, a metal such as chromium, or oxides thereof.

[0161] The dividing layer (310) can cover the second conductive layer (240) of the sensor layer (200). The dividing layer (310) can prevent external light reflection by the second conductive layer (240). The dividing layer (310) overlaps with the second region (DP-A2, see FIG. 7a) and the third region (DP-A3), and can not overlap with the first region (DP-A1, see FIG. 7a). That is, as the dividing layer (310) is not placed in the first region (DP-A1, see FIG. 7a), the transmittance of the first region (DP-A1) can be further improved.

[0162] A second opening (310-OP2) may be defined in the dividing layer (310). The second opening (310-OP2) may overlap with the first electrode (AE3) of the third light-emitting element (LD3). The third color filter (323) may overlap with the third region (DP-A3). The third color filter (323) may overlap with the first electrode (AE3) of the third light-emitting element (LD3). The third color filter (323) may cover the second opening (310-OP2). The third color filter (323) may come into contact with the dividing layer (310).

[0163] The flattening layer (330) can cover the dividing layer (310) and the third color filter (323). The flattening layer (330) may include an organic material and may provide a flat surface on the upper surface of the flattening layer (330). In one embodiment, the flattening layer (330) may be omitted.

[0164] FIGS. 7A and 7B illustrate a second region (DP-A2) to which a fourth insulating layer (40) of the insulating pattern shown in FIG. 6 is applied. In FIGS. 7A and 7B, the oxide transistor (O-TFT) of the second pixel circuit (PC2) is not illustrated, unlike the first pixel circuit (PC1). The description of the first pixel (PX1) and the second pixel (PX2) that are common to the third pixel (PX3) described with reference to FIG. 6 is omitted.

[0165] Referring to FIG. 7a, the first electrode (AE1) of the first sub-emissive element (SLD1) can be electrically connected to a first sub-pixel circuit (SPC1) located in the second region (DP-A2). The first electrode (AE1) of the first sub-emissive element (SLD1) can be electrically connected to a first silicon transistor (S-TFT) or a first oxide transistor (O-TFT). FIG. 7a shows the first electrode (AE1) of the first sub-emissive element (SLD1) connected to the first silicon transistor (S-TFT).

[0166] Specifically, the first electrode (AE1) of the first light-emitting element (SLD1) can be electrically connected to the first subpixel circuit (SPC1) through the second connecting wire (TWL2) and connecting electrodes (CNE1', CNE2', CNE3', CPN). According to one embodiment, one of the connecting electrodes (CNE1', CNE2') may be omitted. The second connecting electrode (CNE2') may be omitted, and the first connecting electrode (CNE1') may be directly connected to the second connecting wire (TWL2). The first connecting electrode (CNE1') and the second connecting electrode (CNE2') may be omitted, and the first electrode (AE1) may be directly connected to the second connecting wire (TWL2).

[0167] Referring to FIG. 7b, the first electrode (AE1) of the second sub-emissive element (SLD1) may be electrically connected to a second sub-pixel circuit (SPC2) located in the second region (DP-A2). The first electrode (AE1) of the second sub-emissive element (LD2) may be electrically connected to a second silicon transistor (S-TFT) or a second oxide transistor (O-TFT). FIG. 7b illustrates the first electrode (AE1) of the second sub-emissive element (LD2) connected to a second silicon transistor (S-TFT).

[0168] Specifically, the first electrode (AE1) of the second sub-emissive element (SLD2) can be electrically connected to the second sub-pixel circuit (SPC2) through the first connecting wire (TWL1) and connecting electrodes (CNE1', CNE2', CPN). According to one embodiment, one of the connecting electrodes (CNE1', CNE2') may be omitted. The second connecting electrode (CNE2') may be omitted, and the first connecting electrode (CNE1') may be directly connected to the first connecting wire (TWL1). The first connecting electrode (CNE1') and the second connecting electrode (CNE2') may be omitted, and the first electrode (AE1) may be directly connected to the first connecting wire (TWL1).

[0169] The connecting wiring (TWL1, TWL2) may overlap with the transmission region (TA). The connecting wiring (TWL1, TWL2) may include a light-transmitting material. The connecting wiring (TWL1, TWL2) may include a transparent conductive oxide (TCO), such as, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). Even if the connecting wires (TWL1, TWL2) overlap with the transmission region (TA) through which the optical signal travels, the transparent connecting wires (TWL1, TWL2) can minimize distortion of the optical signal, such as diffraction.

[0170] The first connecting wires (TWL1) may be spaced apart from each other. The second connecting wires (TWL2) may be spaced apart from each other. The first connecting wires (TWL1) and the second connecting wires (TWL2) may be alternately arranged in one direction perpendicular to the third direction (DR3).

[0171] The first connecting wire (TWL1) and the second connecting wire (TWL2) may be placed on different layers. When connecting wires are placed on a single layer, they must be spaced apart from each other, and there are limitations on the number of connecting wires that can be placed per unit area and the arrangement type. One embodiment includes the first connecting wire (TWL1) and the second connecting wire (TWL2) placed on different layers, thereby allowing connecting wires to be placed more efficiently than when connecting wires are placed on a single layer.

[0172] In one embodiment, the first connecting wire (TWL1) may be superimposed on the first region (DP-A1) and disposed on the second insulating layer (20). That is, the first connecting wire (TWL1) may be disposed on the lower insulating layer (10, 20). The first connecting wire (TWL1) may be covered by the third insulating layer (30). That is, the first connecting wire (TWL1) may be covered by the upper insulating layer (30). Meanwhile, the upper insulating layer (30) may cover the upper electrode (UE) disposed on the same layer as the first connecting wire (TWL1).

[0173] In one embodiment, the second connecting wire (TWL2) may overlap the first region (DP-A1) and the second region (DP-A2) and be disposed on the third insulating layer (30). That is, the second connecting wire (TWL2) may be disposed on the upper insulating layer (30). The second connecting wire (TWL2) may be covered by the fifth insulating layer (50). That is, the second connecting wire (TWL2) may be covered by the cover insulating layer (50).

[0174] The first connecting wire (TWL1) may be placed on the same layer as the upper electrode (UE). The first connecting wire (TWL1) may be placed on the same insulating layer as the upper electrode (UE). The first connecting wire (TWL1) may be formed from the same material in the same process as the upper electrode (UE). That is, for the formation of the first connecting wire (TWL1), a separate process different from the upper electrode (UE) formation process is not required. Accordingly, the stacked structure of the display device (DD, FIG. 2) can be simplified. In addition, in the manufacturing of the display device (DD, FIG. 2), the process can be simplified by reducing the number of masks required for the process.

[0175] The second connecting wire (TWL2) may be placed on the same layer as the oxide semiconductor pattern (SP2). The second connecting wire (TWL2) may be placed on the same insulating layer as the oxide semiconductor pattern (SP2). The second connecting wire (TWL2) may be formed with the same material in the same process as the oxide semiconductor pattern (SP2). That is, for the formation of the second connecting wire (TWL2), a separate process different from the oxide semiconductor pattern (SP2) formation process is not required. Accordingly, the stacked structure of the display device (DD, FIG. 2) can be simplified. In addition, in the manufacturing of the display device (DD, FIG. 2), the process can be simplified by reducing the number of masks required for the process.

[0176] Meanwhile, the second connecting wire (TWL2) can be formed from the same original oxide semiconductor layer as the oxide semiconductor pattern (SP2). The original oxide semiconductor layer is divided into multiple patterns through an etching process, and these multiple patterns include the oxide semiconductor pattern (SP2) and the second connecting wire (TWL2).

[0177] However, the oxide semiconductor pattern (SP2) and the second connecting wire (TWL2) have different electrical properties because the subsequent process is not exactly the same. The second connecting wire (TWL2) may have conductivity corresponding to the source region (SE2) and drain region (DE2) of the oxide semiconductor pattern (SP2). Below, the second connecting wire (TWL2) and the source region (SE2) of the oxide semiconductor pattern (SP2) will be explained in detail.

[0178] The source region (SE2) of the second connecting wire (TWL2) and the oxide semiconductor pattern (SP2) may have high conductivity compared to the active region (AC2) of the oxide semiconductor pattern (SP2). The source region (SE2) and drain region (DE2) of the second connecting wire (TWL2) and the oxide semiconductor pattern (SP2) may have a high content of fluorine elements compared to the active region (AC2) of the oxide semiconductor pattern (SP2). In the process of forming the fourth insulating layer (40) of the insulating pattern, a fluorine gas such as CF4 and / or SF6 is used as an etching gas because fluorine has substituted oxygen in the transparent conductive oxide (TCO). The dry etching process using fluorine gas produces results similar to doping the transparent conductive oxide (TCO) with fluorine.

[0179] The conductivity of the reduced transparent conductive oxide (TCO) is increased. The active region (AC2) of the oxide semiconductor pattern (SP2) has a relatively low content of fluorine elements because the second gate electrode (GT2) masks the fluorine gas.

[0180] A pixel definition pattern (PDP) may be placed on the eighth insulating layer (80) so as to overlap the first region (DP-A1). The pixel definition pattern (PDP) may contain the same material as the pixel definition film (PDL) and may be formed through the same process. The pixel definition pattern (PDP) and the pixel definition film (PDL) may contain a light-transmitting material. The pixel definition pattern (PDP) may cover a portion of the first electrode (AE1) of the first light-emitting element (LD1). For example, the pixel definition pattern (PDP) may cover the edge of the first electrode (AE1) of the first light-emitting elements (SLD1, SLD2) and may suppress the occurrence of an arc, like the pixel definition film (PDL).

[0181] In the first region (DP-A1), the region overlapping with the first electrode (AE1) of the first light-emitting element (SLD1, SLD2) and the region overlapping with the pixel definition pattern (PDP) may be defined as the element region (EA), and the remaining region may be defined as the transmission region (TA). However, this is merely illustrative, and the embodiments are not limited thereto. For example, if the pixel definition pattern (PDP) includes a transparent material, the region overlapping with the first electrode (AE1) of the first light-emitting element (SLD1, SLD2) in the first region (DP-A1) may be defined as the element region, and the remaining region may be defined as the transmission region.

[0182] A first opening (310-OP1) may be defined in the dividing layer (310). The first opening (310-OP1) may overlap with the first electrode (AE2) of the second light-emitting element (LD2). The first color filter (321) may overlap with the first region (DP-A1), and the second color filter (322) may overlap with the second region (DP-A2). Each of the first color filter (321) and the second color filter (322) may overlap with the corresponding electrode among the first electrodes (AE1, AE2).

[0183] Since the dividing layer (310) does not overlap with the first region (DP-A1), the first color filter (321) can be spaced apart from the dividing layer (310). That is, the first color filter (321) may not come into contact with the dividing layer (310). The second color filter (322) can cover the first opening (310-OP1). The flattening layer (330) can cover the dividing layer (310), the first color filter (321), and the second color filter (322).

[0184] FIG. 8 is a cross-sectional view corresponding to the first region (DP-A1) and the second region (DP-A2) of a display device according to one embodiment.

[0185] Referring to FIG. 8, a portion of the second connecting wire (TWL2) may be exposed from the fifth insulating layer (50) by an opening (50-OP). The opening (50-OP) may be defined in the portion of the fifth insulating layer (50) corresponding to the first region (DP-A1). A fluorine gas such as CF4 and / or SF6 is used as an etching gas to form the opening (50-OP), and in the process, the conductivity of the second connecting wire (TWL2) may be increased. The portion of the second connecting wire (TWL2) exposed by the opening (50-OP) may be covered by a sixth insulating layer (60) that fills the opening (50-OP).

[0186] FIG. 9 is a cross-sectional view corresponding to the first region (DP-A1) and the second region (DP-A2) of a display device according to one embodiment.

[0187] The display device of one embodiment shown in FIG. 9 is described mainly in terms of the differences from the display device shown in FIG. 7a. FIG. 9 differs from the display device shown in FIG. 7a in that it does not include a third insulating layer (30).

[0188] Referring to FIG. 9, the upper electrode (UE) may be disposed on the second insulating layer (20). In FIG. 9, the second insulating layer (20) is defined as the lower insulating layer, the fifth insulating layer (50) is defined as the upper insulating layer, and the sixth to eighth insulating layers (60 to 80) are defined as the uppermost insulating layers.

[0189] In one embodiment, the upper electrode (UE) may be disposed on the same layer as the oxide semiconductor pattern (SP2). Additionally, the first connecting wire (TWL1-1) may be disposed on the same layer as the upper electrode (UE) and the oxide semiconductor pattern (SP2). The first connecting wire (TWL1-1), the upper electrode (UE), and the oxide semiconductor pattern (SP2) may be disposed on the lower insulating layer (20). The first connecting wire (TWL1-1), the upper electrode (UE), and the oxide semiconductor pattern (SP2) may be covered by the upper insulating layer (50).

[0190] The first connecting wire (TWL1-1) may be formed from the same material as the upper electrode (UE) and the oxide semiconductor pattern (SP2) in the same process. That is, for the formation of the first connecting wire (TWL1-1), a separate process different from the upper electrode (UE) formation and oxide semiconductor pattern (SP2) formation processes is not required. Accordingly, the stacked structure of the display device (DD, FIG. 2) can be simplified, and the manufacturing process of the display device (DD, FIG. 2) can be simplified by reducing the number of masks required for the process.

[0191] Meanwhile, the first connecting wire (TWL1-1) has different electrical properties because the subsequent process is not exactly the same as that of the oxide semiconductor pattern (SP2). The first connecting wire (TWL1-1) may have electrical conductivity corresponding to the source region (SE2) and drain region (DE2) of the oxide semiconductor pattern (SP2). The specific details may be the same as those described in FIG. 7a regarding the second connecting wire (TWL2, FIG. 7a) and the oxide semiconductor pattern (SP2).

[0192] In one embodiment, the second connecting wire (TWL2-1) may be placed on a different layer from the first connecting wire (TWL1-1). When connecting wires are placed on a single layer, they must be spaced apart from each other, and there is a limitation on the arrangement of connecting wires that can be placed per unit area. One embodiment includes the first connecting wire (TWL1-1) and the second connecting wire (TWL2-1) placed on different layers, thereby allowing connecting wires to be placed more efficiently compared to the case where connecting wires are placed on a single layer.

[0193] The second connecting wire (TWL2-1) may be placed on the same layer as the second gate electrode (GT2). The second gate electrode (GT2) and the second connecting wire (TWL2-1) may be placed on a fourth insulating layer (40, 40-1), which is an insulating pattern. That is, the second gate electrode (GT2) may be placed on the first insulating pattern (40), and the second connecting wire (TWL2-1) may be placed on the second insulating pattern (40-1). The second insulating pattern (40-1) may be placed between the fourth insulating layer (40) and the second connecting wire (TWL2-1).

[0194] The second connecting wire (TWL2-1) may be formed from the same material in the same process as the second gate electrode (GT2). That is, for the formation of the second connecting wire (TWL2-1), a separate process different from the process of forming the second gate electrode (GT2) is not required. Accordingly, the stacked structure of the display device (DD, FIG. 2) can be simplified. In addition, in the manufacturing of the display device (DD, FIG. 2), the number of masks and processes required for the process can be reduced, thereby simplifying the process. Meanwhile, the second gate electrode (GT2) and the second connecting wire (TWL2-1) may each include a transparent conductive oxide. For example, the second gate electrode (GT2) and the second connecting wire (TWL2-1) may each include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3).

[0195] One embodiment provides a display device comprising a first connecting wire and a second connecting wire disposed on different layers. The first connecting wire is disposed on the same layer as an upper electrode that overlaps with a first gate electrode of a silicon semiconductor pattern, and the second connecting wire is disposed on the same layer as an oxide semiconductor pattern. The first connecting wire is formed from the same material in the same process as the upper electrode, and the second connecting wire is formed from the same material in the same process as the oxide semiconductor pattern. Accordingly, the display device may have a simple stacked structure. Furthermore, the display device of one embodiment may be fabricated without the addition of a mask and process for forming the first connecting wire and the second connecting wire. Another embodiment may provide an electronic device comprising a display device and an electronic module having a simple stacked structure.

[0196] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the relevant technical field will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0197] 100: Display panel 110: Base layer 10~80: Insulating layer PX1, PX2, PX3: 1st to 3rd pixels LD1, LD2, LD3: First to third light-emitting elements PC1, PC2, PC3: 1st to 3rd pixel circuits SP1: Silicon semiconductor pattern SP2: Oxide semiconductor pattern GT1: 1st gate electrode GT2: 2nd gate electrode S-TFT: 1st transistor O-TFT: 2nd transistor UE: Upper electrode TWL1, TWL2: 1st and 2nd connecting wires

Claims

Claim 1 A display panel comprising a display area including a first region and a second region adjacent to the first region, a base layer including a peripheral region adjacent to the display area, an insulating layer disposed on the base layer, a first pixel disposed on the base layer, and a second pixel, wherein the first pixel comprises different first subpixels and second subpixels, the first subpixel comprises a first sub-light-emitting element disposed in the first region and a first subpixel circuit electrically connected to the first sub-light-emitting element, the second subpixel comprises a second sub-light-emitting element disposed in the first region and a second subpixel circuit electrically connected to the second sub-light-emitting element, the second pixel comprises a second light-emitting element disposed in the second region and a second pixel circuit disposed in the second region and electrically connected to the second light-emitting element, wherein the first subpixel circuit comprises a first silicon semiconductor pattern including a drain region, an active region, and a source region, and a first gate electrode superimposed on the active region of the first silicon semiconductor pattern, and disposed in the second region or the peripheral region A first silicon transistor; a first oxide semiconductor pattern comprising a drain region, an active region, and a source region, and a second gate electrode superimposed on the active region of the first oxide semiconductor pattern, wherein the first oxide transistor is disposed in the second region or the peripheral region; a first upper electrode superimposed on the first gate electrode; and a first connecting wire comprising a transparent conductive oxide, which electrically connects the first silicon transistor or the first oxide transistor and the first sub-luminescent element, superimposed on the first region, disposed on the same layer as the first upper electrode;A display device comprising: a second silicon semiconductor pattern including a drain region, an active region, and a source region, and a third gate electrode overlapping the active region of the second silicon semiconductor pattern, wherein the second silicon transistor is disposed in the second region or the peripheral region; a second oxide semiconductor pattern including a drain region, an active region, and a source region, and a fourth gate electrode overlapping the active region of the second oxide semiconductor pattern, wherein the second oxide transistor is disposed in the second region or the peripheral region; a second upper electrode overlapping the third gate electrode; and a second connecting wire electrically connecting the second silicon transistor or the second oxide transistor and the second sub-luminescent element, overlapping the first region, disposed on the same layer as the second oxide semiconductor pattern, and comprising a transparent conductive oxide. Claim 2 A display device according to claim 1, wherein the insulating layer comprises: a lower insulating layer disposed below the first upper electrode and the second upper electrode; and an upper insulating layer disposed above the first upper electrode and the second upper electrode. Claim 3 In paragraph 2, the first and second oxide semiconductor patterns and the second connecting wiring are a display device disposed on the upper insulating layer. Claim 4 In paragraph 2, the upper insulating layer is a display device covering the first connecting wiring, the first upper electrode, and the second upper electrode. Claim 5 A display device according to paragraph 2, further comprising an insulating pattern disposed between the active region of the first oxide semiconductor pattern and the second gate electrode, and between the active region of the second oxide semiconductor pattern and the fourth gate electrode, respectively. Claim 6 A display device according to paragraph 2, wherein the insulating layer is disposed on the upper insulating layer and further comprises a cover insulating layer covering the first and second oxide semiconductor patterns and the second connecting wiring. Claim 7 In claim 6, the cover insulating layer has an opening defined corresponding to the first region, and a part of the second connecting wiring is exposed by the opening defined in the cover insulating layer. Claim 8 A display device according to claim 1, wherein the first connecting wire, the second connecting wire, the first and second upper electrodes, and the first and second oxide semiconductor patterns each comprise at least one of In, Zn, and Sn. Claim 9 A display device according to claim 1, wherein the display area further includes a third area adjacent to the second area, and the display panel further includes a third pixel disposed in the third area, and the third pixel includes a third light-emitting element disposed in the third area and a third pixel circuit electrically connected to the third light-emitting element and disposed in the third area, wherein the number of the second light-emitting elements disposed per unit area of ​​the second area is less than the number of the third light-emitting elements disposed per unit area of ​​the third area, and the sum of the number of the first sub-light-emitting elements and the second sub-light-emitting elements disposed per unit area of ​​the first area is less than the number of the third light-emitting elements disposed per unit area of ​​the third area. Claim 10 A display device according to claim 1, wherein the electrical conductivity of the second connecting wire is greater than the electrical conductivity of the active region of the first and second oxide semiconductor patterns. Claim 11 A display panel comprising a first region, a second region adjacent to the first region, and a third region adjacent to the second region, a base layer including a peripheral region adjacent to the display region, an insulating layer disposed on the base layer, and first to third pixels disposed on the base layer, wherein the first pixel comprises different first subpixels and second subpixels, the first subpixel comprises a first sub-light-emitting element disposed in the first region and a first subpixel circuit electrically connected to the first sub-light-emitting element, the second subpixel comprises a second sub-light-emitting element disposed in the first region and a second subpixel circuit electrically connected to the second sub-light-emitting element, the second pixel comprises a second light-emitting element disposed in the second region and a second pixel circuit disposed in the second region that is electrically connected to the second light-emitting element, and the third pixel comprises a third light-emitting element disposed in the third region and a third pixel circuit electrically connected to the third light-emitting element, wherein the first sub-light-emitting element disposed per unit area of ​​the first region The sum of the number of elements and the number of the second sub-luminescent elements is less than the number of the third luminescent elements disposed per unit area in the third region, and the number of the second luminescent elements disposed per unit area in the second region is less than the number of the third luminescent elements disposed per unit area in the third region, and the first sub-pixel circuit includes a first silicon semiconductor pattern comprising a drain region, an active region, and a source region, and a first gate electrode overlapping the active region of the first silicon semiconductor pattern, and a first silicon transistor disposed in the second region or the peripheral region;A first oxide semiconductor pattern comprising a drain region, an active region, and a source region, and a second gate electrode superimposed on the active region of the first oxide semiconductor pattern, wherein the first oxide transistor is disposed in the second region or the peripheral region; a first upper electrode superimposed on the first gate electrode; and a first connecting wire comprising a transparent conductive oxide, which electrically connects the first silicon transistor or the first oxide transistor and the first sub-luminescent element, superimposed on the first region, disposed on the same layer as the first upper electrode; A display device comprising: a second silicon semiconductor pattern including a drain region, an active region, and a source region, and a third gate electrode superimposed on the active region of the second silicon semiconductor pattern, wherein the second silicon transistor disposed in the second region or the peripheral region; a second oxide transistor disposed in the second region or the peripheral region, wherein the second oxide semiconductor pattern including a drain region, an active region, and a source region, and a fourth gate electrode superimposed on the active region of the second oxide semiconductor pattern; a second upper electrode superimposed on the third gate electrode; and a second connecting wire comprising a transparent conductive oxide, which electrically connects the second silicon transistor or the second oxide transistor and the second sub-luminescent element, superimposed on the first region, and disposed on a different layer from the first connecting wire. Claim 12 In claim 11, the insulating layer comprises a lower insulating layer disposed below the first upper electrode and the second upper electrode; and an upper insulating layer disposed above the first upper electrode and the second upper electrode. Claim 13 A display device according to claim 12, wherein the first and second upper electrodes and the first and second oxide semiconductor patterns are disposed on the same layer on the lower insulating layer, and the first and second upper electrodes and the first and second oxide semiconductor patterns are covered by the upper insulating layer. Claim 14 A display device according to claim 12, further comprising a first insulating pattern disposed between the active region of the first oxide semiconductor pattern and the second gate electrode and between the active region of the second oxide semiconductor pattern and the fourth gate electrode, respectively, and a second insulating pattern disposed between the lower insulating layer and the second connecting wire. Claim 15 In claim 14, the first connecting wire, the second connecting wire, the first upper electrode, the second upper electrode, the first oxide semiconductor pattern, the second oxide semiconductor pattern, the second gate electrode, and the fourth gate electrode each comprise at least one of In, Zn, and Sn. Claim 16 A display device comprising a sensing area through which an optical signal passes, a display area adjacent to the sensing area, and a peripheral area adjacent to the display area, wherein the sensing area comprises a first light-emitting element including a first sub-light-emitting element and a second sub-light-emitting element, an element area in which the first light-emitting element overlaps, and a transmission area in which the first light-emitting element does not overlap; and an electronic module disposed on the lower side of the display device, overlapping with the sensing area, and receiving the optical signal, wherein the display device comprises the first sub-light-emitting element disposed in the element area and a first sub-pixel circuit electrically connected to the first sub-light-emitting element; and the second sub-light-emitting element disposed in the element area and a second sub-pixel circuit electrically connected to the second sub-light-emitting element. The first subpixel circuit comprises: a first silicon semiconductor pattern including a drain region, an active region, and a source region, and a first gate electrode overlapping the active region of the first silicon semiconductor pattern, and a first transistor disposed in the display region or the peripheral region; a first oxide semiconductor pattern including a drain region, an active region, and a source region, and a second gate electrode overlapping the active region of the first oxide semiconductor pattern, and a second transistor disposed in the display region or the peripheral region; a first upper electrode overlapping the first gate electrode; and a first connecting wire electrically connecting the first transistor or the second transistor and the first sub-light-emitting element, overlapping the sensing region, disposed on the same layer as the first upper electrode, and comprising a transparent conductive oxide; and the second subpixel circuit comprises a second silicon semiconductor pattern including a drain region, an active region, and a source region, and a third gate electrode overlapping the active region of the second silicon semiconductor pattern, and a third transistor disposed in the display region or the peripheral region.An electronic device comprising: a second oxide semiconductor pattern including a drain region, an active region, and a source region, and a fourth transistor disposed in the display region or the peripheral region, the fourth transistor including a fourth gate electrode superimposed on the active region of the second oxide semiconductor pattern; a second upper electrode superimposed on the third gate electrode; and a second connecting wire electrically connecting the third transistor or the fourth transistor and the second sub-luminescent element, superimposed on the sensing region, disposed on the same layer as the second oxide semiconductor pattern, and comprising a transparent conductive oxide. Claim 17 In claim 16, the display device further comprises a display pixel including a second light-emitting element disposed in the display area and a second pixel circuit electrically connected to the second light-emitting element and disposed in the display area, wherein the sum of the number of the first sub-light-emitting element and the second sub-light-emitting element per unit area disposed in the sensing area is less than the number of the second light-emitting element disposed per unit area in the display area. Claim 18 In paragraph 16, the electronic module is an electronic device including a camera module. Claim 19 An electronic device according to claim 16, wherein the electrical conductivity of the second connecting wire is greater than the electrical conductivity of each of the active region of the first oxide semiconductor pattern and the active region of the second oxide semiconductor pattern. Claim 20 In claim 16, the display device further comprises a window, and the window comprises a base film and a bezel pattern disposed on the base film and overlapping the peripheral area, an electronic device.

Images