Semiconductor device and method of integrating RF antenna interposer with semiconductor package

Abstract

A semiconductor device has a substrate and a first electrical component disposed on a first surface of the substrate. An RF antenna interposer is disposed on the substrate and has a first electrical component connected to a first antenna disposed on the surface of the antenna interposer. The area of ​​the antenna interposer is substantially the same as the area of ​​the substrate. The first antenna disposed on the surface of the antenna interposer has a protrusion consisting of an island of conductive material. Alternatively, the first antenna disposed on the surface of the antenna interposer has a spiral shape of conductive material. A second antenna may be disposed on the surface of the antenna interposer connected to a second electrical component disposed on the substrate. The second electrical component may be disposed on a second surface of the substrate opposite the first surface of the substrate.

Description

Technology Field

[0001] The present invention generally relates to a semiconductor device, and more specifically, to a semiconductor device and method for integrating an RF antenna interposer into a semiconductor package. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, electromagnetic signal transmission and reception, electronic device control, and the generation of visual images for optoelectronic and television displays. Semiconductor devices are used in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. They can also be found in military applications, aviation, automobiles, industrial controllers, and office equipment. The problem to be solved

[0003] In high-frequency applications such as radio frequency (RF) communication, semiconductor devices often include one or more integrated passive devices (IPDs) to perform essential electrical functions, such as RF signal processing. The semiconductor device must be connected to an RF antenna to transmit and receive RF signals. The RF antenna may be located outside the semiconductor device, for example, on a PCB. Alternatively, the RF antenna may be integrated into the semiconductor package. Integrated RF antennas are typically embedded within the semiconductor package or occupy a relatively small area of ​​the package. Integrated RF antennas known in the prior art lack sufficient RF transmission and reception performance and quality. means of solving the problem

[0004] The present invention is described in one or more ways in the following description with reference to the drawings, in which similar numbers indicate identical or similar elements. Although the present invention is described in the best mode for achieving the purposes of the invention, it will be understood by those skilled in the art that it is intended to include alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention. The term "semiconductor die" as used in the invention defined by the appended claims and in the equivalents supported by the following disclosure and drawings has both singular and plural forms and can refer to both a single semiconductor device and multiple semiconductor devices.

[0005] Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, function to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, generate the relationship between voltage and current necessary to perform the electrical circuit function. Effects of the invention

[0006] Backend manufacturing refers to the process of cutting or individualizing a finished wafer into individual semiconductor dies and packaging the dies for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor dies, the wafer is scored and cut along a non-functional area of ​​the wafer known as the top street or scribe. The wafer is individualized using a laser cutting tool or a saw blade. After singulation, the individual semiconductors are mounted on a package substrate containing pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductors are connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, stud bumps, conductive paste, or wire bonds. Encapsulant or other molding materials are deposited on the package to provide physical support and electrical insulation. The finished package is then inserted into an electrical system, allowing the functions of the semiconductor device to be utilized by other system components. Brief explanation of the drawing

[0007] FIG. 1a-1c shows a semiconductor wafer having the shape of a semiconductor die separated by a top street; FIGS. 2a to 2f illustrate a process for forming a semiconductor package having a semiconductor die and an interconnection substrate; FIGS. 3a-3f shows the process of forming an RF antenna interposer; FIGS. 4a-4b illustrate the integration of an RF antenna interposer and a semiconductor package. FIGS. 5a-5c illustrate the integration of an RF antenna interposer with a different semiconductor package; FIG. 6 shows an unencapsulated integrated RF antenna interposer and a semiconductor package; and FIG. 7 is a printed circuit board (PCB) having various types of packages mounted on the surface of the PCB. Specific details for implementing the invention

[0008] FIG. 1a illustrates a semiconductor wafer (100) having a base substrate material (102) such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. The formation of semiconductor dies or components (104) is formed on the wafer (100) separated by an inactive, inter-die wafer region or a top street (106). The top street (106) provides a cutting region for singulating the semiconductor wafer (100) into individual semiconductor dies (104). In one embodiment, the semiconductor wafer (100) has a width or diameter of 100 to 450 millimeters (mm).

[0009] FIG. 1b illustrates a cross-sectional view of a portion of a semiconductor wafer (100). Each semiconductor die (104) has a back or inactive surface (108) and active components, passive components, a conductive layer, and a dielectric layer formed inside the die and electrically interconnected according to the electrical design and function of the die. For example, the circuits are digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, or other signal processing circuits. The semiconductor die (104) may also include IPDs, such as inductors, capacitors, and resistors, and other circuits for RF signal processing. The surface (108) may undergo back grinding to flatten the semiconductor die (104).

[0010] An electrically conductive layer (112) is formed on an active surface (110) using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer (112) may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive materials. The conductive layer (112) acts as a contact pad electrically connected to a circuit on the active surface (110).

[0011] An electrically conductive bump material is deposited onto a conductive layer (112) using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and there are optional flux solutions. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer (112) using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump (114). In one embodiment, the bump (114) is formed on a metallization under the bump (UBM) having a wetting layer, a barrier layer, and an adhesive layer. The bump (114) may also be compression bonded or thermally compressed to the conductive layer (112). The bump (114) represents a type of interconnect structure that can be formed on the conductive layer (112). The interconnect structure may also use bond wire, conductive paste, stud bumps, microbumps, or other electrical interconnects.

[0012] As illustrated in FIG. 1c, a semiconductor wafer (100) is singulated into individual semiconductor dies (104) through a saw street (106) using a saw blade or a laser cutting tool (118). The individual semiconductor dies (104) can be inspected and electrically tested for identification of KGD after singulation.

[0013] FIGS. 2a-2f illustrate a process for forming a semiconductor package having a semiconductor die and an interconnection substrate. FIG. 2a illustrates a cross-sectional view of an interconnection substrate or PCB (120) comprising a conductive layer (122) and an insulating layer (124). The conductive layer (122) is one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. The conductive layer (122) provides horizontal electrical interconnection across the substrate (120) and vertical electrical interconnection between the upper surface (126) and the lower surface (128) of the substrate (120). A portion of the conductive layer (122) may be electrically common or electrically insulated depending on the design and function of the electrical components. The insulating layer (124) comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polymer, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO) and other materials having similar insulating and structural properties. The insulating layer (124) provides insulation between the conductive layers (122).

[0014] In FIG. 2b, an electrical component (130) is positioned on a substrate (120) using a pick-and-place operation. For example, the electrical component (130) may be a semiconductor die (104) of FIG. 1. It is illustrated in FIG. 1c having an active surface (110) and a bump (114) oriented toward the surface (126) of the substrate (120) and electrically connected to a conductive layer (122). In one embodiment, the electrical component (130) is an RF signal processing component. Additional electrical components, such as other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, discrete transistors, diodes, or IPDs, may be mounted on the interconnection substrate (120). FIG. 2c illustrates an electrical component (130) mounted on an interconnection substrate (120) having a bump (114) that makes mechanical and electrical connections to the conductive layer (122).

[0015] An electrically conductive bump material is deposited onto a conductive layer (122) on a surface (126) using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and there are optional flux solutions. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer (122) using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump (132). In one embodiment, the bump (132) is formed on a UBM having a wetting layer, a barrier layer, and an adhesive layer. The bump (132) may also be compression bonded or thermally compressed bonded to the conductive layer (122). The bump (132) represents a type of interconnect structure that can be formed on the conductive layer (122). The interconnect structure may also use bond wire, conductive paste, stud bumps, microbumps, or other electrical interconnects.

[0016] In FIG. 2d, the encapsulant or molding compound (134) is deposited on the surface (126) of the electrical component (130), bump (132), and interconnect substrate (120) using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. The encapsulant (134) may be a polymer composite material such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers. The encapsulant (134) is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0017] In FIG. 2e, a portion of the encapsulant (134) is removed by direct laser ablation (LDA) using a laser (136) to form an opening (138) and expose a bump (132). A portion of the encapsulant (134) may also be removed by etching or drilling. In particular, the encapsulant (134) covers the back surface of the electronic component (130). An electrical component (140), such as an individual electrical device, may be mounted on the surface (128) of the interconnection substrate (120) with terminals (142) that make electrical and mechanical contact with the conductive layer (122).

[0018] In FIG. 2f, an electrical component (150) is mounted on the surface (128) of an interconnection substrate (120) and electrically and mechanically connected to a conductive layer (122) by bumps (152), similar to the electrical component (130) in FIG. 2b-2c. The electrical component (150) is mounted on the surface (128) for heat dissipation. An underfill material (154), such as epoxy resin, is deposited under the electrical component (150). The underfill material (154) is cured. The electrical component (150) may be manufactured to have a different shape and function, possibly similar to the semiconductor die (104) in FIG. 1c. In one embodiment, the electrical component (150) is an RF signal processing component. Alternatively, the electrical component (150) may be a semiconductor package, a surface mount device, a discrete electrical device, a discrete transistor, a diode, or an IPD. The semiconductor package (160) of FIG. 2f constitutes a package-on-package (PoP) that includes multiple electrical components and an interconnection substrate.

[0019] An electrically conductive bump material is deposited onto a conductive layer (122) on a surface (128) using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and there are optional flux solutions. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer (122) using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump (156). In one embodiment, the bump (156) is formed on a UBM having a wetting layer, a barrier layer, and an adhesive layer. The bump (156) may also be compression bonded or thermally compressed bonded to the conductive layer (122). The bump (156) represents a type of interconnect structure that can be formed on the conductive layer (122). The interconnect structure may also use bond wire, conductive paste, stud bumps, microbumps, or other electrical interconnects.

[0020] FIGS. 3a-3f illustrate a process for forming an RF antenna interposer or substrate. In FIG. 3a, the insulating layer (162) is made of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, polymer, BCB, PBO, and other materials having similar insulating and structural properties. A conductive layer (164) is formed on the surface (165) of the insulating layer (162). The conductive layer (164) may be one or more of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive materials. The conductive layer (164) provides horizontal electrical interconnection across the insulating layer (162) including the surface (165). The radius of the via is formed through the insulating layer (162) by etching, drilling, or LDA. The via is filled with a conductive material to form a conductive via (166) for vertical electrical interconnection from the insulating layer (162) to the conductive layer (164).

[0021] In FIG. 3b, a conductive layer (168) is formed over an insulating layer (162). The conductive layer (168) may be one or more of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive materials. The conductive layer (168) provides horizontal electrical interconnection across the insulating layer (162) and is electrically connected to the conductive vias (166). An insulating layer (170) is formed over the conductive layer (168). The insulating layer (170) is made of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, polymer, BCB, PBO, and other materials having similar insulating and structural properties. Multiple vias are formed through the insulating layer (170) by etching, drilling, or LDA. The via is filled with a conductive material to form a conductive via (171) for vertical electrical interconnection to a conductive layer (168) through an insulating layer (170). A conductive layer (172) is formed on the insulating layer (170). The conductive layer (172) may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. In one embodiment, the conductive layer (172) provides a ground plane across the insulating layer (170) and is electrically connected to the conductive via (171).

[0022] In FIG. 3c, an insulating layer (174) is formed over a conductive layer (172). The insulating layer (174) is made of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, polymer, BCB, PBO, and other materials having similar insulating and structural properties. Multiple vias are formed through the insulating layer (174) by etching, drilling, or LDA. The vias are filled with a conductive material to form conductive vias (176) for vertical electrical interconnection through the insulating layer (174) to the conductive layer (172). A conductive layer (178) is formed over the insulating layer (174). The conductive layer (178) may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive materials. A conductive layer (178) provides horizontal electrical interconnection across an insulating layer (174) and is electrically connected to a conductive via (176). The conductive layer (178) may be configured as an RF antenna similar to an RF antenna (194) embedded within an RF antenna interposer (190). An insulating layer (180) is formed over the conductive layer (178). The insulating layer (180) is made of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, polymer, BCB, PBO, and other materials having similar insulating and structural properties. Multiple vias are formed through the insulating layer (180) by etching, drilling, or LDA. The vias are filled with a conductive material to form a conductive via (182) for vertical electrical interconnection through the insulating layer (180) to the conductive layer (178). A conductive layer (184) is formed on the surface (186) of an insulating layer (180) and is electrically connected to a conductive via (182). The conductive layer (184) may be one or more of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive materials. The conductive layer (184) functions as an RF antenna (194) exposed from the surface (186) of the RF antenna interposer (190).

[0023] FIG. 3d is a top view of an RF antenna interposer (190). The conductive layer (184) comprises an array of islands of conductive material in the form of a conductive layer (184) suitable for providing RF signals, i.e., for transmitting and receiving RF antennas. In particular, the array of islands of the conductive layer (184) is exposed from the surface (186) and extends substantially across the surface of the RF antenna interposer (190) to improve RF transmission and reception performance and quality. In one embodiment, the entire array of islands of conductive material can be used as a single antenna (194) for RF transmission and reception of electrical components (130, 140, or 150) in a PoP (160). Alternatively, a first group of conductive material (192a) acts as a first antenna (194a) electrically connected through a conductive layer (164, 168, 172, 178), conductive vias (166, 171, 176, 182), and bumps (188) to provide RF transmission and reception for a first electrical component (130, 140, 150) in the PoP (160). A second group of conductive material (192b) acts as a second antenna (194b) electrically connected through a conductive layer (164, 168, 172, 178), conductive vias (166, 171, 176, 182), and bumps (188) to provide RF transmission and reception for a second electrical component. When configured as an RF antenna, the conductive layer (178) can be electrically connected through the conductive layer (164, 168, 172), the conductive via (166, 171, 176), and the bump (188) to provide RF transmission and reception for the third electrical component (130, 140, 150) of the PoP (160).

[0024] FIG. 3e is a plan view of an alternative embodiment of an RF antenna interposer (190). The conductive layer (184) comprises a helical shape of a conductive material in the form of a conductive layer (184) suitable for providing transmission and reception of RF signals. In particular, the helical shape of the conductive layer (184) is exposed from the surface (186) and extends substantially across the surface of the RF antenna interposer (190) to improve RF transmission and reception performance and quality. The conductive layer (184) acts as a helical RF antenna (194) electrically connected through the conductive layers (164, 168, 172, 178), conductive vias (166, 171, 176, 182), and bumps (188) to provide RF transmission and reception to the first electrical components (130, 140). When configured as an RF antenna, the conductive layer (178) is electrically connected through the conductive layer (164, 168, 172), the conductive vias (166, 171, 176), and the bump (188) to provide RF transmission and reception to the second electrical component (130, 140, 150) in the PoP (160).

[0025] FIG. 3f is a top view of another embodiment of the RF antenna interposer (190). The conductive layer (184) comprises a spiral circle of a conductive material suitable for providing transmission and reception of RF signals. In particular, the spiral shape of the conductive layer (184) is exposed from the surface (186) and extends substantially across the surface of the RF antenna interposer (190) to improve RF transmission and reception performance and quality. In one embodiment, the conductive layer (184a) acts as a first spiral RF antenna (194a) electrically connected through the conductive layers (164, 168, 172, 178) and the conductive vias (166, 171, 176, 182) and bumps (188) to provide RF transmission and reception of the first electrical components (130, 140, 150) of the PoP (160). The conductive layer (184b) serves as a second helical RF antenna (194b) electrically connected through the conductive layers (164, 168, 172, 178), conductive vias (166, 171, 176, 1882), and bumps. It provides RF transmission and reception for the second electrical components (130, 140, 150) in the PoP (160). When configured as an RF antenna, the conductive layer (178) can provide RF transmission and reception for the third electrical components (130, 140, 150) in the PoP (160) by being electrically connected through the conductive layers (164, 168, 172), conductive vias (166, 171, 176), and bumps (188).

[0026] In FIG. 4a, the RF antenna interposer (190) of FIG. 3a-3f is positioned on the semiconductor package (160) of FIG. 2f with a bump (188) aligned with the bump (132). The RF antenna interposer (190) has substantially the same footprint and occupies substantially the same area as the semiconductor package (160). The RF antenna interposer (190) is lowered so that the bump (188) contacts the bump (132) and the bump is electrically reflowed. The RF antenna interposer is mechanically coupled and integrated into the semiconductor package (160) as shown in FIG. 4b. The combination of the semiconductor package (160) and the RF antenna interposer (190) is designated as an antenna-on-package (AoP) (196). The RF antenna interposer (190) integrated into the AoP (196) provides antenna functions for RF electrical components (130, 140, 150) of the semiconductor package (160).

[0027] FIGS. 5a-5c illustrate different processes for forming a semiconductor package having a semiconductor die and an interconnection substrate and integrating an RF antenna interposer with the semiconductor package. FIG. 5a illustrates a cross-sectional view of an interconnection substrate or PCB (200) comprising a conductive layer (202) and an insulating layer (204). The conductive layer (202) may be one or more of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive materials. The conductive layer (202) provides horizontal electrical interconnection across the substrate (200) and vertical electrical interconnection between the upper surface (206) and the lower surface (208) of the substrate (200). A portion of the conductive layer (202) may be electrically common or electrically insulated depending on the design and function of the electrical components. The insulating layer (204) comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polymer, polyimide, BCB, PBO, and other materials having similar insulating and structural properties. The insulating layer (204) provides insulation between the conductive layers (202).

[0028] Electrical components (210a-210c) are placed on the substrate (120) using a pick-and-place operation similar to that of FIG. 2b. For example, the electrical components (210a or 210c) may be the semiconductor die (104) of FIG. 1c. Additional electrical components (210b), such as discrete electrical devices, may be mounted on the surface (206) of the interconnection substrate (200). In one embodiment, the electrical components (210a-210c) are RF signal processing components. Additional electrical components, such as other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, discrete transistors, diodes, or IPDs, may be mounted on the interconnection substrate (200). Electrical components (210a-210c) are mounted on the surface (206) of an interconnection substrate (200) with bumps (212) and terminals (217) that make mechanical and electrical connections to the conductive layer (202), similar to FIG. 2c.

[0029] An electrical component (216) is mounted on the surface (208) of the interconnection substrate (200) and electrically and mechanically connected to a conductive layer (202) via bumps (218), similar to the electrical component (150) of FIGS. 2b-2c. The electrical component (216) is mounted on the surface (208) for heat dissipation. An underfill material (220), such as epoxy resin, is deposited under the electrical component (216). The underfill material (220) is cured. The electrical component (216) can be manufactured in a different form and function, possibly similar to the semiconductor die (104) of FIG. 1c. In one embodiment, the electrical component (216) is an RF signal processing component. Alternatively, the electrical component (216) may be a semiconductor package, a surface mount device, a discrete electrical device, a discrete transistor, a diode, or an IPD. Additional electrical components may be mounted on the surface (208) of the interconnection substrate (200).

[0030] An electrically conductive bump material is deposited onto a conductive layer (202) on surfaces (206) and (208) using evaporation, electroplating, electroless plating, ball drop, or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and there are optional flux solutions. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer (202) using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps (226, 228). In one embodiment, the bumps (226, 228) are formed on a UBM having a wetting layer, a barrier layer, and an adhesive layer. The bumps (226 and 228) may also be compression bonded or thermally compressed bonded to the conductive layer (202). The bumps (226 and 228) represent a type of interconnect structure that can be formed on the conductive layer (202). The interconnect structure may also use bond wire, conductive paste, studs, bumps, microbumps, or other electrical interconnects.

[0031] The semiconductor package (222) constitutes a PoP having a number of electrical components and an interconnection substrate. RF antenna interposer (190). FIGS. 3a-3f are positioned on the PoP (222). FIG. 5b shows an RF antenna interposer (190) mounted on the PoP (222) with bumps (226) electrically and mechanically connected to a conductive layer (164). The RF antenna interposer (190) has substantially the same footprint and occupies substantially the same area as the PoP (222).

[0032] In FIG. 5c, the encapsulant or molding compound (230) is deposited onto the electrical components (210a-210c), bumps (226), and surfaces (206) of the interconnect substrate (200) using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulant (230) may be a polymer composite material such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers. The encapsulant (230) is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0033] The combination of PoP (222) and RF antenna interposer (190) is designated as AoP (240). The RF antenna interposer (190) integrated into AoP (240) provides antenna functions for the RF electrical components (210a-210c, 216) of PoP (222).

[0034] FIG. 6 illustrates an embodiment in which there is no encapsulant between the RF antenna interposer (190) and the PoP (222). In this case, an underfill material (234) is deposited under and around the electrical components (210a-210c). The underfill material (234) is cured. In FIG. 5c and FIG. 6, respectively, the conductive layer (184) of the RF antenna interposer (190) provides transmission and reception of RF signals to the electrical components of the PoP (222). In particular, at least a portion of the conductive layer (184) is exposed and extends from the surface (186) to serve as an RF antenna (194). This improves RF transmission and reception performance and quality substantially across the surface of the RF antenna interposer (190). The RF antenna interposer (190) has substantially the same footprint as the PoP (222) and occupies substantially the same area. The exposed portion of the conductive layer (184) acting as an RF antenna (194) can be electrically connected through the conductive layer (164, 168, 172, 178), conductive vias (166, 171, 176, 182), and bump (188) to provide RF transmission and reception to the first electrical components (210a-210c, 216) of the PoP (222).

[0035] The combination of an unencapsulated PoP (222) and an RF antenna interposer (190) is designated as AoP (250). The RF antenna interposer (190) integrated into the AoP (250) provides antenna functions for the RF electrical components (210a-210c and 216) of the PoP (222).

[0036] FIG. 7 illustrates an electronic device (400) having a chip carrier substrate or a PCB (402) having a splice of a semiconductor package mounted on the surface of a PCB (402) comprising semiconductor packages (196, 240, 250). The electronic device (400) may have one type of semiconductor package or multiple types of semiconductor packages depending on the application.

[0037] The electronic device (400) may be a standalone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device (400) may be a sub-component of a larger system. For example, the electronic device (400) may be part of a tablet, a cellular phone, a digital camera, a communication system, or another electronic device. Alternatively, the electronic device (400) may be a graphics card, a network interface card, or another signal processing card that can be inserted into a computer. The semiconductor package may include a microprocessor, memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor dies or electrical components. Miniaturization and lightweighting are essential for the product to be accepted in the market. To achieve high density, the distance between semiconductor elements can be narrowed.

[0038] In FIG. 7, the PCB (402) provides a general substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces (404) are formed on the surface of or within a layer of the PCB (402) using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces (404) provide electrical communication between each semiconductor package, mounted components, and other external system components. The traces (404) also provide power and ground connections for each semiconductor package.

[0039] In some embodiments, the semiconductor device has two packaging levels. The first level of packaging is a technique for mechanically and electrically attaching the semiconductor to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other dies, the semiconductor device may only have the first level of packaging in which the die is directly mounted mechanically and electrically to the PCB.

[0040] For illustrative purposes, various types of first-level packaging, including bond wire packages (406) and flip-chip (408), are illustrated on the PCB (402). Additionally, various types of second-level packaging (QFN) (420), including ball grid arrays (BGA) (410), bump chip carriers (BCC) (412), land grid arrays (LGA) (416), multi-chip modules (MCM) or SIP modules (418), quad flat lead-free packages, quad flat packages (422), embedded wafer-level ball grid arrays (eWLB) (424), and wafer-level chip scale packages (WLCSP) (426) are illustrated as being mounted on the PCB (402). In one embodiment, the eWLB (424) is a fan-out wafer-level package (Fo-WLP) and the WLCSP (426) is a fan-in wafer-level package (Fi-WLP). Depending on system requirements, a combination of semiconductor packages consisting of a combination of first and second level packaging styles and other electronic components can be connected to the PCB (402). In some embodiments, the electronic device (400) includes a single attached semiconductor package, whereas other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can integrate pre-fabricated components into electronic devices and systems. Because semiconductor packages contain sophisticated functions, electronic devices can be manufactured using cheaper components and simplified manufacturing processes. The resulting device is less likely to fail and has lower manufacturing costs, resulting in reduced consumer costs.

[0041] Although one or more embodiments of the present invention have been illustrated in detail, those skilled in the art will understand that modifications and adaptations to these embodiments may be made without departing from the scope of the present invention as described in the following claims.

Claims

Claim 1 A semiconductor device comprising: (a) a first conductive material formed through an antenna interposer; and (b) a second conductive material formed in the antenna interposer to extend over the surface of the antenna interposer and function as an antenna; and a semiconductor package, wherein the antenna interposer is disposed over the semiconductor package to extend across the semiconductor package and the first conductive material provides communication between the antenna and the semiconductor package. Claim 2 A semiconductor device according to claim 1, wherein the antenna comprises a plurality of islands of a second conductive material. Claim 3 A semiconductor device according to claim 1, wherein the antenna comprises a spiral shape of a second conductive material. Claim 4 A semiconductor device according to claim 1, characterized in that the antenna interposer occupies an area of ​​a semiconductor package. Claim 5 A semiconductor device according to claim 1, further comprising an encapsulant deposited between an antenna interposer and a semiconductor package. Claim 6 A semiconductor device comprising: an antenna interposer comprising a conductive material formed on the antenna interposer to extend over the surface of the antenna interposer and function as an antenna; and a substrate, wherein the antenna interposer is disposed on the substrate to extend across a semiconductor package. Claim 7 A semiconductor device according to claim 6, wherein the antenna comprises a plurality of islands of conductive material. Claim 8 A semiconductor device according to claim 6, wherein the antenna comprises a spiral shape of a conductive material. Claim 9 A semiconductor device according to claim 6, characterized in that the antenna interposer occupies an area of ​​the substrate. Claim 10 A semiconductor device according to claim 6, further comprising an encapsulant disposed between an antenna interposer and a substrate. Claim 11 A method for manufacturing a semiconductor device, comprising the steps of: providing an antenna interposer by forming a conductive material on the antenna interposer so as to extend over the surface of the antenna interposer and function as an antenna; providing a substrate; and placing the antenna interposer on the substrate so as to extend across a semiconductor package. Claim 12 A method according to claim 11, characterized in that the antenna comprises a plurality of islands of a conductive material. Claim 13 A method according to claim 11, wherein the antenna comprises a spiral shape of a conductive material. Claim 14 A method according to claim 11, characterized in that the antenna interposer occupies an area of ​​the substrate. Claim 15 A method according to claim 11, further comprising the step of depositing an encapsulant between the antenna interposer and the substrate.

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