Semiconductor memory device and method for fabricating the same

Abstract

The goal is to provide a semiconductor memory device capable of improving reliability and performance. A semiconductor memory device comprises a substrate including a cell region comprising a dummy cell region and a normal cell region, and a periphery region defined around the cell region, wherein the cell region comprises a substrate including an active region defined by a cell element separator, a cell region separator defining the cell region within the substrate, a normal bit line disposed in the normal cell region and extended in a first direction, a dummy bit line group comprising a plurality of dummy bit lines disposed in the dummy cell region and extended in the first direction, and a plurality of storage contacts connected to the active region and disposed along a second direction perpendicular to the first direction, wherein the dummy cell region is bounded by the cell region separator between the normal cell region and the cell region separator, the width of the dummy cell region in the second direction is greater than or less than 50 nm and less than or equal to 200 nm, the normal bit line has a first width in the second direction, and the ratio of the width of each dummy bit line in the second direction to the first width is greater than or equal to 1 and less than or equal to 2.

Description

Technology Field

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more specifically, to a semiconductor memory device having a plurality of mutually intersecting wiring lines and buried contacts and a method for manufacturing the same. Background Technology

[0002] As semiconductor devices become increasingly highly integrated, individual circuit patterns are becoming finer in order to implement more semiconductor devices in the same area. In other words, as the integration density of semiconductor devices increases, the design rules for the components of semiconductor devices are decreasing.

[0003] In highly scaled semiconductor devices, the process of forming multiple wiring lines and multiple buried contacts (BCs) interposed between them is becoming increasingly complex and difficult. Patent Document 1 discloses a method for forming a memory cell in a DRAM. [Prior Art][Patent Document] Patent Document 1: U.S. Patent Publication US2013 / 0099298 (April 25, 2013) The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a semiconductor memory device capable of improving reliability and performance.

[0005] Another problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor memory device capable of improving reliability and performance.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] One aspect of a semiconductor memory device of the present invention for solving the above problem comprises a substrate including a cell region comprising a dummy cell region and a normal cell region, and a periphery region defined around the cell region, wherein the cell region comprises a substrate including an active region defined by a cell element separator, a cell region separator defining the cell region within the substrate, a normal bit line disposed in the normal cell region and extended in a first direction, a dummy bit line group comprising a plurality of dummy bit lines disposed in the dummy cell region and extended in the first direction, and a plurality of storage contacts connected to the active region and disposed along a second direction perpendicular to the first direction, wherein the dummy cell region forms a boundary with the cell region separator between the normal cell region and the cell region separator, the width of the dummy cell region in the second direction is greater than or less than 50 nm and less than or equal to 200 nm, the normal bit line has a first width in the second direction, and the ratio of the width of each dummy bit line in the second direction to the first width is greater than or equal to 1 and less than or equal to 2 It is the same.

[0008] Another aspect of a semiconductor memory device of the present invention for solving the above problem comprises a substrate including a cell region comprising a dummy cell region and a normal cell region, and a periphery region defined around the cell region, wherein the cell region comprises a substrate including an active region defined by a cell element separator, a cell region separator defining the cell region within the substrate, a normal bit line group disposed in the normal cell region, a dummy bit line group disposed in the dummy cell region and comprising a plurality of dummy bit lines extended in a first direction, and a plurality of storage contacts connected to the active region and disposed along a second direction perpendicular to the first direction, wherein the dummy cell region forms a boundary with the cell region separator between the normal cell region and the cell region separator, and the normal bit line group comprises a plurality of normal bit lines disposed in the second direction at bit line pitch intervals, wherein the width of the dummy cell region in the second direction is greater than the bit line pitch and is less than or equal to five times the bit line pitch, and each of the normal bit lines has a first width in the second direction, and each of the dummy for the first width The ratio of the width of the bit line in the second direction is greater than or equal to 1 and less than or equal to 2.

[0009] Another aspect of a semiconductor memory device of the present invention for solving the above problem comprises a substrate including a cell region comprising a dummy cell region and a normal cell region, and a periphery region defined around the cell region, wherein the cell region comprises a substrate including an active region defined by a cell element separator, a cell region separator defining the cell region within the substrate, a normal bit line disposed in the normal cell region and extended in a first direction, a dummy bit line group comprising a plurality of dummy bit lines disposed in the dummy cell region and extended in the first direction, and a plurality of storage contacts connected to the active region and disposed along a second direction perpendicular to the first direction, wherein the dummy cell region forms a boundary with the cell region separator between the normal cell region and the cell region separator, the width of the dummy cell region in the second direction is greater than or less than 50 nm and less than or equal to 200 nm, the width of the normal bit line in the second direction is greater than or equal to 5 nm and less than or equal to 25 nm, and the width of the dummy bit line in the second direction is greater than or equal to 5 nm. It is smaller than or equal to 30nm.

[0010] A method for manufacturing a semiconductor memory device according to the present invention for solving the above other problems comprises forming, within a substrate, a cell region separator separating a cell region and a periphery region, and a cell element separator separator defining an active region within the cell region; forming a plurality of bit lines disposed on the cell region and extending in a first direction, wherein each bit line is spaced apart in a second direction perpendicular to the first direction, and forming a periphery structure on the periphery region; forming a first semiconductor material film covering the plurality of bit lines and the periphery structure on the substrate; forming a second semiconductor material film by recrystallizing the first semiconductor material film through a laser annealing process using a laser, and forming a storage contact connected to the active region by patterning the second semiconductor material film, wherein the thickness (t) of the first semiconductor material film a-Si ) is the distance from the upper surface of the ferri structure to the upper surface of the first semiconductor material film, and the thickness (t) of the first semiconductor material film a-Si ) is a method for manufacturing a semiconductor memory device satisfying the first relationship:

[0011] (Relationship 1)

[0012]

[0013] Here, λ is the wavelength of the laser, and n a-Si is the refractive index of the first semiconductor material film, N is one of 1, 2, or 3, Δ is an optical path correction factor, and is greater than or equal to -1 / 8 and less than or equal to 1 / 8.

[0014] Other specific details of the present invention are included in the detailed description and drawings. Brief explanation of the drawing

[0015] FIG. 1 is a schematic layout diagram of a semiconductor memory device according to some embodiments. Figure 2 is a schematic layout of the R1 region of Figure 1. Figure 3 is a layout showing only the word lines and active areas of Figure 2. Figure 4 is a schematic layout diagram of the R2 region of Figure 1. Figure 5 is a schematic layout diagram of the R3 region of Figure 1. FIG. 6 is an exemplary cross-sectional view taken along A-A of FIG. 4. Figure 7 is an exemplary cross-sectional view taken along B-B of Figure 4. FIG. 8 is an exemplary cross-sectional view taken along C-C of FIG. 5. FIG. 9 is an exemplary cross-sectional view taken along D-D of FIG. 5. FIG. 10 is a drawing for illustrating a semiconductor memory device according to some embodiments. FIG. 11 is a drawing for illustrating a semiconductor memory device according to some embodiments. FIG. 12 is a schematic layout diagram of a semiconductor memory device according to some embodiments. FIG. 13 is an exemplary cross-sectional view taken along A-A of FIG. 12. FIG. 14 is a schematic layout diagram of a semiconductor memory device according to some embodiments. FIGS. 15 to 21 are intermediate drawings for explaining a method for manufacturing a semiconductor memory device according to some embodiments. FIGS. 22 and 23 are drawings illustrating the effect of the thickness of a semiconductor material film formed on a substrate on the intensity of laser energy absorbed by the semiconductor material film. FIGS. 24 to 27 are drawings illustrating the effect of the arrangement of structures on a substrate on the intensity of laser energy absorbed by a semiconductor material film. FIGS. 28 to 32 are intermediate drawings for explaining a method for manufacturing a semiconductor memory device according to some embodiments. Figure 33 is a diagram showing the reflectivity of a laser according to the thickness of the anti-reflection film. Specific details for implementing the invention

[0016] FIG. 1 is a schematic layout diagram of a semiconductor memory device according to some embodiments. FIG. 2 is a schematic layout of the R1 region of FIG. 1. FIG. 3 is a layout showing only the word line and active region of FIG. 2. FIG. 4 is a schematic layout diagram of the R2 region of FIG. 1. FIG. 5 is a schematic layout diagram of the R3 region of FIG. 1. FIG. 6 is an exemplary cross-sectional view cut along A-A of FIG. 4. FIG. 7 is an exemplary cross-sectional view cut along B-B of FIG. 4. FIG. 8 is an exemplary cross-sectional view cut along C-C of FIG. 5. FIG. 9 is an exemplary cross-sectional view cut along D-D of FIG. 5.

[0017] In the drawings relating to a semiconductor memory device according to some embodiments, a Dynamic Random Access Memory (DRAM) is illustrated as an example, but is not limited thereto.

[0018] Referring to FIGS. 1 to 5, a semiconductor memory device according to some embodiments may include a cell region (20), a cell region separator (22), and a ferri region (24).

[0019] A cell region separator (22) can be formed along the perimeter of a cell region (20). The cell region separator (22) can separate the cell region (20) and the periregion (24). The cell region separator (22) defines the cell region (20). The periregion (24) can be defined around the cell region (20).

[0020] The cell region (20) may include a plurality of cell active regions (ACTs). The cell active regions (ACTs) may be defined by a cell device isolation film (105 in FIG. 5 to 9) formed within a substrate (100 in FIG. 4). Due to the reduction of design rules for semiconductor memory devices, the cell active regions (ACTs) may be arranged in the form of a bar of a diagonal line or oblique line as illustrated. For example, the cell active regions (ACTs) may extend in a third direction (D3).

[0021] A plurality of gate electrodes may be arranged extending in a first direction (D1) across the cell active region (ACT). The plurality of gate electrodes may be arranged parallel to each other. The plurality of gate electrodes may be, for example, a plurality of word lines (WL). The word lines (WL) may be arranged at equal intervals. The width of the word lines (WL) or the spacing between the word lines (WL) may be determined according to design rules.

[0022] The cell area (20) may include a dummy cell area (20_DCR) and a normal cell area (20_NCR). The dummy cell area (20_DCR) may be placed on both sides of the normal cell area (20_NCR) in the first direction (D1).

[0023] The dummy cell region (20_DCR) may be bordered by a cell region separator (22) that extends in the second direction (D2). That is, the boundary between the dummy cell region (20_DCR) and the cell region separator (22) may be extended in the second direction (D2). The dummy cell region (20_DCR) is located between the normal cell region (20_NCR) and the cell region separator (22).

[0024] The word line (WL) can extend to the cell region separator (22). A portion of the word line (WL) can overlap the cell region separator (22) in the fourth direction (D4).

[0025] Each cell active area (ACT) can be divided into three parts by two word lines (WL) extending in the first direction (D1). The cell active area (ACT) may include a storage connection area (103b) and a bit line connection area (103a). The bit line connection area (103a) may be located in the middle part of the cell active area (ACT), and the storage connection area (103b) may be located at the end of the cell active area (ACT).

[0026] A plurality of bit lines (BL) extending in a second direction (D2) orthogonal to the word line (WL) may be arranged on the word line (WL). The plurality of bit lines (BL) may extend parallel to each other. The bit lines (BL) may be arranged at equal intervals. The width of the bit lines (BL) or the spacing between the bit lines (BL) may be determined according to design rules.

[0027] The bit line (BL) may extend to the cell region separator (22). A portion of the bit line (BL) may overlap the cell region separator (22) in a fourth direction (D4). The fourth direction (D4) may be orthogonal to the first direction (D1), the second direction (D2), and the third direction (D3). The fourth direction (D4) may be the thickness direction of the substrate (100).

[0028] A plurality of bit lines (BL) may include a normal bit line group (BL_NG) and a dummy bit line group (BL_DG). The dummy bit line group (BL_DG) may be placed in a dummy cell area (20_DCR). The normal bit line group (BL_NG) may be placed in a normal cell area (20_NCR).

[0029] A dummy bit line group (BL_DG) can be placed at the boundary of the cell region (20). A dummy bit line group (BL_DG) can be placed at the boundary of the cell region (20) extended in the second direction (D2). Since each dummy bit line group (BL_DG) is placed at the boundary of the cell region (20) extended in the second direction (D2), a normal bit line group (BL_NG) can be placed between the dummy bit line groups (BL_DG).

[0030] A normal bit line group (BL_NG) may include a plurality of normal bit lines (BL_N) extended in a second direction (D2). The normal bit lines (BL_N) may be bit lines used for the operation of memory cells included in a semiconductor memory device.

[0031] Each normal bit line (BL_N) can be spaced apart in a first direction (D1). For example, the normal bit lines (BL_N) can be spaced at a bit line pitch (BL_P) interval. That is, the spacing between adjacent normal bit lines (BL_N) in the first direction (D1) can be the bit line pitch (BL_P).

[0032] A dummy bit line group (BL_DG) may include a plurality of dummy bit lines (BL_DA, BL_DB) extended in a second direction (D2). Each of the plurality of dummy bit lines (BL_DA, BL_DB) may be a bit line that is not used for the operation of a memory cell included in a semiconductor memory device. For example, a voltage source or a current source may not be connected to the plurality of dummy bit lines (BL_DA, BL_DB), so that the plurality of dummy bit lines (BL_DA, BL_DB) may each be in an electrically floating state.

[0033] A dummy bit line group (BL_DG) may include an outermost dummy bit line (BL_DA) that is closest to the periphery region (24) and the first direction (D1). A dummy bit line group (BL_DG) may include an inner dummy bit line (BL_DB) positioned between the outermost dummy bit line (BL_DA) and the normal bit line (BL_N).

[0034] The outermost dummy bit line (BL_DA) may be extended in a second direction (D2) parallel to the inner dummy bit line (BL_DB). The outermost dummy bit line (BL_DA) is spaced apart from the inner dummy bit line (BL_DB) in a first direction (D1). The outermost dummy bit line (BL_DA) may be positioned so as not to overlap with the cell region separator (22) in the first direction (D1), but is not limited thereto.

[0035] A dummy bit line group (BL_DG) may include, for example, two or more and six or fewer dummy bit lines. For example, an inner dummy bit line (BL_DB) may include one or more and five or fewer dummy bit lines.

[0036] In FIG. 4, the dummy bit line group (BL_DG) may include two dummy bit lines. The dummy bit line group (BL_DG) placed on one side of the normal bit line group (BL_NG) may, for example, have an outermost dummy bit line (BL_DA) and one inner dummy bit line (BL_DB).

[0037] The width of the dummy cell region (20_DCR) in the first direction (D1) may be, for example, greater than or equal to 50 nm and less than or equal to 200 nm. For example, the width of the dummy cell region (20_DCR) may be the distance from the boundary between the cell region (20) and the cell region separator (22) to the sidewall of the inner dummy bit line (BL_DB) closest to the normal bit line (BL_N).

[0038] The width of the dummy cell region (20_DCR) in the first direction (D1) may be greater than the bit line pitch (BL_P). The width of the dummy cell region (20_DCR) in the first direction (D1) may be less than or equal to five times the bit line pitch (BL_P).

[0039] The width of the dummy cell region (20_DCR) in the first direction (D1) may vary depending on the number of dummy bit lines included in the dummy bit line group (BL_DG).

[0040] The boundary ferry gate (PR_GE) may extend in a second direction (D2) parallel to the outermost dummy bit line (BL_DA). The boundary ferry gate (PR_GE) may be positioned at the boundary of the cell region separator (22) and the ferry region (24). Unlike what is illustrated, in some embodiments of the semiconductor memory device, the boundary ferry gate (PR_GE) may extend in a first direction (D1). Additionally, in some embodiments of the semiconductor memory device, the boundary ferry gate (PR_GE) may not be included.

[0041] A semiconductor memory device according to some embodiments may include various contact arrays formed on a cell active region (ACT). The various contact arrays may include, for example, a direct contact (DC), a buried contact (BC), and a landing pad (LP).

[0042] Here, the direct contact (DC) may refer to a contact that electrically connects the cell active region (ACT) to the bit line (BL). The buried contact (BC) may refer to a contact that connects the cell active region (ACT) to the lower electrode of the capacitor (191 in FIG. 6 and 9). Due to the arrangement structure, the contact area between the buried contact (BC) and the cell active region (ACT) may be small. Accordingly, a conductive landing pad (LP) may be introduced to increase the contact area with the cell active region (ACT) and to increase the contact area with the lower electrode of the capacitor (191 in FIG. 6 and 9).

[0043] A landing pad (LP) may be placed between a cell active region (ACT) and a buried contact (BC), or between a buried contact (BC) and a lower electrode of a capacitor (191 in FIG. 6 and 9). In a semiconductor memory device according to some embodiments, the landing pad (LP) may be placed between a buried contact (BC) and a lower electrode of a capacitor. By expanding the contact area through the introduction of a landing pad (LP), the contact resistance between the cell active region (ACT) and the lower electrode of the capacitor may be reduced.

[0044] The direct contact (DC) can be connected to the bit line connection area (103a). The buried contact (BC) can be connected to the storage connection area (103b). As the buried contact (BC) is positioned at both ends of the cell active area (ACT), the landing pad (LP) can be positioned adjacent to both ends of the cell active area (ACT) and partially overlap with the buried contact (BC). Alternatively, the buried contact (BC) can be formed to overlap with the cell active area (ACT) and the cell device separator (105 in FIG. 6) located between adjacent word lines (WL) and between adjacent bit lines (BL).

[0045] The word line (WL) can be formed as a structure embedded within the substrate (100). The word line (WL) can be positioned across the cell active region (ACT) between the direct contact (DC) or the embedded contact (BC). As illustrated, two word lines (WL) can be positioned to cross one cell active region (ACT). As the cell active region (ACT) extends along the third direction (D3), the word line (WL) can have an angle of less than 90 degrees with the cell active region (ACT).

[0046] Direct contacts (DC) and buried contacts (BC) can be arranged symmetrically. As a result, direct contacts (DC) and buried contacts (BC) can be arranged along a straight line along the first direction (D1) and the second direction (D2). Meanwhile, unlike direct contacts (DC) and buried contacts (BC), landing pads (LP) can be arranged in a zigzag shape in the second direction (D2) where the bit line (BL) extends. Additionally, landing pads (LP) can be arranged to overlap with the same side portion of each bit line (BL) in the first direction (D1) where the word line (WL) extends. For example, each landing pad (LP) of the first line can overlap with the left side of the corresponding bit line (BL), and each landing pad (LP) of the second line can overlap with the right side of the corresponding bit line (BL).

[0047] Referring to FIGS. 1 to 9, a semiconductor memory device according to some embodiments may include a plurality of cell gate structures (110), a plurality of cell conductive lines (140N, 140DA, 140DB), a plurality of storage pads (160), an information storage element (190), and a ferrigate conductive film (240).

[0048] The substrate (100) may include a cell region (20), a cell region separator (22), and a ferri region (24). The substrate (100) may be a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the substrate (100) may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0049] A plurality of cell gate structures (110), a plurality of cell conductive lines (140N, 140DA, 140DB), a plurality of storage pads (160), and an information storage unit (190) may be disposed in the cell area (20). A perigate conductive film (240) may be disposed in the peri area (24).

[0050] A cell device isolation layer (105) can be formed within the substrate (100) of the cell region (20). The cell device isolation layer (105) may have a shallow trench isolation (STI) structure having excellent device isolation characteristics. The cell device isolation layer (105) may define a cell active region (ACT) within the cell region (20). The cell active region (ACT) defined by the cell device isolation layer (105) may have a long island formation including a short axis and a long axis as illustrated in FIGS. 2 to 5. The cell active region (ACT) may have a diagonal shape having an angle of less than 90 degrees with respect to the word line (WL) formed within the cell device isolation layer (105). Additionally, the cell active region (ACT) may have a diagonal shape having an angle of less than 90 degrees with respect to the bit line (BL) formed on the cell device isolation layer (105).

[0051] The cell region separator (22) may also be formed as a cell boundary separator having an STI structure. The cell region (20) may be defined by the cell region separator (22).

[0052] The cell element separator (105) and the cell region separator (22) may each include, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, but are not limited thereto. In FIGS. 6 to 9, the cell element separator (105) and the cell region separator (22) are each shown as being formed of a single insulating film, but this is for convenience of explanation only and is not limited thereto. Depending on the width of the cell element separator (105) and the cell region separator (22), the cell element separator (105) and the cell region separator (22) may each be formed of a single insulating film or may be formed of a plurality of insulating films.

[0053] In FIGS. 6 and 8, the upper surface of the cell element separator (105), the upper surface of the substrate (100), and the upper surface of the cell region separator (22) are shown as being on the same plane, but this is for convenience of explanation only and is not limited thereto.

[0054] A cell gate structure (110) may be formed within a substrate (100) and a cell device isolation layer (105). The cell gate structure (110) may be formed across the cell device isolation layer (105) and the cell active region (ACT) defined by the cell device isolation layer (105).

[0055] The cell gate structure (110) may include a cell gate trench (115) formed within the substrate (100) and the cell device isolation layer (105), a cell gate insulating layer (111), a cell gate electrode (112), a cell gate capping pattern (113), and a cell gate capping conductive layer (114). Here, the cell gate electrode (112) may correspond to a word line (WL). Unlike what is illustrated, the cell gate structure (110) may not include a cell gate capping conductive layer (114).

[0056] The cell gate insulating film (111) may extend along the sidewalls and bottom surface of the cell gate trench (115). The cell gate insulating film (111) may extend along the profile of at least a portion of the cell gate trench (115). The cell gate insulating film (111) may comprise, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide. High dielectric constant materials may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0057] A cell gate electrode (112) may be placed on a cell gate insulating film (111). The cell gate electrode (112) may fill a portion of the cell gate trench (115). A cell gate capping conductive film (114) may extend along the upper surface of the cell gate electrode (112).

[0058] The cell gate electrode (112) may include at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide. The cell gate electrode (112) may include, for example, at least one of TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrOx, RuOx, and combinations thereof, but is not limited thereto. The cell gate capping conductive film (114) may include, for example, polysilicon or polysilicon-germanium, but is not limited thereto.

[0059] A cell gate capping pattern (113) may be disposed on a cell gate electrode (112) and a cell gate capping conductive film (114). The cell gate capping pattern (113) may fill the cell gate trench (115) remaining after the cell gate electrode (112) and the cell gate capping conductive film (114) are formed. Although the cell gate insulating film (111) is illustrated as extending along the sidewall of the cell gate capping pattern (113), it is not limited thereto. The cell gate capping pattern (113) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof.

[0060] Although not shown, an impurity doping region may be formed on at least one side of the cell gate structure (110). The impurity doping region may be the source / drain region of the transistor. The impurity doping region may be formed in the storage connection region (103b) and the bit line connection region (103a) of FIG. 3.

[0061] The bit line structure may include cell conductive lines (140N, 140DA, 140DB) and a cell line capping film (144). The cell conductive lines (140N, 140DA, 140DB) may be formed on a substrate (100) on which a cell gate structure (110) is formed and on a cell device isolation film (105). The cell conductive lines (140N, 140DA, 140DB) may intersect with the cell device isolation film (105) and the cell active region (ACT) defined by the cell device isolation film (105). The cell conductive lines (140N, 140DA, 140DB) may be formed to intersect with the cell gate structure (110). Here, the cell conductive lines (140N, 140DA, 140DB) may correspond to a bit line (BL).

[0062] The cell conduction lines (140N, 140DA, 140DB) may include a normal cell conduction line (140N) and a dummy cell conduction line (140DA, 140DB). The dummy cell conduction lines (140DA, 140DB) may include a first outermost dummy cell conduction line (140DA) and an inner dummy cell conduction line (140DB). The normal cell conduction line (140N) may correspond to a normal bit line (BL_N). The first outermost dummy cell conduction line (140DA) may correspond to an outermost dummy bit line (BL_DA). The inner dummy cell conduction line (140DB) may correspond to an inner dummy bit line (BL_DB).

[0063] The cell conductive lines (140N, 140DA, 140DB) may be multilayer films. The cell conductive lines (140N, 140DA, 140DB) may each include, for example, a first cell conductive film (141), a second cell conductive film (142), and a third cell conductive film (143). The first to third cell conductive films (141, 142, 143) may be sequentially stacked on a substrate (100) and a cell device isolation film (105). Although the cell conductive lines (140N, 140DA, 140DB) are depicted as triple films, they are not limited thereto.

[0064] The first to third cell conductive films (141, 142, 143) may each comprise, for example, at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal alloy. For example, the first cell conductive film (141) may comprise a doped semiconductor material. The first cell conductive film (141) may be a semiconductor conductive line. The second cell conductive film (142) may comprise at least one of a conductive silicide compound and a conductive metal nitride. The third cell conductive film (143) may comprise at least one of a metal and a metal alloy. The second cell conductive film (142) and the third cell conductive film (143) may be metallic conductive lines.

[0065] The normal cell conductive line (140N) may have a first width (W1) in the first direction (D1). The first outermost dummy cell conductive line (140DA) may have a second width (W21) in the first direction (D1). The inner dummy cell conductive line (140DB) may have a third width (W22) in the first direction (D1).

[0066] Here, the width (W1) of the normal cell conductive line (140N), the width (W21) of the first outermost dummy cell conductive line (140DA), and the width (W22) of the inner dummy cell conductive line (140DB) may each be the width of the bottom surface of the cell conductive lines (140N, 140DA, 140DB). That is, the width (W1) of the normal cell conductive line (140N), the width (W21) of the first outermost dummy cell conductive line (140DA), and the width (W22) of the inner dummy cell conductive line (140DB) may be the width of the bottom surface of the first cell conductive film (141) facing the substrate (100).

[0067] The width (W1) of the normal cell conduction line (140N) may be the width of the normal bit line (BL_N). The width (W21) of the first outermost dummy cell conduction line (140DA) may be the width of the outermost dummy bit line (BL_DA). The width (W22) of the inner dummy cell conduction line (140DB) may be the width of the inner dummy bit line (BL_DB).

[0068] For example, the width (W22) of the inner dummy cell conduction line (140DB) is the same as the width (W1) of the normal cell conduction line (140N). In a semiconductor memory device according to some embodiments, the width (W21) of the first outermost dummy cell conduction line (140DA) may be the same as the width (W22) of the inner dummy cell conduction line (140DB). The widths (W21, W22) of each dummy cell conduction line (140DA, 140DB) may be the same as the width (W1) of the normal cell conduction line (140N).

[0069] The ratio of the width (W21, W22) of the dummy cell conduction line (140DA, 140DB) to the width (W1) of the normal cell conduction line (140N) may be 1. That is, the ratio (W21 / W1) of the width (W21) of the first outermost dummy cell conduction line (140DA) to the width (W1) of the normal cell conduction line (140N) may be 1. The ratio (W22 / W1) of the width (W22) of the inner dummy cell conduction line (140DB) to the width (W1) of the normal cell conduction line (140N) may be 1.

[0070] For example, the width (W1) of the normal cell conduction line (140N) may be greater than or equal to 5 nm and less than or equal to 25 nm. Likewise, the widths (W21, W22) of the dummy cell conduction lines (140DA, 140DB) may each be greater than or equal to 5 nm and less than or equal to 25 nm.

[0071] A bit line contact (146) can be formed between the cell conductive lines (140N, 140DA, 140DB) and the substrate (100). That is, the cell conductive lines (140N, 140DA, 140DB) can be formed on the bit line contact (146). For example, the bit line contact (146) can be formed at a point where the cell conductive lines (140N, 140DA, 140DB) intersect with the middle part of the cell active area (ACT) having a long island shape. The bit line contact (146) can be formed between the bit line connection area (103a) of the cell active area (ACT) and the cell conductive lines (140N, 140DA, 140DB). The bit line contact (146) can be connected to the bit line connection area (103a).

[0072] A plurality of bit line contacts (146) may be arranged along the second direction (D2). Each cell conduction line (140N, 140DA, 140DB) may be arranged on the plurality of bit line contacts (146) and extend along the second direction (D2).

[0073] A bit line contact (146) can electrically connect a cell conductive line (140N, 140DA, 140DB) and a substrate (100). Here, the bit line contact (146) may correspond to a direct contact (DC). The bit line contact (146) may include, for example, at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. In a semiconductor memory device according to some embodiments, the bit line contact (146) may include an impurity-doped semiconductor material.

[0074] In FIG. 8, where the normal cell conductive line (140N) is illustrated, in the area overlapping with the upper surface (146US) of the bit line contact, the normal cell conductive line (140N) may include a second cell conductive film (142) and a third cell conductive film (143). In the area not overlapping with the upper surface (146US) of the bit line contact, the normal cell conductive line (140N) may include first to third cell conductive films (141, 142, 143).

[0075] Although not shown, dummy cell conduction lines (140DA, 140DB) may also have the same structure as normal cell conduction lines (140N).

[0076] The second cell conductive film (142) may extend along the upper surface (141US) of the first cell conductive film and the upper surface (146US) of the bit line contact. The bottom surface (142BS) of the second cell conductive film may face the upper surface (141US) of the first cell conductive film and the upper surface (146US) of the bit line contact.

[0077] The bottom surface (142BS) of the second cell conductive film may be in direct contact with the top surface (141US) of the first cell conductive film and the top surface (146US) of the bit line contact. With respect to the top surface of the substrate (100), the height of the bottom surface (142BS) of the second cell conductive film may be the same as the height of the top surface (146US) of the bit line contact. For example, with respect to the top surface of the substrate (100), the height of the top surface (141US) of the first cell conductive film may be the same as the height of the top surface (146US) of the bit line contact.

[0078] A plurality of bit line contacts (146) may include a first bit line contact, a second bit line contact, and a third bit line contact below a cell conductive line (140N, 140DA, 140DB). The first to third bit line contacts may be arranged sequentially in a second direction (D2) from the cell region separator (22). The second bit line contact may be arranged between the first bit line contact and the third bit line contact. In a semiconductor memory device according to some embodiments, the bottom surface (142BS) of the second cell conductive film may be in direct contact with the top surface (146US) of the first bit line contact, the top surface (146US) of the second bit line contact, and the top surface (146US) of the third bit line contact.

[0079] In FIG. 8, a bit line contact (146) is shown not being placed between the normal cell conductive line (140N) closest to the cell region separator (22) and the substrate (100), but is not limited thereto. Unlike what is shown, a bit line contact (146) may be placed between the normal cell conductive line (140N) closest to the cell region separator (22) and the substrate (100).

[0080] A cell line capping film (144) may be disposed on a cell conductive line (140N, 140DA, 140DB). The cell line capping film (144) may extend in a second direction (D2) along the upper surface of the cell conductive line (140N, 140DA, 140DB). In this case, the cell line capping film (144) may include, for example, at least one of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon oxycarbonitride. In a semiconductor memory device according to some embodiments, the cell line capping film (144) may include, for example, a silicon nitride film. Although the cell line capping film (144) is depicted as a single film, it is not limited thereto.

[0081] A cell insulating film (130) may be formed on a substrate (100) and a cell element separator (105). More specifically, the cell insulating film (130) may be placed on a substrate (100) and a cell element separator (105) where bit line contacts (146) are not formed. The cell insulating film (130) may be placed between the substrate (100) and the cell conductive line (140), and between the cell element separator (105) and the cell conductive line (140N, 140DA, 140DB).

[0082] The cell insulating film (130) may be a single film, but as illustrated, the cell insulating film (130) may be a multi-film comprising a first cell insulating film (131) and a second cell insulating film (132). For example, the first cell insulating film (131) may comprise a silicon oxide film and the second cell insulating film (132) may comprise a silicon nitride film, but is not limited thereto. Of course, unlike illustrated, the cell insulating film (130) may comprise three or more insulating films.

[0083] The cell buffer film (101) may be placed between the cell insulating film (130) and the cell region separator (22). The cell buffer film (101) may include, for example, a silicon oxide film, but is not limited thereto.

[0084] A cell line spacer (150) may be disposed on the sidewalls of the cell conductive lines (140N, 140DA, 140DB) and the cell line capping film (144). In the portion of the cell conductive lines (140N, 140DA, 140DB) where the bit line contact (146) is formed, the cell line spacer (150) may be formed on the substrate (100) and the cell device isolation film (105). The cell line spacer (150) may be disposed on the sidewalls of the cell conductive lines (140N, 140DA, 140DB), the cell line capping film (144), and the bit line contact (146).

[0085] In the remainder of the cell conductive lines (140N, 140DA, 140DB) where bit line contacts (146) are not formed, a cell line spacer (150) may be placed on the cell insulating film (130). The cell line spacer (150) may be placed on the sidewalls of the cell conductive lines (140N, 140DA, 140DB) and the cell line capping film (144).

[0086] The cell line spacer (150) may be a single film, but as illustrated, the cell line spacer (150) may be a multi-film comprising first to fourth cell line spacers (151, 152, 153, 154). For example, the first to fourth cell line spacers (151, 152, 153, 154) may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), a silicon oxycarbonitride film (SiOCN), air, and a combination thereof, but are not limited thereto.

[0087] For example, the second cell line spacer (152) is not placed on the cell insulating film (130) but can be placed on the sidewall of the bit line contact (146). The cell line spacer (150) can be placed on the long sidewall of the cell conductive line (140N, 140DA, 140DB) that extends in the second direction (D2).

[0088] A fence pattern (170) may be disposed on a substrate (100) and a cell device separator (105). The fence pattern (170) may be formed to overlap with a cell gate structure (110) formed within the substrate (100) and the cell device separator (105). The fence pattern (170) may be disposed between cell conduction lines (140N, 140DA, 140DB) extending in a second direction (D2). The fence pattern (170) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0089] A plurality of storage contacts (120) may be placed between adjacent cell conduction lines (140N, 140DA, 140DB) in a first direction (D1). Storage contacts (120) may be placed between adjacent fence patterns (170) in a second direction (D2). Storage contacts (120) may overlap with the substrate (100) and cell device isolation film (105) between adjacent cell conduction lines (140N, 140DA, 140DB). Storage contacts (120) may be connected to a storage connection area (103b) of a cell active area (ACT). Here, the storage contacts (120) may correspond to a buried contact (BC).

[0090] A plurality of storage contacts (120) may be arranged along a first direction (D1). In a semiconductor memory device according to some embodiments, the plurality of storage contacts (120) may not include an air gap.

[0091] The storage contact (120) may include, for example, at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. In a semiconductor memory device according to some embodiments, the storage contact (120) may include an impurity-doped semiconductor material.

[0092] A storage pad (160) can be placed on each storage contact (120). The storage pad (160) can be electrically connected to the storage contact (120). The storage pad (160) can be connected to the storage connection area (103b) of the cell active area (ACT). Here, the storage pad (160) can correspond to a landing pad (LP).

[0093] The storage pad (160) may overlap with a portion of the upper surface of the cell conductive lines (140N, 140DA, 140DB). The storage pad (160) may include, for example, at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy.

[0094] A pad separation insulating film (180) may be formed on a storage pad (160) and cell conductive lines (140N, 140DA, 140DB). For example, the pad separation insulating film (180) may be placed on a cell line capping film (144). The pad separation insulating film (180) may define a storage pad (160) that forms a plurality of isolated regions. The pad separation insulating film (180) may not cover the upper surface (160US) of the storage pad. The pad separation insulating film (180) may fill a pad separation recess. The pad separation recess may separate adjacent storage pads (160).

[0095] The pad separation insulating film (180) comprises an insulating material and can electrically separate a plurality of storage pads (160) from each other. For example, the pad separation insulating film (180) may include at least one of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxycarbonitride film, and a silicon carbonitride film, but is not limited thereto.

[0096] The perigate structure may be disposed on the substrate (100) of the perigate region (24). The perigate structure may be disposed on the perigate active region defined by the perigate device isolation layer. The perigate structure may be formed in the perigate region (24) and may be included in a peripheral circuit that controls a memory cell formed in the cell region (20).

[0097] A perigate structure may include a perigate insulating film (230), a perigate conductive film (240), and a pericapping film (244) sequentially stacked on a substrate (100). The perigate structure may include a perispacer (245) disposed on the sidewall of the perigate conductive film (240) and the sidewall of the pericapping film (244).

[0098] The boundary perigate (PR_GE) shown in FIG. 4 may include a perigate conductive film (240). That is, the perigate structure of the perigate region (24) may include a perigate insulating film (230) shown in FIG. 6, a perigate conductive film (240), a perigate capping film (244), and a perispacer (245).

[0099] The perigate conductive film (240) may include first to third perigate conductive films (241, 242, 243) sequentially stacked on the perigate insulating film (230). In one example, no additional conductive film may be disposed between the perigate conductive film (240) and the perigate insulating film (230). In another example, unlike what is illustrated, an additional conductive film, such as a work function conductive film, may be disposed between the perigate conductive film (240) and the perigate insulating film (230).

[0100] The ferrite gate conductive film (240) may have the same stacked structure as the cell conductive lines (140N, 140DA, 140DB). The first ferrite conductive film (241) may contain the same material as the first cell conductive film (141). The second ferrite conductive film (242) may contain the same material as the second cell conductive film (142). The third ferrite conductive film (243) may contain the same material as the third cell conductive film (143).

[0101] The ferrigate insulating film (230) may comprise, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The ferrispacer (245) may comprise, for example, at least one of silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, and combinations thereof. The ferricapping film (244) may comprise, for example, at least one of silicon nitride, silicon oxynitride, and silicon oxide.

[0102] The lower etch stop layer (250) may be disposed on the substrate (100). The lower etch stop layer (250) may be formed along the profile of the ferrite gate structure. The lower etch stop layer (250) may be disposed on the short sidewall of the cell conduction line (140N, 140DA, 140DB) extending in the first direction (D1). The lower etch stop layer (250) may be extended along the long sidewall of the first outermost dummy cell conduction line (140DA) extending in the second direction (D2). The lower etch stop layer (250) may comprise, for example, at least one of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon oxycarbonitride.

[0103] The lower interlayer insulating film (290) may be placed on the lower etch stop film (250). The lower interlayer insulating film (290) may be placed on the cell region separator (22) between the first outermost dummy cell conductive line (140DA) and the interlayer gate conductive film (240).

[0104] The lower interlayer insulating film (290) may include an oxide-based insulating material. The upper surface of the lower interlayer insulating film (290) may be placed in the same plane as the lower etch stop film (250) that extends along the upper surface of the interlayer capping film (244).

[0105] The upper interlayer insulating film (291) is disposed on the interlayer gate conductive film (240) and the lower interlayer insulating film (290). The upper interlayer insulating film (291) can cover the lower etch stop film (250) and the lower interlayer insulating film (290).

[0106] The upper interlayer insulating film (291) may contain a material different from the lower interlayer insulating film (290). The upper interlayer insulating film (291) may contain, for example, a nitride-based insulating material. For example, the upper interlayer insulating film (291) may contain silicon nitride.

[0107] The perimeter wiring line (265) can be placed on the upper perimeter interlayer insulating film (291). The perimeter wiring line (265) can connect the peripheral circuit formed in the perimeter region (24) and the memory cell formed in the cell region (20).

[0108] The bit line contact plug (261) can be connected to a normal cell conductive line (140N) by passing through the upper ferri layer interlayer insulating film (291) and the cell line capping film (144). The bit line contact plug (261) can be connected to a peripheral circuit formed in the ferri region (24).

[0109] For example, the bit line contact plug (261) may not be connected to the dummy cell conduction lines (140DA, 140DB). That is, the bit line contact plug (261) connected to the dummy cell conduction lines (140DA, 140DB) may not be formed on the dummy cell conduction lines (140DA, 140DB). For another example, the bit line contact plug (261) may be connected to the dummy cell conduction lines (140DA, 140DB). However, the bit line contact plug (261) connected to the dummy cell conduction lines (140DA, 140DB) may not be connected to the peripheral circuit formed in the periphery area (24). Alternatively, the bit line contact plug (261) connected to the dummy cell conduction lines (140DA, 140DB) may not be connected to a voltage source or a current source.

[0110] The ferry wiring line (265) and the bit line contact plug (261) may contain the same material as the storage pad (160), but are not limited thereto. The ferry wiring line (265) and the bit line contact plug (261) may be formed at the same level as the storage pad (160), but are not limited thereto. Here, "same level" means formed by the same manufacturing process. The upper surface (265US) of the ferry wiring line and the upper surface of the bit line contact plug (261) may be placed on the same plane as the upper surface (160US) of the storage pad.

[0111] The upper etch stop layer (295) may be placed on the storage pad (160), the pad separation insulating layer (180), the ferry wiring line (265), and the bit line contact plug (261). The upper etch stop layer (195) may extend to the ferry region (24) as well as the cell region (20). The upper etch stop layer (195) may include at least one of silicon nitride, silicon carbonitride, silicon boron nitride (SiBN), silicon oxynitride, and silicon oxycarbonate.

[0112] The information storage element (190) may be placed on the storage pad (160). The information storage element (190) may be electrically connected to the storage pad (160). A portion of the information storage element (190) may be placed within the upper etch stop layer (295). The information storage element (190) may include, for example, a capacitor, but is not limited thereto. The information storage element (190) includes a lower electrode (191), a capacitor dielectric film (192), and an upper electrode (193). For example, the upper electrode (193) may be a plate upper electrode having a plate shape. The upper electrode (193) is depicted as a single film, but this is for convenience of explanation only and is not limited thereto.

[0113] The lower electrode (191) may be placed on the storage pad (160). Although the lower electrode (191) is illustrated as having a pillar shape, it is not limited thereto. Of course, the lower electrode (191) may have a cylinder shape. A capacitor dielectric film (192) is formed on the lower electrode (191). The capacitor dielectric film (192) may be formed along the profile of the lower electrode (191). An upper electrode (193) is formed on the capacitor dielectric film (192). The upper electrode (193) may wrap around the outer wall of the lower electrode (191).

[0114] For example, the capacitor dielectric film (192) may be placed in a portion that overlaps with the upper electrode (193) in the fourth direction (D4). For another example, unlike what is illustrated, the capacitor dielectric film (192) may include a first portion that overlaps with the upper electrode (193) in the fourth direction (D4) and a second portion that does not overlap with the upper electrode (193) in the fourth direction (D4). That is, the second portion of the capacitor dielectric film (192) is a portion that is not covered by the upper electrode (193).

[0115] The lower electrode (191) and the upper electrode (193) may each include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium or tantalum, etc.), and a conductive metal oxide (e.g., iridium oxide or niobium oxide, etc.), but are not limited thereto.

[0116] The capacitor dielectric film (192) may include, for example, one of silicon oxide, silicon nitride, silicon oxynitride, and high dielectric constant materials and combinations thereof, but is not limited thereto. In a semiconductor memory device according to some embodiments, the capacitor dielectric film (192) may include a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked. In a semiconductor memory device according to some embodiments, the capacitor dielectric film (192) may include a dielectric film comprising hafnium (Hf). In a semiconductor memory device according to some embodiments, the capacitor dielectric film (192) may have a stacked film structure of a ferroelectric material film and a paraelectric material film.

[0117] The interlayer insulating film (292) may be placed on the upper etch stop film (295). The interlayer insulating film (292) may cover the sidewalls of the upper electrode (193). The interlayer insulating film (292) may include an insulating material.

[0118] FIG. 10 is a drawing for illustrating a semiconductor memory device according to some embodiments. FIG. 11 is a drawing for illustrating a semiconductor memory device according to some embodiments. For convenience of explanation, the explanation will focus on the differences from the explanation using FIG. 1 to 9.

[0119] Referring to FIG. 10, in a semiconductor memory device according to some embodiments, a storage contact (120) including a first air gap (AG_BC) may be arranged discretely.

[0120] For example, a plurality of storage contacts (120) may include a first storage contact, a second storage contact, and a third storage contact. The first storage contact, the second storage contact, and the third storage contact may be sequentially arranged in a first direction (D1) from the cell region separator (22). The second storage contact may be arranged between the first storage contact and the third storage contact.

[0121] For example, the first storage contact and the third storage contact may each include a first air gap (AG_BC). The second storage contact does not include the first air gap (AG_BC). Between the first storage contact including the first air gap (AG_BC) and the third storage contact including the first air gap (AG_BC), a second storage contact that does not include the first air gap (AG_BC) may be disposed.

[0122] Storage contacts (120) including the first air gap (AG_BC) may be arranged at regular intervals, but the technical concept of the present invention is not limited thereto.

[0123] Although it has been illustrated that two second storage contacts not including the first air gap (AG_BC) are disposed between the first storage contact including the first air gap (AG_BC) and the third storage contact including the first air gap (AG_BC), this is for convenience of explanation only and is not limited thereto.

[0124] Additionally, although it is shown that two storage contacts (120) including the first air gap (AG_BC) are arranged in succession, they are not limited thereto.

[0125] Referring to FIG. 11, a semiconductor memory device according to some embodiments may further include a second air gap (AG_DC) disposed between a cell conduction line (140N, 140DA, 140DB) and a bit line contact (146).

[0126] A single cell conduction line (140N, 140DA, 140DB) may be placed on a plurality of bit line contacts (146) arranged in a first direction (D1). The plurality of bit line contacts (146) may include a first bit line contact, a second bit line contact, and a third bit line contact below a single cell conduction line (140N, 140DA, 140DB).

[0127] The first to third bit line contacts can be sequentially arranged in the second direction (D2) from the cell region separator (22).

[0128] In FIG. 11, where the normal cell conduction line (140N) is shown, the second air gap (AG_DC) may be placed between the first bit line contact and the normal cell conduction line (140N), and between the third bit line contact and the normal cell conduction line (140N). The second air gap (AG_DC) is not placed between the second bit line contact and the normal cell conduction line (140N).

[0129] Between one normal cell conduction line (140N) and a plurality of bit line contacts (146), the second air gap (AG_DC) may be arranged discretely. Although it is illustrated that one second bit line contact is arranged between the second air gaps (AG_DC), this is for convenience of explanation only and is not limited thereto.

[0130] The upper surface (146US) of the first bit line contact where the second air gap (AG_DC) is placed and the upper surface (146US) of the third bit line contact may be lower than the upper surface (146US) of the second bit line contact where the second air gap (AG_DC) is not placed. With respect to the upper surface of the substrate (100), the height of the upper surface (146US) of the first bit line contact where the second air gap (AG_DC) is placed and the height of the upper surface (146US) of the third bit line contact may be smaller than the height of the bottom surface (142BS) of the second cell conductive film. With respect to the upper surface of the substrate (100), the upper surface (146US) of the first bit line contact where the second air gap (AG_DC) is placed and the upper surface (146US) of the third bit line contact may be lower than the upper surface (141US) of the first cell conductive film.

[0131] For example, the upper surface (146US) of the first bit line contact, where the second air gap (AG_DC) is placed, and the upper surface (146US) of the third bit line contact may not be in contact with the bottom surface (142BS) of the second cell conductive film. Unlike what is illustrated, in another example, a portion of the upper surface (146US) of the first bit line contact, where the second air gap (AG_DC) is placed, and a portion of the upper surface (146US) of the third bit line contact may be in contact with the bottom surface (142BS) of the second cell conductive film.

[0132] Meanwhile, a plurality of storage contacts (120) arranged along the first direction (D1) may not include the first air gap (AG_BC of FIG. 10).

[0133] FIG. 12 is a schematic layout diagram of a semiconductor memory device according to some embodiments. FIG. 13 is an exemplary cross-sectional view taken along A-A of FIG. 12. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 through 9.

[0134] For reference, FIG. 12 is a schematic layout of the R2 region of FIG. 1.

[0135] Referring to FIG. 12 and FIG. 13, in a semiconductor memory device according to some embodiments, the width (W21) of the first outermost dummy cell conduction line (140DA) may be greater than the width (W22) of the inner dummy cell conduction line (140DB). The width (W22) of the inner dummy cell conduction line (140DB) may be equal to the width (W1) of the normal cell conduction line (140N).

[0136] The ratio of the width (W21, W22) of the dummy cell conduction line (140DA, 140DB) to the width (W1) of the normal cell conduction line (140N) may be greater than or equal to 1 and less than or equal to 2.

[0137] For example, the ratio (W21 / W1) of the width (W21) of the first outermost dummy cell conductive line (140DA) to the width (W1) of the normal cell conductive line (140N) may be greater than 1 and less than or equal to 2. The ratio (W22 / W1) of the width (W22) of the inner dummy cell conductive line (140DB) to the width (W1) of the normal cell conductive line (140N) may be 1. The ratio (W21 / W22) of the width (W21) of the first outermost dummy cell conductive line (140DA) to the width (W22) of the inner dummy cell conductive line (140DB) may be greater than 1 and less than or equal to 2.

[0138] For example, the width (W1) of the normal cell conduction line (140N) may be greater than or equal to 5 nm and less than or equal to 25 nm. The width (W21, W22) of the dummy cell conduction line (140DA, 140DB) may be less than or equal to 30 nm.

[0139] For example, the width (W21, W22) of the dummy cell conduction lines (140DA, 140DB) may be greater than or equal to 5nm and less than or equal to 30nm. The width (W22) of the inner dummy cell conduction line (140DB) may be greater than or equal to 5nm and less than or equal to 25nm. The width (W21) of the first outermost dummy cell conduction line (140DA) may be greater than 5nm and less than or equal to 30nm.

[0140] As another example, the ratio of the width (W21, W22) of the dummy cell conduction line (140DA, 140DB) to the width (W1) of the normal cell conduction line (140N) may be greater than or equal to 1 and less than or equal to 1.7. The ratio (W21 / W22) of the width (W21) of the first outermost dummy cell conduction line (140DA) to the width (W22) of the inner dummy cell conduction line (140DB) may be greater than 1 and less than or equal to 1.7.

[0141] As another example, the ratio of the width (W21, W22) of the dummy cell conduction line (140DA, 140DB) to the width (W1) of the normal cell conduction line (140N) may be greater than or equal to 1 and less than or equal to 1.5. The ratio (W21 / W22) of the width (W21) of the first outermost dummy cell conduction line (140DA) to the width (W22) of the inner dummy cell conduction line (140DB) may be greater than 1 and less than or equal to 1.5. An explanation regarding this will be provided later using FIGS. 24 to 27.

[0142] FIG. 14 is a schematic layout diagram of a semiconductor memory device according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 to 9.

[0143] For reference, FIG. 14 is a schematic layout of the R2 region of FIG. 1.

[0144] Referring to FIG. 14, in a semiconductor device according to some embodiments, a dummy bit line group (BL_DG) includes 6 dummy bit lines.

[0145] The dummy bit line group (BL_DG) includes five inner dummy bit lines (BL_DB) and one outermost dummy bit line (BL_DA).

[0146] The width (W21) of the outermost dummy bit line (BL_DA) and the width (W22, W23) of the inner dummy bit line (BL_DB) in the first direction (D1) are shown as being the same, but are not limited thereto.

[0147] The inner dummy bit line (BL_DB) may include a first inner dummy bit line (BL_DB) and a second inner dummy bit line (BL_DB). The first inner dummy bit line (BL_DB) may be positioned between the second inner dummy bit line (BL_DB) and the outermost dummy bit line (BL_DA). The first inner dummy bit line (BL_DB) may or may not be the dummy bit line closest to the outermost dummy bit line (BL_DA).

[0148] The width of the first inner dummy bit line (BL_DB) in the first direction (D1) may be W22. The width of the second inner dummy bit line (BL_DB) in the first direction (D1) may be W23.

[0149] For example, the width (W21) of the outermost dummy bit line (BL_DA) may be greater than the width (W22, W23) of the inner dummy bit line (BL_DB) in the first direction (D1). The width (W22) of the first inner dummy bit line (BL_DB) may be equal to the width (W23) of the second inner dummy bit line (BL_DB). The width (W22, W23) of the inner dummy bit line (BL_DB) may be equal to the width (W1) of the normal bit line (BL_N).

[0150] As another example, the width (W22) of the first inner dummy bit line (BL_DB) may be greater than the width (W23) of the second inner dummy bit line (BL_DB). The width (W21) of the outermost dummy bit line (BL_DA) may be less than or equal to the width (W22) of the first inner dummy bit line (BL_DB). The width (W23) of the second inner dummy bit line (BL_DB) may be equal to the width (W1) of the normal bit line (BL_N).

[0151] FIGS. 15 to 21 are intermediate drawings for explaining a method for manufacturing a semiconductor memory device according to several embodiments. Any description of the manufacturing method that overlaps with the description using FIGS. 1 to 14 is briefly explained or omitted. Additionally, the description of the manufacturing method is explained using cross-sections cut along A-A and B-B in FIG. 4.

[0152] Referring to FIGS. 1 to 5 and FIGS. 15 to 17, a substrate (100) is provided that includes a cell region (20), a ferri region (24), and a cell region separator (22).

[0153] A cell device isolation film (105) defining a cell active region (ACT) can be formed within the cell region (20).

[0154] A cell gate structure (110) may be formed within a substrate (100) of a cell region (20). The cell gate structure (110) may be extended in a first direction (D1). The cell gate structure (110) may include a cell gate trench (115), a cell gate insulating film (111), a cell gate electrode (112), a cell gate capping pattern (113), and a cell gate capping conductive film (114).

[0155] Next, a cell insulating film (130) can be formed on the cell region (20). The cell insulating film (130) can expose the substrate (100) of the ferri region (24).

[0156] Next, cell conductive lines (140N, 140DA, 140DB) and a cell line capping film (144) may be formed on the substrate (100) of the cell region (20). That is, a plurality of bit lines (BL) extended in a second direction (D2) may be formed on the substrate (100) of the cell region (20). The outermost dummy cell conductive lines (140DA, 140DAA) and the inner dummy cell conductive lines (140DB) are placed in the dummy cell region (20_DCR), and the normal cell conductive line (140N) is placed in the normal cell region (20_NCR).

[0157] While the cell conductive lines (140N, 140DA, 140DB) and the cell line capping film (144) are being formed, the ferrite gate conductive film (240) and the ferrite capping film (244) may be formed. The cell line capping film (144) may be formed by patterning an insulating material film including the ferrite capping film (244), a lower etching stop film (250), and an upper ferrite interlayer insulating film (291).

[0158] A peristructure (PR_ST) is formed in the peri region (24). The peristructure (PR_ST) may include a perigate conductive film (240), a pericapping film (244), a perigate insulating film (230), a perispacer (245), a lower perilayer insulating film (290), and an upper perilayer insulating film (291).

[0159] While the cell conduction lines (140N, 140DA, 140DB) and the cell line capping film (144) are being formed, a bit line contact (146) can be formed.

[0160] In FIG. 15, the ratio of the width of the first outermost dummy cell conduction line (140DA) in the first direction (D1) to the width of the inner dummy cell conduction line (140DB) in the first direction (D1) may be greater than or equal to 1 and less than or equal to 2.

[0161] In FIG. 16, the ratio of the width of the second outermost dummy cell conduction line (140DAA) in the first direction (D1) to the width of the inner dummy cell conduction line (140DB) in the first direction (D1) may be greater than or equal to 3. The second outermost dummy cell conduction line (140DAA) may correspond to the outermost dummy bit line (BL_DA).

[0162] The following explanation is explained using Fig. 15.

[0163] Next, a cell line spacer (150) may be formed. While the fourth cell line spacer (154) is being formed, a storage contact recess (120R) may be formed between adjacent cell conductive lines (140N, 140DA, 140DB) in the first direction (D1).

[0164] Based on the upper surface of the substrate (100), the height of the upper surface (PR_STUS) of the ferri structure is shown to be the same as the height of the upper surface of the cell line capping film (144), but this is for convenience of explanation only and is not limited thereto.

[0165] Next, a first semiconductor material film (121) may be formed on the substrate (100). The first semiconductor material film (121) may include a semiconductor material containing impurities. For example, the first semiconductor material film (121) may include amorphous silicon containing impurities, but is not limited thereto.

[0166] The first semiconductor material film (121) can cover the cell conductive lines (140N, 140DA, 140DB) and the ferristructure (PR_ST). The first semiconductor material film (121) can cover the upper surface of the cell line capping film (144) and the upper surface (PR_STUS) of the ferristructure. The first semiconductor material film (121) can cover the upper surface of the cell gate capping pattern (113).

[0167] The first semiconductor material film (121) can fill the storage contact recess (120R). The first semiconductor material film (121) can fill the space between adjacent cell conduction lines (140N, 140DA, 140DB) in the first direction (D1).

[0168] The thickness (t1) of the first semiconductor material film (121) can satisfy the first relationship. The thickness (t1) of the first semiconductor material film (121) may be the distance from the upper surface (PR_STUS) of the ferri structure to the upper surface (121US) of the first semiconductor material film.

[0169] (Relationship 1)

[0170] In relation 1, t a-Si t1 may be the thickness of the first semiconductor material film (121). λ is the wavelength of the laser used in the laser annealing process (60 in FIG. 18), and n a-Si is the refractive index of the first semiconductor material film (121). N is one of 1, 2, or 3, and Δ may be an optical path correction factor. Δ may be greater than or equal to -1 / 8 and less than or equal to 1 / 8.

[0171] Unlike the above, N may be a natural number greater than or equal to 4. If N is a natural number greater than 4, the thickness (t1) of the first semiconductor material film (121) may become thicker than necessary. In such a case, the efficiency of the manufacturing process may be compromised and the process cost may increase.

[0172] For example, if the first semiconductor material film (121) includes amorphous silicon, n a-Simay be the refractive index of amorphous silicon. The optical path correction factor may be affected by the height difference between the upper surface (PR_STUS) of the peristructure placed on the substrate (100) and the upper surface of the cell line capping film (144). Additionally, the optical path correction factor may be affected by the shape of the peristructure (PR_ST) placed in the periregion (24) and the width and spacing of the cell conduction lines (140N, 140DA, 140DB) placed in the cell region (20).

[0173] Referring to FIGS. 18 and 19, a laser can be irradiated onto the first semiconductor material film (121). A laser annealing process (60) can be performed.

[0174] A second semiconductor material film (122) can be formed on a substrate (100) through a laser annealing process (60). The second semiconductor material film (122) can be formed by recrystallizing the first semiconductor material film (121). As the first semiconductor material film (121) is heated and melted by a laser irradiated onto the first semiconductor material film (121), the first semiconductor material film (121) can be recrystallized.

[0175] Although not shown, a first air gap (AG_BC in FIG. 10) may be formed within the second semiconductor material film (122). Alternatively, a second air gap (AG_DC in FIG. 11) may be formed between the cell conduction lines (140N, 140DA, 140DB) and the bit line contact (146).

[0176] Referring to FIGS. 20 and 21, the upper surface of the cell line capping film (144) and the second semiconductor material film (122) on the upper surface (PR_STUS) of the ferri structure can be removed.

[0177] A second semiconductor material film (122) can be patterned to form a storage contact (120) on the substrate (100) of the cell region (20). The storage contact (120) can be connected to the active region (ACT) of the cell region (20).

[0178] A fence pattern (170) can be formed on the cell gate structure (110). The fence pattern (170) can fill the space where the second semiconductor material film (122) has been removed.

[0179] Although not shown, after patterning the second semiconductor material film (122), a portion of the storage contact (120) may be removed. The upper surface of the storage contact (120) may be lower than the upper surface of the cell line capping film (144).

[0180] Next, referring to FIGS. 6 and 7, a storage pad (160) may be formed on the storage contact (120). Additionally, an information storage element (190) connected to the storage pad (160) may be formed.

[0181] FIGS. 22 and 23 are drawings illustrating the effect of the thickness of a semiconductor material film formed on a substrate on the intensity of laser energy absorbed by the semiconductor material film.

[0182] A first cell structure (C_ST1), a second cell structure (C_ST2), and a ferri structure (PR_ST) may be disposed on a substrate (100) comprising a cell region (20), a cell region separator (22), and a ferri region (24). The second cell structure (C_ST2) may be a structure disposed at the outermost edge of the cell region (20) among the cell structures (C_ST1, C_ST2).

[0183] The first semiconductor material film (121) can cover the first cell structure (C_ST1), the second cell structure (C_ST2), and the ferri structure (PR_ST).

[0184] If the thickness (t1) of the first semiconductor material film (121) does not satisfy the relationship 1 described above, the intensity of the laser energy absorbed by the first semiconductor material film (121) may be equal to (1) of FIG. 23.

[0185] If the laser annealing process (60) is performed while the thickness (t1) of the first semiconductor material film (121) does not satisfy Equation 1, excess heat may be generated near the cell region separator (22). The heat generated by the laser annealing process (60) may flow to the cell region (20) that forms a boundary with the cell region separator (22). That is, heat flow may occur from the periregion (24) to the cell region (20) within the first semiconductor material film (121). In this way, heat flow may affect the bit line contact (146), etc., formed of the semiconductor material near the boundary of the cell region (20). That is, a defect may occur between the bit line contact (146) placed near the boundary of the cell region (20) and the normal cell conduction line (140N).

[0186] When the thickness (t1) of the first semiconductor material film (121) satisfies the relationship 1 described above, the intensity of the laser energy absorbed by the first semiconductor material film (121) may be equal to (2) of FIG. 23.

[0187] If the laser annealing process (60) is performed when the thickness (t1) of the first semiconductor material film (121) does not satisfy Equation 1, excess heat may not be generated near the cell region separator (22).

[0188] FIGS. 24 to 27 are drawings illustrating the effect of the arrangement of structures on a substrate on the intensity of laser energy absorbed by a semiconductor material film.

[0189] In FIGS. 24 to 27, a first cell structure (C_ST1), a second cell structure (C_ST2), and a ferri structure (PR_ST) may be disposed on a substrate (100).

[0190] The first cell structure (C_ST1) may have a fourth width (W31). The second cell structure (C_ST2) may have a fifth width (W32). The cell structures (C_ST1, C_ST2) may include one second cell structure (C_ST2) and at least one first cell structure (C_ST1).

[0191] The first cell structure (C_ST1) may correspond to the inner dummy cell conduction line (140DB) and the normal cell conduction line (140N) described in FIGS. 1 to 14. The second cell structure (C_ST2) may correspond to the first outermost dummy cell conduction line (140DA).

[0192] FIGS. 25 and FIGS. 27 are graphs showing the intensity of laser energy absorbed by the first semiconductor material film (121) on the cell region (20) by the laser annealing process (60). FIG. 25 is a graph showing the intensity of laser energy absorbed by the first semiconductor material film (121) when a cell structure (C_ST1, C_ST2) as in FIG. 24 is arranged. FIG. 27 is a graph showing the intensity of laser energy absorbed by the first semiconductor material film (121) when a cell structure (C_ST1, C_ST2) as in FIG. 26 is arranged.

[0193] In FIGS. 25 and 27, the cell region (20) may include a dummy cell region (20_DCR) and a normal cell region (20_NCR). The intensity of the laser energy absorbed by the first semiconductor material film (121) on the cell region (20) may be located between the upper limit of the absorbed energy (UL) and the lower limit of the absorbed energy (LL).

[0194] In FIG. 24, the ratio (W32 / W31) of the width (W31) of the first cell structure (C_ST1) to the width (W32) of the second cell structure (C_ST2) is greater than the ratio (W32 / W31) of the width (W31) of the first cell structure (C_ST1) to the width (W32) of the second cell structure (C_ST2) in FIG. 26. In FIG. 26, the ratio (W32 / W31) of the width (W31) of the first cell structure (C_ST1) to the width (W32) of the second cell structure (C_ST2) may be greater than or equal to 1.

[0195] In the normal cell region (20_NCR) of FIG. 25, the difference between the maximum and minimum values ​​of the laser energy intensity absorbed by the first semiconductor material film (121) may be the first energy gap (GAP1). In the normal cell region (20_NCR) of FIG. 27, the difference between the maximum and minimum values ​​of the laser energy intensity absorbed by the first semiconductor material film (121) may be the second energy gap (GAP2).

[0196] The second energy gap (GAP2) in the normal cell region (20_NCR) of FIG. 27 is smaller than the first energy gap (GAP1) in the normal cell region (20_NCR) of FIG. 25. In other words, as the ratio (W32 / W31) of the width (W31) of the second cell structure (C_ST2) to the width (W32) of the first cell structure (C_ST1) decreases, the energy gap in the normal cell region (20_NCR) can be reduced.

[0197] If the process conditions of the laser annealing process (60) fluctuate, the likelihood that the intensity of the laser energy absorbed by the first semiconductor material film (121) will exceed the upper limit (UL) or lower limit (LL) of the absorbed energy is higher in the case of FIG. 25 than in the case of FIG. 27. That is, by reducing the ratio (W32 / W31) of the width (W31) of the first cell structure (C_ST1) to the width (W32) of the second cell structure (C_ST2), the stability and reliability of the manufacturing process can be improved.

[0198] The ratio (W32 / W31) of the width (W32) of the second cell structure (C_ST2) to the width (W31) of the first cell structure (C_ST1) may be greater than or equal to 1 and less than or equal to 2. Preferably, the ratio (W32 / W31) of the width (W32) of the second cell structure (C_ST2) to the width (W31) of the first cell structure (C_ST1) may be greater than or equal to 1 and less than or equal to 1.7. More preferably, the ratio (W32 / W31) of the width (W32) of the second cell structure (C_ST2) to the width (W31) of the first cell structure (C_ST1) may be greater than or equal to 1 and less than or equal to 1.5.

[0199] FIGS. 28 to 32 are intermediate step drawings for explaining a method for manufacturing a semiconductor memory device according to some embodiments. FIG. 33 is a drawing showing the reflectance of a laser according to the thickness of an anti-reflective film.

[0200] For reference, FIGS. 28 to 30 may be manufacturing processes carried out after FIGS. 15 to 17.

[0201] Referring to FIGS. 1 to 9 and FIGS. 28 to 30, an anti-reflection film (70) can be formed on the first semiconductor material film (121).

[0202] The anti-reflection film (70) may be formed of an insulating material. The anti-reflection film (70) may be made of a single film, for example. The refractive index of the anti-reflection film (70) is smaller than the refractive index of the first semiconductor material film (121). The anti-reflection film (70) may include, for example, silicon oxide, but is not limited thereto.

[0203] The thickness (t2) of the anti-reflection film (70) can satisfy the second relationship.

[0204] (Relationship 2)

[0205] In relation 2, t oxt2 may be the thickness of the anti-reflective film (70). λ is the wavelength of the laser used in the laser annealing process (60 in FIG. 31), and n ox is the refractive index of the anti-reflection film (70). If the anti-reflection film (70) includes silicon oxide, n ox can be the refractive index of silicon oxide.

[0206] In FIG. 33, as the thickness of the anti-reflection film increases, the reflectivity of the laser decreases and then increases. In other words, as the thickness of the anti-reflection film increases, the intensity of the laser energy absorbed by the first semiconductor material film (121) increases and then decreases.

[0207] When a specific reflectance (Rc) required for the manufacturing process is determined, the thickness (t2) of the anti-reflection film (70) is t 2a and t 2b It can be determined as such. The specific reflectance (Rc) may vary depending on the amount of energy required for the recrystallization of the first semiconductor material film (121).

[0208] In FIG. 28, the anti-reflection film (70) can be formed on the cell region (20), the cell region separator (22), and the ferri region (24). That is, the anti-reflection film (70) can be formed entirely on the substrate (100).

[0209] In FIG. 29, the anti-reflection film (70) may be formed on the cell region (20). The anti-reflection film (70) may overlap with the cell region (20) in a fourth direction (D4). The anti-reflection film (70) may overlap with at least a portion of the cell region separator (22) in a fourth direction (D4). The anti-reflection film (70) may not overlap with the periphery region (24) in a fourth direction (D4). Unlike what is illustrated, in one example, the anti-reflection film (70) may not overlap with the cell region separator (22) in a fourth direction (D4). In another example, the anti-reflection film (70) may not overlap with a portion of the cell region (20) in a fourth direction (D4). In yet another example, at least a portion of the periphery region (24) does not overlap with the anti-reflection film (70) in a fourth direction (D4). A portion of the periphery area (24) does not overlap with the anti-reflection film (70) in the fourth direction (D4), and the remainder of the periphery area (24) may overlap with the anti-reflection film (70) in the fourth direction (D4).

[0210] The following explanation is explained using Fig. 28.

[0211] Referring to FIGS. 31 and 32, a laser can be irradiated onto a first semiconductor material film (121) on which a reflection-preventing film (70) is formed. A laser annealing process (60) using the reflection-preventing film (70) can be performed.

[0212] Through a laser annealing process (60), the first semiconductor material film (121) is recrystallized so that the second semiconductor material film (122) can be formed on the substrate (100).

[0213] Although not shown, a first air gap (AG_BC in FIG. 10) may be formed within the second semiconductor material film (122). Alternatively, a second air gap (AG_DC in FIG. 11) may be formed between the cell conduction lines (140N, 140DA, 140DB) and the bit line contact (146).

[0214] Next, the anti-reflection film (70) on the second semiconductor material film (122) can be removed. Next, the second semiconductor material film (122) can be patterned to form a storage contact (120) on the substrate (100) of the cell region (20).

[0215] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0216] 110: Gate structure 120: Storage contact (BC) 146: Bit line contact 190: Information storage element 140N, 140DA, 140DB: Cell conduction lines

Claims

Claim 1 A semiconductor memory device comprising: a substrate including a cell region comprising a dummy cell region and a normal cell region, and a periphery region defined around the cell region, wherein the cell region comprises an active region defined by a cell element separator; a cell region separator within the substrate defining the cell region; a normal bit line disposed in the normal cell region and extending in a first direction; a dummy bit line group comprising a plurality of dummy bit lines disposed in the dummy cell region and extending in the first direction; and a plurality of storage contacts connected to the active region and disposed along a second direction perpendicular to the first direction, wherein the dummy cell region forms a boundary with the cell region separator between the normal cell region and the cell region separator, the width of the dummy cell region in the second direction is greater than or equal to 50 nm and less than or equal to 200 nm, the normal bit line has a first width in the second direction, and the ratio of the width of each dummy bit line in the second direction to the first width is greater than or equal to 1 and less than or equal to 2. Claim 2 A semiconductor memory device according to claim 1, wherein the dummy bit line group comprises a first dummy bit line closest to the periphery region and the second direction, and a second dummy bit line between the first dummy bit line and the normal bit line, wherein the first dummy bit line has a second width in the second direction, and the second dummy bit line has a third width in the second direction, and the second width is greater than or equal to the third width. Claim 3 A semiconductor memory device according to claim 1, wherein the first width is greater than or equal to 5 nm and less than or equal to 25 nm. Claim 4 A semiconductor memory device according to claim 3, wherein the width of the dummy bit line in the second direction is less than or equal to 30 nm. Claim 5 A semiconductor memory device according to claim 1, wherein the number of dummy bit lines included in the dummy bit line group is 2 or more and 6 or less. Claim 6 A substrate comprising a cell region including a dummy cell region and a normal cell region, and a periregion defined around the cell region, wherein the cell region comprises an active region defined by a cell device isolation film; a cell region isolation film defining the cell region within the substrate; a normal bit line group disposed in the normal cell region; and a dummy bit line group disposed in the dummy cell region and comprising a plurality of dummy bit lines extended in a first direction. A semiconductor memory device comprising a plurality of storage contacts connected to the active region and arranged along a second direction perpendicular to the first direction, wherein the dummy cell region is bounded by the cell region separator between the normal cell region and the cell region separator, the normal bit line group extends in the first direction and includes a plurality of normal bit lines arranged in the second direction at bit line pitch intervals, the width of the dummy cell region in the second direction is greater than the bit line pitch and less than or equal to five times the bit line pitch, each of the normal bit lines has a first width in the second direction, and the ratio of the width of each of the dummy bit lines in the second direction to the first width is greater than or equal to 1 and less than or equal to 2. Claim 7 A semiconductor memory device according to claim 6, wherein the dummy bit line group comprises a first dummy bit line closest to the ferri region and the second direction, and a second dummy bit line between the first dummy bit line and the normal bit line, wherein the width of the first dummy bit line in the second direction is a second width greater than the first width, and the width of the second dummy bit line in the second direction is the same as the first width. Claim 8 A semiconductor memory device according to claim 6, wherein the width of each of the above-mentioned dummy bit lines in the second direction is the same as the first width. Claim 9 A semiconductor memory device comprising: a substrate including a cell region comprising a dummy cell region and a normal cell region, and a periphery region defined around the cell region, wherein the cell region comprises an active region defined by a cell element separator; a cell region separator within the substrate defining the cell region; a normal bit line disposed in the normal cell region and extending in a first direction; a dummy bit line group comprising a plurality of dummy bit lines disposed in the dummy cell region and extending in the first direction; and a plurality of storage contacts connected to the active region and disposed along a second direction perpendicular to the first direction, wherein the dummy cell region forms a boundary with the cell region separator between the normal cell region and the cell region separator, the width of the dummy cell region in the second direction is greater than or equal to 50 nm and less than or equal to 200 nm, the width of the normal bit line in the second direction is greater than or equal to 5 nm and less than or equal to 25 nm, and the width of the dummy bit line in the second direction is greater than or equal to 5 nm and less than or equal to 30 nm. Claim 10 A cell region separator separating a cell region and a periphery region is formed within a substrate, and a cell device separator separator defining an active region within the cell region is formed; a plurality of bit lines are formed extending in a first direction and disposed on the cell region, each bit line is spaced apart in a second direction perpendicular to the first direction, and a periphery structure is formed on the periphery region; a first semiconductor material film covering the plurality of bit lines and the periphery structure is formed on the substrate; the first semiconductor material film is recrystallized through a laser annealing process using a laser to form a second semiconductor material film; and the second semiconductor material film is patterned to form a storage contact connected to the active region, wherein the thickness (t) of the first semiconductor material film a-Si ) is the distance from the upper surface of the ferri structure to the upper surface of the first semiconductor material film, and the thickness (t) of the first semiconductor material film a-Si ) is a method for manufacturing a semiconductor memory device satisfying the first relationship: (Relationship 1) Here, λ is the wavelength of the laser, and n a-Si is the refractive index of the first semiconductor material film, N is one of 1, 2, or 3, Δ is an optical path correction factor, and is greater than or equal to -1 / 8 and less than or equal to 1 / 8.

Images