Void-free stress integration in semiconductor devices

Abstract

The present invention includes semiconductor devices having improved stress in a channel region. The semiconductor device comprises a substrate, a source region, a drain region, a channel region including at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion interrupt, and the second gate region includes a first gate surrounding the channel between the source region and the drain region. The self-aligned single diffusion interrupt also includes a dielectric liner and a stressed metal filler, wherein the stressed metal filler exhibits a stress of about 350 MPa or more.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] The present application claims priority to and seeks the interest of U.S. Patent Application No. 63 / 487,507, filed on February 28, 2023, under the title "VOID-FREE STRESS INCORPORATION IN SEMICONDUCTOR DEVICES," the entirety of which is incorporated herein by reference.

[0003] The present invention relates to methods for semiconductor processing. More specifically, the present invention relates to methods for incorporating increased stress into doped regions of semiconductor devices. Background Technology

[0004] Integrated circuits have evolved into complex devices capable of containing millions of transistors, capacitors, and resistors on a single chip. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size has decreased. Transistors are circuit components or elements often formed on semiconductor devices. Depending on the circuit design, many transistors can be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Integrated circuits include field-effect transistors (FETs), in which current flows through an inverted conductive channel between the source and drain in response to a voltage applied to a control gate.

[0005] Integrated circuits are made possible by processes that create complexly patterned material layers on substrate surfaces. Creating patterned materials on a substrate requires controlled methods for forming and removing the material. As device sizes continue to decrease, film properties can lead to greater impacts on device performance. As devices shrink and more complex patterning schemes are utilized in the industry, the deposition of thin films has become a challenge. Furthermore, as material thicknesses continue to decrease, the as-deposited properties of films can have a greater impact on device performance. These challenges include depositing void-free and stressed films.

[0006] Accordingly, there is a need for high-quality devices and structures with improved mobility, and methods for making such devices. These and other needs are addressed by the present technology. The present technology includes electronic devices having one or more self-aligned single diffusion breaks and methods for forming such electronic devices. Such electronic devices may include semiconductor transistors, such as n-channel and p-channel MOSFETs, FinFETs, gate-all-around FETs, and nanosheet FETs among other types of transistors, as well as products having such channel regions. In conventional process methods, the stress level within the transistor channel can be controlled by changing the composition of the semiconductor materials of the channel as well as the composition of the materials of adjacent source and drain regions. In many cases, changes to the composition of such doped regions of the transistor to provide the desired amount of stress in the channel region may lead to less desirable transistor performance in other aspects, such as a lower thermal budget and / or increased resistance at the interface between the contact and the doped region. Controlling channel region stress by altering the composition of doped regions also limits the types of materials that can be used in the doped regions. For example, modern PMOS transistors often use silicon-germanium (SiGe) semiconductors doped in the doped regions of the transistor. When the Ge-to-Si ratio becomes too high, lattice mismatches cause disturbances in the material that reduce channel region stress to below an acceptable level. Another conventional method for increasing stress within the channel region of a transistor is to deposit a stress-applied conductive material in a contact trench over the channel region. Stress from the conductive material is transferred downward, imparting the desired stress to the doped material in the channel region.These conventional methods require the careful selection and deposition of conductive materials within the contact trench to meet not only stress requirements but also electrical conductivity, chemical reactivity, airtightness, thermal budget, and other material requirements. In many cases, trade-offs must be made in selecting conductive materials that possess characteristics that are not ideal in some aspects to satisfy stress requirements. Changes in the deposition method or composition of the stress-applied material to generate additional stress can degrade the material's performance in other aspects, such as electrical conductivity. Nevertheless, conventional methods have proven increasingly inefficient as gate and channel surface orientations become more complex. That is, gate orientations of multi-channel semiconducting nanostructures, such as gate-all-around, complementary FETs, nanosheets, and nanowire orientations, are just a few examples that hinder the effectiveness of conventional stress applications. For instance, conventional methods for increasing stress can apply appropriate stress at the top and / or bottom gates, but fail to provide the necessary stress on the gates placed between them. Furthermore, due to at least partially poor stress consistency in addition to adverse surface orientations, multi-channel semiconducting nanostructures also exhibit adverse hole and / or electron mobility. Such hole mobility deficiencies are particularly evident when compared to traditional gate and preferred channel orientations, such as in fin field-effect transistors (FinFETs). Efforts to improve channel strain in multi-channel semiconducting nanostructures involve, in particular, source and drain regions formed through epitaxial growth processes. However, due to complex geometries and surface orientations, epitaxial merging consistently suffers from dislocations during and after formation.Such dislocations can not only pull the epitaxially grown material away from the gates but also create dislocation seams, leading to the relaxation of channel stress over time. This has proven to be a particular problem for hole mobility, for example, in p-type metal-oxide-semiconductor (PMOS) regions. Methods have attempted to improve epitaxial merged defects as a way to impart consistent channel stress. However, none of the existing methods have proven sufficient for providing consistent stress, improving electron and hole mobility, or a combination thereof.

[0007] Embodiments of the present invention include semiconductor devices having improved stress in a channel region. Embodiments of the semiconductor device include a substrate, a source region, a drain region, a channel region comprising at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break of the p-MOS region, and the second gate region includes a first gate surrounding the channel between the source region and the drain region. The self-aligned single diffusion break also includes a dielectric liner and a stressed metal fill, wherein the stressed metal fill exhibits a compressive stress of about 350 MPa or more.

[0008] In the embodiments, the channel region has a compressive stress of about 250 MPa or more. In additional embodiments, the semiconductor device also includes a third gate region, a second gate region disposed between the first gate region and the third gate region, and the third gate region includes a second self-aligned single diffusion interruption. Additional embodiments include cases where the stressed metal filler is selected from aluminum and aluminum-containing materials, tungsten and tungsten-containing materials, copper and copper-containing materials, titanium and titanium-containing materials, tantalum and tantalum-containing materials, nickel and nickel-containing materials, cobalt and cobalt-containing materials, ruthenium and ruthenium-containing materials, molybdenum and molybdenum-containing materials, metals having a Pilling-Bedworth ratio of about 1.5 or more, oxides thereof, or combinations thereof. In additional embodiments, the dielectric material liner has a thickness of about 1 nm to about 6 nm. The embodiments include cases where the channel region comprises a plurality of horizontally extending channels. In the embodiments, the semiconductor device is a nanosheet field-effect transistor or a complementary field-effect transistor. In additional embodiments, the semiconductor device is a gate-all-around complementary metal oxide semiconductor.

[0009] Embodiments include a second gate region having a tensile-stressed metal filler having a compressive stress of about 350 MPa or more. In additional embodiments, a third gate region includes a dielectric liner and a compressive-stressed metal filler having a compressive stress of about 350 MPa or more. In additional embodiments, a third gate region includes a dielectric liner and a tensile-stressed metal filler. In additional embodiments, the self-aligned diffusion rupture defines the volume, and the stressed metal filler and dielectric liner occupy about 95 vol.% or more of the volume. In embodiments, the stressed metal filler generally has no voids or seams. Embodiments include a case where the stressed metal filler and dielectric liner occupy about 99 vol.% or more of the volume of the self-aligned diffusion rupture. In additional embodiments, the stressed metal filler has a compressive stress of about 500 MPa or more, the channel region is a p-channel metal oxide semiconductor, and the channel region has a compressive stress of about 350 MPa or more.

[0010] Embodiments of the present invention also include a semiconductor processing system. The semiconductor processing system includes a first processing chamber; a second processing chamber; a third processing chamber; and a system controller. In the embodiments, the system controller is configured to pattern a substrate in the first processing chamber, etch a shallow trench isolation in a first gate region of a semiconductor device in the second processing chamber—the first gate region is a p-MOS region—line the shallow trench isolation with a dielectric liner in the third processing chamber, and fill the shallow trench isolation with a metallic material configured to provide a compressive stress of at least about 350 MPa.

[0011] Embodiments of the present invention also include a method for forming a semiconductor device having improved stress in a channel region. The method includes the step of etching a shallow trench isolation in a first gate region of the semiconductor device. The semiconductor device includes a substrate, a source region, a drain region, a channel region comprising at least one channel located between the source and the drain, a first gate region, and a second gate region. The second gate region includes a first gate that encloses the channel between the source region and the drain region. The method includes the step of lining the shallow trench isolation with a dielectric liner. The method also includes the step of filling the lined shallow trench isolation with a metal filler configured to provide a stress of at least about 350 MPa.

[0012] In the embodiments, the semiconductor device exhibits a first stress amount in the channel region prior to etching and charging, and a second stress amount in the channel region after etching and charging, and the percentage change from the first stress amount to the second stress amount is about 10% or more. In additional embodiments, the semiconductor device includes a third gate region, and the second gate region is disposed between the first gate region and the third gate region. The embodiments include cases where the third gate region is etched during the etching of the first gate region, or where the third gate region is masked during the etching of the first gate region and undergoes patterning and etching after the first gate region is etched, so that a second shallow trench isolation is formed in the third gate region. In further additional embodiments, the shallow trench isolation is filled with a metal filler subjected to compressive stress, and the second shallow trench isolation is filled with a metal filler subjected to compressive stress or a metal filler subjected to tensile stress. In the embodiments, the filled metal has naturally occurring compressive stress or is oxidized after charging. In additional embodiments, the method further includes the step of annealing the semiconductor device after charging.

[0013] Such technology can provide many advantages over conventional techniques. For example, embodiments of the present technology generate desired levels of stress in the channel region of a semiconductor transistor without altering the composition of adjacent source and drain regions. Furthermore, the present technology generates channel region stress from existing diffusion breaks, thereby allowing more compact devices to be formed with improved stress. Thus, the present technology can provide improved stress without requiring additional channels or diffusion breaks of increased size. These and other embodiments, along with many advantages and features of the embodiments, are described in more detail below and with the accompanying drawings. Brief explanation of the drawing

[0014] Further understanding of the attributes and advantages of the disclosed technology can be realized by referring to the remainder of this specification and the drawings. FIG. 1 illustrates an upper plan view of an exemplary processing chamber according to some embodiments of the present technology. FIG. 2 illustrates selected operations in a forming method according to some embodiments of the present technology. FIGS. 3a through 3e illustrate cross-sectional views of exemplary semiconductor structures according to some embodiments of the present technology. FIG. 4 illustrates a cross-sectional view of exemplary semiconductor structures according to some embodiments of the present technology. FIG. 5 illustrates selected operations in a forming method according to some embodiments of the present technology. Some of the drawings are included as schematics. It should be understood that the drawings are for illustrative purposes only and should not be considered to be of actual scale unless specifically stated otherwise. Additionally, as schematics, the drawings are provided for illustrative purposes and may not include all aspects or information compared to realistic representations, and may include exaggerated data for illustrative purposes. In the attached drawings, similar components and / or features may have the same reference label. Additionally, various components of the same type may be distinguished by a character following the reference label that distinguishes between similar components. Where only the first reference label is used in this specification, the description is applicable to any component among similar components having the same first reference label, regardless of the character. Specific details for implementing the invention

[0015] The present invention includes electronic devices having one or more self-aligned single diffusion breaks and methods for forming such electronic devices. Such electronic devices may include semiconductor transistors, such as n-channel and p-channel MOSFETs, FinFETs, gate-all-around FETs, and nanosheet FETs, among other types of transistors, as well as products having such channel regions. In conventional process methods, the stress level within the transistor channel can be controlled by changing the composition of the semiconductor materials of the channel as well as the composition of the materials of the adjacent source and drain regions. In many cases, changes to the composition of such doped regions of the transistor to provide the desired amount of stress in the channel region may lead to less desirable transistor performance in other aspects, such as a lower thermal budget and / or increased resistance at the interface between the contact and the doped region. Controlling channel region stress by changing the composition of the doped regions also limits the types of materials that can be used in the doped regions. For example, modern PMOS transistors often use silicon-germanium (SiGe) semiconductors doped in the doped regions of the transistor. When the Ge-to-Si ratio becomes too high, lattice mismatches cause disturbances in the material that reduce channel region stress to below an acceptable level.

[0016] Another conventional method for increasing stress within the channel region of a transistor is to deposit a stress-applied conductive material in a contact trench above the channel region. Stress from the conductive material is transferred downward, imparting the desired stress to the doped material in the channel region. These conventional methods require the careful selection and deposition of the conductive material within the contact trench to satisfy not only stress requirements but also electrical conductivity, chemical reactivity, airtightness, thermal budget, and other material requirements. In many cases, there must be a trade-off in selecting a conductive material that has characteristics that are not ideal in some aspects to satisfy stress requirements. Changes in the deposition method or composition of the stress-applied material to generate additional stress can degrade the material's performance in other aspects, such as electrical conductivity.

[0017] Nevertheless, conventional methods have proven increasingly inefficient as gate and channel surface orientations become more complex. Specifically, gate orientations of multi-channel semiconducting nanostructures, such as gate-all-around, complementary FETs, nanosheets, and nanowire orientations, hinder the effectiveness of conventional stress applications, just to name a few. For instance, conventional methods for increasing stress can apply appropriate stress at the top and / or bottom gates, but fail to provide the necessary stress on the gates positioned between them. Furthermore, due to poor stress consistency—at least partially in addition to unfavorable surface orientations—multi-channel semiconducting nanostructures also exhibit poor hole and / or electron mobility. Such hole mobility deficiencies are particularly evident when compared to traditional gate and preferred channel orientations, such as those found in fin field-effect transistors (FinFETs).

[0018] Efforts to improve channel strain in multi-channel semiconducting nanostructures involve, in particular, source and drain regions formed through epitaxial growth processes. However, due to complex geometries and surface orientations, epitaxial merging consistently suffers from dislocations during and after formation. Such dislocations can not only pull the epitaxially grown material away from the gates but also create dislocation seams, leading to the relaxation of channel stress over time. This has proven to be particularly problematic for hole mobility, for example, in p-type metal-oxide-semiconductor (PMOS) regions. Methods have attempted to mitigate epitaxial merging defects as a means to impart consistent channel stress. However, none of the existing methods have proven sufficient for providing consistent stress, improving electron and hole mobility, or a combination thereof.

[0019] The present technology overcomes these challenges by providing consistently stressed channels with improved hole and / or electron mobility. By utilizing one or more self-aligned single diffusion breaks having a thin dielectric stressor film filled with a void-free metal, the desired stress can be provided to the stressed channel regions. Furthermore, by utilizing a unique combination of the thin dielectric film and the metal filler, the formation of voids in the self-aligned diffusion breaks can be avoided without requiring additional processing of the filled material. In embodiments of the present technology, stresses may be derived by depositing a stressed material in one or more self-aligned single diffusion breaks adjacent to one or more doped regions of the transistor, such as the channel region. The stressed material can initially apply stress to one or more self-aligned single diffusion breaks, and those one or more self-aligned single diffusion breaks can, in turn, transfer a portion of the stress to the channel region of the transistor.

[0020] While the remainder of the disclosure will conventionally identify specific metal oxide semiconductor field-effect transistors (MOSFETs), complementary metal oxide semiconductors (CMOS), and their components, it will be readily understood that these devices and methods are equally applicable to other field-effect transistors and their orientations as processes for forming such devices. Accordingly, the present technology should not be construed as being limited to use for these specific devices or methods alone. Before additional variations and adjustments to such devices according to embodiments of the present technology are described, the present disclosure will discuss one possible semiconductor device comprising one or more components utilizing one or more self-aligned single diffusion breaks according to embodiments of the present technology.

[0021] FIG. 1 illustrates a top plan view of a multi-chamber processing system (100) that may be configured to implement aspects or operations according to some embodiments of the present invention, specifically. The multi-chamber processing system (100) may be configured to perform one or more manufacturing processes on individual substrates, such as any number of semiconductor substrates, to form semiconductor devices. The multi-chamber processing system (100) may include some or all of a transfer chamber (106), a buffer chamber (108), single wafer load locks (110 and 112) (however, dual load locks may also be included), processing chambers (114, 116, 118, 120, 122, and 124), preheating chambers (123 and 125), and robots (126 and 128). Single wafer load locks (110 and 112) may include heating elements (113) and may be attached to a buffer chamber (108). Processing chambers (114, 116, 118, and 120) may be attached to a transfer chamber (106). Processing chambers (122 and 124) may be attached to a buffer chamber (108). Two substrate transfer platforms (102 and 104) may be placed between the transfer chamber (106) and the buffer chamber (108) to facilitate transfer between robots (126 and 128). The platforms (102, 104) may be open to the transfer chamber and the buffer chamber, or the platforms may be optionally isolated or sealed from the chambers to allow different operating pressures to be maintained between the transfer chamber (106) and the buffer chamber (108). The transfer platforms (102 and 104) may each include one or more tools (105) for, for example, orientation or measurement operations.

[0022] The operation of the multi-chamber processing system (100) may be controlled by a computer system (130). The computer system (130) may include any device or combination of devices configured to implement the operations described below. Accordingly, the computer system (130) may be a controller or array of controllers, and / or a general-purpose computer, composed of software stored on a non-transient computer-readable medium capable of performing the operations described in relation to the methods according to embodiments of the present invention when executed. Each of the processing chambers (114, 116, 118, 120, 122, and 124) may be configured to perform one or more process steps in the manufacture of a semiconductor structure. More specifically, the processing chambers (114, 116, 118, 120, 122, and 124) may be equipped to perform a number of substrate processing operations, including dry etching processes, periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, and orientation, among any number of other substrate processes.

[0023] FIG. 2 illustrates exemplary operations of a method (200) according to some embodiments of the present invention. The method may be performed in various processing chambers including the processing chamber (100) described above. The method (200) may include a number of optional operations that may or may not be specifically associated with some embodiments of methods according to the present invention. For example, many of the operations are described to provide a wider range of structural formations, but may be performed by alternative methodologies that are not critical to the art or are easily recognizable.

[0024] The method (200) may include additional operations prior to the initiation of the enumerated operations. For example, additional processing operations may include forming structures on a semiconductor substrate, which may include both forming and removing materials. The prior processing operations may be performed in a chamber where the method (200) can be performed, or the processing may be performed in one or more other processing chambers before the substrate is transferred into the semiconductor processing chamber where the method (200) can be performed. Regardless thereof, the method (200) may optionally include the step of transferring a semiconductor substrate to a processing zone of a semiconductor processing chamber, such as the processing chamber (100) described above, or other chambers that may include components as described above. The substrate may be deposited on a substrate support / transfer platform, which may be a pedestal such as the substrate support (104) and may reside in a processing zone of the chamber, such as the processing zone (120) described above. The method (200) describes operations schematically illustrated in FIGS. 3a through 3e, and examples thereof will be described together with operations of the method (200). FIGS. 3a through 3e illustrate only partial schematic diagrams, and it should be understood that the semiconductor substrate may include additional components as illustrated in the drawings, as well as alternative components of any size or configuration that can still benefit from aspects of the present technology.

[0025] The method (200) may or may not involve any operations for developing a semiconductor structure for a specific manufacturing operation. It should be understood that the method (200) may be performed on any number of semiconductor structures (300) or substrates (302), including exemplary structures on which a selectively deposited material may be formed, as illustrated in FIG. 3a through 3e. As illustrated in FIG. 3a, the substrate (302) may have a plurality of material layers deposited to be placed on the substrate. The substrate (302) may be any number of materials, such as silicon or silicon-containing materials, germanium, other substrate materials, as well as a base wafer or substrate made of one or more materials that may be formed to be placed on the substrate during semiconductor processing.

[0026] The structure (300) may illustrate a partial view of a substrate, which, in the embodiments, may be used in n-channel and p-channel MOSFETs, FinFETs, gate-all-around FETs, complementary metal-oxide semiconductors, and nanosheet FETs, among other types of semiconductor transistor structures. The material layers may be produced by any number of methods including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (TECVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or any other forming technique. In the embodiments, plasma-enhanced chemical vapor deposition may be performed in a processing chamber, such as the previously described processing chamber (100). The substrate layers may include silicon oxide and silicon nitride, silicon oxide and silicon, silicon nitride and silicon, silicon and doped silicon, or any number of other materials.

[0027] As illustrated in FIG. 3a, a structure (300) comprising a substrate (302) that has already undergone source / drain (304) formation is provided. In the embodiments, the source / drain (304) formation may involve the epitaxial growth of a doped silicon material, such as a silicon-germanium material. However, since the present technology does not require strict source / drain (304) formation (e.g., attempts to resolve epitaxial growth defects) to maintain hole or electron mobility, it should be understood that the source / drain region (304) can be formed from any suitable deposition and patterning process. Furthermore, the structure (300) comprises a plurality of gate regions (306) and interlayer dielectric / dummy gate regions (308), which can be formed as known in the art and discussed above.

[0028] In the embodiments, the structure (300) may be a bulk semiconductor substrate. As used herein, the term “bulk semiconductor substrate” refers to a substrate in which the entire substrate is composed of a semiconductor material. The bulk semiconductor substrate may include any suitable semiconducting material and / or combinations of semiconducting materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> It may comprise one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconducting materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate (300) comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate (300) comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While some examples of materials capable of forming a substrate are described herein, any material capable of serving as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed falls within the spirit and scope of this disclosure.

[0029] In the embodiments, the semiconductor material may be a doped material, such as n-doped silicon (n-Si) or p-doped silicon (p-Si). In the embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term “n-type” refers to semiconductors produced by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term n-type is derived from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers, and holes are minority carriers. As used herein, the term “p-type” refers to the positive charge of the well (or hole). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers, and electrons are minority carriers. As discussed above, in the embodiments, the present technology can provide improved mobility in both p-type and n-type semiconductors. However, in the embodiments, p-type semiconductors can experience improved hole mobility.

[0030] Nevertheless, in operation (201), the method (200) may include the step of patterning one or more mask layers (310) deposited on a substrate (302) on the upper surface of the source / drain regions (304) and a portion of the gate regions (306). For example, in the embodiments, the substrate (302) may be loaded into a load lock (110, 112) and transferred via robots (126, 128) to a process chamber (e.g., process chamber (114)) where the mask deposition process is performed. That is, as illustrated, one or more mask layers (310) are patterned on five of the seven illustrated gate regions (306), leaving two gate regions (306) exposed. However, as will be discussed in more detail below, it should be understood that the patterned mask layers (310) may be placed over one or more gate zones (306) or spaced apart at intervals as necessary to provide the required stress on the channel zones (316) (more clearly illustrated in FIG. 4).

[0031] As illustrated in FIG. 3b, in operation (202), the method (200) may include the step of etching the structure (300). In embodiments, such operation may include transferring the substrate (302) to a second process chamber (116) configured for etching processes. For example, in one embodiment, one or more of inductively coupled plasma (ICP) etching, reactive ion etching (RIE), or capacitively coupled plasma (CCP) etching are used to form shallow trench isolations or vias (312). Additionally, as the mask layers (310) are aligned with the gate regions (306), the shallow trench isolations (312) may be formed in the gate regions and self-aligned with them, and accordingly, may be considered as self-aligned shallow trench isolations or self-aligned single diffusion disconnects.

[0032] After etching the structure (300) in operation (202), the method (200) may optionally undergo passivation and / or oxidation after the removal of the mask layer(s) (310). Nevertheless, the etched substrate (302) may be transferred to a third process chamber (118) configured for deposition and / or filling processes, including chambers for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), plasma enhanced atomic layer deposition (PEALD), etc. For example, in operation (203), in such a process chamber (118), a dielectric film liner (328) is formed along the outer perimeter (330) (or outer sidewall) of the self-aligned diffusion interruption (312), as illustrated in FIG. 3C.

[0033] In operation (203), after the formation of the dielectric film liner in the self-aligned diffusion rupture (312), the method (200) may include a filling operation (204) of filling the self-aligned diffusion rupture (312) with metal (314). The filling operation (204) may occur in the same deposition chamber (218), or the substrate (302) may be transferred to an additional process chamber. In the embodiments, it should be clear that the filling may occur with a stressed metal or may involve a non-stressed metal, and in any case, both may be configured to provide the necessary stress as an inherent characteristic of the metal or a characteristic that may be derived from the metal. For example, when a non-stressed metal is used, such as when a metal with a high Piling-Bedworth ratio is used, an additional oxidation treatment may be utilized to impart the necessary stress to the filled metal. As illustrated, the dielectric membrane liner (328) forms a barrier between the metal filler (314) and the adjacent source-drain zones (304) to extend the metals that can be used to form the stressed filler, because the stressed metals do not come into contact with the adjacent zones.

[0034] Additionally, as illustrated in FIG. 3b, the self-aligned diffusion (312) interruption defines the volume from the upper surface (332) of the structure to the lowest part (334) of the diffusion interruption (312). As will be discussed in more detail below, the dielectric liner (328) and the stressed metal (314) occupy most or all of the volume defined by the self-aligned diffusion interruption. That is, as mentioned above, the present technology has discovered that by utilizing a thin liner in combination with the stressed metal, joints or voids may be formed in the self-aligned diffusion interruption (312) with little to no gaps during deposition / filling.

[0035] Nevertheless, after the formation of the liner (328) and the stressed metal filler (314), the substrate (302) may be transferred to a fourth process chamber (120), such as a process chamber configured for polishing including chemical mechanical polishing. Accordingly, in operation (205), the method (200) may include the step of polishing the structure (300), such as chemical mechanical polishing of the top surface (332) of the structure (300) (Fig. 3d). An additional drawing of Fig. 3d is illustrated in Fig. 3e, where the interlayer dielectric (308) and gate regions (306) are removed for clarity. Furthermore, Fig. 4 illustrates a cross-sectional view of an exemplary embodiment, such as along the line (A-A') of Fig. 3e. Fig. 4 may more clearly illustrate the source / drain regions (304), gate regions (306), and channel regions (316). As illustrated in the embodiments, the structure (300) may be a horizontal gate-all-around orientation having a plurality of horizontally extending channels (326) in the channel region (316). For example, in the embodiments, the channels (326) may generally be parallel to the top surface (336) of the substrate (302).

[0036] That is, the present invention surprisingly discovered that excellent electron and / or hole mobility can be achieved by utilizing a dielectric material to line the perimeter (330) of self-aligned diffusion interrupt(s) (312) and then filling the dielectric material-lined diffusion interrupt(s) (312) with a stress-applied metal filler (314). This is even true for structures having an avoided channel surface orientation. Furthermore, by utilizing a combination of a stress-applied metal filler and a dielectric material liner in the self-aligned diffusion interrupt(s), the present invention can transfer compressive stress from the stress-applied material to neighboring channel regions without suffering from the difficulties of channel stress relaxation seen in conventional inventions.

[0037] For example, in the present invention, the stress within one or more channel regions (316) (Fig. 3e) (more clearly illustrated in Fig. 4) increases from a first stress amount of lower stress to a second stress amount of higher stress after the deposition and filling discussed herein. In the embodiments, the percentage change in stress in the channel region (316) from the first stress amount to the second stress amount may be about 0.1% or more, e.g., about 1% or more, about 2% or more, about 5% or more, about 10% or more, about 25% or more, about 50% or more, about 75% or more, about 100% or more, or greater than or equal to any range or value between these. In additional embodiments, the first stress amount within the channel region (316) may be about 10 MPa or less, e.g., about 5 MPa or less, about 1 MPa or less, or less than. In additional embodiments, the second stress amount in the channel region (316) may be about 100 MPa or more, e.g., about 200 MPa or more, about 300 MPa or more, about 400 MPa or more, about 500 MPa or more, about 600 MPa or more, or any range or value between these.

[0038] Furthermore, in the embodiments, the present invention has discovered that such stress can be evenly distributed throughout the entire channel section (316). As mentioned above, previous attempts utilized stress-applied materials above and below the channel sections. However, conventional inventions may limit stress improvement to the upper side (318) of the channel section (316) and / or the lower side (320) of the channel section (316). Accordingly, conventional inventions may not provide consistent stress throughout the entire channel. Conversely, in the embodiments, the present invention may have a first channel stress at a first location (322) within the channel section (316) (exemplified merely as being adjacent to, for example, the lower side (320) of the channel section (316), and it should be understood that the first location (322) may be at any location within the channel section (316)) and a second channel stress at a second location (324) within the channel section (316). As illustrated, the first position (322) may be spaced vertically from the second position (424) for exemplary purposes. However, in the embodiments, the zones may be spaced horizontally, or both vertically and horizontally. Nevertheless, the first channel stress may differ from the second channel stress by about 30% or less, e.g., about 27.5% or less, about 25% or less, about 22.5% or less, about 20% or less, about 17.5% or less, less than about 15%, less than about 12.5%, about 10% or less, or any range or value between these.

[0039] Furthermore, as mentioned above, increased stress within the channel region increases the mobility of charge carriers in the channel, which is also thought to increase the driving current through the channel region. Specifically, in embodiments of the present technology, increased stress generated in the channel region can increase the driving current through the transistor channel, such as the p-MOS driving current, by more than about 1%, such as more than about 5%, more than about 10%, more than about 15%, more than about 20%, more than about 25%, more than about 30%, more than about 35%, more than about 40%, more than about 45%, more than about 50%, more than about 55%, or any range or value between these. In the embodiments, increased stress within the channel region may lead to a much larger increase in hole mobility, such as, about 10% or more, about 20% or more, about 30% or more, about 40% or more, about 50% or more, about 60% or more, about 70% or more, about 80% or more, about 90% or more, about 100% or more, about 110% or more, about 120% or more, about 130% or more, about 140% or more, about 150% or more, or any range or value in between. Increases in driving current and hole mobility through the channel region can increase transistor performance in a number of aspects, including but not limited to increased switching speed and / or reduced power consumption. Embodiments of the present technology can achieve these semiconductor device performance improvements without restricting the types of materials used in the devices, which could cause new processing problems or impair device performance in other aspects.

[0040] Nevertheless, the dielectric liner material can be filled into the self-aligned diffusion break(s) (312) using atomic layer deposition, plasma-enhanced atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, among other types of deposition methods. In the embodiments, the dielectric film liner (328) can be characterized by a thickness of about 0.5 nm or more, e.g., about 1 nm or more, about 1.5 nm or more, about 2 nm or more, about 2.5 nm or more, about 3 nm or more, about 3.5 nm or more, about 4 nm or more, about 4.5 nm or more, about 5 nm or more, or greater than that. Additionally, the dielectric film liner (328) can be characterized by a thickness of about 8 nm or less, e.g., about 7 nm or less, about 6 nm or less, about 5 nm or less, about 4.5 nm or less, or less than or any range or value between these. By utilizing dielectric liners within the above ranges, breakdown voltage degradation can be avoided while applying significant stress to the channel region. For example, when the thickness of the dielectric liner is too small (e.g., less than 1 nm, or even 2 nm in the examples), there is a high risk of breakdown voltage degradation due to improper separation of the stressed metal filler from the channel region. Furthermore, as the dielectric liner thickness increases, less stress is transferred from the stressed metal filler to the channel region. Accordingly, it is important to balance a liner that is thick enough to prevent breakdown voltage degradation without losing the desired stress.

[0041] Nevertheless, in the embodiments, the amount of stress in the stressed metal filler and optionally the dielectric liner material may depend on the amount of stress to be imparted to the channel region of the semiconductor device as a result of depositing the stressed material. In the embodiments, this may involve determining the desired amount of stress in one or more channel regions (316). The stressed metal filler may include aluminum and aluminum-containing materials, tungsten and tungsten-containing materials (e.g., tungsten nitride (WN) and tungsten carbide (WC)), copper and copper-containing materials, titanium and titanium-containing materials (titanium nitride (TiN), titanium silicide (TiSi), titanium carbide (TiC), and titanium aluminide (TiAl)), tantalum and tantalum-containing materials (e.g., tantalum nitride (TaN)), nickel and nickel-containing materials (e.g., nickel silicide (NiSi)), cobalt and cobalt-containing materials, ruthenium and ruthenium-containing materials, molybdenum and molybdenum-containing materials, or combinations thereof.

[0042] Additionally or alternatively, metals suitable for use as stress metal fillers include, but are not limited to, metals having a filling-Bedworth ratio of about 1.5 or more, e.g., about 1.75 or more, e.g., about 2 or more, e.g., about 2.25 or more, e.g., about 2.5 or more, or any range or value between these. The filling-Bedworth ratio refers to the ratio of the volume of the base cell of the metal chalcogenide to the volume of the base cell of the corresponding metal-containing film on which the metal chalcogenide is formed. The filling-Bedworth ratio is V chalc / V metal It is defined as, where V is the volume. To determine the Filling-Bedworth ratio of a metallic chalcogenide, V chalc is equal to the product of the molecular mass of the metal chalcogenide and the density of the metal chalcogenide, and V metalIt is equivalent to the product of the density of the metal chalcogenide and the atomic mass of the metal, multiplied by the number of metal atoms per molecule of the metal chalcogenide. Examples of high-filling-Bedworth metal fillers include one or more of Co, Mo, W, Ta, Ti, Ru, Rh, Cu, Fe, Mn, V, Nb, Hf, Zr, Y, Al, Sn, Cr, Os, U, and / or La. That is, as discussed above, when utilizing high-filling-Bedworth non-materials, the metal can be filled in an unstressed form, and subsequently, the unstressed metal oxidizes while contained in the diffusion rupture, causing the volume of the metal to expand and induce the necessary compressive stress in the adjacent channel.

[0043] One or more stressed metal fillers may be filled into a self-aligned diffusion break (312) lined with a dielectric material (328) using void-free and stressed deposition processes as known in the art. For example, chemical vapor deposition (CVD) and ALD deposition of these materials may involve using any suitable precursors. For example, CVD and ALD may be suitable for deposition utilizing any suitable precursor of the stressed metal fillers. As an example, the deposition of a tungsten-containing stressed metal filler, such as tungsten nitride, may involve using a tungsten-containing precursor and a nitrogen-containing precursor. As another example, the deposition of a titanium-containing stressed metal filler may involve using a titanium-containing precursor, such as tetrakis(dimethylamino)titanium (TDMAT) or titanium chloride (TiCl4). The deposition of tantalum-containing stressed metal fillers may include using one or more tantalum-containing precursors, such as pentakis-dimethylamino tantalum (PDMAT) or TaF5. The deposition of cobalt-containing stressed metal fillers may include using one or more cobalt-containing precursors, such as tris(2,2,6,6-tetramethyl-3,5-heptanedionato)cobalt, bis(cyclopentadienyl)cobalt, or dicobalt hexacarbonyl butylacetylene. In the examples, the deposition of the stressed metal filler may include one or more co-reactants, where appropriate.

[0044] Nevertheless, to deposit the stressed metal (314), the deposition of the stressed metal material may occur at a temperature of about 150°C or higher, such as about 200°C or higher, about 250°C or higher, about 300°C or higher, about 350°C or higher, about 400°C or higher, or higher. Additionally, the deposition of the stressed metal material may be performed at a temperature of about 500°C or lower, such as about 450°C or lower, or lower, or any range or value between these.

[0045] Furthermore, in the embodiments, when using, for instance, high-filling Bedworth non-metals, the metal filler may undergo oxidation after deposition. Oxidation of the stressed metal filler can provide the necessary stress or further enhance the stress of the metal filler. That is, oxidizing the metal filler can expand the metal filler and increase the stress within the metal filler. Oxidation of the stressed metal filler can be achieved by utilizing thermal oxidation processes, plasma oxidation processes, etc. Accordingly, in the embodiments, the metal filler may include oxides of the previously discussed metals.

[0046] In the embodiments, the stressed metal filler may be characterized by a stress of about 350 MPa or more, e.g., about 400 MPa or more, 500 MPa or more, about 600 MPa or more, about 700 MPa or more, about 800 MPa or more, about 900 MPa or more, about 1 GPa or more, or greater than, or any range or value between these. For the purposes of this disclosure, a higher stress material is characterized by an absolute value of stress, whether positive or negative, greater than the absolute value of a lower stress material. The convention used herein is that positive stress is characterized as tensile stress, negative stress as compressive stress, and no stress (i.e., 0 GPa) as neutral stress. Positive (i.e., tensile) stress may be characterized by an outward pushing force that may be generated by the expansion of the material. Negative (i.e., compressive) stress can be characterized by an inward pulling force that may be generated by the contraction of a material. Accordingly, "compressive stress applied" values ​​as used herein may refer to negative absolute values ​​(e.g., a compressive stress of 250 MPa may also be read as -250 MPa), and "tensile stress applied" values ​​as used herein may refer to positive absolute values ​​(e.g., a tensile stress of 250 MPa refers to 250 MPa).

[0047] Regardless of the metal and final stress, in the embodiments, the metal filler undergoes an additional annealing process after filling. Although the stressed metals and the deposition methods of the metals may provide a stressed metal filler material having few to no joints or voids, in the embodiments, an additional annealing step, such as a microwave annealing process, may further reduce or eliminate any remaining voids without damaging the surrounding structure or the metal filler.

[0048] As mentioned above, in the embodiments, the self-aligned diffusion interrupt (312) may be filled with a stressed metal material and dielectric liner so as to be generally considered to be free of voids and / or joints. Accordingly, in the embodiments, at least about 90 vol.% of the volume defined by the self-aligned diffusion interrupt, e.g., at least about 92 vol.%, at least about 94 vol.%, at least about 96 vol.%, at least about 98 vol.%, at least about 99 vol.%, or greater than, or any range or value in between, of the volume is occupied by the stressed metal filler and dielectric liner. In the embodiments, the volume defined by the self-aligned diffusion interrupt may be completely occupied by the stressed metal filler and dielectric liner, and no voids or joints may exist. In the art, even small voids or joints in the self-aligned diffusion interrupt may result in undesirable reductions in channel stress. For example, voids or joints characterized by a size of about 3 nm or less, such as about 2 nm or less, or about 1 nm or less, can result in a reduction of more than 60% in average channel stress.

[0049] In the embodiments, the self-aligned diffusion cut may define a channel length (L) defined as the distance between the source region and the drain region, as illustrated in FIG. 4. The channel length (L) may be characterized by a range or value of about 35 nm or less, e.g., about 30 nm or less, about 25 nm or less, about 20 nm or less, or any range or value in between. The self-aligned diffusion cut may be characterized by a high aspect ratio due to the small channel length and large diffusion cut depth. Furthermore, in the embodiments, only single self-aligned diffusion cuts are utilized in the structure (300) and dual diffusion cuts are not utilized while still providing the necessary stress, thereby allowing for a reduced size while maintaining effectiveness.

[0050] Furthermore, it should be understood that the illustrated embodiments include two single self-aligned diffusion interrupts (312) on opposite sides of three gate regions (306) in FIG. 3a through 3e, and two single self-aligned diffusion interrupts (312) on opposite sides of a single gate region (306) in FIG. 4, but that the self-aligned diffusion interrupts can be arranged with any number of gate regions (306) between a pair of diffusion interrupts. For example, depending on the desired stress on the channel regions (316) of the structure (300), one gate region (306), such as two gate regions, three gate regions, such as four gate regions, such as five gate regions, such as six gate regions, such as seven gate regions, or more gate regions can be arranged between a pair of diffusion interrupts. For example, the number of channel zones (304) disposed between opposing self-aligned diffusion disconnects (312) may be selected to maintain channel stress of about 350 MPa or more, e.g., about 400 MPa or more, about 450 MPa or more, about 500 MPa or more, about 550 MPa or more, e.g., about 650 MPa or more, e.g., about 750 MPa or more, e.g., about 850 MPa or more, e.g., about 950 MPa or more, e.g., about 1000 MPa or more, or greater than, or any range or value between these.

[0051] As mentioned above, in the embodiments, the stress imparted by the stress-applied metal filler may be compressive stress, which can significantly improve mobility and driving current. However, in the embodiments, the improvements mentioned above are specific to hole mobility and p-MOS driving current. Accordingly, in one or more embodiments, the patterning discussed above is specific to single-diffusion discontinuity patterning in the p-MOS region. For example, referring to FIG. 5, in embodiments where improvements in both p-MOS and n-MOS regions are desired, the method (500) may include operations (506 to 510), wherein operation (506) occurs after operation (205) of FIG. 2. That is, as illustrated, the method (500) may include a second patterning operation (506) performed in the same manner as operation (201), except that the patterning material is placed over the n-MOS region. In such an embodiment, the substrate (302) may be transferred from the process chamber (120) back to the process chamber (114) for a second patterning step. Subsequently, in operation (507), the substrate may be transferred from the process chamber (114) to the etching chamber (116), and etching may occur. After the second etching process in operation (507), in operation (508), an optional passivation / oxidation step may occur, and subsequently, in operation (508), transfer to the process chamber (118) for liner deposition / stressed metal filling may follow, which may occur in the same or similar manner as the etching and filling operations (202 and 203) by utilizing the second patterning operation (506). Of course, it should be understood that in the embodiments, the method operations (506 to 510) may occur wholly or partially prior to the operations (201 to 205). Nevertheless, after the second deposition filling operation (509), the substrate (302) can be transferred back to the process chamber (120) for the second polishing operation (510).

[0052] Furthermore, the stress-treated metal material (314) as discussed above can still be utilized to fill the formed self-aligned diffusion break (312) lined with the dielectric (328). However, to facilitate further improvement in the n-MOS region, a tensile-stressed material may be utilized, or tensile stress may be induced in the stress-treated metal material. The deposition of the tensile-stressed metal filler within a single self-aligned diffusion break in the n-MOS region can further improve electron mobility and n-MOS current driving without adverse effects on the hole mobility and p-MOS current driving characteristics discussed above.

[0053] Accordingly, in addition to the improvements discussed above, increased stress within the channel region can increase the mobility of charge carriers in the channel, which increases the driving current through the n-MOS channel region. In the embodiments, the increased stress generated in the channel region by the embodiments of the present technology can increase the driving current through the transistor channel by more than about 1%, e.g., more than about 5%, more than about 10%, more than about 15%, more than about 20%, more than about 25%, more than about 30%, more than about 35%, more than about 40%, more than about 45%, more than about 50%, more than about 55%, or greater than or any range or value between these. Increases in driving current and hole mobility through the channel region can increase transistor performance in a number of aspects, including but not limited to increased switching speed and / or reduced power consumption.

[0054] In the preceding description, numerous details have been described for illustrative purposes to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0055] Although various embodiments have been disclosed, it will be recognized by those skilled in the art that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. Additionally, to avoid unnecessarily obscuring the art, many well-known processes and elements have not been described. Accordingly, the foregoing description should not be construed as limiting the scope of the art.

[0056] Where a range of values ​​is provided, it is understood that, unless the context clearly indicates otherwise, each intermediate value is also specifically disclosed between the upper and lower limits of the range, down to the smallest fraction of the unit of the lower limit. Any narrower range is included between any mentioned values ​​or unmentioned intermediate values ​​of the mentioned range and any other mentioned or intermediate value of the mentioned range. The upper and lower limits of such smaller ranges may independently be included or excluded within the range, and each range in which any one of the limits is included, no limit is included, or both limits are included is also included in the description, subject to any specifically excluded limit in the mentioned range. Where the mentioned range includes one or both of the limits, ranges excluding either or both of the included limits are also included.

[0057] As used herein and in the appended claims, singular forms also include plural references unless the context clearly indicates otherwise. Accordingly, for example, a reference to "genomic material" includes plural such genomic materials, and a reference to "gate region" includes one or more gate regions and references to equivalents thereof known to those skilled in the art, and so on.

[0058] Additionally, when the words “include,” “include,” “contain,” “contain,” “have,” and “have” are used in this specification and the following claims, they are intended to specify the presence of the mentioned features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, functions, or groups.

Claims

Claim 1 A semiconductor device comprising: a substrate; a source region; a drain region; a channel region comprising at least one channel located between the source and the drain; a first gate region comprising a self-aligned single diffusion break of the p-MOS region ― said self-aligned single diffusion break comprises a dielectric material liner and a stressed metal fill, said stressed metal fill is characterized by a compressive stress of 350 MPa or more ―; and at least a second gate region of the n-MOS region comprising a first gate surrounding the channel between the source region and the drain region. Claim 2 A semiconductor device according to claim 1, wherein the channel region is characterized by a compressive stress of 250 MPa or more. Claim 3 A semiconductor device according to claim 1, further comprising a third gate region, wherein the second gate region is disposed between the first gate region and the third gate region, and the third gate region comprises a second self-aligned single diffusion interrupt. Claim 4 A semiconductor device according to claim 1, wherein the stressed metal filler is selected from aluminum and aluminum-containing materials, tungsten and tungsten-containing materials, copper and copper-containing materials, titanium and titanium-containing materials, tantalum and tantalum-containing materials, nickel and nickel-containing materials, cobalt and cobalt-containing materials, ruthenium and ruthenium-containing materials, molybdenum and molybdenum-containing materials, oxides of metals having a Pilling-Bedworth ratio of 1.5 or more, or combinations thereof. Claim 5 A semiconductor device according to paragraph 3, wherein the channel region comprises a plurality of horizontally extended channels. Claim 6 In paragraph 5, the semiconductor device is a nanosheet field-effect transistor or a complementary field-effect transistor and / or the semiconductor device is a gate-all-around complementary metal oxide semiconductor. Claim 7 A semiconductor device according to claim 1, wherein the dielectric material liner is characterized by a thickness of 1 nm to 6 nm or less. Claim 8 A semiconductor device according to claim 3, wherein the third gate region comprises a third self-aligned diffusion interruption, and the third self-aligned diffusion interruption comprises a metal filler subjected to compressive stress characterized by a compressive stress of 350 MPa or more. Claim 9 A semiconductor device according to claim 3, wherein the second self-aligned single diffusion interrupt comprises a dielectric liner and a metal filler subjected to tensile stress, and the metal filler subjected to tensile stress is characterized by a compressive stress of 350 MPa or more. Claim 10 A semiconductor device according to claim 1, wherein the self-aligned diffusion interruption defines the volume, and the stressed metal filler and dielectric liner occupy 95 vol.% or more of the volume. Claim 11 A semiconductor device according to claim 10, wherein the stress-applied metal filler generally has no voids or seams. Claim 12 A semiconductor device according to claim 11, wherein the stress-applied metal filler and the dielectric liner occupy 99 vol% or more of the volume. Claim 13 A semiconductor processing system comprising: a first processing chamber; a second processing chamber; a third processing chamber; and a system controller, wherein the system controller is configured to pattern a substrate in the first processing chamber, etch a shallow trench isolation in a first gate region of a semiconductor device in the second processing chamber — the first gate region is a p-MOS region —, line the shallow trench isolation with a dielectric liner in the third processing chamber, and fill the shallow trench isolation with a metallic material configured to provide a compressive stress of at least 350 MPa. Claim 14 A method for forming a semiconductor device, comprising: etching a shallow trench isolation portion in a first gate region of the semiconductor device — wherein the first gate region is a p-MOS region, and the semiconductor device comprises a substrate, a source region, a drain region, a channel region including at least one channel located between the source and the drain, a first gate region, and at least a second gate region including a first gate surrounding the channel between the source region and the drain region —; lining the shallow trench isolation portion with a dielectric liner; and filling the lined shallow trench isolation portion with a metal configured to provide a compressive stress of 350 MPa or more. Claim 15 A method according to claim 14, wherein the channel region is characterized by a first stress prior to the etching, the channel region is characterized by a second stress following the filling, and the first stress with respect to the second stress is characterized by a percentage change of 10% or more. Claim 16 In claim 14, the semiconductor device further comprises a third gate region, and the second gate region is disposed between the first gate region and the third gate region. Claim 17 A method according to claim 16, further comprising the step of etching the third gate region to be etched during the etching of the first gate region, or masking the third gate region during the etching of the first gate region and patterning and etching the third gate region after etching the first gate region to form a second shallow trench isolation portion in the third gate region. Claim 18 A method according to claim 17, further comprising the step of filling the shallow trench isolation portion with a metal filler subjected to compressive stress, and filling the second shallow trench isolation portion with a metal filler subjected to tensile stress or a metal filler subjected to compressive stress. Claim 19 In paragraph 14, a method in which the filled metal has naturally occurring compressive stress or oxidizes after the filling. Claim 20 A method according to claim 14, further comprising the step of annealing the semiconductor device after the above charging.

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