Manufacturing method of semiconductor chip

Abstract

One embodiment of the present invention provides a method for manufacturing a semiconductor chip comprising: providing a semiconductor wafer for a plurality of semiconductor chips; forming a photoresist pattern having a plurality of openings on the semiconductor wafer, wherein each of the plurality of openings defines a connection pad forming region; forming a plurality of connection pads in each of the plurality of openings; removing the photoresist pattern; sequentially forming an insulating layer and a polishing stop film on the semiconductor wafer to cover the plurality of connection pads, wherein the insulating layer and the polishing stop film have a plurality of convex portions corresponding to the upper portions of the plurality of connection pads; performing a first polishing process to polish the upper portions of the plurality of convex portions to expose a plurality of regions in the insulating layer corresponding to the upper portions of the plurality of connection pads; dry etching the exposed plurality of regions to form a plurality of grooves corresponding to the upper portions of the plurality of connection pads; performing a second polishing process to polish the plurality of convex portions using the polishing stop film so as to expose the upper surface of the plurality of connection pads; and removing the polishing stop film to expose the insulating layer.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a semiconductor chip. Background Technology

[0003] Efforts to improve the integration density of various semiconductor packages, such as logic circuits and memory, are ongoing. Stacking technologies, such as three-dimensional integrated circuits (3D ICs), are widely used as a means to integrate more components (e.g., semiconductor chips) into a package structure.

[0004] Recently, 3D IC technology can provide the advantages of high integration density, fast processing speed, and large bandwidth by reducing the length of interconnects between stacked chips using direct bonding. Conventionally, bonding pads for interconnection have been manufactured using the Damascene process, but there are difficulties in achieving the high flatness required for direct bonding. The problem to be solved

[0006] One of the problems to be solved by the present invention is to provide a method for manufacturing a semiconductor chip with improved reliability. means of solving the problem

[0008] One embodiment of the present invention provides a method for manufacturing a semiconductor chip comprising: providing a semiconductor wafer for a plurality of semiconductor chips; forming a photoresist pattern having a plurality of openings on the semiconductor wafer, wherein each of the plurality of openings defines a connection pad forming region; forming a plurality of connection pads in each of the plurality of openings; removing the photoresist pattern; sequentially forming an insulating layer and a polishing stop film on the semiconductor wafer to cover the plurality of connection pads, wherein the insulating layer and the polishing stop film have a plurality of convex portions corresponding to the upper portions of the plurality of connection pads; performing a first polishing process to polish the upper portions of the plurality of convex portions to expose a plurality of regions in the insulating layer corresponding to the upper portions of the plurality of connection pads; dry etching the exposed plurality of regions to form a plurality of grooves corresponding to the upper portions of the plurality of connection pads; performing a second polishing process to polish the plurality of convex portions using the polishing stop film so as to expose the upper surface of the plurality of connection pads; and removing the polishing stop film to expose the insulating layer.

[0009] One embodiment of the present invention provides a method for manufacturing a semiconductor chip comprising: forming a plurality of connection pads on a semiconductor wafer; sequentially forming an insulating layer and a polishing stop film on the semiconductor wafer to cover the plurality of connection pads, wherein the insulating layer and the polishing stop film have a plurality of convex portions corresponding to the upper portions of the plurality of connection pads; polishing the plurality of convex portions using the polishing stop film so as to expose the upper surface of the plurality of connection pads; and removing the polishing stop film.

[0010] One embodiment of the present invention provides a method for manufacturing a semiconductor chip comprising: forming a plurality of connection pads on a semiconductor wafer; forming a first insulating layer to cover the plurality of connection pads; sequentially forming a second insulating layer and a polishing stop layer on the first insulating layer, wherein the insulating layer and the polishing stop layer have a plurality of convex portions corresponding to the upper portions of the plurality of connection pads; polishing the plurality of convex portions using the polishing stop layer so as to expose the upper surface of the plurality of connection pads; and removing the polishing stop layer, wherein the first insulating layer and the second insulating layer comprise different materials. Effects of the invention

[0012] By pre-forming connection pads using a photoresist pattern and polishing the passivation layer using a polishing stop film, a flat surface bonding interface can be formed, and a semiconductor device having a high-quality bonding interface can be realized.

[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0016] FIG. 1 is a side cross-sectional view showing a semiconductor package according to one embodiment of the present invention. Figure 2 is a partial enlarged view showing part "A" of the semiconductor package shown in Figure 1. Figure 3 is a partial enlarged view of a semiconductor chip employed in the semiconductor package shown in Figure 2. FIG. 4 is a partial enlarged view showing a part of a semiconductor package (bonding interface of semiconductor chips) according to one embodiment of the present invention. FIG. 5 is a partial enlarged view of a semiconductor chip employed in a semiconductor package according to one embodiment of the present invention. FIGS. 6a to 6d are cross-sectional views of major processes to explain a semiconductor chip manufacturing method according to one embodiment of the present invention. FIGS. 7a to 7f are cross-sectional views of major processes for explaining a semiconductor chip manufacturing method (a semiconductor chip corresponding to FIG. 3) according to one embodiment of the present invention. FIGS. 8a and 8b are cross-sectional views of major processes to explain a semiconductor chip manufacturing method (a semiconductor chip corresponding to FIG. 3) according to one embodiment of the present invention. FIGS. 9a to 9e are cross-sectional views of major processes for explaining a semiconductor chip manufacturing method (a semiconductor chip corresponding to FIG. 5) according to one embodiment of the present invention. Specific details for implementing the invention

[0017] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0018] FIG. 1 is a side cross-sectional view showing a semiconductor package according to one embodiment of the present invention, and FIG. 2 is a partial enlarged view showing part "A" of the semiconductor package shown in FIG. 1.

[0019] Referring to FIGS. 1 and 2, a semiconductor package (100) may include first to fourth semiconductor chips (100A, 100B, 100C, 100D) stacked on a package substrate (50) and a molding member (90) surrounding the first to fourth semiconductor chips (100A, 100B, 100C, 100D).

[0021] The package substrate (50) may include an upper pad (52) and a lower pad (54) respectively disposed on the upper and lower surfaces of the substrate body (51). The substrate body (210) may include internal wiring (not shown) connecting the upper pad (52) and the lower pad (54). For example, the package substrate (50) may include a printed circuit board (PCB) or a silicon interposer substrate. Additionally, the semiconductor package (100) may further include conductive bumps (55) connected to the first semiconductor chip (100A) and external connection terminals (59) for connecting to an external device (e.g., a motherboard).

[0023] In this embodiment, the first semiconductor chip (100A) may have a structure substantially identical or similar to the second to fourth semiconductor chips (100B, 100C, 100D), identical or similar components are indicated by identical or similar reference numerals, and repeated descriptions of identical components may be omitted. However, unlike the other semiconductor chips, the fourth semiconductor chip (100D) placed at the top does not have through-electrodes and may have a relatively large thickness.

[0024] Specifically, the first to third semiconductor chips (100A, 100B, 100C) may each include a substrate (110), a wiring structure (120), a through electrode (130), a lower connection pad (145), and an upper connection pad (175). However, the fourth semiconductor chip (100D) positioned at the top may include other components identically, except for the through electrode (130).

[0026] A substrate (110) may have a first surface (110a) having an active region and a second surface (110b) located opposite to the first surface. The first surface (110a) and the second surface (110b) are also referred to as the active surface and the inactive surface, respectively. A plurality of individual elements (115), such as transistors, may be formed on the first surface (110a) (i.e., the active region) of the substrate (110). An interlayer insulating layer (117) covering the plurality of individual elements (115) is formed on the first surface (110a) of the substrate (110), and the plurality of individual elements (115) may be connected by an interconnection portion (113) (e.g., a contact plug). A wiring structure (120) having a low dielectric layer (121) and a plurality of wiring layers (125) is disposed on an interlayer insulating layer (117), and the wiring layers (125) can be connected to a plurality of individual elements (115) through an interconnection portion (113). The wiring layers (125) may include a multilayer structure including wiring patterns and vias. Additionally, the wiring structure (120) may be connected to a through electrode (130). For example, as shown in FIG. 2, the wiring layers (125) may include a landing pad (125P) connected to the through electrode (130).

[0027] The interlayer insulating layer (117) or low dielectric layer (121) may be FOX (Flowable Oxide), TOSZ (Tonen SilaZen), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), HDP (High Density Plasma) oxide, PEOX (Plasma Enhanced Oxide), FCVD (Flowable CVD) oxide, or a combination thereof. The interlayer insulating layer (117) or low dielectric layer (121) may be formed using a chemical vapor deposition (CVD), a flowable-CVD process, or a spin coating process.

[0028] Referring to FIG. 2, an insulating protective layer (151) disposed on a second surface (110b) of a substrate (110) may be included, and a through electrode (130) may be formed to penetrate the substrate (110), the interlayer insulating layer (117), and the insulating protective layer (151). The through electrode (130) may include a via plug (135) and a side insulating layer (131) surrounding the side of the via plug (135). The side insulating layer (131) may electrically isolate the via plug (135) from the substrate (110).

[0030] Each of the first to fourth semiconductor chips (100A, 100B, 100C, 100D) may include a lower insulating layer (141) disposed on the lower insulating layer (141) and connected to a wiring layer (125). Additionally, each of the first to third semiconductor chips (100A, 100B, 100C) may include an upper insulating layer (171) disposed on the upper insulating layer (157) and connected to a through electrode (130) disposed on the upper insulating layer (171). In each of the first to third semiconductor chips (100A, 100B, 100C), the upper and lower connecting pads (145, 175) may be vertically connected to the wiring layer (125) by the through electrode (130).

[0032] In this embodiment, the first to fourth semiconductor chips (100A, 100B, 100C, 100D) can be stacked by hybrid bonding. As shown in FIG. 2, the bonding of the first and second semiconductor chips (100A, 100B) can form a hybrid bonding interface (BS) by combining an intermetal bonding interface (BS1) formed by the lower connecting pad (145) and the upper connecting pad (175), and a dielectric bonding interface (BS2) between the lower insulating layer (141) and the upper insulating layer (171). Similarly, the bonding of the second and third semiconductor chips (100B, 100C) and the third and fourth semiconductor chips (100C, 100D) can also be implemented.

[0033] Specifically, as illustrated in FIG. 2, the upper connection pad (175) of the first semiconductor chip (100A) and the lower connection pad (145) of the second semiconductor chip (100B) are directly bonded so that electrical connection between the first and second semiconductor chips (100A, 100B) and bonding of the first and second semiconductor chips (100A, 100B) can be realized.

[0034] The lower connection pad (145) and the upper connection pad (175) may each contain the same metal, for example, copper (Cu). The lower connection pad (145) and the upper connection pad (175), which are directly bonded, can be joined by the mutual diffusion of copper through a high-temperature annealing process. The metal constituting the lower connection pad (145) and the upper connection pad (175) is not limited to copper and may include other metallic materials (e.g., Au) that can be similarly bonded. Through this metal bonding, electrical connections can be achieved through direct bonding without separate connection bumps, along with robust bonding of the stacked semiconductor chips. A path can be provided for transmitting and receiving at least one of a control signal, a power signal, a ground signal, and a data signal between the first to fourth semiconductor chips (100A, 100B, 100C, 100D). Since connection bumps such as solder are not used, transmission loss can be reduced.

[0035] Additionally, the upper insulating layer (171) disposed on the upper surface of each of the first to third semiconductor chips (100A, 100B, 100C) and the lower insulating layer (141) disposed on the lower surface of each of the second to fourth semiconductor chips (100B, 100C, 100D) can be directly bonded. The upper insulating layer (171) and the lower insulating layer (141) may include the same or similar materials. For example, the upper insulating layer (171) and the lower insulating layer (141) may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), and aluminum oxide carbide (AlOC).

[0037] The upper connecting pad (175) employed in this embodiment may be formed by a different process than the lower connecting pad (145). For example, while the lower connecting pad (145) is formed by a conventional damascene process, the upper connecting pad (175) may be formed by a new method proposed by the inventor, namely a photoresist process and a planarization process using a polishing stop film. The upper connecting pad (175) formed by the new process may have different structural features from the lower connecting pad (145).

[0038] As illustrated in FIG. 2, the lower connecting pad (145) has a width that widens toward the bonding interface (BS), whereas the upper connecting pad (175) employed in this embodiment may have a width that narrows toward the bonding interface (BS). In the case of the lower connecting pad (145), the lower connecting pad (145) can be formed by first forming a lower insulating layer (141), then forming an opening for the pad, and then forming a conductive barrier layer (142) in the opening, and then using a plating process. The conductive barrier layer (142) may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0039] On the other hand, the upper connecting pad (175) has a side (175S) inclined toward the bonding interface (BS) and can come into direct contact with the upper insulating layer (171). That is, the upper connecting pad (175) and the upper insulating layer (171) can come into direct contact without an additional metal layer. Therefore, a different metal layer is interposed between the upper connecting pad (175) and the upper insulating layer (171), so that galvanic corrosion can be prevented from occurring on the side of the upper connecting pad (175). The upper connecting pads (175) can be formed with a diameter of at least 8 μm or less. In addition, the upper connecting pads (175) can be spaced apart from other upper connecting pads (175) by a gap of at least 12 μm or more.

[0041] A seed layer (164) may be disposed on the lower surface (175U) of the upper connection pad (175). Specifically, as illustrated in FIGS. 2 and 3, the seed layer (164) may be disposed on an insulating protective layer (151) so as to be positioned between the upper connection pad (175) and the through electrode (130). The seed layer (164) may contain the same material as the upper connection pad (175). Thus, the seed layer (164) may be used as a seed for a plating process for forming the upper connection pad (175). For example, the seed layer (164) may contain copper (Cu), chromium-copper (Cr-Cu), palladium (Pd), platinum (Pt), gold (Au), or a combination thereof. In some embodiments, the seed layer (164) may contain Cu. Additionally, the seed layer (164) may have a multilayer structure including a lower layer containing titanium (Ti) and an upper layer containing copper (Cu).

[0043] As illustrated in FIG. 3, the upper connecting pad (175) may have an upper surface (171T) of the upper insulating layer (171) and a substantially flat upper surface (175T).

[0044] As such, the hybrid bonding employed in this embodiment can be implemented by a metal bonding structure in which an upper connecting pad (175) and a lower connecting pad (145) are directly bonded, and a dielectric bonding structure in which an upper insulating layer (171) and a lower insulating layer (141) are directly bonded. In addition, the bonding of the second and third semiconductor chips (100B, 100C) and the bonding of the third and fourth semiconductor chips (100C, 100D) can also be implemented by the hybrid bonding described with reference to FIG. 2.

[0045] The first to fourth semiconductor chips (100A, 100B, 100C, 100D) may be memory chips or logic chips. In the present embodiment, the first to fourth semiconductor chips (100A, 100B, 100C, 100D) may all be memory chips of the same type, and in another example, some of the first to fourth semiconductor chips (100A, 100B, 100C, 100D) may be memory chips and others may be logic chips.

[0046] For example, the memory chip may be a volatile memory chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or a non-volatile memory chip such as PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory). In some embodiments, the first to fourth semiconductor chips (100A, 100B, 100C, 100D) may be HBM (High Bandwidth Memory) DRAM.

[0048] In this embodiment, first to fourth semiconductor chips (100A, 100B, 100C, 100D) may be stacked on a package substrate (50). The semiconductor package according to this embodiment is exemplified as a multi-chip package comprising four identical semiconductor chips (100A, 100B, 100C, 100D), but is not limited thereto and may include a different number of semiconductor chips and may stack different types of semiconductor chips.

[0050] FIG. 4 is a partial enlarged view showing a part of a semiconductor package (bonding interface of semiconductor chips) according to one embodiment of the present invention, and FIG. 5 is a partial enlarged view of a semiconductor chip employed in a semiconductor package according to one embodiment of the present invention.

[0051] Here, Fig. 4 is a part corresponding to part A of Fig. 1, similar to Fig. 2, and Fig. 5 may be a partial enlarged view of a semiconductor chip (before bonding), similar to Fig. 3.

[0052] Referring to FIGS. 4 and 5, the semiconductor package (100') according to the present embodiment can be understood as having a structure similar to the semiconductor package (100) shown in FIGS. 1 to 3, except that the structure of the lower connection pad (145) of the second semiconductor chip (100B') is different and the upper insulating layer (171) and the lower insulating layer (141) are composed of a composite film. Unless specifically stated otherwise, the components of the present embodiment can be understood by referring to the description of identical or similar components of the semiconductor package (100) shown in FIGS. 1 to 3.

[0054] The lower connection pad (145) employed in this embodiment can be formed by a process similar to that of the upper connection pad (175). As shown in FIG. 4, the lower connection pad (145) may have a width that narrows toward the bonding interface. That is, the lower connection pad (145) has a side inclined toward the bonding interface, and a capping insulating layer (147) may be formed extending from the side of the lower connection pad (145) and the side of the wiring structure (120).

[0055] A capping insulating layer (167) may be continuously formed on the side (175S) of the upper connecting pad (175) and the upper surface of the buffer film (157). The capping insulating layer (167) employed in this embodiment may be an insulating material. The capping insulating layer (167) may include a material identical or similar to that of the buffer film (157). For example, the capping insulating layer (167) may include at least one of silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), and aluminum oxide carbide (AlOC). In some embodiments, the thickness of the capping insulating layer (167) may be formed to be similar to the thickness of the seed layer (164).

[0057] A seed layer (144) may be disposed on the upper surface of the lower connection pad (145) to be connected to the wiring structure (120). The lower connection pad (145) may have a lower surface that is substantially flat with the lower surface of the lower insulation layer (141).

[0059] FIGS. 6a to 6d are cross-sectional views of major processes for explaining a method for manufacturing a semiconductor chip according to an embodiment of the present invention. The manufacturing method according to the present embodiment can be understood as the method for manufacturing a first semiconductor chip (100A) described in FIGS. 1 to 3.

[0061] First, referring to FIG. 6a, a semiconductor wafer (100W) for a plurality of semiconductor chips (100A) can be temporarily bonded to a carrier substrate (510) using a bonding material layer (520) so as to be supported.

[0062] In this process, the active surface side of the semiconductor wafer (100W) can be bonded so as to face the carrier substrate, and the semiconductor wafer (100W) can be stably supported during subsequent processes by an adhesive material such as glue. Components for the first semiconductor chip (100A) can be implemented on the semiconductor wafer (100W). Specifically, a through electrode (130) can be formed on the active surface of the semiconductor wafer (100W) along with a device area, a wiring structure (120), and a lower connection pad (145). The wiring structure (120) may have a low dielectric layer (121) and a plurality of wiring layers (125). The through electrode (130) may be formed in advance to penetrate a part of the substrate (110) before or during the formation of the device area, and may be formed to a depth greater than the thickness of the final semiconductor chip from the active surface. That is, the through electrode (130) may not completely penetrate the semiconductor wafer (100W).

[0064] Next, referring to FIG. 6b, the thickness of the semiconductor wafer (100W) can be reduced by applying a polishing process to the upper surface (inactive surface) of the semiconductor wafer (100W).

[0065] In this process, by removing a portion of the semiconductor wafer (100W), the top (130T') of the through-electrode (130) can protrude from the upper surface of the semiconductor wafer (100W). Through this polishing process, the thickness of the semiconductor wafer (100W) can be reduced to a desired thickness of the first semiconductor chip (100A). For this process, a grinding process such as chemical mechanical polishing (CMP), an etch-back process, or a combination thereof may be used. For example, this process may reduce the thickness of the semiconductor wafer (100W) by a certain amount by performing a grinding process and sufficiently expose the through-electrode (130) by applying an etch-back under appropriate conditions.

[0067] Next, referring to FIG. 6c, an insulating protective layer (151) and a buffer film (157) can be sequentially formed on the upper surface of a semiconductor wafer (100W) to cover the exposed top (130T') of a through electrode (130). The insulating protective layer (151) may be silicon oxide, and the buffer film (157) may be silicon nitride or silicon oxynitride.

[0069] Next, referring to FIG. 6d, the insulating protective layer (151) and the buffer film (157) can be ground so that the top (130T) of the through electrode (130) is exposed. The grinding process can be performed up to a predetermined line (GL1) so that the insulating protective layer (151) and the buffer film (157) are partially removed to expose the through electrode (130). Through this grinding process, the insulating protective layer (151) can have a substantially flat top surface with respect to the top (130T) of the through electrode (130). Additionally, the damaged portion of the top (130T) of the through electrode (130) can also be removed.

[0071] FIGS. 7a to 7f are cross-sectional views of major processes for explaining a method for forming a bonded structure (a semiconductor chip corresponding to FIG. 3) according to an embodiment of the present invention.

[0073] First, the portion shown in FIG. 7a corresponds to the portion shown in FIG. 3 and can be understood as corresponding to a part of the first semiconductor chip (100A) at the wafer level manufactured in FIG. 6d. Additionally, subsequent processes can be continuously implemented as wafer-level processes of FIG. 6a to 6d.

[0075] Next, referring to FIG. 7b, a seed layer (164L) can be formed on the insulating protective layer (151). The seed layer (164L) can be formed to cover the through electrode (130) and the buffer film (157).

[0076] The seed layer (164L) is used as a seed for a plating process to form an upper connecting pad (175 in FIG. 7c). For example, the seed layer (164L) may include copper (Cu), chrome-copper (Cr-Cu), palladium (Pd), platinum (Pt), gold (Au), or a combination thereof. Additionally, the seed layer (164L) may have a multilayer structure comprising a lower layer containing titanium (Ti) and an upper layer containing copper (Cu).

[0078] Next, referring to FIG. 7c, a photoresist pattern (PR) having an opening can be formed on a seed layer (164L), and an upper connecting pad (175) can be formed in the opening. For example, the upper connecting pad (175) may contain Cu.

[0079] In this embodiment, an opening is provided to define an area where a connection pad is formed, and a desired opening can be formed through an exposure / development process after forming a photoresist layer. The opening may have a space that narrows toward the top. An upper connection pad (175) may be formed on the area of ​​the seed layer (164L) exposed to the opening using a plating process. The side (175S) of the upper connection pad (175) may have a surface inclined toward the upper surface (175T').

[0081] Next, referring to FIG. 7d, the photoresist pattern (PR) is removed, and the exposed portions of the seed layer (164) are removed.

[0082] The photoresist pattern (PR) can be removed using an ashing process. After the photoresist pattern (PR) is removed, the exposed portion of the seed layer (164) can be etched. A portion of the seed layer (164) from which the exposed portion has been removed may have a region in contact with the insulating protective layer (151) and the buffer film (157).

[0084] Next, referring to FIG. 7e, an upper insulating layer (171) and a polishing stop layer (179) can be sequentially formed to cover the upper connecting pad (175).

[0085] For example, the upper insulating layer (171) may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO) and aluminum oxide carbide (AlOC).

[0086] The level of the polishing block (179) can be determined by the thickness (t1) of the upper insulating layer (171). For example, the thickness (t1) of the upper insulating layer (171) may be substantially the same as the sum of the thickness of the upper connecting pad (175) and the thickness of the seed layer (164). Accordingly, among the upper insulating layer (171), the upper surface of the first region (A1) that overlaps with the upper connecting pad (175) forms an area protruding upward (hereinafter referred to as a 'convex portion'), and the upper surface of the second region (A2) that does not overlap with the upper connecting pad (175) may form a flat surface. The lower surface of the first region (A1) and the upper surface of the second region (A2) of the upper insulating layer (171) may be located at substantially the same level (L1). As a result, in a subsequent process, if the convex portion of the upper insulating layer (171) is polished and removed using a polishing block (179), the upper surface (175T) of the upper connecting pad (175) can be exposed.

[0088] The polishing stop layer (179) can be formed on the upper insulating layer (171) with a uniform thickness (t2). Accordingly, the polishing stop layer (179) can be formed convexly along the shape of the convex portion of the upper insulating layer (171). The polishing stop layer (179) can be used as a reference for the polishing level in the process of polishing and removing the convex portion of the upper insulating layer (171) so that the upper surface (175T) of the upper connecting pad (175) is exposed in a subsequent process. For example, the polishing stop layer (179) may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). For example, the polishing stop layer (179) can be formed with a thickness (t2) of 3000 Å to 5000 Å.

[0090] Next, referring to FIG. 7f, the upper surface of the upper connecting pad (175) can be exposed by removing the convex portion of the upper insulating layer (171) using a polishing stop layer (179). This polishing process can be performed as a CMP process. The CMP process can be performed using a slurry in which the polishing rate for the upper insulating layer (171) is higher than the polishing rate for the polishing stop layer (179). Thus, the convex portion of the upper insulating layer (171) can be removed while minimizing polishing of the polishing stop layer (179). Through the polishing process, the upper surface of the upper insulating layer (171) can be flattened while removing the convex portion, thereby exposing the upper surface of the upper connecting pad (175). Additionally, the upper surface (175T) of the upper insulating layer (171) and the upper surface (175T) of the upper connecting pad (175) can form a substantially flat joint surface.

[0092] Next, the polishing block layer (179) can be removed to expose the upper insulating layer (171). The removal of the polishing block layer (179) can be performed through a wet etching process. The wet etching process can be performed using an etching solution that has a higher etching selectivity for the polishing block layer (179) than for the upper connection pad (175). As such an etching solution, an alkaline or hydrofluoric acid aqueous solution etching solution may be used. Thus, the polishing block layer (179) can be removed while minimizing damage to the upper surface (175T) of the upper connection pad (175).

[0094] FIGS. 8A and 8B are cross-sectional views of major processes for explaining a semiconductor chip formation method (a semiconductor chip corresponding to FIG. 3) according to an embodiment of the present invention. Here, the process illustrated in FIG. 8A according to the present embodiment can be understood as a subsequent process of FIG. 7e.

[0095] First, referring to FIG. 8a, the upper portion of the convex part can be polished to expose an area corresponding to the upper portion of the upper connecting pad (175) of the upper insulating layer (171). The width (W1) of the exposed area may be larger than the width (W2) of the lower portion (175U) of the upper connecting pad (175). This polishing process can be performed as a CMP process. The CMP process can be performed using a slurry in which the polishing rate for the polishing stop layer (179) is higher than the polishing rate for the upper insulating layer (171). Thus, the upper portion of the polishing stop layer (179) can be removed while minimizing the polishing of the upper insulating layer (171).

[0097] Next, referring to FIG. 8b, the upper surface of the exposed upper insulating layer (171) can be dry-etched. The dry-etching can be performed to a depth (t3) such that the upper surface (175U) of the upper connecting pad (175) is not exposed. The dry-etching can be performed using the polishing stop layer (179) as a mask. When the dry-etching process is performed, the upper surface of the exposed upper polishing stop layer (179) can be anisotropically etched to form a groove (H). The groove (H) can be formed to a depth (t3) such that the upper surface (175T) of the upper connecting pad (175) is not exposed on the bottom surface (HS). Thus, in a subsequent process of removing the upper insulating layer (171), damage to the upper surface (175T) of the upper connecting pad (175) can be prevented.

[0098] The subsequent process is identical to the process described above in Fig. 7f, so a detailed description is omitted.

[0100] FIGS. 9a to 9e are cross-sectional views of major processes for explaining a method for manufacturing a semiconductor chip (a semiconductor chip corresponding to FIG. 5) according to an embodiment of the present invention. Here, the process illustrated in FIG. 9a according to the present embodiment can be understood as a subsequent process of FIG. 7d.

[0102] First, referring to FIG. 9a, a capping insulating layer (167L) can be formed to cover the surface of the upper connection pad (175). The capping insulating layer (167L) can be formed continuously to cover the upper surface (175T) and side surface (175S) of the upper connection pad (175) and the upper surface of the buffer film (157). The capping barrier film (168L) employed in this embodiment can be formed of an insulating material. The capping insulating layer (167L) can be formed of the same or similar material as the buffer film (157). For example, the capping insulating layer (167L) may include at least one of silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), and aluminum oxide carbide (AlOC). In some embodiments, the thickness of the capping insulating layer (167L) may be formed to be similar to the thickness of the seed layer (164).

[0103] Additionally, the capping insulating layer (167L) may be formed of a material different from the upper insulating layer (171) described later, and may be formed with a thinner thickness than the upper insulating layer (171).

[0105] Referring to FIG. 9b, an upper insulating layer (171) and a polishing blocking film (179) can be sequentially formed to cover the capping insulating layer (167L).

[0107] Referring to FIG. 9c, the upper part of the convex portion can be polished to expose an area corresponding to the upper part of the upper connecting pad (175) of the upper insulating layer (171). The width (W3) of the exposed area may be larger than the width (W4) of the lower surface (175U) of the upper connecting pad (175). This polishing process can be performed as a CMP process. The CMP process can be performed using a slurry in which the polishing rate for the polishing stop layer (179) is higher than the polishing rate for the upper insulating layer (171). Thus, the upper part of the polishing stop layer (179) can be removed while minimizing the polishing of the upper insulating layer (171).

[0109] Referring to FIG. 9d, the upper surface of the exposed upper insulating layer (171) can be dry-etched. The dry-etching can be performed to a depth (t3) such that the upper surface (175U) of the upper connecting pad (175) is not exposed. The dry-etching can be performed using the polishing stop layer (179) as a mask.

[0111] Referring to FIG. 9e, the upper surface (175T) of the upper connecting pad (175) can be exposed by removing the convex portion of the upper insulating layer (171) using a polishing stop layer (179). This polishing process can be performed as a CMP process. The CMP process can be performed using a slurry in which the polishing rate for the upper insulating layer (171) is higher than the polishing rate for the polishing stop layer (179). Thus, the convex portion of the upper insulating layer (171) can be removed while minimizing polishing of the polishing stop layer (179). Through the polishing process, the convex portion of the upper insulating layer (171) is removed and the upper surface is flattened, thereby exposing the upper surface (175T) of the upper connecting pad (175). Additionally, the upper surface of the upper insulating layer (171) and the upper surface of the upper connecting pad (175) can form a substantially flat joint surface.

[0112] The subsequent process is identical to the process described above in Fig. 7f, so a detailed description is omitted.

[0114] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0116] 100: Semiconductor package 100A, 100B, 100C, 100D: 1st to 4th semiconductor chips 110: Substrate 110a: First surface (active surface) 110b: Second surface (inactive surface) 113: Interconnection part 115: Element 117: Interlayer insulation layer 120: Wiring structure 121: Low dielectric layer 125: Wiring layer 125P: Landing pad 130: Through-electrode 131: Side insulating layer 135: Via plug 141: Lower insulation layer 142: Conductive barrier layer 145: Lower connection pad 157: Buffer layer 164: Seed layer 167: Capping insulation layer 171: Upper insulation layer 175: Upper connection pad 179: Grinding film

Claims

Claim 1 A method for manufacturing a semiconductor chip comprising: a step of providing a semiconductor wafer for a plurality of semiconductor chips; a step of forming a photoresist pattern having a plurality of openings on the semiconductor wafer, wherein each of the plurality of openings defines a connection pad forming region; a step of forming a plurality of connection pads in each of the plurality of openings; a step of removing the photoresist pattern; a step of sequentially forming an insulating layer and a polishing stop film on the semiconductor wafer to cover the plurality of connection pads, wherein the insulating layer and the polishing stop film have a plurality of convex portions corresponding to the upper portions of the plurality of connection pads; a step of performing a first polishing process to polish the upper portions of the plurality of convex portions to expose a plurality of regions in the insulating layer corresponding to the upper portions of the plurality of connection pads; a step of dry etching the exposed plurality of regions to form a plurality of groove portions corresponding to the upper portions of the plurality of connection pads; a step of performing a second polishing process to polish the plurality of convex portions using the polishing stop film so as to expose the upper surface of the plurality of connection pads; and a step of removing the polishing stop film to expose the insulating layer. Claim 2 A method for manufacturing a semiconductor chip according to claim 1, wherein the polishing film comprises a material different from the plurality of connection pads. Claim 3 A semiconductor chip manufacturing method according to claim 2, wherein the step of removing the polishing stop film is to wet-etch the polishing stop film using an etching solution having a higher etching selectivity ratio for the polishing stop film than for the plurality of connection pads. Claim 4 A semiconductor chip manufacturing method according to claim 1, further comprising the step of forming a seed layer on a semiconductor wafer prior to the step of forming a photoresist pattern, wherein the step of forming a plurality of connection pads comprises plating copper (Cu) on the seed layer to form the plurality of connection pads. Claim 5 A semiconductor chip manufacturing method according to claim 4, wherein the thickness of the insulating layer is equal to the sum of the thicknesses of the plurality of connection pads and the thickness of the seed layer. Claim 6 A method for manufacturing a semiconductor chip according to claim 4, wherein the seed layer comprises the same material as the polishing stop film. Claim 7 A method for manufacturing a semiconductor chip according to claim 4, wherein the polishing film comprises at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). Claim 8 A method for manufacturing a semiconductor chip according to claim 1, wherein the thickness of the polished stop film is in the range of 3000 Å to 5000 Å. Claim 9 A semiconductor chip manufacturing method according to claim 1, wherein the bottom surface of the plurality of grooves is spaced apart from the top surface of the plurality of connection pads. Claim 10 A semiconductor chip manufacturing method according to claim 9, wherein the bottom surface of the plurality of grooves is spaced apart from the top surface of the plurality of connection pads by the same thickness as the polishing film. Claim 11 A semiconductor chip manufacturing method according to claim 1, wherein the first polishing process and the second polishing process are performed using a chemical mechanical polishing process. Claim 12 A semiconductor chip manufacturing method according to claim 11, wherein the first polishing process is performed using a first slurry with a polishing rate for the polishing stop film higher than that for the insulating layer, and the second polishing process is performed using a second slurry with a polishing rate for the insulating layer higher than that for the polishing stop film. Claim 13 A semiconductor chip manufacturing method according to claim 1, wherein the insulating layer is in direct contact with the plurality of connection pads. Claim 14 A method for manufacturing a semiconductor chip according to claim 1, wherein the plurality of connection pads are spaced apart from each other by at least 12 μm. Claim 15 A semiconductor chip manufacturing method according to claim 1, further comprising the step of forming a capping insulating layer covering the side and top surfaces of the plurality of connection pads before the step of forming the insulating layer. Claim 16 A semiconductor chip manufacturing method according to claim 15, wherein the capping insulating layer comprises a material different from the insulating layer. Claim 17 A method for manufacturing a semiconductor chip according to claim 16, wherein the capping insulating layer comprises at least one of silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO) and aluminum oxide carbide (AlOC). Claim 18 A method for manufacturing a semiconductor chip comprising: a step of forming a plurality of connection pads on a semiconductor wafer; a step of sequentially forming an insulating layer and a polishing stop film on the semiconductor wafer to cover the plurality of connection pads, wherein the insulating layer and the polishing stop film have a plurality of convex portions corresponding to the upper portions of the plurality of connection pads; a step of polishing the upper portions of the plurality of convex portions to partially expose the insulating layer; a step of partially etching the exposed regions of the insulating layer to form a plurality of grooves; a step of polishing the plurality of convex portions using the polishing stop film so as to expose the upper surface of the plurality of connection pads; and a step of removing the polishing stop film. Claim 19 A method for manufacturing a semiconductor chip comprising: forming a plurality of connection pads on a semiconductor wafer; forming a first insulating layer to cover the plurality of connection pads; sequentially forming a second insulating layer and a polishing stop layer on the first insulating layer, wherein the insulating layer and the polishing stop layer have a plurality of convex portions corresponding to the upper portions of the plurality of connection pads; polishing the upper portions of the plurality of convex portions to partially expose the second insulating layer; partially etching the exposed regions of the second insulating layer to form a plurality of grooves that partially expose the first insulating layer; polishing the plurality of convex portions using the polishing stop layer so as to expose the upper surface of the plurality of connection pads; and removing the polishing stop layer, wherein the first insulating layer and the second insulating layer comprise different materials. Claim 20 A semiconductor chip manufacturing method according to claim 19, wherein the thickness of the first insulating layer is smaller than the thickness of the second insulating layer.

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