Semiconductor device and method for fabricating the same

Abstract

A semiconductor device according to the present invention may include a substrate; a body recess formed on the substrate; a body insulating layer formed on the body recess; an active layer extending along a direction parallel to the substrate on the upper surface of the substrate; a contact node formed vertically on the side of one end of the active layer; and a conductive line connected to the contact node and extending vertically from the body insulating layer.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device with a three-dimensional structure and a method for manufacturing the same. Background Technology

[0003] To increase the net die of a memory device, the size of memory cells is being continuously reduced. As the size of memory cells becomes finer, parasitic capacitance (Cb) should decrease and capacitance should increase; however, it is difficult to increase the net die due to the structural limitations of memory cells.

[0004] Recently, three-dimensional semiconductor memory devices equipped with memory cells arranged in three dimensions have been proposed. The problem to be solved

[0006] Embodiments of the present invention provide a semiconductor device having a highly integrated memory cell and a method for manufacturing the same. means of solving the problem

[0008] A semiconductor device according to an embodiment of the present invention may include: a substrate; a body recess formed on the substrate; a body insulating layer formed on the body recess; an active layer extending along a direction parallel to the substrate on the upper surface of the substrate; a contact node formed vertically on a side surface of one end of the active layer; and a conductive line connected to the contact node and extending vertically from the body insulating layer.

[0009] A semiconductor device according to an embodiment of the present invention may include: a substrate including a peripheral circuit portion; a memory cell array including a vertical conductive line including a contact pad surface and a bonding pad surface; a first bonding pad connected to the bonding pad surface of the vertical conductive line; a second bonding pad located above the peripheral circuit portion and connected to the first bonding pad; a body insulating layer covering the contact pad surface of the vertical conductive line; and a conductive pad connected to the contact pad surface of the vertical conductive line by penetrating the body insulating layer.

[0010] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include the steps of: forming a stack body on a substrate including insulating layers, first sacrificial layers and second sacrificial layers between the insulating layers, and active layers between the first sacrificial layers and the second sacrificial layers; etching the stack body to form an opening; etching the substrate below the opening to form a body recess; forming a body insulating layer on the body recess; replacing the first sacrificial layers and the second sacrificial layers with double word lines; exposing one end of the active layers; and forming contact nodes connected to one end of the active layers.

[0011] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include the steps of: forming a memory cell array comprising a first substrate including a body insulating layer and a vertical bit line including a contact pad surface covered by the body insulating layer and a bonding pad surface facing the contact pad surface; forming a second substrate including a peripheral circuit portion; flipping the first substrate to bond the bonding pad surface of the vertical bit line to the peripheral circuit portion; selectively removing the first substrate; and forming a bit line pad connected to the contact pad surface of the vertical bit line. The body insulating layer may include silicon oxide covering the contact pad surface of the vertical bit line. Effects of the invention

[0013] This technology forms a body insulating layer that covers vertical conductive lines, thereby preventing electrical bridging between adjacent vertical conductive lines and thereby suppressing leakage current to the substrate. Brief explanation of the drawing

[0015] FIG. 1 is a schematic perspective view of a semiconductor device according to one embodiment. Figure 2 is a schematic cross-sectional view of the memory cell of Figure 1. FIG. 3 is a schematic perspective view of a semiconductor device according to another embodiment. Figure 4 is a schematic cross-sectional view of the memory cell array of Figure 3. FIG. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment. FIGS. 6 to 19 are drawings for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. FIGS. 20 to 24 are drawings for illustrating an example of a method for manufacturing a semiconductor device according to another embodiment. Specific details for implementing the invention

[0016] The embodiments described herein will be explained with reference to cross-sectional views, plan views, and block drawings, which are ideal schematic diagrams of the invention. Accordingly, the shapes of the exemplary drawings may be modified due to manufacturing techniques and / or tolerances, etc. Therefore, the embodiments of the invention are not limited to the specific shapes depicted but include variations in shape resulting from the manufacturing process. Accordingly, the regions illustrated in the drawings have schematic properties, and the shapes of the regions illustrated in the drawings are intended to illustrate specific forms of the regions of the device and are not intended to limit the scope of the invention.

[0017] The embodiments described below can increase memory cell density and reduce parasitic capacitance by vertically stacking memory cells.

[0018] FIG. 1 is a schematic perspective view of a semiconductor device according to one embodiment. FIG. 2 is a schematic cross-sectional view of a memory cell of FIG. 1.

[0019] Referring to FIGS. 1 and 2, a semiconductor device (100) according to embodiments may include a memory cell (MC). The memory cell (MC) may include a bit line (BL), a transistor (TR), and a capacitor (CAP). The transistor (TR) may include an active layer (ACT) and a double word line (DWL), and the double word line (DWL) may include first and second word lines (WL1, WL2) facing each other with the active layer (ACT) in between. The capacitor (CAP) may include a storage node (SN), a dielectric layer (DE), and a plate node (PN).

[0020] The bit line (BL) may have a pillar shape extending along the first direction (D1). The active layer (ACT) may have a bar shape extending along the second direction (D2) intersecting the first direction (D1). The double word line (DWL) may have a line shape extending in the third direction (D3) intersecting the first and second directions (D1, D2). The plate node (PN) of the capacitor (CAP) may be connected to the plate line (PL).

[0021] The bit line (BL) may be vertically oriented along a first direction (D1). The bit line (BL) may be referred to as a vertically oriented bit line or a pillar-type bit line. The bit line (BL) may include a conductive material. The bit line (BL) may include a silicon-base material, a metal-base material, or a combination thereof. The bit line (BL) may include silicon, metal, metal nitride, metal silicide, or a combination thereof. The bit line (BL) may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line (BL) may include polysilicon or titanium nitride (TiN) doped with N-type impurities. The bit line (BL) may include a TiN / W stack comprising titanium nitride and tungsten on titanium nitride.

[0022] The double word line (DWL) may be extended along the third direction (D3), and the active layer (ACT) may be extended along the second direction (D2). The active layer (ACT) may be arranged horizontally along the second direction (D2) from the bit line (BL). The double word line (DWL) may include a pair of word lines, namely a first word line (WL1) and a second word line (WL2). The first word line (WL1) and the second word line (WL2) may face each other in the first direction (D1) with the active layer (ACT) in between. A gate insulating layer (GD) may be formed on the upper surface and the lower surface of the active layer (ACT).

[0023] The active layer (ACT) may include a semiconductor material or an oxide semiconductor material. For example, the active layer (ACT) may include single-crystal silicon, germanium, silicon-germanium, or IGZO (Indium Gallium Zinc Oxide). The active layer (ACT) may include polysilicon or single-crystal silicon. The active layer (ACT) may include a channel (CH), a first source / drain region (SR) between the channel (CH) and a bit line (BL), and a second source / drain region (DR) between the channel (CH) and a capacitor (CAP). The channel (CH) may be defined between the first source / drain region (SR) and the second source / drain region (DR).

[0024] The first source / drain region (SR) and the second source / drain region (DR) may be doped with impurities of the same conductivity type. The first source / drain region (SR) and the second source / drain region (DR) may be doped with N-type impurities or P-type impurities. The first source / drain region (SR) and the second source / drain region (DR) may contain at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first side of the first source / drain region (SR) may be in contact with the bit line (BL), and the second side of the first source / drain region (SR) may be in contact with the channel (CH). The first side of the second source / drain area (DR) may be in contact with the storage node (SN), and the second side of the second source / drain area (DR) may be in contact with the channel (CH). The horizontal length of the channel (CH) along the second direction (D2) may be smaller than the horizontal length of the first and second source / drain areas (SR, DR) along the second direction (D2). In another embodiment, the horizontal length of the channel (CH) along the second direction (D2) may be larger than the horizontal length of the first and second source / drain areas (SR, DR) along the second direction (D2).

[0025] The transistor (TR) is a cell transistor and may have a double word line (DWL). In the double word line (DWL), the first word line (WL1) and the second word line (WL2) may have the same potential. For example, the first word line (WL1) and the second word line (WL2) may form a pair, and the same word line driving voltage may be applied to the first word line (WL1) and the second word line (WL2). In this way, the memory cell (MC) according to the present embodiment may have a double word line (DWL) in which two first and second word lines (WL1, WL2) are adjacent in one channel (CH).

[0026] In another embodiment, the first word line (WL1) and the second word line (WL2) may have different potentials. For example, a word line driving voltage may be applied to the first word line (WL1), and a ground voltage may be applied to the second word line (WL2). The second word line (WL2) may be referred to as a back word line or a shield word line. In another embodiment, a ground voltage may be applied to the first word line (WL1), and a word line driving voltage may be applied to the second word line (WL2).

[0027] The active layer (ACT) may have a thickness thinner than the first and second word lines (WL1, WL2). To elaborate, the vertical thickness of the active layer (ACT) along the first direction (D1) may be thinner than the vertical thickness of each of the first and second word lines (WL1, WL2) along the first direction (D1). Thus, the thin active layer (ACT) may be referred to as a thin-body active layer. The thin active layer (ACT) may include a thin-body channel (CH), and the thickness of the thin-body channel (CH) may be 10 nm or less. In another embodiment, the channel (CH) may have the same vertical thickness as the first and second word lines (WL1, WL2).

[0028] The gate insulating layer (GD) may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, anti-ferroelectric material, or a combination thereof. The gate insulating layer (GD) may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or HfZrO.

[0029] The double word line (DWL) may include a metal, a metal mixture, a metal alloy, or a semiconductor material. The double word line (DWL) may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the double word line (DWL) may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The double word line (DWL) may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of 4.5 eV or less, and the P-type work function material may have a high work function of 4.5 eV or more.

[0030] A capacitor (CAP) may be horizontally positioned along a second direction (D2) from a transistor (TR). The capacitor (CAP) may include a storage node (SN) that extends horizontally from an active layer (ACT) along the second direction (D2). The capacitor (CAP) may further include a dielectric layer (DE) and a plate node (PN) on the storage node (SN). The storage node (SN), the dielectric layer (DE), and the plate node (PN) may be horizontally arranged along the second direction (D2). The storage node (SN) may be a horizontally oriented cylinder shape. The dielectric layer (DE) may conformally cover the inner wall and outer wall of the cylinder of the storage node (SN). The plate node (PN) may be a shape that extends from the dielectric layer (DE) to the inner wall and outer wall of the cylinder of the storage node (SN). A plate node (PN) can be connected to a plate line (PL). A storage node (SN) can be electrically connected to a second source / drain area (DR).

[0031] The storage node (SN) has a three-dimensional structure, and the storage node (SN) of the three-dimensional structure may be a horizontal three-dimensional structure oriented along the second direction (D2). As an example of the three-dimensional structure, the storage node (SN) may have a cylinder shape. In another embodiment, the storage node (SN) may have a pillar shape or a cylinder shape. A cylinder shape may refer to a structure in which a pillar shape and a cylinder shape are merged.

[0032] The storage node (SN) and the plate node (PN) may comprise metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the storage node (SN) and the plate node (PN) may comprise titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, and tungsten nitride / tungsten (WN / W) stacks. The plate node (PN) may also comprise a combination of metal-based materials and silicon-based materials. For example, the plate node (PN) may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-fill material that fills the inside of the cylinder of the storage node (SN) on the titanium nitride, titanium nitride (TiN) may serve as the plate node (PN) of the capacitor (CAP), and tungsten nitride may be a low-resistance material.

[0033] The dielectric layer (DE) may comprise silicon oxide, silicon nitride, a high dielectric constant material, or a combination thereof. The high dielectric constant material may have a dielectric constant higher than that of silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and the dielectric layer (DE) may comprise a high dielectric constant material having a dielectric constant of 4 or more. The high dielectric constant material may have a dielectric constant of about 20 or more. The high dielectric constant material may comprise hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In another embodiment, the dielectric layer (DE) may be composed of a composite layer comprising two or more layers of the aforementioned high dielectric constant material.

[0034] The dielectric layer (DE) may be formed of zirconium-base oxide (Zr-base oxide). The dielectric layer (DE) may be a stack structure comprising at least zirconium oxide (ZrO2). The stack structure comprising zirconium oxide (ZrO2) may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. A ZA stack may be a structure in which aluminum oxide (Al2O3) is stacked on top of zirconium oxide (ZrO2). A ZAZ stack may be a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3), and zirconium oxide (ZrO2) are sequentially stacked. ZA stacks and ZAZ stacks may be referred to as zirconium oxide-base layers (ZrO2-base layer). In another embodiment, the dielectric layer (DE) may be formed of hafnium-base oxide (Hf-base oxide). The dielectric layer (DE) may be a stack structure comprising at least hafnium oxide (HfO2). The stack structure comprising hafnium oxide (HfO2) may include an HA (HfO2 / Al2O3) stack or an HAH (HfO2 / Al2O3 / HfO2) stack. An HA stack may be a structure in which aluminum oxide (Al2O3) is stacked on top of hafnium oxide (HfO2). An HAH stack may be a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2) are sequentially stacked. An HA stack and an HAH stack may be referred to as a hafnium oxide-base layer (HfO2-base layer). In ZA stacks, ZAZ stacks, HA stacks, and HAH stacks, aluminum oxide (Al2O3) may have a higher band gap energy (hereinafter abbreviated as band gap) than zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a lower dielectric constant than zirconium oxide (ZrO2) and hafnium oxide (HfO2).Accordingly, the dielectric layer (DE) may include a stack of a high dielectric constant material and a high band gap material having a larger band gap than the high dielectric constant material. The dielectric layer (DE) may include silicon oxide (SiO2) as a high band gap material other than aluminum oxide (Al2O3). Leakage current can be suppressed by including the high band gap material in the dielectric layer (DE). The high band gap material may be thinner than the high dielectric constant material. In another embodiment, the dielectric layer (DE) may include a laminated structure in which the high dielectric constant material and the high band gap material are alternately stacked. For example, it may include a ZAZA(ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ(ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA(HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH(HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In such a laminate structure, the aluminum oxide (Al2O3) may be thinner than the zirconium oxide (ZrO2) and the hafnium oxide (HfO2).

[0035] In another embodiment, the dielectric layer (DE) may include a stack structure, a laminate structure, or a mutual mixing structure comprising zirconium oxide, hafnium oxide, and aluminum oxide.

[0036] In another embodiment, the dielectric layer (DE) may include a ferroelectric material or an antiferroelectric material.

[0037] In another embodiment, an interface control layer (not shown) for improving leakage current may be further formed between the storage node (SN) and the dielectric layer (DE). The interface control layer may include titanium oxide (TiO2), niobium oxide, or niobium nitride. The interface control layer may also be formed between the plate node (PN) and the dielectric layer (DE).

[0038] The capacitor (CAP) may include a Metal-Insulator-Metal (MIM) capacitor. The storage node (SN) and the plate node (PN) may include a metal-base material.

[0039] The capacitor (CAP) may be replaced with other data storage materials. For example, the data storage material may be a phase change material, a Magnetic Tunnel Junction (MTJ), or a variable resistor material.

[0040] A bit line contact node (BLC) may be formed between the first source / drain region (SR) of the active layer (ACT) and the bit line (BL). A storage contact node (SNC) may be formed between the second source / drain region (DR) of the active layer (ACT) and the storage node (SN) of the capacitor (CAP). The storage contact node (SNC) and the bit line contact node (BLC) may be extended vertically along the first direction (D1). The bit line contact node (BLC) and the storage contact node (SNC) may be extended to be formed on the upper and lower surfaces of both ends of the active layers (ACT). The bit line contact node (BLC) and the storage contact node (SNC) may have a height that fully covers the sides of both ends of the active layer (ACT). The combination of the bit line contact node (BLC) and the first source / drain region (SR) may form a horizontal T-shape. The combination of the storage contact node (SNC) and the second source / drain region (DR) can form a horizontal T-shape. The bit line contact node (BLC) and the storage contact node (SNC) can cover the upper surface, the lower surface, and one side of one end of the active layer (ACT). The bit line contact node (BLC) and the storage contact node (SNC) may be doped polysilicon, for example, polysilicon containing n-type impurities such as phosphorus. The first and second source / drain regions (SR, DR) may contain impurities diffused from the bit line contact node (BLC) and the storage contact node (SNC).

[0041] FIG. 3 is a schematic perspective view of a semiconductor device according to another embodiment. FIG. 4 is a schematic cross-sectional view of a vertical memory cell array (MCA_C) of FIG. 3.

[0042] Referring to FIGS. 3 and 4, the semiconductor device (110) may include a memory cell array (MCA). The memory cells (MC) of FIG. 1 may be arranged in first to third directions (D1, D2, D3) to form the memory cell array (MCA) of FIG. 3. The memory cell array (MCA) may include a three-dimensional array of memory cells (MC), and the three-dimensional memory cell array may include a vertical memory cell array (MCA_C) and a horizontal memory array (MCA_R). The vertical memory cell array (MCA_C) may refer to an array of memory cells (MC) arranged vertically along the first direction (D1). The horizontal memory cell array (MCA_R) may refer to an array of memory cells (MC) arranged horizontally along the third direction (D3). A vertical memory cell array (MCA_C) can be referred to as a column array of memory cells (MC), and a horizontal memory cell array (MCA_R) can be referred to as a row array of memory cells (MC). Bit lines (BL) can be oriented vertically so as to be connected to the vertical memory cell array (MCA_C), and double word lines (DWL) can be oriented horizontally so as to be connected to the horizontal memory cell array (MCA_R). Bit lines (BL) connected to the vertical memory cell array (MCA_C) can be referred to as common bit lines (Common BL), and adjacent vertical memory cell arrays (MCA_C) along the third direction (D3) can be connected to different common bit lines. A double word line (DWL) connected to a horizontal memory cell array (MCA_R) can be referred to as a common double word line (Common DWL), and adjacent horizontal memory cell arrays (MCA_R) along a first direction (D1) can be connected to different common double word lines.

[0043] A memory cell array (MCA) may include a plurality of memory cells (MC), and an individual memory cell (MC) may include a vertically oriented bit line (BL), a horizontally oriented active layer (ACT), a double word line (DWL), and a horizontally oriented capacitor (CAP). For example, FIG. 3 illustrates a three-dimensional DRAM memory cell array composed of four memory cells (MC).

[0044] In one bit line (BL), adjacent active layers (ACTs) may be in contact along the first direction (D1). Adjacent active layers (ACTs) along the third direction (D3) may share a double word line (DWL). Capacitors (CAPs) may be connected to each of the active layers (ACTs). The capacitors (CAPs) may share a single plate line (PL). An individual active layer (ACT) may be thinner than the first and second word lines (WL1, WL2) of the double word line (DWL).

[0045] A memory cell array (MCA) may have a plurality of double word lines (DWL) stacked vertically along a first direction (D1). Each double word line (DWL) may include a pair of a first word line (WL1) and a second word line (WL2). Between the first word line (WL1) and the second word line (WL2), a plurality of active layers (ACT) may be arranged horizontally spaced apart from each other along a third direction (D2). A channel (CH) of the active layer (ACT) may be located between the first word line (WL1) and the second word line (WL2).

[0046] The semiconductor device (110) may further include a substructure (LS), and the substructure (LS) may include a substrate or a peripheral circuit portion. Bit lines (BL) of the memory cell array (MCA) may be oriented perpendicularly along a first direction (D1) with respect to the surface of the substructure (LS), and double word lines (DWL) may be oriented parallel to the surface of the substructure (LS) with respect to a third direction (D3).

[0047] If the substructure (LS) includes a peripheral circuit, the peripheral circuit may be located at a lower level than the memory cell array (MCA). This may be referred to as a Cell over Peri-Field (COP) structure. The peripheral circuit may include at least one control circuit for driving the memory cell array (MCA). At least one control circuit of the peripheral circuit may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit may include an address decoder circuit, a read circuit, a write circuit, etc. At least one control circuit of the peripheral circuit may include a planar channel transistor, a recess channel transistor, a buried gate transistor, a fin channel transistor (FinFET), etc.

[0048] In another embodiment, the semiconductor device (110) may have peripheral circuitry located at a higher level than the memory cell array (MCA). This may be referred to as a POC (PERI over Cell) structure.

[0049] FIG. 5 is a schematic cross-sectional view of a semiconductor device (200) according to another embodiment.

[0050] Referring to FIG. 5, the semiconductor device (200) may be similar to the memory cell array (MCA_C) of FIG. 4. Further details regarding redundant components will be omitted below.

[0051] The semiconductor device (200) may include a substructure (LS), a bit line (BL'), a transistor (TR), and a capacitor (CAP). The transistor (TR) may include a double word line (DWL) and an active layer (ACT). A bit line contact node (BLC') may be formed between a first source / drain region (SR) of the active layer (ACT) and the bit line (BL'). A storage contact node (SNC') may be formed between a second source / drain region (DR) of the active layer (ACT) and a storage node (SN) of the capacitor (CAP). The bit line contact node (BLC') and the storage contact node (SNC') may be doped polysilicon, for example, polysilicon containing n-type impurities such as phosphorus.

[0052] The bit line contact node (BLC') and the storage contact node (SNC') can be extended to be formed on the upper and lower surfaces of both ends of the active layers (ACT). The combination of the bit line contact node (BLC') and the first source / drain region (SR) can form a horizontal T-shape. The bit line contact node (BLC') can cover the upper surface, the lower surface, and one side of one end of the active layer (ACT).

[0053] A bit line contact node (BLC') may include a first part (P1) and second parts (P2). The first part (P1) may directly contact one end of the active layer (ACT), and the second parts (P2) may extend from the first part (P1) to partially cover one end of the active layer (ACT). A storage contact node (SNC') may also have the same structure as the bit line contact node (BLC').

[0054] The bit line (BL') may include a vertical extension (P11) and a protrusion (P12). The protrusion (P12) may be located between the vertical extension (P11) and the bit line contact node (BLC'). The vertical extension (P11) may be shared by memory cells (MC), and the protrusion (P12) may be formed independently on a memory cell (MC) basis.

[0055] A body insulating layer (BDL) may be formed on the substructure (LS), and the body insulating layer (BDL) and the bit line (BL') may be in direct contact. The bit line (BL') may extend vertically from the body insulating layer (BDL). The body insulating layer (BDL) may include an insulating material such as silicon oxide.

[0056] FIGS. 6 to 19 are drawings for illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. FIGS. 6 to 19 may be an example of a method for manufacturing the semiconductor device (200) of FIG. 5.

[0057] As illustrated in FIG. 6, a stack body (15) may be formed on a substrate (10). The substrate (10) may include a semiconductor substrate. The stack body (15) may have sub-stacks stacked alternately. Here, the sub-stacks may include insulating layers (11), sacrificial layers (12, 14), and active layers (13). The topmost material of the stack body (15) may be an insulating layer (11). The sacrificial layers (12, 14) may include first sacrificial layers (12) and second sacrificial layers (14). The first sacrificial layers (12) and second sacrificial layers (14) may be located between the insulating layers (11), and the active layers (13) may be located between the first sacrificial layers (12) and the second sacrificial layers (14). The insulating layers (11) may include silicon oxide, and the sacrificial layers (12, 14) may include silicon nitride. The active layers (13) may include a semiconductor material or an oxide semiconductor material. The active layers (13) may include single-crystal silicon, polysilicon, or IGZO. In another embodiment, as a method for forming a stack body (15), after alternately stacking a single-crystal silicon layer and a silicon germanium layer, the silicon germanium layer may be replaced with a stacked structure of silicon nitride and silicon oxide. Here, the single-crystal silicon layer may correspond to the active layers (13), the substituted silicon nitride may correspond to the sacrificial layers (12, 14), and the substituted silicon oxide may correspond to the insulating layers (11).

[0058] Next, a portion of the stack body (15) can be etched to form a first opening (16). The first opening (16) may be a hole shape that penetrates vertically through the stack body (15). The first opening (16) may extend into the interior of the substrate (10). To extend the first opening (16), a portion of the substrate (10) may be etched.

[0059] Although not illustrated, a plurality of active layers (13) may be formed between the sacrificial layers (12, 14). For example, similar to the active layer (ACT) illustrated in FIG. 3, a plurality of active layers (13) may be arranged horizontally in the same plane. For example, the step of forming a plurality of active layers (13) may include the step of forming a stack body (15) such that the sacrificial layers (12, 14) are located between the insulating layers (11) and a planar semiconductor layer is located between the sacrificial layers (12, 14); the step of etching the stack body (15) to form a plurality of device isolation holes (not illustrated); and the step of recess etching the planar semiconductor layer through the device isolation holes to form a plurality of semiconductor layer patterns arranged horizontally between the sacrificial layers (12, 14).

[0060] As shown in FIG. 7, the active layers (13) can be selectively etched to form recesses (17). A portion of the sacrificial layers (12, 14) may be exposed by the recesses (17).

[0061] While recessing the active layers (13), a body recess (18) may be formed in the substrate (10). The width of the body recess (18) may be larger than the width of the first opening (16).

[0062] As illustrated in FIGS. 8 and 9, cap layers (19) can be formed to fill the recesses (17). For example, the cap layers (19) can be formed by the deposition and etch-back of silicon nitride (19A). A body spacer (19B) can be formed on the side wall of the body recess (18) by the etch-back of silicon nitride (19A). The body spacer (19B) can partially expose the bottom surface of the body recess (18).

[0063] As illustrated in FIG. 10, the insulating layers (11) can be horizontally recessed to a certain depth from the first opening (16). Accordingly, edge recesses (20) that expose parts of the sacrificial layers (12, 14) can be formed.

[0064] As illustrated in FIG. 11, a body protective layer (21) that partially fills the body recess (18) may be formed. The body protective layer (21) may have an etch selectivity with respect to the body spacer (19B). The body protective layer (21) and the body spacer (19B) may be made of different materials. The body protective layer (21) may include silicon oxide.

[0065] The method of forming the body protective layer (21) may include the following two methods.

[0066] In the first method, an oxidation process may be performed to form a body protective layer (21).

[0067] A second method can form a body protective layer (21) using Area Selective Deposition (ASD). That is, the body protective layer (21) can be selectively deposited using Area Selective Deposition (ASD) instead of an oxidation process.

[0068] As illustrated in FIG. 12, the sacrificial layers (12, 14) can be recessed. Accordingly, gate recesses (22) can be formed on the upper and lower sides of the active layers (13), respectively. While removing the sacrificial layers (12, 14), the body spacer (19B) and the cap layers (19) can also be removed. As the cap layers (19) and the sacrificial layers (12, 1) are recessed, one end (23) of the active layers (13) can be exposed.

[0069] As illustrated in FIG. 13, gate insulating layers (24) can be formed on the exposed portions of the active layers (13). The gate insulating layers (24) can be optionally formed on the surfaces of the active layers (13) by an oxidation process. In another embodiment, the gate insulating layers (24) can be formed by a deposition process, in which case the gate insulating layers (24) can be formed on the surface of the gate recesses (23) and on the active layers (13).

[0070] A first body liner (24A) may be formed on the surface of the body recess (18) while forming the gate insulating layers (24). The first body liner (24A) may be optionally formed on the surfaces of the body recess (18) by an oxidation process. A body protective layer (21) may remain on the bottom surface of the body recess (18).

[0071] Next, double word lines (25) can be formed by filling each of the gate recesses (23) with a conductive material. The double word lines (25) may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the step of forming the double word lines (25) may include conformally depositing titanium nitride, depositing tungsten on the titanium nitride to fill the gate recesses (23), and etching back the titanium nitride and tungsten. The double word lines (25) may partially fill the gate recesses (23), thereby exposing a portion of the gate insulating layers (24). Individual double word lines (25) may face each other perpendicularly with an individual active layer (13) in between. In other embodiments, a single word line or a gate-all-around word line may be formed in place of the double word lines (25).

[0072] According to FIGS. 6 to 13 described above, a portion of the first sacrifice layers (12) and a portion of the second sacrifice layers (14) can be replaced with a double word line (25).

[0073] As illustrated in FIG. 14, liner layers (26) can be formed in contact with one side of the double word lines (25). The liner layers (26) may be located within the gate recesses (23). The liner layers (26) may comprise silicon oxide or silicon nitride. The liner layers (26) may expose a portion of the gate recesses (23). That is, a void (or air gap) may be formed on one side of the liner layers (26). For example, the liner layers (26) may be formed by a deposition and etch-back process of silicon oxide (26A). A second body liner (26L) may be formed while forming the liner layers (26).

[0074] The body insulating layer (BDL) may include a body protective layer (21), a first body liner (24A), and a second body liner (26L). The first body liner (24A) and the second body liner (26L) may include silicon oxide, and the body protective layer (21) may include silicon nitride.

[0075] Next, a portion of the gate insulating layer (24) exposed by the liner layers (26) can be etched to expose the ends (23) of the active layers (13).

[0076] As illustrated in FIG. 15, a conductive layer (27A) containing impurities may be formed. The conductive layer (27A) may be polysilicon containing n-type impurities such as phosphorus. A portion of the conductive layer (27A) may fill a void provided on one side of the liner layers (26). The conductive layer (27A) may be in direct contact with the ends (23) of the active layers (13).

[0077] Although not illustrated, heat treatment may be performed after the formation of the conductive layer (27A). Through this heat treatment, impurities may diffuse from the conductive layer (27A) into one end of the active layers (13). The diffused impurities may form the first source / drain region (SR) of FIGS. 1 to 5.

[0078] As illustrated in FIG. 16, the conductive layer (27A) can be recessed to form contact nodes (27). The contact nodes (27) can fill the empty space provided on one side of the liner layers (26). The contact nodes (27) can be extended to be formed on the upper and lower surfaces of one end (23) of the active layers (13). The combination of the contact nodes (27) and the active layers (13) can form a horizontal T-shape. The contact nodes (27) can cover the upper surface, the lower surface, and one side of one end (23) of the active layers (13). The contact nodes (27) may be referred to as bit line contact nodes or storage contact nodes. The contact nodes (27) may correspond to the bit line contact nodes (BLC, BLC') of FIGS. 1 through 5.

[0079] As illustrated in FIG. 17, a conductive line (28) connected to contact nodes (27) can be formed. The conductive line (28) may be referred to as a vertical conductive line. The conductive line (28) may be a metal-base material. The conductive line (28) may correspond to the bit lines (BL, BL') of FIG. 1 through 5. The conductive line (28) may be in direct contact with the body protection layer (21) and may extend vertically over the body protection layer (21). The contact nodes (27) may be connected in common to the conductive line (28). The substrate (10) and the conductive line (28) may be electrically separated from each other by a body insulating layer (BDL), i.e., the body protection layer (21), the first body liner (24A), and the second body liner (26L).

[0080] As illustrated in FIG. 18, a different part of the stack body (15) can be etched to form second openings (29). Next, the sacrificial layers (12, 14) and active layers (13) can be recessed through the second openings (29). Accordingly, capacitor openings (30) can be formed.

[0081] A double word line (25) may be formed with individual active layers (13) in between, and gate insulating layers (24) may be formed between the double word line (25) and the individual active layers (13). Contact nodes (27) may be connected to one end of the active layers (13). Liner layers (26) may be formed between the contact nodes (27) and one side of the double word line (25). Sacrificial layers (12, 14) may remain on the other side of the double word line (25).

[0082] Although not illustrated, after forming the capacitor openings (30), deposition and heat treatment of polysilicon doped with n-type impurities may be performed. Accordingly, impurities may diffuse into the other end of the active layers (13). The diffused impurities may form the second source / drain region (DR) of FIGS. 1 to 5. The polysilicon doped with n-type impurities may be etched to remain in the shape of the contact nodes (27) of FIG. 16. The polysilicon doped with n-type impurities may correspond to the storage contact nodes (SNC, SNC') of FIGS. 1 to 5.

[0083] As shown in FIG. 19, capacitors, namely a storage node (31), a dielectric layer (32), and a plate node (33), can be formed sequentially.

[0084] The bit line (28) may include a contact pad surface (28A) covered by a body insulating layer (BDL) and a bonding pad surface (28B) facing the contact pad surface (28A).

[0085] According to FIGS. 6 to 19 described above, the semiconductor device may include a substrate (10), a body recess (18) formed on the substrate (10), a body insulating layer (BDL) formed on the body recess (18), an active layer (13) extended along a direction parallel to the substrate (10) on the upper side of the substrate (10), a contact node (27) formed vertically on the side of the end of the active layer (13), and a bit line (28) connected to the contact node (27) and extended vertically from the body insulating layer (BDL).

[0086] The above-described embodiments form a body insulating layer (BDL) only at the bottom of the bit line (28) regardless of the memory cell structure, thereby preventing electrical bridging between the bit line (28) and the substrate (10), and thus enabling control of leakage current to the substrate (10). In addition, electrical bridging between adjacent bit lines (28) can be prevented.

[0087] FIGS. 20 to 24 are drawings for explaining an example of a method for manufacturing a semiconductor device according to another embodiment. FIGS. 20 to 24 illustrate a method of connecting a memory cell array and a peripheral circuit by wafer bonding.

[0088] Following FIG. 19, as illustrated in FIG. 20, a plurality of first bonding pads (BP1) and first bonding insulating layers (BP11) can be formed. The first bonding pads (BP1) can be connected to a bit line (28) and a plate node (33). The first bonding insulating layer (BP11) can be located between the first bonding pads (BP1). The first bonding insulating layer (BP11) can expose the surface of the first bonding pads (BP1).

[0089] The substrate (10) can be flipped to change the positions of the bit line (28) and the capacitors (CAP). Accordingly, the first bonding pads (BP1) and the first bonding insulating layer (BP11) can be located below the memory cell array (MCA). The memory cell array (MCA) can be formed according to FIGS. 6 through 19. The substrate (10) can be abbreviated as 'first substrate (10)', and the storage node (31), dielectric layer (32), and plate node (33) can constitute the capacitor (CAP).

[0090] The bit line (28) may include a contact pad surface (28A) covered by a body insulating layer (BDL) and a bonding pad surface (28B) facing the contact pad surface (28A).

[0091] Next, a peripheral circuit section (PERI) can be prepared. The peripheral circuit section (PERI) may include a second substrate (40) and peripheral circuit transistors (41). The peripheral circuit section (PERI) may further include a multilayer level metal wiring (UM), and the multilayer level metal wiring (UM) may be connected to the peripheral circuit transistors (41). The peripheral circuit transistors (41) may be part of a sense amplifier. Although not illustrated, the peripheral circuit section (PERI) may further include a multilayer level metal wiring connected to plate nodes (33) and peripheral circuit transistors connected to the multilayer level metal wiring. Although not illustrated, the peripheral circuit section (PERI) may further include a multilayer level metal wiring connected to double word lines (25) and sub-word line drivers connected to the multilayer level metal wiring.

[0092] A plurality of second bonding pads (BP2) and second bonding insulating layers (BP12) can be formed. The second bonding pads (BP2) can be connected to multilayer level metal wiring (UM) of the peripheral circuit section (PERI). The second bonding insulating layer (BP12) can be located between the second bonding pads (BP2). The second bonding insulating layer (BP12) can expose the surface of the second bonding pads (BP2).

[0093] The first and second bonding pads (BP1, BP2) may comprise a metal-base material. The first and second bonding insulating layers (BP11, BP12) may comprise silicon oxide, silicon nitride, or a combination thereof.

[0094] The memory cell array (MCA) can be located on top of the peripheral circuit section (PERI).

[0095] As illustrated in FIG. 21, the memory cell array (MCA) and the peripheral circuit (PERI) can be interconnected by wafer bonding, that is, by first bonding pads (BP1) and second bonding pads (BP2). Additionally, the first bonding insulating layer (BP11) and the second bonding insulating layer (BP12) can be bonded. Wafer bonding can utilize metal-to-metal bonding, hybrid bonding, etc. Metal-to-metal bonding may refer to the bonding of the first bonding pads (BP1) and the second bonding pads (BP2). Hybrid bonding may refer to a bonding method that further includes the bonding of the first and second bonding insulating layers (BP11, BP12) in addition to metal-to-metal bonding. The bonding pad surface (28B) of the bit line (28) can be connected to the peripheral circuit (PERI) by the first bonding pads (BP1) and the second bonding pads (BP2).

[0096] As described above, after forming the peripheral circuit portion (PERI) and the memory cell array (MCA) separately, they can be bonded using wafer bonding. During the wafer bonding process, a body insulating layer (BDL) can be applied as a material to protect the bit line (28).

[0097] As illustrated in FIG. 22, the first substrate (10) can be selectively stripped. At this time, the stripping process of the first substrate (10) may utilize wet etching that can selectively strip silicon. During the wet etching of the first substrate (10), the body insulating layer (BDL) can act as a barrier for the wet etching, thereby preventing attacks on the bit line (28).

[0098] As illustrated in FIG. 23, a front insulating layer (50) can be formed to fill the space from which the first substrate (10) has been removed. The front insulating layer (50) may include silicon oxide. The front insulating layer (50) may not expose the body insulating layer (BDL).

[0099] As illustrated in FIG. 24, a conductive pad, for example, a bit line pad (51), can be formed that penetrates the front insulating layer (50) and is connected to the bit line (28). The bit line pad (51) can penetrate a part of the body insulating layer (BDL), for example, the body protective layer (21). The bit line pad (51) may include a metal-base material.

[0100] According to FIGS. 20 to 24, the memory cell array (MCA) may include a second substrate (40) including a peripheral circuit portion (PERI), a vertical conductive line, i.e., a bit line (28), including a contact pad surface (28A) and a bonding pad surface (28B), a first bonding pad (BP1) connected to the bonding pad surface (28B) of the bit line (28), a second bonding pad (BP2) located above the peripheral circuit portion (PERI) and connected to the first bonding pad (BP1), a body insulating layer (BDL) covering the contact pad surface (28A) of the bit line (28), and a bit line pad (51) connected to the contact pad surface (28A) of the bit line (28) by penetrating the body insulating layer (BDL).

[0101] According to FIGS. 20 to 24, a method for manufacturing a semiconductor device may include the steps of: forming a memory cell array (MCA) comprising a first substrate (10) including a body insulating layer (BDL) and a bit line (28) including a contact pad surface (28A) covered by the body insulating layer (BDL) and a bonding pad surface (28B) facing the contact pad surface (28A); forming a second substrate (40) including a peripheral circuit portion (PERI); flipping the first substrate (10) to bond the bonding pad surface (28B) of the bit line (28) with the peripheral circuit portion (PERI); selectively removing the first substrate (10); and forming a bit line pad (51) connected to the contact pad surface (28A) of the bit line (28). The body insulating layer (BDL) may include a body protective layer (21) covering the contact pad surface (28A) of the bit line (28) and first and second body liners (24A, 26L).

[0102] It will be obvious to those skilled in the art that the present invention is not limited by the aforementioned embodiments and attached drawings, and that various substitutions, modifications, and changes are possible within the scope of the technical concept of the present invention. Explanation of the symbols

[0104] DWL: Double Word Line ACT: Active Layer GD: Gate insulation layer CH: Channel SR: 1st Source / Drain Area DR: 2nd Source / Drain Area BL : Bit line TR : Transistor CAP: Capacitor SN: Storage Node DE: Dielectric layer PN: Plate node PL: Plate line WL1: 1st word line WL2: Second word line MCA: Memory cell array MC: Memory cell BDL: Body insulation layer SNC, SNC' : Storage Contact Node BLC, BLC' : Bit line contact node

Claims

Claim 1 A semiconductor device comprising: a substrate; a body recess formed on the substrate; a body insulating layer formed on the body recess; an active layer extending along a direction parallel to the substrate on the upper surface of the substrate; a contact node formed vertically on the side of one end of the active layer; and a bit line connected to the contact node, extending vertically from the body insulating layer, and including a portion embedded within the substrate. Claim 2 A semiconductor device according to claim 1, wherein the active layer comprises: a channel; and a source / drain region located on one side of the channel and connected to the contact node. Claim 3 In claim 1, the semiconductor device having a height in which the contact node fully covers the side of one end of the active layer. Claim 4 In claim 1, the contact node is a semiconductor device comprising doped polysilicon. Claim 5 A semiconductor device according to claim 1, wherein the active layer comprises single-crystal silicon, polysilicon, germanium, silicon-germanium, or IGZO (Indium Gallium Zinc Oxide). Claim 6 A semiconductor device according to claim 1, further comprising a word line extended along a direction traversing the active layer on the active layer. Claim 7 In claim 6, the word line comprises a double word line, a single word line, or a gate-all-around word line, in a semiconductor device. Claim 8 delete Claim 9 A semiconductor device according to claim 1, wherein the body insulating layer comprises a plurality of silicon oxides formed on the surface of the body recess. Claim 10 A semiconductor device comprising: a body recess formed on a substrate; a body insulating layer formed on the body recess; an active layer extending along a direction parallel to the substrate on the upper side of the substrate and having a first end and a second end; a bit line contact node formed on the side, upper surface and lower surface of the first end of the active layer; a bit line extending vertically from the body insulating layer and connected to the bit line contact node; a storage contact node formed on the side, upper surface and lower surface of the second end of the active layer; and a capacitor connected to the second end of the active layer and the storage contact node. Claim 11 A semiconductor device according to claim 10, wherein the active layer comprises: a channel; a first source / drain region located on one side of the channel and connected to the bit line contact node; and a second source / drain region located on the other side of the channel and connected to the storage contact node. Claim 12 In claim 10, the bit line contact node and the storage contact node are each semiconductor devices comprising doped polysilicon. Claim 13 In claim 10, the above active layer comprises a semiconductor device comprising single-crystal silicon, polysilicon, germanium, silicon-germanium, or IGZO (Indium Gallium Zinc Oxide). Claim 14 In claim 10, the capacitor is a semiconductor device comprising a cylindrical storage node connected to the storage contact node. Claim 15 A semiconductor device according to claim 10, further comprising a word line extended along a direction traversing the active layer. Claim 16 A semiconductor device according to claim 15, wherein the word line comprises a double word line, a single word line, or a gate-all-around word line. Claim 17 In claim 10, the above body insulating layer is a semiconductor device comprising silicon oxide. Claim 18 A semiconductor device comprising: a substrate including a peripheral circuit portion; a memory cell array including a vertical bit line including a contact pad surface and a bonding pad surface; a first bonding pad connected to the bonding pad surface of the vertical bit line; a second bonding pad located above the peripheral circuit portion and connected to the first bonding pad; a body insulating layer covering the contact pad surface of the vertical bit line; and a conductive pad connected to the contact pad surface of the vertical bit line by penetrating the body insulating layer. Claim 19 A semiconductor device according to claim 18, wherein the contact pad surface of the vertical bit line has a protruding shape positioned at a higher level than the memory cell array. Claim 20 In paragraph 18, the above body insulating layer is a semiconductor device comprising silicon oxide. Claim 21 A method for manufacturing a semiconductor device comprising: forming a stack body on a substrate including insulating layers, first sacrificial layers and second sacrificial layers between the insulating layers, and active layers between the first sacrificial layers and the second sacrificial layers; etching the stack body to form an opening; etching the substrate below the opening to form a body recess; forming a body insulating layer on the body recess; replacing the first sacrificial layers and the second sacrificial layers with double word lines; exposing one end of the active layers; forming contact nodes connected to one end of the active layers; and forming a bit line that is commonly connected to the contact nodes, extends vertically over the body insulating layer, and includes a portion embedded within the substrate. Claim 22 A method for manufacturing a semiconductor device according to claim 21, wherein the contact nodes cover the upper surface, lower surface, and one side of one end of the active layers. Claim 23 In claim 21, the above contact nodes are a method for manufacturing a semiconductor device comprising polysilicon. Claim 24 A method for manufacturing a semiconductor device according to claim 21, wherein the step of forming the contact nodes comprises: forming a conductive layer on one end of the active layers; diffusing impurities from the conductive layer to form a source / drain region within one end of the active layers; and selectively etching the conductive layer to form the contact nodes. Claim 25 In claim 21, the first and second sacrificial layers are a method for manufacturing a semiconductor device comprising silicon nitride. Claim 26 In claim 21, the step of forming the body insulating layer is performed by an oxidation process in a method for manufacturing a semiconductor device. Claim 27 In claim 21, the step of forming the body insulating layer is performed by ASD (Area Selective Deposition) in a method for manufacturing a semiconductor device. Claim 28 delete Claim 29 A semiconductor device according to claim 1, wherein the buried portion of the bit line is surrounded by the body insulating layer. Claim 30 A method for manufacturing a semiconductor device according to claim 21, wherein the buried portion of the bit line is surrounded by the body insulating layer.

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