Apparatuses, systems, and methods for invalidating expired memory

Abstract

A device and / or system is described comprising a memory device including a memory range and a time data management unit (TDMU) coupled to the memory device, receiving from an interface a time range corresponding to the validity of the memory range and the data in the memory range, checking the time range against a time and / or date value provided by a timer or clock to identify the data in the memory range as expired, and invalidating the expired data in the memory device. In some embodiments, the TDMU includes hardware logic coupled to the memory module to reside with the memory device and invalidate the expired data when the memory module is disconnected from the interface. Other embodiments may be disclosed and claimed.

Description

Technology Field

[0001] The embodiments of the present disclosure generally relate to the field of integrated circuits (ICs), and in particular, to memory devices. Background Technology

[0002] Data retention and aging policies are becoming increasingly important. For example, there may be requirements not only regarding how long data can be retained, but also that data must be retained for a defined period of time (e.g., for the purposes of preventing, investigating, detecting, and prosecuting criminal offenses). For instance, data subject to such regulations includes, for example, telephone call duration, call recipient information, IP (Internet Protocol) addresses, connection times, and location data for cellular phone connections. Since retention can be determined by various policies (e.g., how / when data is acquired, type / source, and how data should be handled), data handling is required to be dynamic. Data aging policies may require data to be deleted from memory after a certain amount of time has elapsed. For example, in some cases, such as when using persistent memory, data undergoing operations may even remain in memory from time to time. This is because persistence is inherent in the memory itself (e.g., phase-change memories, 3DXPOINT TM This is an inherent property of persistent memories and is due to the use of a persistent medium (material) that does not require a power supply to retain data. In various types of memory (not limited to persistent memories), when power is removed—for example, when a module or drive containing the memory is moved to a different location—the data continues to reside in the memory. Brief explanation of the drawing

[0003] The embodiments will be easily understood from the following detailed description in conjunction with the accompanying drawings. For ease of explanation, similar reference numbers designate similar components. The embodiments are illustrated in the drawings of the accompanying drawings as examples, not as limitations. FIG. 1 is a simplified diagram illustrating an exemplary memory module according to embodiments of the present disclosure. FIG. 2 is a functional diagram including an exemplary memory module similar to the memory module of FIG. 1, according to embodiments of the present disclosure. FIG. 3 is an exemplary data expiration table associated with the embodiment of FIG. 2, according to embodiments of the present disclosure. FIG. 4 is a flowchart illustrating an exemplary process according to embodiments of the present disclosure. FIG. 5 illustrates a computing system according to embodiments of the present disclosure. Specific details for implementing the invention

[0004] In the embodiments described herein, the temporal data management unit (TDMU) receives a memory range of a memory device and a time range corresponding to the validity of data in the memory range. In the embodiments, the memory range is an address range corresponding to memory locations in the memory device. In the embodiments, the memory locations contain data undergoing a data aging policy. In the embodiments, the temporal range includes a time range during which data in the memory locations is valid, and the TDMU includes hardware logic to check the time range against a time value provided by a timer or clock to identify the data in the memory range as expired and to invalidate the expired data in the memory device. In some embodiments, the memory module includes a timer (or clock) and a battery source as well as the TDMU and the memory device. In some embodiments, the TDMU invalidates the expired data when the memory module is disconnected from an interface (e.g., a memory controller or another platform interface).

[0005] In the following description, various aspects of exemplary embodiments will be described using terms commonly adopted by those skilled in the art to convey the substance of the work to other people skilled in the art. However, it will be apparent to those skilled in the art that the embodiments of this disclosure may be practiced by only some of the described aspects. For the purpose of explanation, specific numbers, materials, and configurations are presented to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that the embodiments of this disclosure may be practiced without specific details. In other examples, known features are omitted or simplified so as not to obscure the exemplary embodiments.

[0006] In the following detailed description, reference is made to the accompanying drawings, which form part thereof, where similar numbers designate similar parts throughout, and where embodiments in which the subject matter of the present disclosure can be practiced are illustrated by way of example. It should be understood that other embodiments may be utilized and that structural or logical modifications may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0007] In some cases, various operations will be described in turn as multiple individual operations in a manner most helpful to understanding the present disclosure; however, the order of description should not be interpreted as implying that these operations are necessarily order-dependent. In particular, these operations do not need to be performed in the order presented.

[0008] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), (A) or (B), or (A and B). For the purposes of this disclosure, the phrase “A, B, and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0009] This description may use perspective-based descriptions such as top / bottom, in / out, over / under, and similar terms. These descriptions are used merely to facilitate discussion and are not intended to limit the application of the embodiments described herein in any particular direction.

[0010] This description may use phrases such as "in examples" or "in examples" which may refer to one or more of the same or different embodiments. Additionally, as used for the embodiments of this disclosure, the terms "comprising, including," "having," and similar terms are synonyms.

[0011] The term “coupled with” may be used herein with its derivatives. “Coupled” may mean one or more of the following: “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “Coupled” may also mean that two or more elements are in indirect contact with each other but still interact or cooperate with each other, and that one or more other elements are coupled or connected between the elements referred to as being coupled. Furthermore, it should be understood that the various embodiments depicted in the drawings (“Drawings”) are exemplary representations and are not necessarily depicted in a fixed proportion. For example, note that because memory modules such as DIMMs (dual in line memory modules) can be moved from system to system (resulting in the loss of data aging policies), data aging policies may need to reside with the memory modules. Particularly for persistent memory, a hardware mechanism of fine granularity is required to manage data lifetime. As noted earlier, aging mechanisms can be easily bypassed in software simply by resetting the clock or timer.

[0012] FIG. 1 is a simplified diagram illustrating an exemplary memory module according to an embodiment of the present disclosure. As illustrated in FIG. 1, the memory module (100) comprises a temporal data management unit (TDMU) (101), a clock or timer (103), a battery source (105), and a plurality of memory devices (107) (for clarity of the drawings, only one memory device (107) is labeled). In embodiments, for example, a TDMU (101) including hardware logic resides on the memory module (100) having one or more memory device(s) (107) and, as discussed in more detail with reference to FIG. 2, invalidates expired data when the memory module (100) is disconnected from an interface (e.g., a memory controller interface). In embodiments, the memory module (100) is any suitable memory module or memory board coupled to or integrated with one or more memory devices that store data. In the embodiments, the memory device comprises any volatile or non-volatile memory having a plurality of memory ranges that store data that may be required to be deleted or invalidated according to a memory aging policy. It should be noted that in the context of this disclosure, a data aging policy refers to any instruction, instruction, requirement, or similar characteristic that prevents stored data from being deleted or otherwise inaccessible at a future time and / or date.

[0013] As noted above, in the embodiments, the memory range is an address range (logical or physical address range) describing specific memory locations containing data that undergoes a data aging policy. In the embodiments, the time range indicates the time range during which the data at the memory locations is valid. Thus, in the embodiments, the memory range includes a logical or physical address range identifying specific memory locations that store data to be invalidated upon expiration, for example. In some embodiments, the memory range includes a starting physical memory address and the length of the address range. In the embodiments, the memory module (100) is a dual-in-line-memory module (DIMM).

[0014] In the embodiments, the battery source (105) is charged when the memory module (100) is coupled to an interface of a platform such as a memory controller or a host system (see, for example, FIG. 5). Thus, in the embodiments, the battery source (105) provides power to the timer (103) and can continue to provide power to the timer (103) when there is no power supply from the host system computer. As further discussed below, in the embodiments, the timer (103) provides a current time value to determine whether the time range for the validity of the data has expired. In the embodiments, the current time value may be checked against a timestamp associated with the memory range, where the timestamp indicates the initial time of data storage. In the embodiments, note that the memory device (107) contained on the DIMM is discussed in more detail in relation to FIG. 5 and includes, for example, any suitable type of non-volatile (NVM) memory containing data to be invalidated due to a data aging policy. In other embodiments, the TDMU does not need to be located on a memory unit such as a memory module board, but may be coupled to any memory device that includes, for example, any suitable type of non-volatile (NVM) memory that stores data to be invalidated due to a data aging policy. In various embodiments, the TDMU may be located on a memory drive or may be embedded memory in a processor.

[0015] FIG. 2 is a simplified functional diagram illustrating an environment including a memory module according to embodiments of the present disclosure. As illustrated, the memory module (200) is similar to the memory module (100) of FIG. 1 and includes a TDMU (201), a timer (203), and a battery (205). A plurality of data in memory range blocks (209) represents actual data itself stored in a memory medium of a memory device (e.g., memory device (107) of FIG. 1). In embodiments, the TDMU (201) is coupled to an interface (215) (e.g., a memory controller interface) and / or a system address decoder (211).

[0016] In embodiments, the system address decoder (211) is implemented by the hardware logic of the TDMU (201). In other embodiments, the system address decoder (211) is included or implemented by a memory controller outside the DIMM. In embodiments, the TDMU (201) includes hardware logic that receives from the interface (215) a memory range and a time range corresponding to the validity of the data in the memory range (e.g., data in memory range blocks (209)). In embodiments, the time range includes a time range or other information from which the expiration date for the data stored in the memory range can be determined. For example, in some embodiments, the time range includes how many time units (e.g., milliseconds (ms), seconds, or hours, and units that are numbers (e.g., 10)) the corresponding data in the memory range will be valid for. In embodiments, the time range is a time-to-live (TTL) value. In the embodiments, the memory range and time range are represented by a memory mapping function, e.g., mmap(*addr, length,..., TTL), which includes at least a memory address, a length, and a TTL value. For example, if the data is to be deleted after 17,520 hours (one year in the calendar) and the unit is one hour, when the TDMU (201) checks the time range using the current time and / or date, it may sequentially decrement the time value for each time elapsed from the timestamp associated with the storage of the data to determine whether the data has expired.

[0017] Note that, as illustrated in FIG. 2, the TDMU (201) monitors the expiration table (213) to identify expiration dates and which action should be taken in the expiration table (213). Accordingly, in embodiments, the TDMU (201) checks the time range for the timer to identify the data in the memory range as expired, and then invalidates the expired data in the memory device. In embodiments, the TDMU (201) includes hardware logic including circuits and firmware and / or circuits that are coupled to the memory device (107) to perform operations associated with invalidating the expired data (e.g., see actions associated with FIG. 3) and / or issue commands to the memory device (107) to perform the same. In embodiments, the time range is a time-to-live (TTL) value, and when the TTL value expires, the data in the memory range (209) is identified as expired. Note that in the embodiments, the clock or timer (203) tracks the current date and time for the start time associated with the storage or data or timestamp and can be implemented without the option to be reset for security reasons.

[0018] In the embodiments, as further discussed below, the TDMU (201) invalidates expired data using any suitable method to ensure that the expired data cannot be accessed, such as, for example, marking a memory range as expired with a metadata flag, and / or clearing or zeroing out the memory range encryption key, or forcibly writing zeros to a data location that may be stored in the memory device (107).

[0019] As mentioned in relation to FIG. 2, in other embodiments, the TDMU (201) may be implemented by a memory controller rather than by a memory module, for example, the DIMM board itself. Accordingly, in other embodiments, a system address decoder (211) located in a combined memory controller of a central processing unit (CPU) can monitor an expiration table (213) to identify whether data in a memory range has expired and which action should be taken in the expiration table (213).

[0020] FIG. 3 is an exemplary data expiration table associated with the embodiment of FIG. 2, according to embodiments of the present disclosure. The data expiration table (313) may be similar or identical to the data expiration table (213) of FIG. 2. In some embodiments, the data expiration table is stored in a section of a memory device (e.g., memory device (107) of FIG. 1) reserved for the data expiration table or other information related to tracking data to be invalidated. As illustrated, the data expiration table (313) includes three columns: a memory range (321), an expiration time stamp (323), and an action (325). Note that the data expiration table is merely an example and may include fewer or more elements suitable for assisting the TDMU (201) in determining which data should be invalidated. In embodiments, the memory range (321) is a column for identifiers, e.g., identifier (326), each of which uniquely tracks an address range and is associated with a specific data set. In this example, the identifier (326) includes, for example, a Universally Unique Identifier (UUID). In embodiments, the identifier (326) corresponds to a definition of how long the data should exist and an appropriate action upon expiration. For example, as illustrated, the identifier (326) corresponds to a timestamp in a column of expiration timestamps (323) from which the expiration date is determined, and an action (325), for example, a wipe (327). In embodiments, it should be noted that the timestamp does not need to be synchronized with a network time protocol (NTP) or a similar standard time reference. In embodiments, the action (325) includes, for example, an action taken on the expired data in an address range to invalidate the expired data.For example, the wipe (327) may include the deletion of the encryption key for the expired data, as noted above, to effectively wipe the data. Other examples of methods for invalidating data include zeroing (329), for example, forcibly writing zeros into the data location. In embodiments, the interrupt (331) for invalid access includes a command to generate an interrupt acknowledgment to notify the host system that an attempt to access the invalid data has been made. In some embodiments, the expired data to be invalidated is marked as expired with a metadata flag.

[0021] FIG. 4 is a flowchart illustrating an exemplary process (400) performed, for example, by a TDMU (e.g., the TDMU (201) of FIG. 2) to identify data in a memory range as expired and to invalidate the expired data, according to embodiments of the present disclosure. In an embodiment, in the first block (401), the process (400) includes receiving a memory range and a time range of a memory device. In embodiments, the memory range is an address range corresponding to a plurality of memory locations in the memory device, and the time range is a time range during which data stored in the memory locations is valid according to a data aging policy. In embodiments, receiving the memory range and the time range of the memory device may include receiving or retrieving parameters such as a memory address, length, and TTL value stored in an expiration table, for example. Other parameters received may include, for example, what action (e.g., see action (325) of FIG. 3) should be taken once the data exceeds or deviates from the TTL value and is therefore expired.

[0022] In the next block (403), the process (400) includes checking the time range for the time value to identify the data in the memory range as expired according to the data aging policy. In embodiments, the time ranges are checked every n time units (or every cycle) by checking the time value provided by the timer or clock. In some embodiments, upon receiving the memory range and the time range, the TDMU (201) is associated with the storage of the data and receives or records a timestamp from which the time value from the timer can be checked. Furthermore, in some embodiments, for security reasons, the timer or clock is implemented without an option to be reset.

[0023] In the next block (405), the process (405) includes invalidating data that expires in the memory device. In embodiments, the data will be invalidated to comply with the data aging policy. In embodiments, invalidating the data includes issuing a command to the appropriate memory device (e.g., memory device (107)) to take an action or take associated actions, as described, for example, in relation to the action (325) of the expiration table (313) of FIG. 2. In some embodiments, invalidating data that expires in the memory device includes invalidating the data when the memory module is detached from the platform interface. Note that in the various embodiments described above, the TDMU is implemented by the memory controller and can perform the same functions as described above. In some embodiments, the TDMU may include hardware logic coupled to the embedded memory in the processor.

[0024] FIG. 5 illustrates an exemplary electronic device (500) (e.g., a computer, a server, or some other electronic device) that may be suitable for carrying out selected embodiments of the present disclosure. In the embodiments, the system or electronic device (500) comprises one or more memories (504) coupled to a TDMU (555), such as the TDMU described in relation to FIG. 1 through 4, for example. As illustrated, the electronic device (500) may comprise one or more processors or processor cores (502). For the purposes of this application, including the claims, the term “processor” refers to a physical processor, and the terms “processor” and “processor core” may be considered synonyms unless the context clearly requires otherwise. In embodiments, the memories (504) comprise a memory module further comprising a clock or timer coupled to a battery source and a TDMU (555), wherein the battery source provides power to the timer when there is no power supply from the system or platform (e.g., when the module is detached from the PCB). In embodiments, the clock or timer tracks the current date or timestamp and is implemented without an option to be reset. In embodiments, a memory device mounted on a memory module, such as a DIMM (e.g., memory device (107) of FIG. 1), comprises any suitable type of memory device containing data to be invalidated, for example, due to a data aging policy. In some embodiments, the memories (504) comprise a memory drive having a disk form factor. In embodiments, the TDMU (555) may also be coupled to embedded memory in a processor (e.g., see processor (502)), and may include, for example, high bandwidth memory (HBM) or embedded DRAM (eDRAM).Note that the TDMU (555) can be combined to perform the actions on any suitable memory medium that stores data undergoing invalidation, e.g., NAND, 3D NAND, or other suitable materials, e.g., memory based on phase change memory (PCM or cross point array) (504).

[0025] For example, in some embodiments, the memory device to which the TDMU (555) is coupled to perform data invalidation is an NVM device, for example, a byte-addressable write-in-place 3D crosspoint memory device, or other byte-addressable write-in-place NVM devices such as single or multi-level phase change memory (PCM) or phase change memory with a switch (PCMS) (also referred to as persistent memory), NVM devices using chalcogenide phase change materials (e.g., chalcogenide glass), resistive memory including metal oxide bases and oxygen vacancy bases, CB-RAM (Conductive Bridge Random Access Memory), nanowire memory, ferroelectric random access memory (FeRAM, FRAM), MRAM (magneto-resistive random access memory) incorporating memristor technology, STT (spin transfer torque)-MRAM, spintronic magnetic junction memory-based devices, MTJ (magnetic tunneling junction)-based devices, DW (Domain Wall) and SOT (Spin It includes an Orbit Transfer-based device, a thyristor-based memory device, or any combination of the above, or other memory.

[0026] In the embodiments, the memory module may be a DIMM such as a double data rate (DDR) synchronous random access memory (DDR SRAM) DIMM and / or the RAM components include a memory unit or medium comprising a cross-point memory array.

[0027] The memory subsystems described herein include DDR3 (Double Data Rate version 3, originally released by JEDEC (Joint Electronic Device Engineering Council) on June 27, 2007), DDR4 (DDR version 4, initial specification published by JEDEC in September 2012), DDR4E (DDR version 4), LPDDR3 (Low Power DDR version 3, JESD209-3B, published by JEDEC in August 2013), LPDDR4 (LPDDR version 4, JESD209-4, originally published by JEDEC in August 2014), WIO2 (Wide Input / Output version 2, JESD229-2, originally published by JEDEC in August 2014), HBM (High Bandwidth Memory, JESD325, originally published by JEDEC in October 2013), It should be noted that it may be compatible with a number of memory technologies, such as DDR5 (DDR version 5, currently under discussion by JEDEC), LPDDR5 (currently under discussion by JEDEC), HBM2 (HBM version 2, currently under discussion by JEDEC), or other memory technologies or combinations thereof, and technologies based on derivatives or extensions of these specifications.

[0028] Additionally, the electronic device (500) may include a mass storage device (506) (such as a diskette, hard drive, CD-ROM (compact disc read-only memory), etc.), an input / output (I / O) device (508) (such as a display, keyboard, cursor control, etc.), and a communication interface (510) (such as a network interface card, modem, etc.). In some embodiments, the TDMU (555) may be coupled to the mass storage devices (506) to perform the same functions as described above in relation to FIGS. 1 through 4. In some embodiments, the I / O device (508) may be a solid-state drive (SSD) including a memory device to which the TDMU can be coupled to perform the same functions as described above in relation to FIGS. 1 through 4.

[0029] The elements may be combined with each other via a system bus (512) that may represent one or more buses. In the case of multiple buses, they may be bridged by one or more bus bridges (not shown). Each of these elements may perform its own ordinary functions known in the art. In particular, in some embodiments, memory (504) and mass storage devices (506) may be adopted to store working and permanent copies of programming instructions configured to perform one or more process or memory / storage transactions for the electronic device (500). The programming instructions may be collectively referred to as controller logic (522). The various elements may be implemented by assembler instructions supported by the processor(s) (502) or by high-level languages ​​such as C, for example, which can be compiled into such instructions.

[0030] The number, capability, and / or capacity of the elements shown in FIG. 5 may vary depending on whether the electronic device (500) is used as a server, a communication device, or some other type of computing device.

[0031] Otherwise, the configurations of the elements illustrated in FIG. 5 may be known and thus will not be described further. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. As used herein, singular forms (“a,” “an,” “the”) are intended to include plural forms unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “comprising” specify the presence of the mentioned features, integers, steps, actions, elements, and / or components when used herein, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0032] Accordingly, various exemplary embodiments of the present disclosure are described as including, but not limited to, the following:

[0033] Example 1 includes a device, the device includes: a memory device including memory locations; and hardware logic, the hardware logic being coupled to the memory device and receiving a memory range and a time range from an interface - the memory range is an address range corresponding to a plurality of memory locations in the memory device, and the time range is a time range during which data stored in the memory locations is valid according to a data aging policy -; checking a time value to determine that the time value is outside the time range and that the data in the memory locations has expired; and invalidating the expired data in the memory device to comply with the data aging policy.

[0034] Example 2 is the device of claim 1, the time value is the current time, and additionally includes a timer or clock combined to provide the current time to hardware logic.

[0035] Example 3 is the device of claim 2 and additionally includes a battery source coupled to the timer or clock to provide power to the timer or clock when there is no power supply from the platform.

[0036] Example 4 is the device of Example 1, the device is a DIMM (dual-in-line-memory module), and the hardware logic resides on the DIMM along with the memory device.

[0037] Example 5 is the device of Example 2, the interface is the memory controller interface, and the hardware logic invalidates the data when the DIMM is disconnected from the interface.

[0038] Example 6 is the device of Example 1, the device is a memory drive, and the hardware logic resides on the memory drive along with the memory device.

[0039] Example 7 is the device of Example 1, where the time range is the time-to-live (TTL) value, and when the TTL value expires, the data at memory locations is identified as expired.

[0040] Example 8 is a device of any one of Examples 1 through 7, wherein the hardware logic for invalidating data includes marking a memory range as expired, clearing or deleting an encryption key, or writing zeros within the data locations of memory locations.

[0041] Example 9 is a method comprising: receiving, by hardware logic coupled to a memory device having a plurality of memory locations, a memory range of the memory device and a time range corresponding to the validity of data in the memory range, wherein the time range is a time range during which data stored in the memory locations is valid according to a data aging policy; by hardware logic checking the time range for a time value to identify the data in the memory range as expired according to a data aging policy; and by hardware logic invalidating the expired data in the memory device to comply with the data aging policy.

[0042] Example 10 is the method of Example 9, wherein the step of invalidating data that expires in a memory device by hardware logic includes the step of invalidating data when the memory device is separated from the platform interface.

[0043] Example 11 is the method of Example 9, where the step of checking the time range by hardware logic includes the step of checking a timer or clock to determine whether the time-to-live (TTL) value expires or is exceeded.

[0044] Example 12 is the method of Example 11, and the timer or clock is implemented without the option to be reset.

[0045] Example 13 is a system as: a processor; a memory device coupled to the processor - the memory device includes multiple memory locations -; and

[0046] It includes hardware logic, the hardware logic is coupled to a memory device, checks a time range for a time value to identify data in the memory range as expired - the memory range is an address range corresponding to multiple memory locations in the memory device, and the time range is a time range in which the data stored in the memory locations is valid according to the data aging policy -; and, to comply with the data aging policy, invalidates the expired data in the memory device.

[0047] Example 14 is the system of Example 13, and the time range is the TTL (time-to-live) value.

[0048] Example 15 is the system of Example 13, and the memory device and hardware logic are located on a memory module so as to be separated from the processor.

[0049] Example 16 is the system of Example 15, and the memory module is a DIMM.

[0050] Example 17 is the system of Example 16, additionally including a battery source and a timer coupled to hardware logic on a DIMM, and the battery source provides power to the timer when there is no power supply from the system.

[0051] Example 18 is the system of Example 13, and the timer for providing time values ​​is implemented without the option to be reset.

[0052] Example 19 is the system of Example 13, where the memory device is the built-in memory included in the memory drive or the processor.

[0053] Example 20 is a system of any one of Examples 13 to 19, wherein invalidating data includes marking a memory range as expired, deleting a memory range encryption key, or forcibly zeroing out memory locations of data.

[0054] Example 21 is a device comprising means for performing the methods of Examples 9 to 12.

[0055] Various embodiments may include any suitable combination of the aforementioned embodiments, including alternative (or) embodiments of the embodiments described in the form of the conjunction (and) above (e.g., "and" may be "and / or"). Furthermore, some embodiments may include one or more manufactured articles (e.g., non-transient computer-readable media) storing instructions that, when executed, can produce actions of any of the aforementioned embodiments. Additionally, some embodiments may include devices or systems having any suitable means for performing the various operations of the aforementioned embodiments.

[0056] The above description of the exemplified embodiments, including those described in the abstract, is not intended to present all but none or to limit the embodiments of the disclosure to the exact form disclosed. While specific embodiments and examples are described herein for illustrative purposes, as will be recognized by a person skilled in the art, various equivalent modifications are possible within the scope of the disclosure.

[0057] Such modifications may be made to the embodiments of the present disclosure in light of the detailed description above. The terms used in the following claims should not be interpreted as limiting the various embodiments of the present disclosure only to the specific implementations disclosed in the specification and claims. Rather, the scope thereof should be determined entirely by the following claims, which should be interpreted in accordance with established principles of claim interpretation.

Claims

Claim 1 A device comprising: a memory device including memory locations; and a device coupled to the memory device, receiving, from an interface, a memory range and a time range, wherein the memory range is an address range corresponding to a plurality of the memory locations in the memory device and the time range is a time range during which data stored in the memory locations is valid according to a data aging policy; checking a time value to determine that the time value is outside the time range and that the data in the memory locations has expired; and a hardware logic for invalidating the expired data in the memory device to comply with the data aging policy. Claim 2 A device according to claim 1, wherein the time value is the current time, and further comprising a timer or clock combined to provide the current time to the hardware logic. Claim 3 A device according to paragraph 2, further comprising a battery source coupled to the timer or the clock to provide power to the timer or the clock when there is no power supply from the platform. Claim 4 In claim 1, the device is a DIMM (dual-in-line-memory module), and the hardware logic is a device residing on the DIMM together with the memory device. Claim 5 In paragraph 4, the interface is a memory controller interface, and the hardware logic is a device that invalidates the data when the DIMM is disconnected from the interface. Claim 6 In paragraph 1, the device is a memory drive. Claim 7 A device according to claim 1, wherein the time range is a TTL (time-to-live) value, and when the TTL value expires, the data at the memory locations is identified as expired. Claim 8 A device according to claim 1, wherein the hardware logic for invalidating the data includes marking the memory range as expired, clearing or deleting the encryption key, or writing zeros to the data locations of the memory locations. Claim 9 A method performed by a device, wherein the device comprises hardware logic coupled to a memory device having a plurality of memory locations, and the method comprises: receiving a memory range and a time range of the memory device by the hardware logic, wherein the memory range is an address range corresponding to the plurality of memory locations in the memory device, and the time range is a time range during which data stored in the memory locations is valid according to a data aging policy; checking the time range for a time value by the hardware logic to identify the data in the memory range as expired according to a data aging policy; and invalidating the expired data in the memory device by the hardware logic to comply with the data aging policy. Claim 10 In claim 9, the step of invalidating the expired data in the memory device by the hardware logic includes the step of invalidating the data when the memory device is separated from the platform interface. Claim 11 In claim 9, the step of checking the time range by the hardware logic includes checking a timer or clock to determine whether the time-to-live (TTL) value has expired or been exceeded. Claim 12 In paragraph 11, the method is implemented such that the timer or the clock is not an option to be reset. Claim 13 A system comprising: a processor; a memory device coupled to the processor, wherein the memory device comprises a plurality of memory locations; and a hardware logic coupled to the memory device, wherein the time range is checked for a time value to identify data in the memory range as expired, wherein the memory range is an address range corresponding to the plurality of memory locations in the memory device and the time range is a time range during which data stored in the memory locations is valid according to a data aging policy; and a system comprising a hardware logic that invalidates the expired data in the memory device to comply with the data aging policy. Claim 14 In paragraph 13, the above time range is a system in which the time range is a TTL (time-to-live) value. Claim 15 In paragraph 13, a system in which the memory device and the hardware logic are located on a memory module so as to be separated from the processor. Claim 16 In item 15, the above memory module is a DIMM in the system. Claim 17 In claim 16, a system further comprising a battery source and a timer coupled to the hardware logic on the DIMM, wherein the battery source provides power to the timer when there is no power supply from the system. Claim 18 In Clause 13, the system for providing the above time value is implemented without an option to be reset. Claim 19 In paragraph 13, the memory device is a system that is an embedded memory included in a memory drive or included on the processor. Claim 20 A system according to claim 13, wherein invalidating the data includes marking the memory range as expired, deleting the memory range encryption key, or forcibly zeroing out the memory locations of the data.

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