Semiconductor package and method fabricating of the same

Abstract

A semiconductor package is provided comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower molding film surrounding the lower semiconductor chip on the lower substrate, a redistribution layer disposed on the lower molding film, and a vertical connection terminal connecting the lower substrate and the redistribution layer on one side of the lower semiconductor chip, wherein the lower semiconductor chip includes a recognition mark provided on its upper surface, and the recognition mark includes a marking pattern formed in intaglio on the upper surface of the lower semiconductor chip and a molding pattern filling the interior of the marking pattern, and the first material constituting the molding pattern may be the same as the second material constituting the lower molding film.

Description

Technology Field

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same, and more specifically, to a semiconductor package having an identification mark and a method for manufacturing the same. Background Technology

[0002] A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting semiconductor chips on a substrate, such as a printed circuit board (PCB), and electrically connecting them using bonding wires or bumps.

[0003] With the development of the electronics industry, there is an increasing demand for high functionality, high speed, and miniaturization of electronic components. To meet these demands, there is a need to develop technology that forms multiple chips into a single package, which enables high-speed signal transmission and the manufacturing of semiconductor devices or packages of the smallest possible size.

[0004] Laser marking to form recognition marks on semiconductor packages is typically performed on mold films on semiconductor chips. In the case of laser marking using only laser patterning, there are problems such as poor visibility of the marks and a decrease in the stacking yield of the packages. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a semiconductor package having a recognition mark with high visibility and a method for manufacturing the same.

[0006] Another problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor package with low defect occurrence and a semiconductor package manufactured thereby.

[0007] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0008] A semiconductor package according to embodiments of the present invention for solving the aforementioned technical problems may include a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower molding film surrounding the lower semiconductor chip on the lower substrate, a redistribution layer disposed on the lower molding film, and a vertical connection terminal connecting the lower substrate and the redistribution layer at one side of the lower semiconductor chip. The lower semiconductor chip may include an identification mark provided on its upper surface. The identification mark may include a marking pattern formed in intaglio on the upper surface of the lower semiconductor chip, and a molding pattern filling the interior of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower molding film.

[0009] A semiconductor package according to embodiments of the present invention for solving the aforementioned technical problems may include a substrate, a semiconductor chip mounted on the substrate, a molding film surrounding the semiconductor chip on the substrate, a redistribution layer disposed on the molding film, and a through electrode connecting the substrate and the redistribution layer on one side of the semiconductor chip. The semiconductor chip may include an identification mark provided on its upper surface. The identification mark may include a marking pattern provided on the upper surface of the semiconductor chip and located at a different level from the upper surface of the semiconductor chip, and a molding pattern provided on the semiconductor chip so as to expose the marking pattern. The uppermost surface of the semiconductor chip may be coplanar with the upper surface of the molding pattern.

[0010] A method for manufacturing a semiconductor package according to embodiments of the present invention for solving the aforementioned technical problems may include patterning the upper surface of a semiconductor chip to form an intaglio marking pattern, mounting the semiconductor chip on a substrate, forming a vertical connection terminal on the substrate, forming a molding film covering the semiconductor chip and the vertical connection terminal on the substrate, a portion of the molding film filling the interior of the marking pattern, and performing a thinning process on the molding film to expose the upper surface of the semiconductor chip and the upper surface of the vertical connection terminal, forming a molding pattern on the portion of the molding film remaining inside the marking pattern after the thinning process, and forming a redistribution layer on the molding film and forming an opening that penetrates the redistribution layer to expose the marking pattern and the molding pattern. Effects of the invention

[0011] A semiconductor package according to embodiments of the present invention can form a recognition mark by filling a molding pattern within a marking pattern formed as an intaglio on a lower semiconductor chip. The recognition mark can be recognized by utilizing the color difference between the molding pattern and the lower semiconductor chip, and accordingly, the visibility of the recognition mark can be high.

[0012] Furthermore, the upper surface of the lower semiconductor chip and the upper surface of the molding pattern can form a co-plane with each other. That is, the curvature formed by the marking pattern on the upper surface of the lower semiconductor chip can be compensated by the molding pattern, and the upper surfaces of the lower semiconductor chip and the recognition mark can be flat overall. As a result, it may be easy to form the redistribution layer described later on the lower semiconductor chip.

[0013] In addition, an opening that exposes the recognition mark may be formed in the redistribution layer, or the insulation pattern may be formed of a transparent material so that the wiring pattern of the redistribution layer does not obscure the recognition mark. Accordingly, when viewed from above the semiconductor package, the recognition mark may not be obscured by the redistribution layer, and the reliability of the recognition mark may be further enhanced. Brief explanation of the drawing

[0014] FIG. 1 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. Figures 2 and 3 are enlarged drawings of area A of Figure 1. FIG. 4 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. Figure 5 is an enlarged view of area B of Figure 4. FIG. 6 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. Figures 7 and 8 are enlarged drawings of area C of Figure 6. FIGS. 9 and FIGS. 10 are cross-sectional views illustrating a semiconductor package according to embodiments of the present invention. FIGS. 11 to 23 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to embodiments of the present invention. Specific details for implementing the invention

[0015] A semiconductor package according to the concept of the present invention is described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. FIG. 2 and FIG. 3 are enlarged views of area A of FIG. 1.

[0016] Referring to FIGS. 1 and 2, a lower package substrate (100) may be provided. The lower package substrate (100) may be a redistribution substrate. The lower package substrate (100) may include at least one first substrate wiring layer stacked on top of each other. Each of the first substrate wiring layers may include a first substrate insulating pattern (110) and a first substrate wiring pattern (120) within the first substrate insulating pattern (110). The first substrate wiring pattern (120) of any one first substrate wiring layer may be electrically connected to the first substrate wiring pattern (120) of an adjacent other first substrate wiring layer. Hereinafter, the configuration of the lower package substrate (100) will be described based on one first substrate wiring layer.

[0017] The first substrate insulating pattern (110) may include an insulating polymer or a photoimageable dielectric (PID). For example, the photoimageable dielectric may include at least one of photoimageable polyimide (PI), polybenzoxazole (PBO), phenol-based polymer, or benzocyclobutene-based polymer. Alternatively, the first substrate insulating pattern (110) may include an insulating material. For example, the first substrate insulating pattern (110) may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or an insulating polymer.

[0018] A first substrate wiring pattern (120) may be provided on a first substrate insulating pattern (110). The first substrate wiring pattern (120) may extend horizontally on the first substrate insulating pattern (110). The first substrate wiring pattern (120) may be configured for rewiring within the first substrate wiring layer. The first substrate wiring pattern (120) may include a conductive material. For example, the first substrate wiring pattern (120) may include copper (Cu).

[0019] The first substrate wiring pattern (120) may have a damascene structure. For example, the first substrate wiring pattern (120) may have a head portion and a tail portion that are integrally connected to each other. The head portion and the tail portion may not have a boundary surface between them. In this case, the width of the head portion connected to the tail portion may be greater than the width of the tail portion. Accordingly, the head portion and the tail portion of the first substrate wiring pattern (120) may have a 'T' shaped cross-section.

[0020] The head portion of the first substrate wiring pattern (120) may be a wiring portion or a pad portion that horizontally extends the wiring within the package substrate (100). The head portion may be provided on the upper surface of the first substrate insulation pattern (110). For example, the head portion may protrude onto the upper surface of the first substrate insulation pattern (110). The head portion of the first substrate wiring pattern (120) of the first substrate wiring layer positioned at the top of the first substrate wiring layers may correspond to first substrate pads (122) for mounting a lower semiconductor chip (200) on the lower package substrate (100) and a second substrate pad (124) for connecting a through electrode (315).

[0021] The tail portion of the first substrate wiring pattern (120) may be a via portion that vertically connects wiring within the package substrate (100). The tail portion may be connected to the lower surface of the head portion. The tail portion may be connected to another first substrate wiring layer positioned below it. For example, the tail portion of the first substrate wiring pattern (120) may extend from the lower surface of the head portion and penetrate the first substrate insulation pattern (110) to be connected to the head portion of the first substrate wiring pattern (120) of another first substrate wiring layer positioned below it. The tail portion of the first substrate wiring pattern (120) of the first substrate wiring layer positioned at the bottom of the first substrate wiring layers may be exposed onto the lower surface of the first substrate insulation pattern (110). The tail portion of the first substrate wiring pattern (120) positioned and exposed on the lower surface of the first substrate insulation pattern (110) at the bottom may correspond to under-bump pads (126) for connecting external terminals (105) to the lower package substrate (100).

[0022] A first seed / barrier film (130) may be interposed between the first substrate insulation pattern (110) and the first substrate wiring pattern (120). The first seed / barrier film (130) may cover the side and bottom surfaces of the first substrate wiring pattern (120). The first seed / barrier film (130) may include a metallic material such as gold (Au), titanium (Ti), or tantalum (Ta). Alternatively, the first seed / barrier film (130) may include a metallic nitride such as titanium nitride (TiN) or tantalum nitride (TaN).

[0023] A protective layer (102) may be provided below the first substrate wiring layer at the bottom. The protective layer (102) may cover the lower surface of the first substrate insulation pattern (110) at the bottom. The protective layer (102) may be configured to protect the lower surface of the lower package substrate (100). In this case, the under-bump pads (126) may be exposed by a recess formed in the protective layer (102). The recess may be an area where external terminals (105) are provided. The protective layer (102) may include an insulating material. For example, the protective layer (102) may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or an insulating polymer.

[0024] External terminals (105) may be disposed below the lower package substrate (100). For example, the external terminals (105) may be disposed on under bump pads (126) disposed on the lower surface of the lower package substrate (100). More specifically, the external terminals (105) may be connected to the lower surface of the under bump pads (126) within the recess formed in the protective layer (102). The external terminals (105) may include solder balls or solder bumps, and depending on the type and placement of the external terminals (105), the semiconductor package may be provided in the form of a ball grid array (BGA), a fine ball grid array (FBGA), or a land grid array (LGA).

[0025] A lower semiconductor chip (200) may be disposed on a lower package substrate (100). The lower semiconductor chip (200) may be disposed on the upper surface of the lower package substrate (100). The lower semiconductor chip (200) may include a memory chip or a logic chip. Alternatively, the lower semiconductor chip (200) may include a passive element. The lower semiconductor chip (200) may be disposed face down on the lower package substrate (100). For example, the lower semiconductor chip (200) may have a front surface facing the lower package substrate (100) and a rear surface facing the front surface. In the following specification, the front surface is defined as a surface on the side of the active surface of an integrated element within the semiconductor chip, and is defined as the surface on which the pads of the semiconductor chip are formed, and the rear surface is defined as the opposite surface facing the front surface. Depending on the position of the lower package substrate (100) and the lower semiconductor chip (200), the lower surface of the lower semiconductor chip (200) corresponds to the front surface of the lower semiconductor chip (200), and the upper surface (200a) of the lower semiconductor chip (200) corresponds to the rear surface of the lower semiconductor chip (200). In this specification, the upper surface (200a) of the lower semiconductor chip (200) refers to the upper surface of the base layer of the lower semiconductor chip (200) where the first circuit layer (210), described later, is formed, and corresponds to the widest surface among the surfaces facing upward of the lower semiconductor chip (200). The lower semiconductor chip (200) may include a semiconductor material such as silicon (Si). The lower semiconductor chip (200) may include a first circuit layer (210) provided adjacent to the lower surface of the lower semiconductor chip (200) facing the lower package substrate (100).

[0026] A first circuit layer (210) may be provided on the lower surface of a lower semiconductor chip (200). The first circuit layer (210) may be electrically connected to an integrated element or integrated circuit formed within the lower semiconductor chip (200). The lower semiconductor chip (200) may have first chip pads (220) provided on the lower surface of the lower semiconductor chip (200). The first chip pads (220) may be electrically connected to the integrated element or integrated circuit within the lower semiconductor chip (200) through the first circuit layer (210).

[0027] A lower semiconductor chip (200) can be mounted on a lower package substrate (100). The lower semiconductor chip (200) can be mounted on the lower package substrate (100) in a flip chip manner. For example, the first circuit layer (210) of the lower semiconductor chip (200) may face the lower package substrate (100). At this time, first chip terminals (230) may be provided below the first chip pads (220) of the lower semiconductor chip (200). The lower semiconductor chip (200) can be mounted on the lower package substrate (100) through the first chip terminals (230). The first chip terminals (230) can connect the first chip pads (220) of the lower semiconductor chip (200) and the first substrate pads (122) of the lower package substrate (100).

[0028] The lower semiconductor chip (200) may have a recognition mark (240). As illustrated in FIGS. 1 and 2, the recognition mark (240) may include a marking pattern (242) and a molding pattern (244).

[0029] A marking pattern (242) may be formed on the upper surface (200a) of the lower semiconductor chip (200). For example, the marking pattern (242) may be formed by carving the upper surface (200a) of the lower semiconductor chip (200). The marking pattern (242) may be located at a different level from the upper surface (200a) of the lower semiconductor chip (200). For example, in the embodiment of FIGS. 1 and 2, a marking pattern (242) formed in intaglio on the upper surface (200a) of the lower semiconductor chip (200) may be provided. Alternatively, the marking pattern (242) may have a shape that is recessed from the upper surface (200a) of the lower semiconductor chip (200) toward the lower surface of the lower semiconductor chip (200).

[0030] A molding pattern (244) may be provided on the lower semiconductor chip (200). The molding pattern (244) may expose a marking pattern (242). Here, the marking pattern (242) refers to the entire area of ​​the recessed indentation from the upper surface (200a) of the semiconductor chip (200), and the exposure of the marking pattern (242) means that the planar shape of the marking pattern (242) is visually visible on the lower semiconductor chip (200). For example, in the embodiment of FIGS. 1 and 2, the molding pattern (244) may fill the interior of the marking pattern (242). That is, the molding pattern (244) may fill the indented area of ​​the marking pattern (242). The molding pattern (244) may not extend onto the upper surface (200a) of the lower semiconductor chip (200). For example, the molding pattern (244) completely fills the interior of the marking pattern (242), and the molding pattern (244) may not protrude to a level higher than the upper surface (200a) of the lower semiconductor chip (200). That is, the planar shape of the recognition mark (240) may be defined by the boundary between the molding pattern (244) filling the interior of the marking pattern (242) and the upper surface (200a) of the lower semiconductor chip (200) located outside the marking pattern (242). The upper surface (244a) of the molding pattern (244) may be provided at the same level as the upper surface (200a) of the lower semiconductor chip (200), and the upper surface (244a) of the molding pattern (244) and the upper surface (200a) of the lower semiconductor chip (200) may form a coplanar plane. The upper surface (244a) of the molding pattern (244) and the upper surface (200a) of the lower semiconductor chip (200) can be provided on a substantially flat plane. The first material constituting the molding pattern (244) may have the same material as the second material constituting the lower molding film (310) described later.This is because, in the method of manufacturing a semiconductor package, the molding pattern (244) is formed in the same process as the process of forming the lower molding film (310), and this will be explained in detail later along with the method of manufacturing a semiconductor package. The first material of the molding pattern (244) may include an insulating material such as an epoxy molding compound (EMC). The first material of the molding pattern (244) may have a different color from the upper surface (200a) of the lower semiconductor chip (200). For example, the upper surface (200a) of the lower semiconductor chip (200), which is composed of silicon (Si), may have a gray metallic luster, and the upper surface (244a) of the molding pattern (244), which is composed of an epoxy molding compound (EMC), may have a black matte finish.

[0031] When a recognition mark (240) is formed using only the marking pattern (242), the recognition mark (240) can be recognized only by the difference in surface shape (or curvature) between the marking pattern (242) and the upper surface (200a) of the lower semiconductor chip (200), and accordingly, the visibility of the recognition mark (240) may be low.

[0032] According to embodiments of the present invention, in addition to forming a marking pattern (242) in intaglio on the upper surface (200a) of a lower semiconductor chip (200), a recognition mark (240) can be formed by filling a molding pattern (244) within the marking pattern (242). In particular, the molding pattern (244) is formed using a material having a color different from that of the upper surface (200a) of the lower semiconductor chip (200), so that the recognition mark (240) can be recognized by utilizing the color difference between the molding pattern (244) and the lower semiconductor chip (200), and accordingly, the visibility of the recognition mark (240) can be high.

[0033] Furthermore, the upper surface (200a) of the lower semiconductor chip (200) and the upper surface (244a) of the molding pattern (244) can be coplanar with each other. That is, the curvature formed by the marking pattern (242) on the upper surface (200a) of the lower semiconductor chip (200) can be compensated by the molding pattern (244), and the upper surfaces of the lower semiconductor chip (200) and the recognition mark (240) can be flat overall. As a result, it may be easy to form the redistribution layer (400), which will be described later, on the lower semiconductor chip (200).

[0034] A lower molding film (310) may be provided on a lower package substrate (100). The lower molding film (310) may cover the upper surface of the lower package substrate (100). The lower molding film (310) may surround the lower semiconductor chip (200) in a planar view. The lower molding film (310) may cover the side of the lower semiconductor chip (200) and expose the uppermost surface of the lower semiconductor chip (200). In the embodiment of FIGS. 1 and 2, the uppermost surface of the lower semiconductor chip (200) may be the upper surface (200a, i.e., the rear surface of the lower semiconductor chip (200)). That is, the lower molding film (310) may cover the side of the lower semiconductor chip (200) and expose the upper surface (200a) of the lower semiconductor chip (200). The upper surface (310a) of the lower molding film (310) and the upper surface (200a) of the lower semiconductor chip (200) can be coplanar. At this time, the upper surface (310a) of the lower molding film (310) and the upper surface (200a) of the lower semiconductor chip (200) can be flat. In other words, the upper surface (310a) of the lower molding film (310) and the upper surface (200a) of the lower semiconductor chip (200) can be located on the same plane. The upper surface (310a) of the molding film (310), the upper surface (200a) of the lower semiconductor chip (200), and the upper surface (244a) of the molding pattern (244) can be coplanar. The lower molding film (310) can fill the space between the lower package substrate (100) and the lower semiconductor chip (200). The lower molding film (310) may surround the first chip terminals (230) between the lower package substrate (100) and the lower semiconductor chip (200). The lower molding film (310) may include the same material as the molding pattern (244). The lower molding film (310) may include an insulating material such as an epoxy molding compound (EMC).

[0035] At least one through electrode (315) may be provided on the lower package substrate (100). The through electrode (315) may correspond to a vertical connection terminal for connecting the lower package substrate (100) and the redistribution layer (400) described later. The through electrode (315) may be positioned horizontally spaced apart from the lower semiconductor chip (200). The through electrode (315) may penetrate vertically through the lower molding film (310). One end of the through electrode (315) may extend toward the lower package substrate (100) and be connected to a second substrate pad (124) of the lower package substrate (100). The other end of the through electrode (315) may be exposed to the upper surface of the lower molding film (310). The upper surface of the through electrode (315) may be coplanar with the upper surface (310a) of the lower molding film (310). At this time, the upper surface (310a) of the lower molding film (310) and the upper surface of the through electrode (315) may be flat. Alternatively, the upper surface (310a) of the lower molding film (310) and the upper surface of the through electrode (315) may be located on the same plane. That is, the upper surface (310a) of the lower molding film (310), the upper surface (200a) of the lower semiconductor chip (200), and the upper surface of the through electrode (315) may form a coplanar plane. The through electrode (315) may have a cylindrical or polygonal column shape that penetrates the lower molding film (310) vertically. The width of the through electrode (315) may be uniform regardless of the distance from the lower package substrate (100). Alternatively, the width of the through electrode (315) may decrease as it approaches the lower package substrate (100). The through electrodes (315) may be provided in multiple numbers as needed. In this case, the second substrate pads (124) to which the through electrodes (315) are connected may also be provided in multiple numbers, and each of the through electrodes (315) may be connected to a corresponding second substrate pad (124). The through electrodes (315) may include metal.For example, the penetrating electrode (315) may contain copper (Cu).

[0036] In this specification, the term "through electrode" means an electrode that penetrates a component vertically, and the planar shape of the "through electrode" is not limited. That is, the shape of the "through electrode" includes a cylindrical or polygonal column shape, and may also have a partition or wall shape.

[0037] A redistribution layer (400) may be provided on the lower molding film (310). The redistribution layer (400) may be in direct contact with the upper surface (310a) of the lower molding film (310), the upper surface of the through electrode (315), and the upper surface (200a) of the lower semiconductor chip (200).

[0038] The redistribution layer (400) may include at least one second substrate wiring layer stacked on top of each other. Each of the second substrate wiring layers may include a second substrate insulating pattern (410) and a second substrate wiring pattern (420) within the second substrate insulating pattern (410). When the second substrate wiring layers are provided in plurality, the second substrate wiring pattern (420) of any one second substrate wiring layer may be electrically connected to the second substrate wiring pattern (420) of an adjacent other second substrate wiring layer.

[0039] The second substrate insulating pattern (410) may include an insulating polymer or a photosensitive insulating material (PID). For example, the photosensitive insulating material may include at least one of photosensitive polyimide (PI), polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer. Alternatively, the second substrate insulating pattern (410) may include an insulating material. For example, the second substrate insulating pattern (410) may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or an insulating polymer.

[0040] A second substrate wiring pattern (420) may be provided on a second substrate insulation pattern (410). The second substrate wiring pattern (420) may extend horizontally on the second substrate insulation pattern (410). The second substrate wiring pattern (420) may be configured for rewiring within the second substrate wiring layer. The second substrate wiring pattern (420) may include a conductive material. For example, the second substrate wiring pattern (420) may include copper (Cu). The second substrate wiring pattern (420) may have a damascene structure. For example, the second substrate wiring pattern (420) may have a head portion and a tail portion that are integrally connected to each other. The head portion and the tail portion of the second substrate wiring pattern (420) may have a 'T' shaped cross-section.

[0041] The head portion of the second substrate wiring pattern (420) may be a wiring portion or a pad portion that horizontally extends the wiring within the redistribution layer (400). The head portion may be provided on the upper surface of the second substrate insulation pattern (410). For example, the head portion may protrude onto the upper surface of the second substrate insulation pattern (410).

[0042] The tail portion of the second substrate insulation pattern (410) may be a via portion that vertically connects wiring within the redistribution layer (400). The tail portion may be connected to another second substrate wiring layer positioned below it. For example, the tail portion of the second substrate insulation pattern (410) may extend from the lower surface of the head portion and may be connected to the head portion of the second substrate wiring pattern (420) of another second substrate wiring layer positioned below it by penetrating the second substrate insulation pattern (410). The tail portion of the second substrate wiring pattern (420) of the second substrate wiring layer positioned at the bottom of the second substrate wiring layers may be connected to a through electrode (315) by penetrating the second substrate insulation pattern (410).

[0043] A second seed / barrier film (430) may be interposed between the second substrate insulation pattern (410) and the second substrate wiring pattern (420). The second seed / barrier film (430) may cover the side and bottom surfaces of the second substrate wiring pattern (420). The second seed / barrier film (430) may include a metallic material such as gold (Au), titanium (Ti), or tantalum (Ta). Alternatively, the second seed / barrier film (430) may include a metallic nitride such as titanium nitride (TiN) or tantalum nitride (TaN).

[0044] The redistribution layer (400) may have a first opening (OP1). The first opening (OP1) may penetrate the redistribution layer (400) vertically. The first opening (OP1) may be located above the lower semiconductor chip (200). The first opening (OP1) may expose a recognition mark (240) provided on the upper surface (200a) of the lower semiconductor chip (200).

[0045] According to embodiments of the present invention, a first opening (OP1) is formed in the redistribution layer (400), and the first opening (OP1) can expose a recognition mark (240). Accordingly, when viewed from above the semiconductor package, the recognition mark (240) may not be obscured by the redistribution layer (400), and the reliability of the recognition mark (240) may be further enhanced.

[0046] The inner surface of the first opening (OP1) may have a stepped shape. For example, as shown in FIG. 1, the first opening (OP1) may be defined by the redistribution layer (400), more specifically by the second substrate insulation patterns (410) of the redistribution layer (400). In this case, each of the second substrate insulation patterns (410) of the redistribution layer (400) may form a single step. For example, each of the second substrate insulation patterns (410) may have sub-openings (OPs) that penetrate them vertically, and the width of the sub-openings (OPs) may be larger for the second substrate insulation patterns (410) that are positioned further from the upper surface of the lower semiconductor chip (200).

[0047] According to other embodiments, as illustrated in FIG. 3, the width of the first opening (OP1) may be uniform depending on the distance from the upper surface (200a) of the lower semiconductor chip (200). That is, the sub-openings (OPs) of the second substrate insulating patterns (410) may all have the same width.

[0049] FIG. 4 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. FIG. 5 is an enlarged view of region B of FIG. 4. In the following embodiments, the components described with reference to FIG. 1 to 3 use the same reference numerals, and for convenience of explanation, descriptions thereof are omitted or briefly described. That is, the description focuses on the differences between the embodiments of FIG. 1 to 3 and the embodiments below.

[0050] Referring to FIGS. 4 and 5, a redistribution layer (400) may be provided on the lower molding film (310). The redistribution layer (400) may be in direct contact with the upper surface (310a) of the lower molding film (310), the upper surface of the through electrode (315), and the upper surface (200a) of the lower semiconductor chip (200). The redistribution layer (400) may cover the entire upper surface (200a) of the lower semiconductor chip (200).

[0051] The redistribution layer (400) may include at least one second substrate wiring layer stacked on top of each other. Each of the second substrate wiring layers may include a second substrate insulating pattern (410) and a second substrate wiring pattern (420) within the second substrate insulating pattern (410). When the second substrate wiring layers are provided in plurality, the second substrate wiring pattern (420) of any one second substrate wiring layer may be electrically connected to the second substrate wiring pattern (420) of an adjacent other second substrate wiring layer.

[0052] The second substrate insulating pattern (410) may include a transparent insulating material. For example, the second substrate insulating pattern (410) may include a transparent photosensitive insulating material (: PID). For example, the photosensitive insulating material may include photosensitive polyimide (PI) or polybenzoxazole (PBO).

[0053] A second substrate wiring pattern (420) may be provided on a second substrate insulation pattern (410). The second substrate wiring pattern (420) may extend horizontally on the second substrate insulation pattern (410). The second substrate wiring pattern (420) may include a conductive material. The second substrate wiring pattern (420) may have a damascene structure. For example, the second substrate wiring pattern (420) may have a head portion and a tail portion that are integrally connected to each other. The head portion and the tail portion of the second substrate wiring pattern (420) may have a 'T'-shaped cross-section.

[0054] The second substrate wiring pattern (420) may not overlap vertically with the recognition mark (240). For example, from a planar perspective, the second substrate wiring pattern (420) may be located outside the recognition mark (240). That is, the recognition mark (240) may be located on the center of the lower package substrate (100), and the second substrate wiring pattern (420) may be located on the periphery of the lower package substrate (100).

[0055] According to embodiments of the present invention, a second substrate wiring pattern (420) composed of metal may not obscure the recognition mark (240). Additionally, the second substrate insulation pattern (410) may be formed of a transparent material. Thus, the recognition mark (240) may be visible through the redistribution layer (400). Furthermore, the recognition mark (240) of the present invention, with improved visibility, may be more advantageous for being visible through the redistribution layer (400).

[0057] FIG. 6 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. FIG. 7 and FIG. 8 are enlarged views of region C of FIG. 6.

[0058] Referring to FIGS. 6 and 7, the lower semiconductor chip (200) may have a recognition mark (240'). The recognition mark (240') may include a marking pattern (242') and a molding pattern (244').

[0059] A marking pattern (242') may be formed on the upper surface (200a) of the lower semiconductor chip (200). For example, the marking pattern (242') may be formed by carving the upper surface (200a) of the lower semiconductor chip (200). The marking pattern (242') may be located at a different level from the upper surface (200a) of the lower semiconductor chip (200). For example, in the embodiment of FIGS. 6 and 7, a marking pattern (242') formed in relief on the upper surface (200a) of the lower semiconductor chip (200) may be provided. Alternatively, the marking pattern (242') may have a shape protruding upward from the upper surface (200a) of the lower semiconductor chip (200). In this case, the uppermost surface of the lower semiconductor chip (200) may correspond to the upper surface (242'a) of the marking pattern (242').

[0060] A molding pattern (244') may be provided on the lower semiconductor chip (200). The molding pattern (244') may expose a marking pattern (242'). Here, the marking pattern (242) refers to the entire raised area protruding from the upper surface (200a) of the semiconductor chip (200), and the exposure of the marking pattern (242') means that the planar shape of the marking pattern (242') is visually visible on the lower semiconductor chip (200). For example, in the embodiment of FIGS. 6 and 7, the molding pattern (244') may surround the marking pattern (242') on the upper surface (200a) of the lower semiconductor chip (200). That is, the molding pattern (244') may surround the raised area of ​​the marking pattern (242'). The molding pattern (244') may not extend onto the upper surface (242'a) of the marking pattern (242'). For example, the molding pattern (244') may not protrude to a level higher than the upper surface (242'a) of the marking pattern (242'). That is, the planar shape of the recognition mark (240') may be defined by the boundary between the marking pattern (242') and the molding pattern (244') surrounding the marking pattern (242'). The upper surface (244'a) of the molding pattern (244') may be provided at the same level as the upper surface (242'a) of the marking pattern (242'), and the upper surface (244'a) of the molding pattern (244') and the upper surface (242'a) of the marking pattern (242') may be coplanar. The upper surface (244'a) of the molding pattern (244') and the upper surface (242'a) of the marking pattern (242') can be provided on a substantially flat plane. The first material constituting the molding pattern (244') may have the same material as the second material constituting the lower molding film (310). The first material of the molding pattern (244') may include an insulating material such as epoxy molding compound (EMC). The first material of the molding pattern (244') may have a different color from the upper surface (242'a) of the marking pattern (242').

[0061] A lower molding film (310) may be provided on a lower package substrate (100). The lower molding film (310) may cover the upper surface of the lower package substrate (100). The lower molding film (310) may surround the lower semiconductor chip (200) in a planar view. The lower molding film (310) may cover the side of the lower semiconductor chip (200) and expose the top surface of the lower semiconductor chip (200). In the embodiments of FIGS. 6 and 7, the top surface of the lower semiconductor chip (200) may be the upper surface (242'a) of the marking pattern (242'). The lower molding film (310) may be connected to the molding pattern (244') of the recognition mark (240) and may form an integral part. That is, the lower molding film (310) and the molding pattern (244') may be composed of the same material, and there may be no interface between the lower molding film (310) and the molding pattern (244'). The upper surface (310a) of the lower molding film (310), the upper surface (244'a) of the molding pattern (244'), and the upper surface (242'a) of the marking pattern (242') may form a coplanar plane. At this time, the upper surface (310a) of the lower molding film (310), the upper surface (244'a) of the molding pattern (244'), and the upper surface (242'a) of the marking pattern (242') may be flat. In other words, the upper surface (310a) of the lower molding film (310), the upper surface (244'a) of the molding pattern (244'), and the upper surface (242'a) of the marking pattern (242') can be located on the same plane.

[0062] A redistribution layer (400) may be provided on the lower molding film (310). The redistribution layer (400) may be in direct contact with the upper surface (310a) of the lower molding film (310), the upper surface of the through electrode (315), and the upper surface (200a) of the lower semiconductor chip (200).

[0063] The redistribution layer (400) may include at least one second substrate wiring layer stacked on top of each other. Each of the second substrate wiring layers may include a second substrate insulating pattern (410) and a second substrate wiring pattern (420) within the second substrate insulating pattern (410). When the second substrate wiring layers are provided in plurality, the second substrate wiring pattern (420) of any one second substrate wiring layer may be electrically connected to the second substrate wiring pattern (420) of an adjacent other second substrate wiring layer.

[0064] The redistribution layer (400) may have a first opening (OP1). The first opening (OP1) may penetrate the redistribution layer (400) vertically. The first opening (OP1) may be located above the lower semiconductor chip (200). The first opening (OP1) may expose a recognition mark (240) provided on the upper surface (200a) of the lower semiconductor chip (200).

[0065] The inner surface of the first opening (OP1) may have a stepped shape. For example, as shown in FIG. 7, the second substrate insulation patterns (410) of the redistribution layer (400) may each form a single step. For example, each of the second substrate insulation patterns (410) may have sub-openings (OPs) that penetrate them vertically, and the width of the sub-openings (OPs) may be larger for the second substrate insulation patterns (410) that are positioned further from the upper surface of the lower semiconductor chip (200).

[0066] According to other embodiments, as illustrated in FIG. 8, the width of the first opening (OP1) may be uniform depending on the distance from the upper surface (200a) of the lower semiconductor chip (200). That is, the sub-openings (OPs) of the second substrate insulating patterns (410) may all have the same width.

[0068] FIG. 9 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention.

[0069] Referring to FIG. 9, a connecting substrate (500) may be provided as a vertical connecting terminal for connecting the lower package substrate (100) and the redistribution layer (400) described later, in place of a through electrode (315, see FIG. 1).

[0070] A connection substrate (500) may be provided on a lower package substrate (100). The connection substrate (500) may have a second opening (OP2) penetrating the interior. For example, the second opening (OP2) may have the form of an open hole connecting the upper surface and the lower surface of the connection substrate (500). The connection substrate (500) may include a substrate base layer (510) and a conductive portion (520), which is a wiring pattern provided within the substrate base layer (510). As an example, the substrate base layer (510) may include silicon oxide (SiO). The conductive portion (520) may be positioned outside the connection substrate (500) from the opening. The conductive portion (520) may include upper pads (522) of the connection substrate, lower pads (524) of the connection substrate, and vias (526) of the connection substrate. The upper pads (522) of the connection substrate may be positioned on the upper surface of the connection substrate (500). The lower pads (524) of the connecting substrate can be disposed on the lower surface of the connecting substrate (500). The connecting substrate vias (526) penetrate the substrate base layer (510) and can electrically connect the upper pads (522) of the connecting substrate and the lower pads (524) of the connecting substrate.

[0071] A connection board (500) can be mounted on a lower package board (100). For example, connection board terminals (530) may be provided on the lower pads (524) of the connection board. The connection board (500) can be connected to a second board pad (124) of the lower package board (100) using the connection board terminals (530). Accordingly, the connection board (500) can be electrically connected to a semiconductor chip (200) and external terminals (105).

[0072] A lower semiconductor chip (200) may be disposed on a lower package substrate (100). The lower semiconductor chip (200) may be the same or similar as described with reference to FIG. 1. For example, the lower semiconductor chip (200) may have a recognition mark (240) provided on its upper surface (200a). The recognition mark (240) may have a marking pattern (242) and a molding pattern (244). The lower semiconductor chip (200) may be disposed within a second opening (OP2) of a connection substrate (500).

[0073] The lower molding film (310) can fill the space between the connection substrate (500) and the lower semiconductor chip (200) on the lower package substrate (100). The lower molding film (310) can surround the lower semiconductor chip (200) within the second opening (OP2) and expose the upper surface of the lower semiconductor chip (200). The lower molding film (310) can expose the upper surface (500a) of the connection substrate (500). The upper surface (500a) of the connection substrate (500) can be provided at the same level as the upper surface (310a) of the lower molding film (310) and the upper surface (200a) of the lower semiconductor chip (200).

[0074] A redistribution layer (400) may be provided on a connection substrate (500). The redistribution layer (400) may be in contact with the upper surface (500a) of the connection substrate (500) and the upper surface (200a) of the lower semiconductor chip (200). The redistribution layer (400) may be the same or similar as described with reference to FIGS. 1 to 5. For example, the redistribution layer (400) may have a first opening (OP1) that exposes a recognition mark (240) of the lower semiconductor chip (200). The redistribution layer (400) may include at least one second substrate wiring layer stacked on top of each other. Each of the second substrate wiring layers may include a second substrate insulation pattern (410) and a second substrate wiring pattern (420). The second substrate wiring pattern (420) of the second substrate wiring layer at the bottom can penetrate the second substrate insulation pattern (410) and be connected to the upper pads (522) of the connecting substrate of the connecting substrate (500).

[0076] FIG. 10 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention.

[0077] Referring to FIG. 10, the semiconductor package may include a lower package (10) and an upper package (20). That is, the semiconductor package may be a Package on Package (PoP) in which the upper package (20) is mounted on the lower package (10).

[0078] The lower package (10) may have the same or similar structure as the semiconductor package described with reference to FIGS. 1 to 9. The description of the semiconductor packages of FIGS. 1 to 9 may likewise apply to the lower package (10).

[0079] The upper package (20) may include an upper package substrate (610), an upper semiconductor chip (620), and an upper molding part (630).

[0080] The upper package substrate (610) may be placed on the redistribution layer (400). At this time, the upper package substrate (610) may be spaced vertically apart from the redistribution layer (400). The upper package substrate (610) may be a printed circuit board (PCB) having signal patterns. Alternatively, the upper package substrate (610) may have a structure in which an insulating film and a wiring layer are stacked alternately.

[0081] The upper package substrate (610) can be mounted on the redistribution layer (400). For example, substrate terminals (612) can be disposed below the upper package substrate (610). The substrate terminals (612) can be connected to a second substrate wiring pattern (420) of the redistribution layer (400). The substrate terminals (612) may include a solder ball or a solder bump.

[0082] At least one upper semiconductor chip (620) may be disposed on the upper package substrate (610). If multiple upper semiconductor chips (620) are provided, the upper semiconductor chips (620) may be stacked vertically from each other or spaced apart from each other in a planar view. The upper semiconductor chip (620) may be mounted on the upper surface of the upper package substrate (610). For example, the upper semiconductor chip (620) may be mounted on the substrate pads of the upper package substrate (610) by a wire bonding method. That is, the upper semiconductor chip (620) may be electrically connected to the upper package substrate (610) by a bonding wire (622). Alternatively, the upper semiconductor chip (620) may be mounted on the substrate pads of the upper package substrate (610) by a flip chip bonding method. However, embodiments of the present invention are not limited thereto, and the upper semiconductor chip (820) may be mounted on the upper package substrate (610) by various mounting means such as a solder ball or a solder bump. The upper semiconductor chip (620) may be, for example, a logic chip or a memory chip. The upper semiconductor chip (620) may be electrically connected to the lower package substrate (100) through the upper package substrate (610), the redistribution layer (400), and the through electrode (315). Although FIG. 10 illustrates the inclusion of two upper semiconductor chips (620), the upper semiconductor chips (620) may be provided as one or more than three.

[0083] An upper molding portion (630) may be provided on an upper package substrate (610). The upper molding portion (630) may surround an upper semiconductor chip (620) on the upper surface of the upper package substrate (610). For example, the upper molding portion (630) may embed the upper semiconductor chip (620) on the upper package substrate (610).

[0085] FIGS. 11 to 20 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to embodiments of the present invention.

[0086] Referring to FIG. 11, a carrier substrate (900) may be provided. The carrier substrate (900) may be an insulating substrate including glass or a polymer, or a conductive substrate including a metal. An adhesive member may be provided on the upper surface of the carrier substrate (900). For example, the adhesive member may include an adhesive tape.

[0087] A first substrate insulating pattern (110) may be formed on a carrier substrate (900). The first substrate insulating pattern (110) may be formed by applying and curing an insulating material on the carrier substrate (900). The first substrate insulating pattern (110) may cover the upper surface of the carrier substrate (900). The insulating material may include a photosensitive insulating material (PID).

[0088] Openings can be formed by patterning the first substrate insulation pattern (110). The openings can expose the upper surface of the carrier substrate (900). The openings can define an area where under-bump pads (126) are formed.

[0089] A first substrate wiring pattern (120) may be formed on a first substrate insulating pattern (110). For example, a first seed / barrier film (130) may be formed on the upper surface of the first substrate insulating pattern (110), a mask pattern may be formed on the first seed / barrier film (130), and a plating process may be performed using the first seed / barrier film (130) exposed by the mask pattern as a seed to form the first substrate wiring pattern (120). Afterward, the mask pattern and the first seed / barrier film (130) located below the mask pattern may be removed.

[0090] As described above, a first substrate wiring layer having a first substrate insulation pattern (110) and a first substrate wiring pattern (120) can be formed. By repeating the process of forming the first substrate wiring layer, a lower package substrate (100) having the first substrate wiring layer stacked thereon can be formed. The first substrate wiring pattern (120) of the first substrate wiring layer located at the top may correspond to the first substrate pads (122) and the second substrate pad (124) of the lower package substrate (100).

[0091] Referring to FIG. 12, a through electrode (315) may be formed on a lower package substrate (100). Specifically, a sacrificial film may be formed on the lower package substrate (100). The sacrificial film may cover the upper surface of the package substrate (100). The sacrificial film may, for example, include a photoresist material. An etching process (or an exposure and development process) may be performed on the sacrificial film to form a via hole that penetrates the sacrificial film and exposes a second substrate pad (124). Subsequently, a conductive material may be filled into the via hole to form the through electrode (315). The sacrificial film may then be removed. Multiple through electrodes (315) may be formed as needed.

[0092] Referring to FIG. 13, a lower semiconductor chip (200) may be provided. The configuration of the lower semiconductor chip (200) may be the same or similar as described with reference to FIG. 1. For example, the lower semiconductor chip (200) may include a first circuit layer (210) provided on the active surface of the lower semiconductor chip (200), and first chip pads (220) connected to the first circuit layer (210).

[0093] A marking pattern (242) may be formed on an inactive surface (200a) of a lower semiconductor chip (200). The marking pattern (242) may be formed using a laser patterning process. However, the present invention is not limited thereto, and various processes capable of forming an intaglio marking pattern (242) on the inactive surface (200a) of the lower semiconductor chip (200) may be used.

[0094] Referring to FIG. 14, a lower semiconductor chip (200) may be mounted on a package substrate (100). For example, first chip terminals (230) may be provided on first chip pads (220) of the lower semiconductor chip (200). After the lower semiconductor chip (200) is aligned so that the first chip terminals (230) are positioned on the first substrate pads (122) of the lower package substrate (100), a reflow process may be performed to connect the first chip terminals (230) to the first substrate pads (122). The upper surface (200a, corresponding to the inactive surface (200a) of the lower semiconductor chip (200)) of the lower semiconductor chip (200) may be located at the same level as or lower than the upper surface of the through electrode (315).

[0095] Referring to FIG. 15, a lower molding film (310) may be formed on a lower package substrate (100). For example, a molding material may be applied to embed a lower semiconductor chip (200) on the upper surface of the lower package substrate (100). The molding material may be cured to form a lower molding film (310). The lower molding film (310) may cover the side and upper surfaces of the lower semiconductor chip (200). At this time, the lower molding film (310) may fill the interior of a marking pattern (242) formed on the upper surface (200a) of the lower semiconductor chip (200). The lower molding film (310) may surround a through electrode (315). At this time, the through electrode (315) may be embedded by the lower molding film (310).

[0096] Referring to FIG. 16, a portion of the lower molding film (310) may be removed. In detail, the lower molding film (310) may be thinned. For example, a grinding process or a chemical mechanical polishing (CMP) process may be performed on the upper surface (310a) of the lower molding film (310). Accordingly, the upper surface (310a) of the lower molding film (310) may be flattened. The thinning process may be performed until both the upper surface (200a) of the lower semiconductor chip (200) and the upper surface of the through electrode (315) are exposed. By the thinning process, the upper portion of the lower molding film (310) may be removed, and if necessary, the upper portion of the through electrode (315) or the upper portion of the lower semiconductor chip (200) may be removed together. For example, if the upper surface of the through electrode (315) is located at a higher level than the upper surface of the lower semiconductor chip (200), the upper portion of the through electrode (315) may be removed together during the thinning process. Alternatively, if the upper surface of the lower semiconductor chip (200) is located at a higher level than the upper surface of the through electrode (315), the upper portion of the lower semiconductor chip (200) may be removed together during the thinning process. As the thinning process is performed so that the upper surface (200a) of the lower semiconductor chip (200) is exposed, the portion of the lower molding film (310) that filled the inside of the marking pattern (242) may be separated from the remainder of the lower molding film (310) surrounding the lower semiconductor chip (200), and a molding pattern (244) may be formed within the marking pattern (242). The marking pattern (242) and the molding pattern (244) filling the marking pattern (242) can form a recognition mark (240).

[0097] After the above thinning process, the upper surface (200a) of the lower semiconductor chip (200) and the upper surface of the through electrode (315) may be exposed. The upper surface (200a) of the lower semiconductor chip (200), the upper surface (244a) of the molding pattern (244), the upper surface of the through electrode (315), and the upper surface (310a) of the lower molding film (310) may form a substantially flat coplanar surface.

[0098] According to embodiments of the present invention, the molding pattern (244) can compensate for curvature occurring on the upper surface (200a) of the lower semiconductor chip (200) by forming a recognition mark (240), and the upper surface (200a, 244a) of the lower semiconductor chip (200) and the recognition mark (240) can be flat overall. As a result, it may be easy to form a redistribution layer (400) on the lower semiconductor chip (200).

[0099] Referring to FIG. 17, a second substrate insulation pattern (410) may be formed on the lower molding film (310). The second substrate insulation pattern (410) may be formed by applying and curing an insulating material on the lower molding film (310). By patterning the second substrate insulation pattern (410), sub-openings (OPs) in the center and holes in the periphery may be formed. The holes may expose the upper surface of the through electrode (315). The sub-openings (OPs) may expose the upper surface (200a) of the lower semiconductor chip (200). More specifically, the sub-openings (OPs) may expose the recognition mark (240) of the lower semiconductor chip (200).

[0100] A second substrate wiring pattern (420) may be formed on a second substrate insulation pattern (410). For example, a second seed / barrier film (430) may be formed on the upper surface of the second substrate insulation pattern (410), a mask pattern may be formed on the second seed / barrier film (430), and a plating process may be performed using the second seed / barrier film (430) exposed by the mask pattern as a seed to form the second substrate wiring pattern (420). Subsequently, the mask pattern and a portion of the second seed / barrier film (430) located below the mask pattern may be removed. As described above, a second substrate wiring layer having the second substrate insulation pattern (410) and the second substrate wiring pattern (420) may be formed.

[0101] By repeating the process of forming the second substrate wiring layer, a redistribution layer (400) on which the second substrate wiring layer is stacked can be formed. For example, with reference to FIG. 18, a second substrate insulation pattern (410) can be formed on the bottommost second substrate wiring layer. By patterning the second substrate insulation pattern (410), sub-openings (OPs) in the center and holes in the periphery can be formed. The sub-openings (OPs) can expose the recognition mark (240) of the lower semiconductor chip (200). At this time, the width of the sub-openings (OPs) of the second substrate insulation pattern (410) formed therein may be larger than the width of the sub-openings (OPs) of the second substrate insulation pattern (410) that are pre-formed below it. A second substrate wiring pattern (420) can be formed on the second substrate insulation pattern (410). Subsequently, as illustrated in FIG. 19, a second substrate insulating pattern (410) may be formed on the result of FIG. 18. By patterning the second substrate insulating pattern (410), sub-openings (OPs) in the center and holes in the periphery may be formed. The sub-openings (OPs) may expose the recognition mark (240) of the lower semiconductor chip (200). At this time, the width of the sub-openings (OPs) of the second substrate insulating pattern (410) formed may be greater than the width of the sub-openings (OPs) of the second substrate insulating pattern (410) previously formed below it. A second substrate wiring pattern (420) may be formed on the second substrate insulating pattern (410).

[0102] As described above, the second substrate insulating patterns (410) are formed sequentially, and in the process of forming each of the second substrate insulating patterns (410), the sub-openings (OPs) of the second substrate insulating patterns (410) are formed together, and the inner surface of the first opening (OP1) formed by connecting the sub-openings (OPs) may have a stepped shape.

[0103] According to other embodiments, as illustrated in FIG. 20, sub-openings (OPs) may not be formed in each of the second substrate insulating patterns (410) during the formation process of the redistribution layer (400). In this case, the redistribution layer (400) may cover the recognition mark (240). Subsequently, if necessary, a first opening (OP1) may be formed that vertically penetrates the second substrate insulating patterns (410) of the redistribution layer (400). At this time, the width of the first opening (OP1) may be uniform depending on the distance from the upper surface (200a) of the lower semiconductor chip (200). The following description will continue based on the embodiments of FIG. 17 to 19.

[0104] Referring again to FIG. 1, a protective layer (102) may be formed on the lower surface of a package substrate (100). Specifically, the carrier substrate (900) may be removed so that the lower surface of the first substrate insulating pattern (110) is exposed. The protective layer (102) may be formed by depositing an insulating material on the lower surface of the first substrate insulating pattern (110). For example, the insulating material may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or an insulating polymer. Subsequently, the protective layer (102) may be patterned to expose the lower surface of the under bump pads (126).

[0105] External terminals (105) may be provided on the lower surface of the package substrate (100). In detail, the external terminals (105) may be disposed on under bump pads (126) exposed by the protective layer (102). The external terminals (105) may include a solder ball or a solder bump.

[0107] FIGS. 21 to 23 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to embodiments of the present invention.

[0108] Referring to FIG. 21, a connection substrate (500) may be mounted on a lower package substrate (100) in the result of FIG. 11. The connection substrate (500) may be the same or similar as described with reference to FIG. 9. For example, the connection substrate (500) may have a second opening (OP2) penetrating the interior. The connection substrate (500) may include a substrate base layer (510) and a conductive portion (520), which is a wiring pattern provided within the substrate base layer (510). The conductive portion (520) may be positioned outside the connection substrate (500) from the opening. The conductive portion (520) may include upper pads (522) of the connection substrate, lower pads (524) of the connection substrate, and vias (526) of the connection substrate. The upper pads (522) of the connection substrate may be positioned on the upper side of the connection substrate (500). The lower pads (524) of the connecting substrate can be disposed on the lower surface of the connecting substrate (500). The connecting substrate vias (526) penetrate the substrate base layer (510) and can electrically connect the upper pads (522) of the connecting substrate and the lower pads (524) of the connecting substrate.

[0109] A connection board (500) can be mounted on a lower package board (100). For example, connection board terminals (530) may be provided on the lower pads (524) of the connection board. After the connection board (500) is aligned so that the connection board terminals (530) are positioned on the second board pads (124) of the lower package board (100), a reflow process can be performed to connect the connection board terminals (530) to the second board pads (124).

[0110] A lower semiconductor chip (200) may be mounted on a package substrate (100). For example, first chip terminals (230) may be provided on first chip pads (220) of the lower semiconductor chip (200). After the lower semiconductor chip (200) is aligned so that the first chip terminals (230) are positioned on the first substrate pads (122) of the lower package substrate (100), a reflow process may be performed to connect the first chip terminals (230) to the first substrate pads (122). The upper surface (200a) of the lower semiconductor chip (200) may be located at the same or similar level as the upper surface of the connection substrate (500).

[0111] Referring to FIG. 22, a lower molding film (310) may be formed on a lower package substrate (100). For example, a molding material may be applied to embed a lower semiconductor chip (200) on the upper surface of the lower package substrate (100). The molding material may be cured to form a lower molding film (310). The lower molding film (310) may cover the side and upper surfaces of the lower semiconductor chip (200). At this time, the lower molding film (310) may fill the interior of a marking pattern (242) formed on the upper surface (200a) of the lower semiconductor chip (200). The lower molding film (310) may fill the space between the connection substrate (500) and the lower semiconductor chip (200) within the second opening (OP2) of the connection substrate (500). The lower molding film (310) may cover the upper surface of the connection substrate (500).

[0112] Referring to FIG. 22, a portion of the lower molding film (310) may be removed. In detail, the lower molding film (310) may be thinned. For example, a grinding process or a chemical mechanical polishing (CMP) process may be performed on the upper surface (310a) of the lower molding film (310). Accordingly, the upper surface (310a) of the lower molding film (310) may be flattened. The thinning process may be performed until both the upper surface (200a) of the lower semiconductor chip (200) and the upper surface of the connecting substrate (500) are exposed. As the thinning process is performed so that the upper surface (200a) of the lower semiconductor chip (200) is exposed, a portion of the lower molding film (310) that filled the inside of the marking pattern (242) can be separated from the remainder of the lower molding film (310) surrounding the lower semiconductor chip (200), and a molding pattern (244) can be formed within the marking pattern (242). The marking pattern (242) and the molding pattern (244) filling the inside of the marking pattern (242) can form a recognition mark (240).

[0113] After the above thinning process, the upper surface (200a) of the lower semiconductor chip (200) and the upper surface of the connecting substrate (500) may be exposed. The upper surface (200a) of the lower semiconductor chip (200), the upper surface (244a) of the molding pattern (244), the upper surface of the connecting substrate (500), and the upper surface (310a) of the lower molding film (310) may form a substantially flat coplanar surface.

[0114] Subsequently, a redistribution layer (400) may be formed according to the process described with reference to FIGS. 17 to 20. For example, a second substrate insulation pattern (410) may be formed on a lower molding film (310), and the second substrate insulation pattern (410) may be patterned to form sub-openings (OPs) in the center and holes in the periphery. The holes may expose the upper surface of the upper pads (522) of the connection substrate of the connection substrate (500). The sub-openings (OPs) may expose the recognition mark (240) of the lower semiconductor chip (200). A second substrate wiring pattern (420) may be formed on the second substrate insulation pattern (410). For example, a second seed / barrier film (430) may be formed on the upper surface of a second substrate insulating pattern (410), a mask pattern may be formed on the second seed / barrier film (430), and a plating process may be performed using the second seed / barrier film (430) exposed by the mask pattern as a seed to form a second substrate wiring pattern (420). Subsequently, the mask pattern and a portion of the second seed / barrier film (430) located below the mask pattern may be removed. As described above, a second substrate wiring layer having the second substrate insulating pattern (410) and the second substrate wiring pattern (420) may be formed, and the above process may be repeated to form a redistribution layer (400).

[0115] Referring again to FIG. 1, a protective layer (102) may be formed on the lower surface of a package substrate (100). Specifically, the carrier substrate (900) may be removed so that the lower surface of the first substrate insulating pattern (110) is exposed. An insulating material may be deposited on the lower surface of the first substrate insulating pattern (110) to form the protective layer (102). Subsequently, the protective layer (102) may be patterned to expose the lower surface of the under bump pads (126).

[0116] External terminals (105) may be provided on the lower surface of the package substrate (100). In detail, the external terminals (105) may be placed on under bump pads (126) exposed by the protective layer (102).

[0118] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0119] 100: Lower package substrate 200: Lower semiconductor chip 240: Recognition mark 242: Marking pattern 244: Molding pattern 310: Bottom molding membrane 315: Through-electrode 400: Rewiring layer 500: Connection board

Claims

Claim 1 A semiconductor package comprising: a lower substrate; a lower semiconductor chip mounted on the lower substrate; a lower molding film surrounding the lower semiconductor chip on the lower substrate; a redistribution layer disposed on the lower molding film; and a vertical connection terminal connecting the lower substrate and the redistribution layer at one side of the lower semiconductor chip, wherein the lower semiconductor chip includes an identification mark provided on its upper surface, and the identification mark includes: a marking pattern formed in intaglio on the upper surface of the lower semiconductor chip; and a molding pattern filling the interior of the marking pattern; wherein a first material constituting the molding pattern is identical to a second material constituting the lower molding film, and the redistribution layer has a first opening penetrating it vertically, wherein the first opening is located on the lower semiconductor chip and exposes the identification mark. Claim 2 A semiconductor package according to claim 1, wherein the upper surface of the molding pattern and the upper surface of the lower semiconductor chip form a coplanar plane. Claim 3 In claim 1, the semiconductor package wherein the molding pattern and the lower molding film comprise an epoxy molding compound. Claim 4 delete Claim 5 In claim 1, the redistribution layer comprises: insulating patterns stacked vertically; and wiring patterns that each provide horizontal wiring within the insulating patterns and are electrically connected to each other; wherein the inner surface of the first opening has a stepped shape in which each of the insulating patterns forms a single step. Claim 6 In claim 1, the redistribution layer comprises: an insulating pattern; and a wiring pattern that provides horizontal wiring within the insulating pattern and is connected to the vertical connection terminal; wherein the insulating pattern comprises a transparent material. Claim 7 In claim 6, the wiring pattern is a semiconductor package located outside the recognition mark in a planar view. Claim 8 In claim 6, the insulating pattern comprises a semiconductor package including a transparent PID (photoimaginable dielectric). Claim 9 A semiconductor package according to claim 1, wherein the upper surface of the lower semiconductor chip forms a co-plane with the upper surface of the lower molding film. Claim 10 In claim 1, the first material constituting the molding pattern is a semiconductor package having a color different from the upper surface of the lower semiconductor chip. Claim 11 A semiconductor package comprising: a substrate; a semiconductor chip mounted on the substrate; a molding film surrounding the semiconductor chip on the substrate; a redistribution layer disposed on the molding film; and a through electrode connecting the substrate and the redistribution layer at one side of the semiconductor chip, wherein the semiconductor chip includes an identification mark provided on its upper surface, and the identification mark includes: a marking pattern provided on the upper surface of the semiconductor chip and located at a different level from the upper surface of the semiconductor chip; and a molding pattern provided on the semiconductor chip so as to expose the marking pattern, wherein the uppermost surface of the semiconductor chip is coplanar with the upper surface of the molding pattern. Claim 12 In claim 11, the marking pattern includes an indented area that is recessed from the upper surface of the semiconductor chip toward the interior of the semiconductor chip, the molding pattern fills the indented area, and the uppermost surface of the semiconductor chip is the upper surface of the semiconductor chip, forming a semiconductor package. Claim 13 A semiconductor package according to claim 11, wherein the marking pattern includes a raised area protruding from the upper surface of the semiconductor chip, the molding pattern surrounds the raised area on the upper surface of the semiconductor chip, and the uppermost surface of the semiconductor chip is the upper surface of the raised area. Claim 14 In claim 11, the first material constituting the molding pattern is the same as the second material constituting the molding film in the semiconductor package. Claim 15 In claim 11, the rewiring layer has an opening that penetrates it vertically, said opening is located on the semiconductor chip and exposes the recognition mark in the semiconductor package. Claim 16 In claim 15, the redistribution layer comprises: insulating patterns stacked vertically; and wiring patterns that each provide horizontal wiring within the insulating patterns and are electrically connected to each other; wherein the inner surface of the opening has a stepped shape in which each of the insulating patterns constitutes a single step. Claim 17 In claim 11, the redistribution layer comprises: an insulating pattern; and a wiring pattern that provides horizontal wiring within the insulating pattern and is connected to the through electrode; wherein the redistribution layer covers the entire semiconductor chip on the molding film, and the insulating pattern comprises a transparent material. Claim 18 In claim 17, the wiring pattern is a semiconductor package located outside the recognition mark in a planar view. Claim 19 In claim 11, the uppermost surface of the semiconductor chip forms a co-plane with the upper surface of the molding film in a semiconductor package. Claim 20 A method for manufacturing a semiconductor package comprising: patterning the upper surface of a semiconductor chip to form an intaglio marking pattern; mounting the semiconductor chip on a substrate; forming a vertical connection terminal on the substrate; forming a molding film on the substrate that covers the semiconductor chip and the vertical connection terminal, wherein a portion of the molding film fills the interior of the marking pattern; performing a thinning process on the molding film to expose the upper surface of the semiconductor chip and the upper surface of the vertical connection terminal, wherein a portion of the molding film remaining inside the marking pattern after the thinning process forms a molding pattern; and forming a redistribution layer on the molding film and forming an opening that penetrates the redistribution layer to expose the marking pattern and the molding pattern.

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