Semiconductor package

Abstract

According to embodiments of the present invention, a semiconductor package comprises a package substrate; a semiconductor chip mounted on the package substrate; a connection solder pattern provided between the package substrate and the semiconductor chip; and a dummy bump provided between the package substrate and the semiconductor chip and spaced apart from the connection solder pattern, wherein the connection solder pattern comprises a first intermetallic compound layer, a connection solder layer, and a second intermetallic compound layer, and the dummy bump comprises a dummy pillar and a dummy solder pattern, wherein the thickness of the dummy solder pattern is smaller than the thickness of the connection solder pattern, and the melting point of the dummy solder pattern may be greater than the melting point of the connection solder layer.

Description

Technology Field

[0001] The present invention relates to a semiconductor package, more specifically to a bump of a semiconductor package. Background Technology

[0002] The number of pins and the narrowing of pitch on electrode terminals of semiconductor devices are progressing rapidly. Consequently, research on the miniaturization of semiconductor devices is increasing. It is common for semiconductor devices to have electrical connection terminals, such as solder balls or bumps, to be electrically connected to other electronic components or printed circuit boards. There is a growing demand for these connection terminals to have finer pitches. The problem to be solved

[0003] The problem that the present invention aims to solve is to improve defects in the manufacturing process of semiconductor packages. means of solving the problem

[0004] The present invention relates to a semiconductor package. According to the concept of the present invention, the semiconductor package comprises: a package substrate; a semiconductor chip mounted on the package substrate; a connection solder pattern provided between the package substrate and the semiconductor chip; and a dummy bump provided between the package substrate and the semiconductor chip and spaced apart from the connection solder pattern, wherein the connection solder pattern comprises a first intermetallic compound layer, a connection solder layer, and a second intermetallic compound layer, and the dummy bump comprises a dummy pillar and a dummy solder pattern, wherein the thickness of the dummy solder pattern is smaller than the thickness of the connection solder pattern, and the melting point of the dummy solder pattern may be greater than the melting point of the connection solder layer.

[0005] According to the concept of the present invention, a semiconductor package comprises: a package substrate; a semiconductor chip mounted on the package substrate; a connection bump provided between the package substrate and the semiconductor chip and comprising a connection solder layer; and a dummy bump provided between the package substrate and the semiconductor chip and spaced apart from the connection bump, wherein the connection solder layer comprises a first solder material, and the dummy bump comprises: a dummy pillar; and a dummy solder pattern on the dummy pillar, wherein the dummy solder pattern comprises an intermetallic compound comprising a second solder material, wherein the second solder material is different from the first solder material. The melting point of the dummy solder pattern may be greater than the melting point of the connection solder layer.

[0006] According to the concept of the present invention, a semiconductor package may comprise a package substrate including a connection substrate pad and a dummy substrate pad, wherein the connection substrate pad and the dummy substrate pad are provided on an upper surface of the package substrate; solder balls provided on a lower surface of the package substrate; a semiconductor chip mounted on the upper surface of the package substrate, wherein the semiconductor chip includes a connection chip pad and a dummy chip pad provided on its lower surface; a molding film provided on the upper surface of the package substrate and covering the semiconductor chip; connection bumps between the connection substrate pad and the connection chip pad; and a dummy bump provided between the dummy substrate pad and the dummy chip pad and spaced apart from the connection bumps. Each of the connection bumps may include: a connection pillar; and a connection solder pattern provided on one surface of the connection pillar and comprising a first intermetallic compound layer, a connection solder layer, and a second intermetallic compound layer, and the dummy bump may include: a dummy pillar; and a dummy solder pattern on one surface of the dummy pillar. The above-mentioned connection solder layer comprises a first solder material, and the above-mentioned dummy solder pattern comprises an intermetallic compound comprising a second solder material, wherein the second solder material may be different from the first solder material. The thickness of the above-mentioned dummy solder pattern may be smaller than the thickness of the above-mentioned connection solder pattern. Effects of the invention

[0007] According to embodiments of the present invention, a semiconductor package may include dummy bumps and connection bumps. The dummy bumps may include dummy pillars and dummy solder patterns. The dummy solder patterns are formed by a transition liquid-phase bonding process and may include intermetallic compounds. The connection bumps may include connection pillars and connection solder. During a reflow process for forming the connection solder pattern, the dummy bumps can prevent warping of the semiconductor chip. Accordingly, the connection solder can be well connected to the package substrate and the semiconductor chip. The occurrence of defects in the manufacturing process of the semiconductor package can be prevented. Brief explanation of the drawing

[0008] FIG. 1a is a plan view illustrating a semiconductor package according to embodiments. Figure 1b is a cross-section taken along the line I-I' of Figure 1a. FIG. 1c is an enlarged view of area II of FIG. 1b. FIGS. 2a to 2g are drawings for explaining a method of manufacturing a semiconductor package according to embodiments. Figure 3 is a diagram illustrating an example of a reflow process. FIG. 4a is a plan view illustrating a semiconductor package according to embodiments. FIG. 4b is a plan view illustrating a semiconductor package according to embodiments. Figure 4c is a cross-section taken along the line I-I' of Figure 4b. FIG. 4d is a plan view illustrating a semiconductor package according to embodiments. FIG. 4e is a plan view illustrating a semiconductor package according to embodiments. FIG. 4f is a plan view illustrating a semiconductor package according to embodiments. FIG. 5a is a drawing for explaining a substrate structure and a semiconductor device according to embodiments. FIG. 5b is a drawing for explaining a substrate structure and a semiconductor device according to embodiments. FIG. 5c is a drawing for explaining a substrate structure and a semiconductor device according to embodiments. FIG. 6a is a drawing for explaining a substrate structure and a semiconductor device according to embodiments. FIG. 6b is a diagram illustrating a semiconductor package manufactured using the substrate structure and semiconductor device of FIG. 6a. FIG. 7a is a drawing for explaining a substrate structure and a semiconductor device according to embodiments. FIG. 7b is a diagram illustrating a semiconductor package manufactured using the substrate structure and semiconductor device of FIG. 7a. Specific details for implementing the invention

[0009] In this specification, the same reference numerals throughout the text may refer to the same components. Hereinafter, a semiconductor package and a method for manufacturing the same according to the concept of the present invention will be described.

[0011] FIG. 1a is a plan view illustrating a semiconductor package according to embodiments. FIG. 1b is a cross-sectional view taken along the line I-I' of FIG. 1a. FIG. 1c is an enlarged view of region II of FIG. 1b.

[0012] Referring to FIGS. 1a, 1b, and 1c, the semiconductor package (1) may include a package substrate (100), solder balls (500), a semiconductor chip (200), a bonding bump, a dummy bump (320), and a molding film (400). The package substrate (100) may include, for example, a printed circuit board (PCB). As another example, a redistribution layer (220) may be used as the package substrate (100). The first direction (D1) may be parallel to the upper surface of the package substrate (100). The first direction (D1) may be diagonal. For example, the first direction (D1) may not be parallel to the sides of the package substrate (100). The second direction (D2) may be substantially perpendicular to the upper surface of the package substrate (100). Any two components spaced laterally apart from each other may be spaced horizontally apart from each other. Horizontal may mean parallel to the upper surface of the package substrate (100). For example, horizontal may include parallel to the first direction (D1). Vertical may mean parallel to the second direction (D2).

[0013] The package substrate (100) may include connection substrate pads (111), dummy substrate pads (112), internal wiring (130), and lower pads (140). The lower pads (140) may be provided on the lower surface of the package substrate (100). The lower pads (140) may function as pads for solder balls (500). Internal wiring (130) may be provided within the package substrate (100) to connect with the lower pads (140). The internal wiring (130) and the lower pads (140) may include a conductive material such as metal.

[0014] Connection board pads (111) may be provided on the upper surface of the package substrate (100). The upper surface of the package substrate (100) may face the lower surface. The connection board pads (111) may be electrically connected to the lower pads (140) through internal wiring (130). Being electrically connected to any component includes a direct connection or an indirect connection through other conductive components. The connection board pads (111) may include metals such as copper, aluminum, and / or tungsten, for example.

[0015] Dummy substrate pads (112) are provided on the upper surface of the package substrate (100) and may be spaced apart from the connection substrate pads (111). The dummy substrate pads (112) are spaced apart from the internal wiring (130) and may not be electrically connected to the internal wiring (130). The dummy substrate pads (112) may not be electrically connected to the solder balls (500). The dummy substrate pads (112) may include a metal such as, for example, copper, aluminum, and / or tungsten. The dummy substrate pads (112) may include the same or different metal as the connection substrate pads (111).

[0016] Solder balls (500) may be disposed on the lower surface of the package substrate (100). For example, the solder balls (500) may be disposed on the lower surfaces of the lower pads (140) respectively and connected to the lower pads (140) respectively. The solder balls (500) may be electrically connected to the connection substrate pad (111) and the dummy substrate pad (112). The solder balls (500) may be electrically separated from each other. The solder balls (500) may include a solder material. The solder material may include, for example, tin, bismuth, lead, silver, or an alloy thereof.

[0017] A semiconductor chip (200) may be mounted on the upper surface of a package substrate (100). As shown in FIG. 1a, the semiconductor chip (200) may have a first region (R1) and a second region (R2) in a planar view. The first region (R1) and the second region (R2) of the semiconductor chip (200) may be a center region and an edge region, respectively. For example, the second region (R2) of the semiconductor chip (200) may be provided between the first region (R1) and the side walls of the semiconductor chip (200). The second region (R2) of the semiconductor chip (200) may surround the first region (R1). The second region (R2) of the semiconductor chip (200) may include first edge regions (ER1) and second edge regions (ER2). The semiconductor chip (200) may have corners where the sides meet. The first edge regions (ER1) of the semiconductor chip (200) may be adjacent to the corners. The second edge regions (ER2) of the semiconductor chip (200) may be provided between the first edge regions (ER1).

[0018] The semiconductor chip (200) may be a memory chip, a logic chip, or a buffer chip. The semiconductor chip (200) may include a semiconductor substrate (210), integrated circuits (215), a wiring layer (220), dummy chip pads (252), and connection chip pads (251), as shown in FIG. 1c. The semiconductor substrate (210) may include a semiconductor material such as, for example, silicon, germanium, or silicon-germanium. The upper surface of the semiconductor substrate (210) may correspond to the upper surface of the semiconductor chip (200).

[0019] Integrated circuits (215) may be provided on the lower surface of the semiconductor substrate (210). The integrated circuits (215) may include, for example, transistors.

[0020] A wiring layer (220) may be provided on the lower surface of a semiconductor substrate (210). The wiring layer (220) may include an insulating layer (221) and wiring structures (223). The insulating layer (221) is provided on the lower surface of the semiconductor substrate (210) and may cover integrated circuits (215). The insulating layer (221) may be multilayer. The insulating layer (221) may include a silicon-containing insulating material. The silicon-containing insulating material may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or tetraethyl orthosilicate. Wiring structures (223) may be provided within the insulating layer (221). Wiring structures (223) may be electrically connected to the integrated circuits (215). That a component is electrically connected to the semiconductor chip (200) may mean that it is electrically connected to the integrated circuits (215) of the semiconductor chip (200) through the connection chip pads (251) of the semiconductor chip (200). The wiring structures (223) may include wiring portions and via portions connected to said wiring portions. The lower surface of the wiring layer (220) may be the lower surface of the semiconductor chip (200).

[0021] Dummy chip pads (252) may be provided on the lower surface of the second region (R2) of the semiconductor chip (200). For example, dummy chip pads (252) may be provided on the first edge regions (ER1) of the semiconductor chip (200). The dummy chip pads (252) may include a first metal element. The first metal element may include copper, aluminum, nickel, gold, and / or palladium. As shown in FIG. 1a, the dummy chip pads (252) may have circular shapes. The dummy chip pads (252) may not be electrically connected to the wiring structures (223) and the integrated circuits (215).

[0022] Connection chip pads (251) may be provided on the lower surface of the first region (R1) of the semiconductor chip (200). The connection chip pads (251) may be spaced apart from the dummy chip pads (252). The connection chip pads (251) may be electrically connected to the integrated circuits (215) through wiring structures (223). The connection chip pads (251) may be spaced apart from each other. The connection chip pads (251) may include copper, aluminum, palladium, nickel, and / or gold.

[0023] Connection bumps (310) may be interposed between a first region (R1) of a semiconductor chip (200) and a package substrate (100). For example, the connection bumps (310) may be interposed between connection substrate pads (111) and connection chip pads (251) so as to be electrically connected to the connection substrate pads (111) and the connection chip pads (251). Accordingly, the semiconductor chip (200) may be electrically connected to the package substrate (100) through the connection bumps (310). Hereinafter, for the sake of simplicity of description, a single connection chip pad (251), a single dummy chip pad (252), a single connection substrate pad (111), and a single dummy substrate pad (112) will be described.

[0024] Each of the connection bumps (310) may include a connection pillar (312) and a connection solder pattern (315). The connection pillar (312) may be provided on the lower surface of the corresponding connection chip pad (251). The connection pillar (312) may have a cylindrical shape. The connection pillar (312) may include a metal element such as copper or tungsten. The connection pillar (312) may have a first height (H1).

[0025] A connection solder pattern (315) may be provided on the lower surface of a connection pillar (312). The connection solder pattern (315) may be interposed between the connection pillar (312) and the connection substrate pad (111) and electrically connected to the connection pillar (312) and the connection substrate pad (111).

[0026] The connection solder pattern (315) may include a first solder material. The first solder material may include tin (Sn), silver (Ag), copper (Cu), manganese (Mn), lead (Pb), and / or alloys thereof. The main element of the first solder material may be, for example, tin. The main element of any component may have the highest content ratio among the elements included in said component. For example, tin may be 50 wt% or more of the first solder material. The first solder material may have a melting point of 210°C to 240°C.

[0027] Dummy bumps (320) may be provided between the second region (R2) of the semiconductor chip (200) and the package substrate (100). For example, dummy bumps (320) may be provided on the first edge region (ER1) of the semiconductor chip (200). Dummy bumps (320) may be interposed between dummy substrate pads (112) and dummy chip pads (252). As shown in FIG. 1a, the semiconductor chip (200) may include at least four dummy bumps (320).

[0028] Each of the dummy bumps (320) may include a dummy pillar (322) and a dummy solder pattern (325). The dummy pillar (322) may be provided on the upper surface of the corresponding dummy substrate pad (112). The dummy pillar (322) may have a cylindrical shape. For example, the dummy pillar (322) may have a circular shape in a planar view, as in FIG. 1a. The width of the dummy pillar (322) may be smaller than the width of the dummy chip pad (252). The dummy pillar (322) may include a second metal element. For example, the second metal element may include copper or tungsten. The second metal element may be the same as or different from the first metal element.

[0029] A dummy solder pattern (325) may be provided on a dummy pillar (322). For example, the dummy solder pattern (325) may be interposed between the dummy pillar (322) and the dummy substrate pad (112). The dummy solder pattern (325) may be in direct contact with the dummy pillar (322) and the dummy substrate pad (112). The dummy solder pattern (325) may include an intermetallic compound (IMC). The dummy solder pattern (325) may be electrically connected to the dummy pillar (322) and the dummy substrate pad (112).

[0030] Hereinafter, the connection bump (310) and the dummy bump (320) will be described in more detail with reference to FIG. 1c. Hereinafter, for the sake of simplification, a single connection bump (310) and a single dummy bump (320) will be described.

[0031] The connection bump (310) may include a connection pillar (312) and a connection solder pattern (315). The connection solder pattern (315) may include a first intermetallic compound layer (316), a connection solder layer (315S), and a second intermetallic compound layer (317).

[0032] A first intermetallic compound layer (316) may be provided on the lower surface of the connection solder layer (315S). The first intermetallic compound layer (316) may be in contact with the connection substrate pad (111) and the connection solder layer (315S). The first intermetallic compound layer (316) may include an intermetallic compound of the metal contained in the connection substrate pad (111) and the first solder material. A second intermetallic compound layer (317) may be provided on the upper surface of the connection solder layer (315S). The second intermetallic compound layer (317) may be in contact with the connection solder layer (315S) and the connection pillar (312). The first intermetallic compound layer (316) may include an intermetallic compound of the metal contained in the connection pillar (312) and the first solder material.

[0033] A connecting solder layer (315S) may be interposed between the first intermetallic compound layer (316) and the second intermetallic compound layer (317). The connecting solder layer (315S) may contain the first solder material but may not contain an intermetallic compound. That is, the connecting solder layer (315S) may be the remaining portion that does not form an intermetallic compound during the reflow process. The first solder material is as described above. Accordingly, the melting point of the connecting solder layer (315S) may be the same as the melting point of the first solder material. The connecting solder layer (315S) may have a melting point of 210°C to 240°C. The melting point of the connecting solder layer (315S) may be lower than the melting points of the first intermetallic compound layer (316) and the second intermetallic compound layer (317). The thickness of the connecting solder layer (315S) may be greater than the thickness of the first intermetallic compound layer (316) and the second intermetallic compound layer (317).

[0034] The connection solder pattern (315) may have a first thickness (T1). The first thickness (T1) may be equal to the sum of the thickness of the first intermetallic compound layer (316), the connection solder layer (315S), and the thickness of the second intermetallic compound layer (317). The connection pillar (312) may have a first height (H1). As another example, the connection bump (310) may not include the first intermetallic compound layer (316) and the second intermetallic compound layer (317).

[0035] In drawings other than FIG. 1c, for the sake of simplification, the first intermetallic compound layer (316), the connecting solder layer (315S), and the second intermetallic compound layer (317) are not separately depicted, but the present invention is not limited thereto. In drawings other than FIG. 1c, for the sake of simplification, the depiction of the semiconductor substrate (210), integrated circuits (215), and wiring layer (220) is omitted.

[0036] The dummy bump (320) may include a dummy pillar (322) and a dummy solder pattern (325). The dummy pillar (322) pattern may have a second height (H2). The second height (H2) may be smaller than the first height (H1).

[0037] The dummy solder pattern (325) may include a second metal element contained in the dummy pillar (322), a first metal element contained in the dummy chip pad (252), and an intermetallic compound of the second solder material. The metal compound may be an alloy in which the first metal element, the second metal element, and the second solder material are combined in a specific stoichiometric ratio. The intermetallic compound may have physicochemical properties different from those of the first metal element, the second metal element, and the second solder material. The dummy solder pattern (325) may not include a second solder material in a form other than an intermetallic compound. The second solder material may be different from the first solder material. The second solder material may include bismuth (Bi), indium (In), and / or alloys thereof. The main element of the second solder material may include, for example, bismuth (Bi) or indium (In). For example, the bismuth content ratio or the indium content ratio may be 20 wt% or more of the second solder material. The bismuth content ratio or the indium content ratio may be 20 wt% or more of the dummy solder pattern (325).

[0038] The melting point of the dummy solder pattern (325) may be substantially the same as the melting point of the intermetallic compound of the first metal element, the second metal element, and the second solder material. The dummy solder pattern (325) may have a relatively high melting point by including the intermetallic compound. The melting point of the dummy solder pattern (325) may be higher than the melting point of the connection solder pattern (315). The melting point of the dummy solder pattern (325) may be 270°C or higher. For example, the melting point of the dummy solder pattern (325) may be from 270°C to 3000°C.

[0039] The dummy solder pattern (325) may have a second thickness (T2). The second thickness (T2) may be smaller than the first thickness (T1) and the second height (H2). For example, the second thickness (T2) may be 5 μm to 10 μm.

[0040] The sum of the second thickness (T2) and the second height (H2) may be substantially the same as the sum of the first thickness (T1) and the first height (H1). The fact that the widths, heights, and levels of certain components are identical to one another may mean that the error range that may occur during the process is identical.

[0041] Referring again to FIG. 1b, the semiconductor package (1) may further include an underfill film (410). The underfill film (410) is provided in a gap region between the package substrate (100) and the semiconductor chip (200) to seal the dummy bump (320) and the connection bump (310). The underfill film (410) may include an insulating polymer, for example, an epoxy-based polymer.

[0042] A molding film (400) may be provided on the upper surface of a package substrate (100) to cover a semiconductor chip (200). The molding film (400) may include an insulating polymer, for example, an epoxy-based molding compound. As another example, the underfill film (410) may be omitted, and the molding film (400) may be extended further between the package substrate (100) and the semiconductor chip (200) to seal a dummy bump (320) and a connection bump (310).

[0044] FIGS. 2a to 2g are drawings illustrating a method for manufacturing a semiconductor package according to embodiments. FIGS. 2a, 2b, 2e, and 2g correspond to cross-sections cut along the line I-I' of FIG. 1a. FIG. 2f is an enlarged view of region II of FIG. 2e. Hereinafter, content that overlaps with what has been previously described is omitted.

[0045] Referring to FIG. 2a, a semiconductor device (20) may be provided on a substrate structure (10). The substrate structure (10) may include a package substrate (100), a first connection solder portion (315B), a dummy pillar (322), and a dummy solder portion (325S). The package substrate (100) and the dummy pillar (322) may be substantially the same as those described above in the examples of FIG. 1a through 1c. For example, the first connection solder portion (315B) may be provided on a connection substrate pad (111). The first connection solder portion (315B) may include a first solder material.

[0046] A dummy pillar (322) may be placed on a dummy substrate pad (112). A dummy solder portion (325S) may be provided on the dummy pillar (322). The thickness (T2') of the dummy solder portion (325S) may be substantially the same as the second thickness (T2) of the dummy solder pattern (325) of FIGS. 1a through 1c. For example, the thickness (T2') of the dummy solder portion (325S) may be 5 μm to 10 μm.

[0047] The dummy solder portion (325S) may include a second solder material in a state that is not an intermetallic compound. The second solder material may be different from the first solder material. The melting point of the dummy solder portion (325S) may be lower than the melting point of the first connection solder portion (315B). The melting point of the dummy solder portion (325S) may be lower than 210°C. For example, the melting point of the dummy solder portion (325S) may be between 100°C and 180°C. The dummy solder portion (325S) may include an indium-based solder material and a bismuth-based solder material.

[0048] The semiconductor device (20) may include a semiconductor chip (200) and a conductive connection bump (310A). The semiconductor chip (200) may be substantially the same as described in the examples of FIGS. 1a through 1c. For example, the semiconductor chip (200) may include a dummy chip pad (252) and a connection chip pad (251). However, the semiconductor chip (200) may be flexible. The conductive connection bump (310A) may be provided on the lower surface of the connection chip pad (251). The conductive connection bump (310A) may include a connection pillar (312) and a second connection solder portion (325A). The second connection solder portion (325A) may include a first solder material. The melting point of the dummy solder portion (325S) may be lower than the melting point of the second connection solder portion (315A). The sum of the thickness of the first connecting solder part (315B) and the thickness of the second connecting solder part (315A) may be greater than the first thickness (T1).

[0049] The connecting pillar (312) may be substantially the same as the connecting pillar (312) of FIGS. 1a to 1c. For example, the first height (H1) of the connecting pillar (312) may be smaller than the second height (H2).

[0050] A semiconductor chip (200) may be placed on the upper surface of a package substrate (100). Placing the semiconductor device (20) may be performed at room temperature (e.g., about 27°C). At room temperature, the semiconductor chip (200) may have a cry face shape. For example, the semiconductor chip (200) may have an upwardly convex cross-section. The lower surface of the second region (R2) of the semiconductor chip (200) may be provided at a lower level than the lower surface of the first region (R1). The level of a component may refer to a vertical level. The level difference between the two components may be measured in a second direction (D2). At this time, the conductive connection bump (310A) and the dummy chip pad (252) may be vertically aligned with the first connection solder part (315B) and the dummy solder part (325S), respectively.

[0051] Referring to FIG. 2b, the semiconductor device (20) and the substrate structure (10) are provided to a first temperature condition, and a dummy bump (320) may be formed. The first temperature may be lower than the melting point of the first connecting solder part (315B) and the melting point of the second connecting solder part (315A). The first temperature may be, for example, 130°C to 190°C. The shape of the semiconductor chip (200) may be determined by the difference in the coefficient of thermal expansion (CTE) of the components of the semiconductor chip (200) and the temperature condition. The semiconductor chip (200) at the first temperature condition may have a different shape from the semiconductor chip (200) at room temperature. At the first temperature condition, the upper and lower surfaces of the semiconductor chip (200) may be substantially flat. For example, the upper and lower surfaces of the semiconductor chip (200) may be substantially parallel to the first direction (D1).

[0052] The first temperature may be higher than the melting point of the dummy solder portion (325S). Accordingly, the dummy solder portion (325S) may melt. The dummy solder portion (325S) may form a dummy solder pattern (325) in a transient liquid phase bonding method. The transient liquid phase bonding may be transient liquid phase diffusion bonding. The dummy solder pattern (325) may be bonded to the dummy chip pad (252) and the dummy pillar (322). Hereinafter, the formation of the dummy solder pattern (325) will be described with reference to FIG. 2c and FIG. 2d together.

[0053] FIGS. 2c and 2d are drawings for explaining the formation of a dummy solder pattern according to embodiments, corresponding to drawings showing an enlarged view of region II of FIG. 2b.

[0054] Referring to FIG. 2c, the dummy solder portion (325S) may be melted under a first temperature condition. The second solder material within the dummy solder portion (325S) may be in a liquid state. The second solder material may move into the dummy chip pad (252) and the dummy pillar (322). The second solder material may react with the first metal element within the dummy chip pad (252) and with the second metal element within the dummy pillar (322). The first metal element or intermetallic compound within the dummy chip pad (252) may move into the dummy solder portion (325S) and react with the second solder material. The second metal element within the dummy pillar (322) may move into the dummy solder portion (325S) and react with the second solder material. An intermetallic compound may be formed by these reactions.

[0055] Referring to FIG. 2d, the transition liquid phase process continues so that no second solder material remains in a state other than an intermetallic compound within the dummy solder part (325S). For example, the second solder material may react with the first metal element and the second metal element to form an intermetallic compound of the first metal element, the second metal element, and the second solder material. The intermetallic compound may have a melting point higher than the first temperature condition. Accordingly, a solid dummy solder pattern (325) may be formed.

[0056] If the thickness (T2' in FIG. 2c) of the dummy solder portion (325S) is greater than 10 μm, the second solder material may not be completely converted into an intermetallic compound. The intermetallic compound contained in the dummy solder pattern (325) may not be an intermetallic compound of the first metal element, the second metal element, and the second solder material. For example, a portion of the second solder material may remain within the dummy solder pattern (325), and the dummy solder pattern (325) may contain an intermetallic compound of the first metal element and the second solder material and / or an intermetallic compound of the second metal element and the second solder material. In this case, since the second solder material is in a liquid state during the reflow process described later, it may be difficult to fix the semiconductor chip (200) and the package substrate (100).

[0057] The melting point of the first connecting solder part (315B) and the melting point of the second connecting solder part (315A) may be greater than the first temperature. During the transition liquid phase process, the first connecting solder part (315B) and the second connecting solder part (315A) may not be bonded to each other.

[0058] Referring to FIGS. 2e and 2f, a reflow process of the first connecting solder part (315B) and the second connecting solder part (315A) can be performed to form connecting bumps (310). The reflow process can be performed at a second temperature higher than the first temperature. The second temperature may be equal to or higher than the melting point of the first solder material. For example, the second temperature may be 240°C to 260°C. The first connecting solder part (315B) and the second connecting solder part (315A) can be joined together to form a connecting solder pattern (315). Accordingly, the manufacture of a connecting bump (310) including a connecting pillar (312) and a connecting solder pattern (315) can be completed.

[0059] During the process of forming the connection solder pattern (315), a second connection solder portion (315A) within the connection pillar (312) may move into the second connection solder portion (315A) and react with the second solder material. Accordingly, a second intermetallic compound layer (317) may be formed. A metal element within the connection substrate pad (111) may move into the first connection solder portion (315B) and react with the first solder material. Accordingly, a first intermetallic compound layer (316) may be formed. A connection solder layer (315S) may be provided between the first intermetallic compound layer (316) and the second intermetallic compound layer (317). A portion of the first solder material may remain without forming an intermetallic compound, thereby forming the connection solder pattern (315).

[0061] Figure 3 is a diagram illustrating an example of a reflow process.

[0062] Referring to FIG. 3, the dummy bump (320) may not be formed. The transition liquid bonding process may be omitted, and the process of forming the connection bump (310) may be performed. The process of forming the connection bump (310) may include performing a reflow process under a second temperature condition as previously described in FIG. 2e and FIG. 2f. However, warpage of the semiconductor chip (200) may occur under the second temperature condition. For example, under the second temperature condition, the semiconductor chip (200) may have a smile face shape. For example, the semiconductor chip (200) may have a downwardly convex cross-section. At least one first connection solder part (315B) and at least one second connection solder part (315A) may not be bonded to each other. Accordingly, a defect in the electrical connection between the semiconductor chip (200) and the package substrate (100) may occur. The above at least one first connection solder part (315B) includes the outermost first connection solder part (315B), and the above at least one second connection solder part (315A) may include the outermost second connection solder part (315A).

[0064] According to the embodiments, as described in FIG. 2b, the second solder material contained in the dummy solder portion (325S) can form a dummy solder pattern (325) by a transition liquid phase bonding process under first temperature conditions. The intermetallic compound within the dummy solder pattern (325) may have a very high melting point.

[0065] Referring again to FIGS. 2e and 2f, a reflow process can be performed under a second temperature condition. Since the melting point of the dummy solder pattern (325) is greater than the second temperature, it may be in a solid state during the reflow process. Accordingly, the dummy solder pattern (325) can stably fix the first edge region (ER1) of the semiconductor chip (200) and the package substrate (100). In addition, since the dummy solder pattern (325) contains an intermetallic compound, the bonding force between the dummy solder pattern (325) and the dummy pillar (322), and the bonding force between the dummy solder pattern (325) and the dummy chip pad (252) can be very strong. That is, the bonding force between the dummy bump (320) and the package substrate (100), and the bonding force between the dummy bump (320) and the semiconductor chip (200) can be very strong. The bending of the semiconductor chip (200) described in FIG. 3 can be concentrated in the edge region. For example, the bending of the semiconductor chip (200) may be concentrated in the first edge regions (ER1) of the semiconductor chip (200). According to the embodiments, the semiconductor chip (200) may include at least four dummy bumps (320). Since the dummy bumps (320) are each provided in the first edge regions (ER1) of the semiconductor chip (200), the bending of the semiconductor chip (200) under the second temperature conditions may be prevented / reduced. Accordingly, the phenomenon in which the outermost first connection solder portion (315B) and the outermost second connection solder portion (315A) are not bonded to each other may be prevented. The first connection solder portion (315B) and the second connection solder portion (315A) may be well bonded to each other to form a connection bump (310). The connection bump (310) may be formed in multiple numbers. Accordingly, the semiconductor chip (200) is electrically connected well with the package substrate (100), and the occurrence of defects (e.g., bonding defects) in the manufacturing process of the semiconductor package (1) can be prevented. The manufacturing process yield of the semiconductor package (1) can be improved.

[0066] If the second thickness (T2) is less than 5 μm, the bonding force between the dummy solder pattern (325) and the semiconductor chip (200) or between the dummy solder pattern (325) and the package substrate (100) may be reduced. In this case, it may be difficult to prevent the dummy solder pattern (325) from bending the semiconductor package (1) during the reflow process. If the second thickness (T2) is greater than 10 μm, the dummy solder portion (325S) of FIG. 2a may not be completely converted into a dummy solder pattern (325). That is, the dummy solder portion (325S) may remain within the dummy bump (320). Since the dummy solder portion (325S) is in a liquid state during the reflow process described later, it may be difficult to fix the semiconductor chip (200) and the package substrate (100).

[0067] According to the embodiments, since the second thickness (T2) is 5 μm to 10 μm, the dummy solder pattern (325) can stably fix the semiconductor chip (200) and the package substrate (100). Accordingly, the first connecting solder part (315B) and the second connecting solder part (315A) are well connected to each other, and the occurrence of defects in the manufacturing process of the semiconductor package (1) can be further prevented.

[0068] Referring to FIG. 2g, an underfill film (410) is formed in the gap region between the package substrate (100) and the semiconductor chip (200) to seal the dummy bumps (320) and the connection bumps (310). A molding film (400) is formed on the package substrate (100) to cover the semiconductor chip (200).

[0069] Referring again to FIG. 1b, solder balls (500) can be formed on the lower surfaces of the lower pads (140). Accordingly, the manufacturing of the semiconductor package (1) can be completed.

[0070] In the manufacturing process of the semiconductor package of the present invention, for the sake of simplification of the explanation, a single semiconductor package (1) is illustrated and described, but the method of manufacturing the semiconductor package of the present invention is not limited to manufacturing at the chip level.

[0072] The arrangement of dummy pillars according to the embodiments is described below.

[0073] FIGS. 4a, FIGS. 4b, FIGS. 4d, FIGS. 4e, and FIGS. 4f are plan views illustrating semiconductor packages according to embodiments, respectively. FIG. 4c is a cross-section taken along the line I-I' of FIG. 4b.

[0074] Referring to FIGS. 4a, 4b, 4d, 4e, and 4f, the planar shape or arrangement of the dummy pillar (322) can be varied. The dummy chip pad (255) and the dummy solder pattern (325 in FIG. 1b) may overlap with the dummy pillar (322). The dummy pillar (322) may be provided in multiple numbers.

[0075] As shown in FIG. 4a, dummy pillars (322) can be placed in the first edge region (ER1) and the second edge region (ER2) of the semiconductor chip (200).

[0076] As shown in FIGS. 4b and 4c, dummy pillars (322) can be placed in the first region (R1) and the second region (R2) of the semiconductor chip (200).

[0077] As shown in FIG. 4d, the dummy pillars (322) may have a polygonal shape in a planar view. For example, each of the dummy pillars (322) may have a square shape. As another example, the planar shape of the dummy pillars (322) may be varied in various ways, such as a hexagon or an octagon.

[0078] As shown in FIG. 4e, the dummy pillars (322) may have a rectangular shape in a planar view. At least one of the dummy pillars (322) may overlap with the first edge region (ER1) and the second edge region (ER2) of the semiconductor chip (200).

[0079] As shown in FIG. 4f, the dummy pillars (322) may have an elliptical shape in a planar view. At least one of the dummy pillars (322) may overlap with the first edge region (ER1) and the second edge region (ER2) of the semiconductor chip (200), but is not limited thereto.

[0080] The embodiments of FIGS. 4a, 4b, 4d, 4e, and 4f can be combined with each other. For example, dummy pillars (322) may have a rectangular shape as in FIG. 4d and may be further provided in the first region (R1) of the semiconductor chip (200) as in FIG. 4b.

[0082] Hereinafter, a substrate structure and a semiconductor device according to the embodiments will be described.

[0083] FIG. 5a is a drawing for explaining a substrate structure and a semiconductor device according to embodiments, corresponding to a cross-section cut along line I-I' of FIG. 1a.

[0084] Referring to FIG. 5a, a semiconductor device (20) may be disposed on a substrate structure (10). The substrate structure (10) and the semiconductor device (20) may be substantially the same as those described in the example of FIG. 2a. For example, the semiconductor device (20) may include protection patterns (255) in addition to the semiconductor chip (200) and conductive connection bumps (310A). The protection patterns (255) may be provided on the lower surface of the dummy chip pad (252) and the lower surface of the connection chip pad (251), respectively. In another example, the protection patterns (255) may not be provided on the lower surface of the connection chip pad (251). The protection patterns (255) may include a material different from that of the dummy chip pad (252). For example, the protection patterns (255) may include a metallic material such as nickel, gold, and / or palladium. As another example, the protection patterns (255) may include an organic film such as an organic solderability preservative. The protection patterns (255) can prevent oxidation of the dummy chip pad (252).

[0085] Subsequently, the semiconductor package (10) of FIG. 1b can be manufactured by the methods described in the examples of FIG. 2b to 2g.

[0087] FIG. 5b is a drawing for explaining a substrate structure and a semiconductor device according to embodiments, corresponding to a cross-section cut along line I-I' of FIG. 1a.

[0088] Referring to FIG. 5b, a semiconductor device (20) may be placed on a substrate structure (10). The substrate structure (10) may not include a dummy solder portion (325S), and the semiconductor device (20) may include a dummy solder portion (325S). For example, the dummy solder portion (325S) may be provided on the lower surface of a dummy chip pad (252). Placing the semiconductor device (20) on the substrate structure (10) may include aligning the dummy solder portion (325S) vertically with the dummy pillar (322).

[0089] Subsequently, the semiconductor package (10) of FIG. 1b can be manufactured by the methods described in the examples of FIG. 2b to 2g.

[0091] FIG. 5c is a drawing for explaining a substrate structure and a semiconductor device according to embodiments, corresponding to a cross-section cut along line I-I' of FIG. 1a.

[0092] Referring to FIG. 5c, a semiconductor device (20) may be placed on a substrate structure (10). The substrate structure (10) may not include a first connection solder portion (315B).

[0093] Subsequently, the semiconductor package (10) of FIG. 1b can be manufactured by the methods described in the examples of FIG. 2b to 2g. However, the second connection solder portion (315A) may be in direct contact with the connection substrate pad (111). The reflow process described in FIG. 2e and 2f may include reflowing the second connection solder portion (315A) to form a connection solder pattern (315). The connection solder pattern (315) may be bonded to the connection substrate pad (111).

[0095] FIG. 6a is a drawing for explaining a substrate structure and a semiconductor device according to embodiments. FIG. 6b is a drawing showing a semiconductor package manufactured using the substrate structure and semiconductor device of FIG. 6a. FIG. 6a and FIG. 6b correspond to cross-sections cut along the line I-I' of FIG. 1a.

[0096] Referring to FIG. 6a, a semiconductor device (20) may be disposed on a substrate structure (10). The semiconductor device (20) may include a semiconductor chip (200) and a conductive connection bump (310A), in addition to a dummy pillar (322) and a dummy solder portion (325S). The dummy pillar (322) may be interposed between a dummy chip pad (252) and a dummy solder portion (325S). The second height (H2) of the dummy pillar (322) may be greater than the first height (H1) of the connection pillar (312). Accordingly, the lower surface of the dummy pillar (322) pattern may be provided at a lower level than the lower surface of the connection pillar (312). The dummy solder portion (325S) may be vertically spaced apart from the dummy substrate pad (112).

[0097] The substrate structure (10) may include a package substrate (100) and a first connection solder portion (315B). Unlike what is illustrated, the first connection solder portion (315B) may be omitted.

[0098] Referring to FIG. 6b, dummy bumps (320) and connection bumps (310) can be formed by the same methods as described in the examples of FIG. 2b through 2g. Accordingly, the semiconductor chip (200) can be electrically connected to the package substrate (100). The dummy bump (320) may include a dummy pillar (322) and a dummy solder pattern (325). The dummy solder pattern (325) may be interposed between the dummy pillar (322) and the dummy substrate pad (112). The dummy solder pattern (325) may include a second metal element contained in the dummy pillar (322), a metal element contained in the dummy substrate pad (112), and an intermetallic compound of the second solder material. As an example, the metal element contained in the dummy substrate pad (112) may be the same element as the second metal element (e.g., copper). As another example, the metal element included in the dummy substrate pad (112) may be different from the second metal element. The second thickness (T2) of the dummy solder pattern (325) may be smaller than the second height (H2).

[0099] The connection bump (310) may include a connection solder pattern (315) and a connection pillar (312). The first thickness (T1) of the connection solder pattern (315) may be greater than the second thickness (T2). The sum of the second thickness (T2) and the second height (H2) may be substantially the same as the sum of the first thickness (T1) and the first height (H1).

[0100] Solder balls (500) are attached to the lower surface of the package substrate (100), so that a semiconductor package (1A) can be manufactured.

[0102] FIG. 7a is a drawing for explaining a substrate structure and a semiconductor device according to embodiments. FIG. 7b is a drawing showing a semiconductor package manufactured using the substrate structure and semiconductor device of FIG. 7a. FIG. 7a and FIG. 7b correspond to cross-sections cut along line I-I' of FIG. 1a.

[0103] Referring to FIG. 7a, a semiconductor device (20) may be disposed on a substrate structure (10). In addition to a semiconductor chip (200) and a conductive connection bump (310A), the semiconductor device (20) may include an upper dummy pillar (322SA) and an upper dummy solder portion (325SA). The upper dummy pillar (322SA) may include materials described in the example of the dummy pillar (322) of FIG. 1a to 1c. The upper dummy pillar (322SA) may be interposed between a dummy chip pad (252) and a dummy solder portion (325S). The dummy solder portion (325S) may be vertically spaced from the substrate structure (10). The upper dummy solder portion (325SA) may include a second solder material.

[0104] The substrate structure (10) may include a package substrate (100), a first connection solder portion (315B), a lower dummy pillar (322B), and a lower dummy solder portion (325SB). The lower dummy pillar (322B) may include materials described in the example of the dummy pillar (322) of FIGS. 1a to 1c. The lower dummy pillar (322B) may include a third solder material. The third solder material may include any one of the elements described in the example of the second solder material and may have a melting point of 100°C to 180°C. As an example, the third solder material may include the same element as the second solder material and may have the same composition ratio.

[0105] Referring to FIG. 7b, dummy bumps (320) and connection bumps (310) can be formed by the same methods described in the examples of FIG. 2b to 2g. Accordingly, the semiconductor chip (200) can be electrically connected to the package substrate (100). However, the dummy bump (320) may include a lower dummy pillar (322B), an upper dummy pillar (322SA), and a dummy solder pattern (325). The dummy solder pattern (325) may be interposed between the lower dummy pillar (322B) and the upper dummy pillar (322SA). The dummy solder pattern (325) may include a metal contained in the lower dummy pillar (322B), a metal contained in the upper dummy pillar (322SA), a second solder material, and an intermetallic compound of a third solder material.

[0106] The sum of the height (T3) of the lower dummy pillar (322B), the height (T4) of the upper dummy pillar (322SA), and the second thickness (T2) may be substantially the same as the sum of the first thickness (T1) and the first height (H1). The sum of the height (T3) of the lower dummy pillar (322B) and the height (T4) of the upper dummy pillar (322SA) may be greater than the first height (H1). The second thickness (T2) is as described in FIG. 1b and FIG. 1c.

[0107] Solder balls (500) are attached to the lower surface of the package substrate (100), so that a semiconductor package (1B) can be manufactured.

[0109] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments and may be used in various other combinations, modifications, and environments without departing from the essence of the invention. The appended claims should be interpreted as including other embodiments.

Claims

Claim 1 A semiconductor package comprising: a package substrate; a semiconductor chip mounted on the package substrate; a connection bump provided between the package substrate and the semiconductor chip and comprising a connection solder pattern; and a dummy bump provided between the package substrate and the semiconductor chip and spaced apart from the connection bump, wherein the connection solder pattern comprises a first intermetallic compound layer, a connection solder layer, and a second intermetallic compound layer, wherein the connection solder layer comprises a first solder material, and the dummy bump comprises: a dummy pillar; and a dummy solder pattern on the dummy pillar, wherein the dummy solder pattern comprises an intermetallic compound comprising a second solder material, wherein the second solder material is different from the first solder material, the thickness of the dummy solder pattern is smaller than the thickness of the connection solder pattern, and the melting point of the dummy solder pattern is greater than the melting point of the connection solder layer. Claim 2 delete Claim 3 In claim 1, the connection solder layer is a semiconductor package that does not include an intermetallic compound. Claim 4 A semiconductor package according to claim 1, wherein the semiconductor chip comprises a dummy chip pad provided on its lower surface, the dummy chip pad comprises a first metal element, the dummy pillar comprises a second metal element, and the dummy solder pattern comprises an intermetallic compound of the first metal element, the second metal element, and the solder material. Claim 5 In claim 4, the second metal element is the same or different from the first metal element in the semiconductor package. Claim 6 A semiconductor package according to claim 1, further comprising a connection pillar connected to the connection solder pattern, wherein the connection pillar is interposed between the semiconductor chip and the connection solder pattern, and the dummy pillar is interposed between the package substrate and the dummy solder pattern. Claim 7 In claim 1, the semiconductor chip includes a center region and an edge region in a planar view, and the dummy bump is a semiconductor package provided on the lower surface of the edge region of the semiconductor chip. Claim 8 A semiconductor package comprising: a package substrate; a semiconductor chip mounted on the package substrate; a connection bump provided between the package substrate and the semiconductor chip and comprising a connection solder layer; and a dummy bump provided between the package substrate and the semiconductor chip and spaced apart from the connection bump, wherein the connection solder layer comprises a first solder material, and the dummy bump comprises: a dummy pillar; and a dummy solder pattern on the dummy pillar, wherein the dummy solder pattern comprises an intermetallic compound comprising a second solder material, wherein the second solder material is different from the first solder material, and the melting point of the dummy solder pattern is greater than the melting point of the connection solder layer. Claim 9 In claim 8, the connection bump further comprises a connection pillar electrically connected to the connection solder layer, and the height of the dummy pillar is greater than the height of the connection pillar in a semiconductor package. Claim 10 A package substrate comprising a connection substrate pad and a dummy substrate pad, wherein the connection substrate pad and the dummy substrate pad are provided on an upper surface of the package substrate; solder balls provided on a lower surface of the package substrate; a semiconductor chip mounted on the upper surface of the package substrate, wherein the semiconductor chip comprises a connection chip pad and a dummy chip pad provided on its lower surface; a molding film provided on the upper surface of the package substrate and covering the semiconductor chip; connection bumps between the connection substrate pad and the connection chip pad; and a dummy bump provided between the dummy substrate pad and the dummy chip pad and spaced apart from the connection bumps, wherein each of the connection bumps comprises: a connection pillar; and a connection solder pattern provided on one surface of the connection pillar and comprising a first intermetallic compound layer, a connection solder layer, and a second intermetallic compound layer, wherein the dummy bump comprises: a dummy pillar; A semiconductor package comprising a dummy solder pattern on one side of the dummy pillar, wherein the connecting solder layer comprises a first solder material, and the dummy solder pattern comprises an intermetallic compound comprising a second solder material, wherein the second solder material is different from the first solder material. The thickness of the dummy solder pattern is smaller than the thickness of the connecting solder pattern.

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