Semiconductor package

Abstract

According to embodiments of the present invention, a semiconductor package may include a first redistribution substrate comprising a first under-bump pattern, a second under-bump pattern, and a third under-bump pattern; a semiconductor chip disposed on the first redistribution substrate; conductive structures; and a second redistribution substrate. The third under-bump pattern may be insulated from the first and second under-bump patterns. The conductive structures include: a first conductive structure connected to the first under-bump pattern; a second conductive structure connected to the second under-bump pattern; and a third conductive structure connected to the third under-bump pattern and adjacent to the first and second conductive structures, wherein the third conductive structure is disposed between the first conductive structure and the second conductive structure, and the width of the first under-bump pattern and the width of the second under-bump pattern may be greater than the width of the third under-bump pattern.

Description

Technology Field

[0001] The present invention relates to a semiconductor package, more specifically, a semiconductor package including a redistribution substrate, and a method for manufacturing the same. Background Technology

[0002] A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting semiconductor chips on a printed circuit board and electrically connecting them using bonding wires or bumps. With the advancement of the electronics industry, various studies are underway to improve the reliability and electrical characteristics of semiconductor packages. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor package with improved reliability and electrical characteristics and a method for manufacturing the same. means of solving the problem

[0004] A semiconductor package according to the concept of the present invention is provided. According to the present invention, the semiconductor package may include: a first redistribution substrate comprising a first under-bump pattern, a second under-bump pattern, and a third under-bump pattern; a semiconductor chip disposed on the first redistribution substrate; conductive structures disposed adjacent to the semiconductor chip on the first redistribution substrate, wherein the conductive structures are spaced apart from each other; and a second redistribution substrate on the semiconductor chip and the conductive structures. The third under-bump pattern may be insulated from the first and second under-bump patterns. The conductive structures include: a first conductive structure connected to the first under-bump pattern; a second conductive structure connected to the second under-bump pattern; and includes a third conductive structure adjacent to the first and second conductive structures, wherein the third conductive structure is positioned between the first conductive structure and the second conductive structure, the width of the first under-bump pattern may be greater than the width of the third under-bump pattern, and the width of the second under-bump pattern may be greater than the width of the third under-bump pattern.

[0005] According to the present invention, a semiconductor package may include a first redistribution substrate; a semiconductor chip disposed on the first redistribution substrate; conductive structures disposed on the first redistribution substrate and spaced apart from the semiconductor chip; and a second redistribution substrate on the semiconductor chip and the conductive structures. The conductive structures include a first conductive structure, a second conductive structure, and a third conductive structure adjacent to each other, wherein the third conductive structure is disposed between the first and second conductive structures and may be insulated from the first and second conductive structures. The second redistribution substrate comprises: a first redistribution pattern electrically connected to the first conductive structure; and a second redistribution pattern electrically connected to the second conductive structure. and includes a third redistribution pattern electrically connected to the third conductive structure, wherein the upper surface area of ​​the first redistribution pattern is larger than the upper surface area of ​​the third redistribution pattern, and the upper surface area of ​​the second redistribution pattern may be larger than the upper surface area of ​​the third redistribution pattern.

[0006] According to the present invention, a semiconductor package comprises: a first redistribution substrate including a first insulating layer, under-bump patterns, under-bump seed patterns, a first ground / power conductive pattern, a second ground / power conductive pattern, and a signal conductive pattern; solder balls disposed on the lower surface of the first redistribution substrate and connected to the under-bump patterns; a semiconductor chip disposed on the upper surface of the first redistribution substrate; conductive structures disposed on the upper surface of the first redistribution substrate and positioned adjacent to the semiconductor chip; a molding film disposed on the upper surface of the first redistribution substrate and covering the sidewalls of the semiconductor chip and the sidewalls of the conductive structures; and a second redistribution substrate disposed on the molding film and the conductive structures and electrically connected to the conductive structures, wherein the conductive structures may be spaced apart from each other. The conductive structures include: a first conductive structure connected to the first ground / power conductive pattern; A second conductive structure connected to the second ground / power conductive pattern; a third conductive structure connected to the signal conductive pattern; and a fourth conductive structure connected to the first ground / power conductive pattern, wherein the third conductive structure is disposed between the first and second conductive structures and is adjacent to the first and second conductive structures, and the under-bump seed patterns cover the side walls of the under-bump patterns and may be spaced apart from the lower surfaces of the under-bump patterns. Effects of the invention

[0007] According to the present invention, a conductive structure may include a signal structure, a first ground structure, and a second ground structure. The signal structure is interposed between the first ground structure and the second ground structure and may be adjacent to the first and second ground structures. Accordingly, the occurrence of coupling noise of the signal structure can be prevented. The semiconductor package may exhibit improved reliability and electrical characteristics. Brief explanation of the drawing

[0008] FIG. 1a is a plan view illustrating a semiconductor package according to embodiments. FIG. 1b is a plan view for illustrating a first redistribution substrate according to embodiments. FIG. 1c is a plan view illustrating the arrangement relationship of lower ground / power redistribution patterns, lower signal redistribution patterns, and conductive structures according to embodiments. Figure 1d is a cross-section cut along line AB of Figure 1a. Figure 1e shows an enlarged view of region E in Figure 1d. Figure 1f is a cross-section cut along the CD line of Figure 1a. FIG. 2 is a drawing for explaining the planar arrangement of conductive structures according to embodiments. FIGS. 3a and FIGS. 3b are drawings for illustrating semiconductor packages according to embodiments. FIGS. 4a and FIGS. 4b are drawings for illustrating semiconductor packages according to embodiments. FIGS. 5A and FIGS. 5B are drawings for illustrating semiconductor packages according to embodiments. FIGS. 6a and FIGS. 6b are drawings for illustrating semiconductor packages according to embodiments. FIG. 7a is a plan view of a semiconductor package according to embodiments. Figure 7b is a cross-section taken along the line A'-B' of Figure 7a. Figure 7c is a cross-section taken along the line C'-D' of Figure 7a. FIG. 8a is a plan view of a semiconductor package according to embodiments. Figure 8b is a cross-section cut along the line A''-B'' of Figure 8a. Figure 8c is a cross-section taken along the line C''-D'' of Figure 8a. FIGS. 9a to 9l are drawings for explaining a method of manufacturing a semiconductor package according to embodiments. FIGS. 10a to 10c are drawings for explaining a method of manufacturing a semiconductor package according to embodiments. Specific details for implementing the invention

[0009] In this specification, the same reference numerals throughout the text may refer to the same components. A semiconductor package and a method for manufacturing the same according to the concept of the present invention are described.

[0011] FIG. 1a is a plan view illustrating a semiconductor package according to embodiments. FIG. 1b is a plan view for explaining a first redistribution substrate according to embodiments. FIG. 1c is a plan view for explaining the arrangement relationship of lower ground / power redistribution patterns, lower signal redistribution patterns, and conductive structures according to embodiments. FIG. 1d is a cross-section cut along line AB of FIG. 1a, corresponding to the cross-section cut along line AB of FIG. 1b and line AB of FIG. 1c. FIG. 1e is an enlarged view of region E of FIG. 1d. FIG. 1f is a cross-section cut along line CD of FIG. 1a, corresponding to the cross-section cut along line CD of FIG. 1b and line CD of FIG. 1c.

[0012] Referring to FIGS. 1a, 1b, 1c, 1d, and 1e, the semiconductor package (10) may include a first redistribution substrate (100), solder balls (500), a semiconductor chip (200), conductive structures (300), a molding film (400), and a second redistribution substrate (600).

[0013] Solder balls (500) may be placed on the lower surface of a rewiring board. The solder balls (500) may function as terminals of a semiconductor package (10). The solder balls (500) may include ground / power solder balls (500PG) and signal solder balls (500S). The ground / power solder balls (500PG) and the signal solder balls (500S) may be spaced apart from each other and electrically separated from each other. The ground / power solder balls (500PG) may be terminals to which a ground voltage or a power voltage is applied. The voltage applied to any one of the ground / power solder balls (500PG) may be different from the voltage applied to the other of the ground / power solder balls (500PG). The signal solder balls (500S) may function as a channel for inputting and outputting data signals to and from a semiconductor chip (200). The solder balls (500) may contain a solder material. The solder material may include tin, bismuth, lead, silver, or an alloy thereof.

[0014] The first redistribution substrate (100) may include a first insulating layer (101), under-bump patterns (170PG, 170S), under-bump seed patterns (175), ground / power conduction patterns (130PG), signal conduction patterns (130S), first seed patterns (135), upper seed pads (655), and first redistribution pads (150PG, 150S). The first insulating layer (101) may include an organic material, for example, a photosensitive insulating material. The photosensitive insulating material may be a polymer. The photosensitive insulating material may include at least one of, for example, a photosensitive polyimide, a polybenzoxazole, a phenolic polymer, and a benzocyclobutene polymer. The first insulating layer (101) may be provided in multiples. The number of stacked first insulating layers (101) may vary. For example, a plurality of first insulating layers (101) may contain the same material. The interface between adjacent first insulating layers (101) may not be distinguishable.

[0015] The first direction (D1) may be parallel to the bottom surface (101b) of the lowest first insulating layer (101). The second direction (D2) may be parallel to the bottom surface (101b) of the lowest first insulating layer (101), but substantially perpendicular to the first direction (D1). The third direction (D3) may be substantially perpendicular to the first direction (D1) and the second direction (D2).

[0016] Under bump patterns (170PG, 170S) may include ground / power under bump patterns (170PG) and signal under bump patterns (170S). Each of the under bump patterns (170PG, 170S) may be disposed within and on the lowest first insulating layer (101). The lower portion of each of the under bump patterns (170PG, 170S) may be provided within the lowest first insulating layer (101). The lower portion of each of the under bump patterns (170PG, 170S) may function as a solder pad. For example, ground / power solder balls (500PG) may be provided on the lower portions of the ground / power under bump patterns (170PG) to be connected to the ground / power under bump patterns (170PG). Signal solder balls (500S) are provided on the lower surfaces of the signal under-bump patterns (170S) so as to be connected to the signal under-bump patterns (170S). The upper surface of each of the under-bump patterns (170PG, 170S) has a greater width than the lower surface and can extend onto the upper surface of the lowest first insulating layer (101).

[0017] As shown in FIG. 1d, the width of each ground / power under-bump pattern (170PG) may be greater than the width of each signal under-bump pattern (170S). For example, the width of the upper surface of each ground / power under-bump pattern (170PG) may be greater than the width of the upper surface of each signal under-bump pattern (170S). For example, the under-bump patterns (170PG, 170S) may include a first under-bump pattern (171) and a second under-bump pattern (172) arranged side by side with each other. The signal under-bump patterns (170S) may include a third under-bump pattern (173). The width of the upper surface (W1) of the first under-bump pattern (171) and the width of the upper surface (W2) of the second under-bump pattern (172) may be smaller than the width of the upper surface (W3) of the third under-bump pattern (173). The width of a component can be measured in the first direction (D1).

[0018] The length of each ground / power under-bump pattern (170PG) may be greater than the length of each signal under-bump pattern (170S). For example, the length of the upper surface of each ground / power under-bump pattern (170PG) may be greater than the length of the upper surface of each signal under-bump pattern (170S). For example, the length of the upper surface (L1) of the first under-bump pattern (171) and the length of the upper surface (L2) of the second under-bump pattern (172) may be greater than the length of the upper surface (L3) of the third under-bump pattern (173). The length of a component may be measured in the second direction (D2).

[0019] From a planar perspective, the upper surface area of ​​each of the ground / power under-bump patterns (170PG) may be smaller than the upper surface area of ​​each of the signal under-bump patterns (170S). For example, the upper surface area of ​​the third under-bump pattern (173) may be smaller than the upper surface area of ​​the first under-bump pattern (171) and the upper surface area of ​​the second under-bump pattern (172).

[0020] Since the upper portion of the ground / power under-bump patterns (170PG) has a relatively large width and length, the upper portion of each ground / power under-bump pattern (170PG) can horizontally transmit the voltage received from the solder terminal connected thereto. The voltage may be a ground voltage or a power voltage. “Horizontal” may mean parallel to the first direction (D1) or the second direction (D2).

[0021] Since the upper surfaces of the ground / power under-bump patterns (170PG) have a relatively large width and length, the ground / power under-bump patterns (170PG) can shield the electrical signal of the signal conduction patterns (130S) or the electrical signal of an external device. Electrical interference between the signal conduction patterns (130S) and the external device can be prevented by the ground / power under-bump patterns (170PG). The semiconductor package (10) can exhibit improved operational reliability.

[0022] Hereinafter, the planar arrangement and shape of the under-bump patterns (170PG, 170S) will be described. As shown in FIG. 1b, the planar shape of each signal under-bump pattern (170S) may be circular. The planar areas of the signal under-bump patterns (170S) may be identical to one another, but are not limited thereto. The fact that the level, width, length, or area of ​​certain components are identical to one another may mean that the error range that may occur during the process is identical. Unless otherwise specified in this specification, the planar area of ​​a certain component may mean the area of ​​the upper surface of said component. The planar shape of a certain component may mean the planar shape of the upper surface of said component. The upper surfaces of the ground / power under-bump patterns (170PG) may have different shapes and different areas than the upper surfaces of the signal under-bump patterns (170S). The ground / power under-bump patterns (170PG) may have different shapes and different areas.

[0023] If any one of the ground / power under-bump patterns (170PG) has a relatively large planar area, said ground / power under-bump pattern (170PG) may have a first hole (179). The first hole (179) may penetrate the upper and lower surfaces of the ground / power under-bump pattern (170PG). Although not illustrated, the first insulating layers (101) adjacent to the ground / power under-bump patterns (170PG) may come into direct contact with each other through the first hole (179). Even if the ground / power under-bump pattern (170PG) has a large planar area, the first hole (179) is provided, so that the ground / power under-bump patterns (170PG) may not be concentrated in a specific area from a planar perspective. Accordingly, the reliability of the first redistribution board (100) may be improved. Whether the first hole (179) is formed and the number of the first holes (179) may be determined according to the planar area of ​​the ground / power under-bump patterns (170PG). For example, one of the ground / power under-bump patterns (170PG) may not have the first hole (179). As another example, another of the ground / power under-bump patterns (170PG) may have a plurality of first holes (179), and said first holes (179) may have different shapes or different diameters. The size and shape of the first holes (179) may vary. The signal under-bump patterns (170S) may not have a hole penetrating their interior.

[0024] The under-bump patterns (170PG, 170S) may contain a metallic material such as copper. The under-bump patterns (170PG, 170S) may not contain titanium, for example.

[0025] Referring to FIG. 1d and FIG. 1e, the lower surfaces (170b) of the under-bump patterns (170PG, 170S) may be positioned at a higher level than the bottom surface (101b) of the first insulating layer (101). The level may refer to a vertical level, and the level difference of the components may be measured in a third direction (D3).

[0026] Under-bump seed patterns (175) may be interposed between the lowest first insulating layer (101) and the under-bump patterns (170PG, 170S). For example, the under-bump seed patterns (175) may cover the side walls of the lower parts and the lower surfaces of the upper parts of the under-bump patterns (170PG, 170S). The under-bump seed patterns (175) may include conductive seed materials. The conductive seed materials may include copper, titanium, and / or alloys thereof. The under-bump seed patterns (175) may function as barrier layers to prevent the diffusion of materials contained in the under-bump patterns (170PG, 170S). The under-bump seed patterns (175) may function as an adhesive layer. For example, the adhesion between the bottom first insulating layer (101) and the under bump patterns (170PG, 170S) can be improved by the under bump seed patterns (175). Accordingly, damage to the under bump patterns (170PG, 170S) can be prevented. The reliability and durability of the semiconductor package (10) can be improved.

[0027] The bonding force between the solder balls (500) and the conductive seed material may be relatively low. The under-bump seed patterns (175) may not be placed on the under-sides (170b) of the under-bump patterns (170PG, 170S). The solder balls (500) may be in direct physical contact with the under-sides (170b) of the under-bump patterns (170PG, 170S). The adhesion force between the solder balls (500) and the under-bump patterns (170PG, 170S) may be greater than the bonding force between the solder balls (500) and the conductive seed material. Accordingly, the solder balls (500) can be stably attached to the under-bump patterns (170PG, 170S).

[0028] As shown in FIG. 1e, each of the under-bump seed patterns (175) may have a first thickness (T). The first thickness (T) may be the thickness of a first portion of each of the under-bump patterns (170PG, 170S), and the bottom surface of the first portion may be parallel to the first direction (D1). The bottom surface (175b) of each of the under-bump seed patterns (175) may be placed at the same or a higher level as the bottom surface (170b) of the corresponding under-bump pattern (170PG, 170S). For example, the level difference between the bottom surface (175b) of the under-bump seed pattern (175) and the bottom surface (170b) of the under-bump pattern (170PG, 170S) may be greater than the first thickness (T) and less than 10 times the first thickness (T). The lower surface (170b) of each under-bump pattern (170PG, 170S) may be provided at a higher level than the bottom surface (101b) of the lowest first insulating layer (101). The level difference between the lower surface (170b) of each under-bump pattern (170PG, 170S) and the bottom surface (101b) of the lowest first insulating layer (101) may be substantially the same as the first thickness (T).

[0029] Referring to FIGS. 1d and 1f, conductive patterns (130PG, 130S) may be provided on under-bump patterns (170PG, 170S). The conductive patterns (130PG, 130S) may include ground / power conductive patterns (130PG) and signal conductive patterns (130S). The conductive patterns (130PG, 130S) may include a metal such as copper. Connecting to the first redistribution board (100) may include connecting to at least one of the conductive patterns (130PG, 130S).

[0030] Ground / power conduction patterns (130PG) can be electrically connected to ground / power under-bump patterns (170PG). Each of the ground / power conduction patterns (130PG) may include a first ground / power conduction pattern (131PG), a second ground / power conduction pattern (132PG), and a third ground / power conduction pattern (133PG). The first ground / power conduction pattern (131PG) is provided on the corresponding ground / power under-bump pattern (170PG) so as to be connected to the ground / power under-bump pattern (170PG). The second ground / power conduction pattern (132PG) is provided between the first ground / power conduction pattern (131PG) and the third ground / power conduction pattern (133PG) so as to be connected to the first and third ground / power conduction patterns (131PG, 133PG). The number of stacked ground / power conduction patterns (130PG) is not limited to what is shown and can be varied in many ways.

[0031] Each of the signal conduction patterns (130S) may include a first signal conduction pattern (131S), a second signal conduction pattern (132S), and a third signal conduction pattern (133S). The first signal conduction pattern (131S) is provided on a corresponding signal under-bump pattern (170S) and can be connected to the signal under-bump pattern (170S). The second signal conduction pattern (132S) is provided between the first signal conduction pattern (131S) and the third signal conduction pattern (133S) and can be connected to the first and third signal conduction patterns (131S, 133S). The first signal conduction pattern (131S), the second signal conduction pattern (132S), and the third signal conduction pattern (133S) may be spaced apart laterally from the first ground / power conduction pattern (131PG), the second ground / power conduction pattern (132PG), and the third ground / power conduction pattern (133PG), respectively. Being spaced apart laterally may mean being spaced apart horizontally. The first signal conduction pattern (131S), the second signal conduction pattern (132S), and the third signal conduction pattern (133S) may each contain the same material as the first ground / power conduction pattern (131PG), the second ground / power conduction pattern (132PG), and the third ground / power conduction pattern (133PG).

[0032] Each of the ground / power conduction patterns (130PG) and each of the signal conduction patterns (130S) may include a via portion and a wiring portion. The via portion may be provided within the corresponding first insulating layer (101). The wiring portion may be provided on the via portion and may be connected to the via portion without a boundary surface. The width of the wiring portion may be greater than the width of the via portion. The wiring portion may extend onto the upper surface of the corresponding first insulating layer (101). In this specification, the via may be a configuration for vertical connection and the wiring may be a configuration for horizontal connection. “Vertical” may mean perpendicular to the bottom surface (101b) of the lowest first insulating layer (101).

[0033] The first seed patterns (135) may be placed on the lower surfaces of the corresponding conduction patterns (130PG, 130S). For example, the first seed patterns (135) may be placed on the lower surfaces of the signal conduction patterns (130S) and on the lower surfaces of the ground / power conduction patterns (130PG). For example, each of the first seed patterns (135) may cover the lower surface and sidewall of the via portion of the corresponding conduction pattern (130PG, 130S) and the lower surface of the wiring portion. The first seed patterns (135) may not extend onto the sidewall of the wiring portion. The first seed patterns (135) may comprise a material different from the under-bump patterns (170PG, 170S), the ground / power conduction patterns (130PG), and the signal conduction patterns (130S). For example, the first seed patterns (135) may include a conductive seed material. The first seed patterns (135) may function as barrier layers to prevent the diffusion of the material contained in the ground / power conductive patterns (130PG) and the signal conductive patterns (130S).

[0034] Rewiring pads (150PG, 150S) may be provided within the uppermost first insulating layer (101). The rewiring pads (150PG, 150S) may extend further over the upper surface of the uppermost first insulating layer (101). The rewiring pads (150PG, 150S) may include ground / power rewiring pads (150PG) and signal rewiring pads (150S). Each of the ground / power rewiring pads (150PG) may be placed on a corresponding third ground / power conductive pattern (133PG). The ground / power rewiring pads (150PG) may be connected to ground / power under-bump patterns (170PG) through the ground / power conductive patterns (130PG). Each of the signal rewiring pads (150S) may be placed on a corresponding third signal conductive pattern (133S). The signal redistribution pads (150S) can be electrically connected to the signal under-bump patterns (170S) through the signal conduction patterns (130S). The signal redistribution pads (150S) can be insulated from the ground / power redistribution pads (150PG). Since the conduction patterns (130PG, 130S) are provided, at least one of the redistribution pads (150PG, 150S) may not be vertically aligned with the under-bump pattern (170PG, 170S) electrically connected thereto. Accordingly, the arrangement of the under-bump patterns (170PG, 170S) or the redistribution pads (150PG, 150S) can be designed more freely.

[0035] The rewiring pads (150PG, 150S) may comprise a metal such as copper. Although not illustrated, each of the rewiring pads (150PG, 150S) may further comprise a protective pad. The protective pads are provided on the upper surfaces of the rewiring pads (150PG, 150S) and may comprise nickel, gold, and / or an alloy thereof.

[0036] Upper seed pads (655) may be provided on the lower surfaces of the redistribution pads (150PG, 150S), respectively. Each upper seed pad (655) may be interposed between the signal redistribution pad (150S) corresponding to the third signal conduction pattern (133S) or between the ground / power redistribution pad (150PG) corresponding to the third ground / power conduction pattern (133PG). The upper seed pads (655) may extend between the uppermost first insulating layer (101) and the redistribution pads (150PG, 150S). The upper seed pads (655) may comprise a material different from that of the first redistribution pads (150PG, 150S). The upper seed pads (655) may comprise, for example, a conductive seed material.

[0037] According to the embodiments, as shown in FIG. 1d, the under-bump patterns (170PG, 170S) may have relatively thick thicknesses (T1). For example, the thicknesses (T1) of the under-bump patterns (170PG, 170S) may be greater than the thickness (T2) of the wiring portion of each ground / power conduction pattern (130PG) and the thickness (T3) of the wiring portion of each signal conduction pattern (130S). Accordingly, the first redistribution board (100) may exhibit improved reliability. If the thicknesses (T1) of the under-bump patterns (170PG, 170S) are less than 5 μm, the reliability of the semiconductor package (10) may be reduced. If the thicknesses (T1) of the under-bump patterns (170PG, 170S) are greater than 20 μm, it may be difficult to miniaturize the semiconductor package (10). The thicknesses (T1) of the under-bump patterns (170PG, 170S) according to the embodiments may be approximately 5 μm to 20 μm. The semiconductor package (10) may exhibit improved reliability and be miniaturized.

[0038] If the upper surface of each of the under-bump patterns (170PG, 170S) has the same width as the lower surface, the upper surfaces of the first insulating layers (101) may have undulations due to the thicknesses (T1) of the under-bump patterns (170PG, 170S). In this case, due to the undulation of the upper surfaces of the first insulating layers (101), electrical connection failures may occur between the stacked first to third signal conduction patterns (131S, 132S, 133S) or between the first to third ground / power conduction patterns (131PG, 132PG, 133PG). According to the embodiments, the upper surface of each of the under-bump patterns (170PG, 170S) may have a greater width than the lower surface. Accordingly, the occurrence of undulations in the upper surfaces of the second insulating layers (601) may be reduced or prevented. Accordingly, electrical connections between the stacked first to third signal conduction patterns (131S, 132S, 133S) and between the stacked first to third ground / power conduction patterns (131PG, 132PG, 133PG) may be good.

[0039] A semiconductor chip (200) may be mounted on the upper surface of the first redistribution board (100). The semiconductor chip (200) may be placed on the center area of ​​the first redistribution board (100) in a planar view. The semiconductor chip (200) may be any one of a logic chip, a buffer chip, and a memory chip. The logic chip may include an ASIC chip or an application processor (AP) chip. The ASIC chip may include an application specific integrated circuit (ASIC). As another example, the semiconductor chip (200) may include a Central Processing Unit (CPU) or a Graphic Processing Unit (GPU).

[0040] The semiconductor chip (200) may include chip pads (230) and integrated circuits (not shown). The integrated circuits may be provided within the semiconductor chip (200). The chip pads (230) may be provided on the lower surface of the semiconductor chip (200) to be connected to the integrated circuits. Being electrically connected to the semiconductor chip (200) may mean being electrically connected to the integrated circuits through the chip pads (230) of the semiconductor chip (200).

[0041] Bumps (250) may be interposed between the first redistribution board (100) and the semiconductor chip (200). For example, the bumps (250) may be connected to the redistribution pads (150PG, 150S) and the chip pads (230). Accordingly, the semiconductor chip (200) may be connected to the first redistribution board (100) through the bumps (250). Among the chip pads (230), the ground chip pads may be connected to at least one of the first to third ground / power conduction patterns (131PG, 132PG, 133PG) through the bumps (250). Among the chip pads (230), the signal chip pads may be connected to at least one of the first to third signal conduction patterns (131PG, 132PG, 133PG) through the bumps (250). The bumps (250) may include solder materials. The bumps (250) may further include pillar patterns, and the pillar patterns may include a metal such as copper. In this case, the pillar patterns may come into contact with the chip pads (230).

[0042] Conductive structures (300) may be disposed on the upper surface of the first redistribution substrate (100). Conductive structures (300) may be disposed on the edge region of the first redistribution substrate (100) in a planar view. The edge region of the first redistribution substrate (100) may be provided between the center region and the sides of the first redistribution substrate (100) in a planar view. The edge region of the first redistribution substrate (100) may surround the center region in a planar view. The conductive structures (300) may be spaced apart laterally from the semiconductor chip (200). The conductive structures (300) may be spaced apart laterally from each other. The width of the conductive structures (300) may be smaller than the width of the upper surface of the redistribution pads (150PG, 150S).

[0043] The conductive structures (300) may include ground / power structures (300PG) and signal structures (300S). The ground / power structures (300PG) may be placed on ground / power rewiring pads (150PG). The ground / power structures (300PG) may be electrically connected to ground / power underbump patterns (170PG) through ground / power conductive patterns (130PG). In this specification, electrical connection may include a direct connection or an indirect connection through other components. The signal structures (300S) may be placed on signal rewiring pads (150S). The signal structures (300S) may be electrically connected to signal underbump patterns (170S) or a semiconductor chip (200) through signal conductive patterns (130S). The width of the signal structures (300S) may be the same as or different from the width of the ground / power structures (300PG). The number of signal structures (300S) may be fewer than the number of ground / power structures (300PG). Alternatively, the number of signal structures (300S) may be the same as or greater than the number of ground / power structures (300PG).

[0044] The conductive structures (300) can function as electrical paths between the first redistribution board (100) and the second redistribution board (600). For example, the ground / power structures (300PG) can transmit ground voltage or power voltage. The signal structures (300S) can transmit data signals from an external device or semiconductor chip (200).

[0045] The grounding / power structures (300PG) may include a first grounding / power structure (310) and a second grounding / power structure (320). The first grounding / power structure (310) and the second grounding / power structure (320) may each be a first conductive structure and a second conductive structure. The grounding / power structures (300PG) may further include a fourth grounding / power structure (340) and a fifth grounding / power structure (350). The fourth grounding / power structure (340) and the fifth grounding / power structure (350) may each be a fourth conductive structure and a fifth conductive structure. The fourth grounding / power structure (340) and the fifth grounding / power structure (350) will be described later.

[0046] Signal structures (300S) may include a third conductive structure (330). The third conductive structure (330) may be a channel for rapidly transmitting data signals. When other signal structures (300S) are placed adjacent to the third conductive structure (330), coupling noise may occur between the other signal structures (300S) and the third conductive structure (330). According to embodiments, the third conductive structure (330) may be placed between the first ground / power structure (310) and the second ground / power structure (320) in a first direction (D1). In this case, the third conductive structure (330) may be adjacent to the first ground / power structure (310) and the second ground / power structure (320). For example, none of the conductive structures (300) may be provided in the first region between the third conductive structure (330) and the first ground / power structure (310) and in the second region between the third conductive structure (330) and the second ground / power structure (320). The ground / power structures (300PG) can shield electrical interference between conductive components. Since the third conductive structure (330) is placed between the first and second ground / power structures (310, 320), coupling noise of the third conductive structure (330) can be prevented. Accordingly, the reliability and electrical characteristics of the semiconductor package (10) can be improved.

[0047] As shown in FIG. 1a, the third conductive structure (330) in the second direction (D2) can be placed between the ground / power structures (300PG). Accordingly, the reliability and electrical characteristics of the semiconductor package (10) can be further improved. The planar arrangement of the signal structures (300S) and the ground / power structures (300PG) is not limited to what is shown and can be varied in many ways.

[0048] As shown in FIG. 1d, a molding film (400) may be placed on a first redistribution substrate (100) to cover a semiconductor chip (200). The molding film (400) may cover the top first insulating layer (101). The molding film (400) may cover the sidewalls of the conductive structures (300). The upper surface of the molding film (400) may be provided at substantially the same level as the upper surfaces of the conductive structures (300). The molding film (400) may extend further into the gap between the semiconductor chip (200) and the first redistribution substrate (100) to seal the bumps (250). The molding film (400) may comprise an insulating polymer, for example, an epoxy-based molding compound. Unlike what is illustrated, the molding film (400) does not extend over the lower surface of the semiconductor chip (200), and an underfill film (not illustrated) may be further provided in the gap region between the redistribution substrate and the semiconductor chip (200). The underfill film may include, for example, an insulating polymer such as an epoxy polymer.

[0049] A second redistribution substrate (600) may be disposed on a molding film (400) and conductive structures (300) and electrically connected to the conductive structures (300). For example, the second redistribution substrate (600) may be disposed on a semiconductor chip (200) and spaced apart from the upper surface of the semiconductor chip (200). The molding film (400) may extend between the upper surface of the semiconductor chip (200) and the second redistribution substrate (600).

[0050] The second redistribution substrate (600) may include a second insulating layer (601), redistribution patterns, second seed patterns (615), third seed patterns (625), upper seed pads (655), and bonding pads (650PG, 650S). The second insulating layer (601) may include a plurality of second insulating layers (601). The plurality of second insulating layers (601) may be laminated on a molding film (400). The second insulating layers (601) may include a photosensitive insulating material or an insulating polymer. For example, the second insulating layers (601) may include the same material. The interface between adjacent second insulating layers (601) may not be distinguishable, but is not limited thereto. The number of second insulating layers (601) may vary.

[0051] The rewiring patterns may include lower rewiring patterns (610PG, 610S) and upper rewiring patterns (620PG, 620S). The lower rewiring patterns (610PG, 610S) may include lower ground / power rewiring patterns (610PG) and lower signal rewiring patterns (610S). The lower rewiring patterns (610PG, 610S) may be spaced apart from each other and may be electrically isolated. Each of the lower rewiring patterns (610PG, 610S) may include a first via portion and a first wiring portion. Each of the lower rewiring patterns (610PG, 610S) may have its first via portion provided within the lowest second insulating layer (601) and on the upper surface of the corresponding conductive structure (300). The width of the first via portion of each of the lower redistribution patterns (610PG, 610S) may be smaller than the width of the corresponding conductive structure (300). The first wiring portion may be provided on the first via portion and connected to the first pattern portion without a boundary surface. The width of the first wiring portion of each of the lower redistribution patterns (610PG, 610S) may be larger than the width of the upper surface of the first via portion. The first wiring portion may extend onto the upper surface of the corresponding second insulating layer (601). At least one of the lower ground / power redistribution patterns (610PG) includes a plurality of first via portions, and the first wiring portion may be connected to the plurality of first via portions. The lower redistribution patterns (610PG, 610S) may include a metal such as copper.

[0052] The lower ground / power redistribution patterns (610PG) are placed on the ground / power structures (300PG) and may be electrically connected to the ground / power structures (300PG). The lower ground / power redistribution patterns (610PG) may include a first ground / power redistribution pattern (611) and a second ground / power redistribution pattern (612). The first ground / power redistribution pattern (611) may be electrically connected to the first ground / power structure (310). The second ground / power redistribution pattern (612) may be electrically connected to the second ground / power structure (320). The second ground / power redistribution pattern (612) may be spaced apart from the first ground / power redistribution pattern (611) and may be electrically separated, but is not restricted therefrom.

[0053] Lower signal redistribution patterns (610S) are placed on signal structures (300S) and can be electrically connected to the signal structures (300S). For example, the lower signal redistribution patterns (610S) can correspond one-to-one with the signal structures (300S). That is, each of the lower signal redistribution patterns (610S) can be electrically connected to a corresponding singular signal structure (300S) as shown in FIG. 1c and FIG. 1d. The lower signal redistribution patterns (610S) may include a third redistribution pattern (613). The third redistribution pattern (613) can be electrically connected to a third conductive structure (330). The third redistribution pattern (613) may not be electrically connected to other conductive structures (300) other than the third conductive structure (330). Below, the lower ground / power redistribution patterns (610PG) and lower signal redistribution patterns (610S) will be described in more detail.

[0054] As shown in FIG. 1c, the upper surface of each of the lower ground / power redistribution patterns (610PG) may have a larger planar area than the upper surface of each of the lower signal redistribution patterns (610S). For example, the planar area of ​​the upper surface of the first ground / power redistribution pattern (611) may be larger than the planar area of ​​the upper surface of the third redistribution pattern (613). The area of ​​the upper surface of the second ground / power redistribution pattern (612) may be larger than the area of ​​the upper surface of the third redistribution pattern (613).

[0055] If any one of the lower ground / power redistribution patterns (610PG) has a relatively large planar area, said lower ground / power redistribution pattern (610PG) may have a second hole (619). The second hole (619) may penetrate the upper and lower surfaces of the lower ground / power redistribution pattern (610PG). For example, the planar area of ​​the first ground / power redistribution pattern (611) may be relatively large. The first ground / power redistribution pattern (611) may have a second hole (619). Since the second holes (619) are provided, the lower ground / power redistribution patterns (610PG) may not be concentrated in a specific area from a planar perspective. Accordingly, the reliability of the second redistribution board (600) may be improved. The second hole (619) may not be provided within the second ground / power redistribution pattern (612). Alternatively, a second hole (619) may be further provided within the second ground / power redistribution pattern (612). Whether the second holes (619) are formed and the number of second holes (619) may be determined by the planar area of ​​the lower ground / power redistribution patterns (610PG). The second insulating layers (601) adjacent to the lower ground / power redistribution patterns (610PG) may come into direct contact with each other through the second hole (619). The lower signal redistribution patterns (610S) may not have a hole penetrating their interior.

[0056] As shown in FIGS. 1c, 1d, and 1e, at least one of the lower ground / power redistribution patterns (610PG) may overlap with a plurality of ground / power structures (300PG) in a planar view. Any one of the lower ground / power redistribution patterns (610PG) may be electrically connected to the plurality of ground / power structures (300PG). For example, a first ground / power redistribution pattern (611) may be provided on a fourth ground / power structure (340) and electrically connected to the fourth ground / power structure (340). The fourth ground / power structure (340) may be electrically connected to the first ground / power structure (310) through the first ground / power redistribution pattern (611). That is, the first ground / power structure (310) and the fourth ground / power structure (340) can be merged by the first ground / power redistribution pattern (611). The same voltage can be applied to the first ground / power structure (310) and the fourth ground / power structure (340).

[0057] As shown in FIGS. 1c and 1e, a second ground / power redistribution pattern (612) may be further provided on a fifth ground / power structure (350) and may be electrically connected to the fifth ground / power structure (350). The fifth ground / power structure (350) may be electrically connected to the second ground / power structure (320) through the second ground / power redistribution pattern (612). The second ground / power structure (320) and the fifth ground / power structure (350) may be merged by the second ground / power redistribution pattern (612). The same voltage may be applied to the second ground / power structure (320) and the fifth ground / power structure (350). The number of ground / power structures (300PG) connected to the first ground / power redistribution pattern (611) and the number of ground / power structures (300PG) connected to the second ground / power redistribution pattern (612) can be varied.

[0058] Second seed patterns (615) may be disposed on the lower surfaces of the lower ground / power redistribution patterns (610PG) and the lower surfaces of the lower signal redistribution patterns (610S), respectively. For example, the second seed patterns (615) may be in direct contact with the upper surfaces of the conductive structures (300). The second seed patterns (615) may extend between the lower redistribution patterns (610PG, 610S) and the lowest second insulating layer (601). The second seed patterns (615) may include a conductive seed material. The second seed patterns (615) may function as barrier layers.

[0059] The upper rewiring patterns (620PG, 620S) may include upper ground / power rewiring patterns (620PG) and upper signal rewiring patterns (620S). Each of the upper rewiring patterns (620PG, 620S) may include a second via portion and a second wiring portion. Each of the upper rewiring patterns (620PG, 620S) may have a second via portion provided within a corresponding second insulating layer (601). The second wiring portion may be connected to the second wiring portion without a boundary surface on the second via portion. The width of the second wiring portion may be greater than the width of the upper surface of the second via portion. The second wiring portion may extend onto the upper surface of the corresponding second insulating layer (601). The upper rewiring patterns (620PG, 620S) may include a metal such as copper.

[0060] The upper signal redistribution patterns (620S) are placed on the lower signal redistribution patterns (610S) and can be electrically connected to the lower signal redistribution patterns (610S). The upper signal redistribution patterns (620S) can be connected one-to-one with the signal structures (300S) through the lower redistribution patterns (610PG, 610S).

[0061] Upper ground / power redistribution patterns (620PG) are positioned on lower signal redistribution patterns (610S) and may be electrically connected to the lower signal redistribution patterns (610S). At least one of the upper ground / power redistribution patterns (620PG) may be electrically connected to a plurality of ground / power structures (300PG). The upper ground / power redistribution patterns (620PG) may be positioned adjacent to the upper signal redistribution patterns (620S) and may be electrically insulated. The upper surface of each upper ground / power redistribution pattern (620PG) may have a larger area than the upper surface of each upper signal redistribution pattern (620S). In this case, at least one of the upper ground / power redistribution patterns (620PG) may have additional holes (not shown). The holes may be similar to those described in the example of the second holes (619) of FIG. 1c. However, the present invention is not limited thereto.

[0062] Unlike what is illustrated, the first ground / power structure (310) and the fourth ground / power structure (340) may be merged through either of the upper ground / power redistribution patterns (620PG). As another example, the second ground / power structure (320) and the fifth ground / power structure (350) may be merged through the other of the upper ground / power redistribution patterns (620PG).

[0063] Being electrically connected to the second redistribution board (600) may include being electrically connected to at least one of the lower ground / power redistribution patterns (610PG), lower signal redistribution patterns (610S), upper ground / power redistribution patterns (620PG), and upper signal redistribution patterns (620S).

[0064] Third seed patterns (625) may be placed on the lower surfaces of the upper ground / power redistribution patterns (620PG) and the lower surfaces of the upper signal redistribution patterns (620S). For example, the third seed patterns (625) may be interposed between the lower redistribution patterns (610PG, 610S) and the upper redistribution patterns (620PG, 620S). For example, the second seed patterns (615) may include a conductive seed material. The second seed patterns (615) may function as barrier layers.

[0065] Bonding pads (650PG, 650S) may include ground / power bonding pads (650PG) and signal bonding pads (650S). Ground / power bonding pads (650PG) are provided on upper ground / power redistribution patterns (620PG) and can be connected to upper ground / power redistribution patterns (620PG). Signal bonding pads (650S) can be connected to upper signal redistribution patterns (620S) on upper signal redistribution patterns (620S). Bonding pads (650PG, 650S) may be arranged side by side with each other.

[0066] The lower portion of each of the bonding pads (650PG, 650S) may be provided within the uppermost second insulating layer (601). The upper portion of each of the bonding pads (650PG, 650S) may extend further over the upper surface of the uppermost second insulating layer (601). The upper portion of each of the bonding pads (650PG, 650S) may have a greater width than the lower portion. The bonding pads (650PG, 650S) may comprise a metal, for example, copper. Since upper redistribution patterns (620PG, 620S) and lower redistribution patterns (610PG, 610S) are provided, at least one bonding pad (650PG, 650S) may not be vertically aligned with the conductive structure (300) electrically connected thereto. Accordingly, the arrangement of the bonding pads (650PG, 650S) can be designed more freely.

[0067] Upper seed pads (655) may be provided on the lower surfaces of the bonding pads (650PG, 650S), respectively. Upper seed pads (655) may be interposed between the upper rewiring patterns (620PG, 620S) and the bonding pads (650PG, 650S). The upper seed pads (655) may include a conductive seed material.

[0069] FIG. 2 is a drawing for explaining the planar arrangement of conductive structures according to embodiments. Hereinafter, content that overlaps with what has been previously described is omitted.

[0070] Referring to FIG. 2, the conductive structures (300) may include ground / power structures (300PG) and signal structures (300S). The ground / power structures (300PG) and signal structures (300S) may be arranged alternately in a planar view. For example, the ground / power structures (300PG) and signal structures (300S) may be arranged alternately with each other in a first direction (D1). The ground / power structures (300PG) and signal structures (300S) may be arranged alternately with each other in a second direction (D2). Among the signal structures (300S), the third conductive structure (330) may be arranged between the first ground / power structure (310) and the second ground / power structure (320). The arrangement of the challenge structures (300) can be varied.

[0072] FIG. 3a is a drawing for explaining a semiconductor package according to embodiments and corresponds to a cross-section cut along line AB of FIG. 1a. FIG. 3b is a drawing for explaining a semiconductor package according to embodiments and corresponds to a cross-section cut along line CD of FIG. 1a. Hereinafter, content that overlaps with what has been previously described is omitted.

[0073] Referring to FIGS. 1a, 3a, and 3b, the semiconductor package (10A) may include a first redistribution substrate (100), solder balls (500), a semiconductor chip (200), conductive structures (300), a molding film (400), and a second redistribution substrate (600). The conductive structures (300), signal under-bump patterns (170S), and ground / power under-bump patterns (170PG) may be substantially the same as those previously described in the examples of FIGS. 1a through 1f. For example, the widths of the ground / power under-bump patterns (170PG) may be greater than the widths of the signal under-bump patterns (170S), and the lengths of the ground / power under-bump patterns (170PG) may each be greater than the lengths of the signal under-bump patterns (170S). The planar areas of the ground / power under-bump patterns (170PG) may each be larger than the planar areas of the signal under-bump patterns (170S). The conductive structures (300) may include ground / power structures (300PG) and signal structures (300S). However, the ground / power structures (300PG) may not be merged by the lower ground / power rewiring patterns (610PG).

[0074] At least two of the ground / power structures (300PG) may be merged by the ground / power conduction patterns (130PG) of the first redistribution board (100). For example, the ground / power conduction patterns (130PG) may include a first ground / power shared pattern (1301PG) and a second ground / power shared pattern (1302PG). The first ground / power shared pattern (1301PG) and the second ground / power shared pattern (1302PG) may be referred to as the first shared conduction pattern and the second shared conduction pattern, respectively. The first ground / power shared pattern (1301PG) may have a relatively large planar area. The first ground / power shared pattern (1301PG) may be any one of a plurality of second ground / power conduction patterns (132PG). The first ground / power structure (310) can be electrically connected to the first ground / power sharing pattern (1301PG) through the corresponding third ground / power conduction pattern (133PG). The fourth ground / power structure (340) can be electrically connected to the first ground / power sharing pattern (1301PG) through the corresponding third ground / power conduction pattern (133PG). Accordingly, the first ground / power structure (310) and the fourth ground / power structure (340) can be electrically connected to each other through the first ground / power sharing pattern (1301PG). The same voltage can be applied to the first ground / power structure (310) and the fourth ground / power structure (340) through the first under-bump patterns (171). Since a first ground / power sharing pattern (1301PG) is provided, the design of the electrical path between the first under-bump patterns (171) and the first and fourth ground / power structures (310, 340) can be simplified. That is, the design of the ground / power conduction patterns (130PG) can be simplified.

[0075] The second ground / power sharing pattern (1302PG) can be electrically connected to the second under-bump pattern (172). The second ground / power sharing pattern (1302PG) may be another of the second ground / power conduction patterns (132PG). The second ground / power sharing pattern (1302PG) may have a relatively large planar area. As shown in FIG. 3b, the second ground / power sharing pattern (1302PG) can be electrically connected to the second ground / power structure (320) and the fifth ground / power structure (350) through the third ground / power conduction patterns (133PG) and ground / power rewiring pads (150PG). Accordingly, the second ground / power structure (320) and the fifth ground / power structure (350) can be electrically connected to each other through the second ground / power sharing pattern (1302PG). The same voltage can be applied to the second ground / power structure (320) and the fifth ground / power structure (350). Since the second ground / power sharing pattern (1302PG) is provided, the design of the ground / power conduction patterns (130PG) can be simplified.

[0076] Unlike what is described, the first ground / power sharing pattern (1301PG) may be any one of the first ground / power conduction patterns (131PG) or any one of the third ground / power conduction patterns (133PG).

[0077] As another example, the second ground / power sharing pattern (1302PG) may be any one of the first ground / power conduction patterns (131PG) or any one of the third ground / power conduction patterns (133PG).

[0078] Although not illustrated, at least one of the first ground / power sharing pattern (1301PG) and the second ground / power sharing pattern (1302PG) may further have a hole penetrating the interior. The hole may be similar to the first holes (179) of the under-bump patterns (170PG, 170S) of FIG. 1B.

[0080] FIG. 4a is a drawing for explaining a semiconductor package according to embodiments and corresponds to a cross-section cut along line AB of FIG. 1a. FIG. 4b is a drawing for explaining a semiconductor package according to embodiments and corresponds to a cross-section cut along line CD of FIG. 1a.

[0081] Referring to FIGS. 1a, FIGS. 4a, and FIGS. 4b, the semiconductor package (10B) may include a first redistribution substrate (100), solder balls (500), a semiconductor chip (200), conductive structures (300), a molding film (400), and a second redistribution substrate (600). The semiconductor chip (200), conductive structures (300), molding film (400), and the second redistribution substrate (600) may be substantially the same as those previously described in the examples of FIGS. 1a through 1f. However, the semiconductor package (10B) may not include the bumps (250) described in FIG. 1d.

[0082] The first rewiring board (100) may include under-bump patterns (170PG, 170S), under-bump seed patterns (175), first insulating layers (101), ground / power conduction patterns (130PG), signal conduction patterns (130S), and first seed patterns (135). The first rewiring board (100) may not include the rewiring pads (150PG, 150S) and seed pads (155) of FIG. 1d.

[0083] The first rewiring substrate (100) can be in direct contact with the semiconductor chip (200) and the molding film (400). For example, the top first insulating layer (101) can be in direct physical contact with the bottom surface of the semiconductor chip (200) and the bottom surface of the molding film (400). The first seed patterns (135) within the top first insulating layer (101) can be directly connected to the chip pads (230) and the conductive structures (300). The first seed patterns (135) can be provided on the top surfaces of the ground / power conductive patterns (130PG) and the top surfaces of the signal conductive pads. The wiring portion of each of the ground / power conductive patterns (130PG) and the signal conductive patterns (130S) can be provided on the bottom surface of the via portion.

[0084] The lower portion of each signal under-bump pattern (170S) may have a wider width than the upper portion. Signal solder balls (500S) may be placed on the lower portions of each signal under-bump pattern (170S). The lower portion of each ground / power under-bump pattern (170PG) may have a wider width than the upper portion. Ground / power solder balls (500PG) may be placed on the lower portions of each ground / power under-bump pattern (170PG). The width of the lower portions of the ground / power under-bump patterns (170PG) may be greater than the width of the lower portions of the signal under-bump patterns (170S). For example, the width of the lower portion of each of the first and second under-bump patterns (171, 172) may be greater than the width of the lower portion of the third under-bump pattern (173). Although not illustrated, the length of the bottom surface of each ground / power under-bump pattern (170PG) may be greater than the length of the bottom surface of the signal under-bump pattern (170S). The area of ​​the bottom surface of each ground / power under-bump pattern (170PG) may be greater than the area of ​​the bottom surface of the signal under-bump pattern (170S).

[0085] The first ground / power redistribution pattern (611) can be electrically connected to the first ground / power structure (310) and the fourth ground / power structure (340). As shown in FIG. 3b, the second ground / power redistribution pattern (612) can be electrically connected to the second ground / power structure (320) and the fifth ground / power structure (350).

[0086] Alternatively, the first ground / power structure (310) and the fourth ground / power structure (340) may be electrically connected to any one of the ground / power conduction patterns (130PG) of the first redistribution board (100), as described in the example of FIG. 3a. Any one of the ground / power conduction patterns (130PG) may be the first ground / power sharing pattern (1301PG) of FIG. 3a. The second ground / power structure (320) and the fifth ground / power structure (350) may be electrically connected to another of the ground / power conduction patterns (130PG). Any other of the ground / power conduction patterns (130PG) may be the second ground / power sharing pattern (1302PG) described in FIG. 3a and FIG. 3b.

[0087] The semiconductor package (10B) can be manufactured by a chip-first process, but is not limited thereto.

[0089] FIG. 5a is a drawing for explaining a semiconductor package according to embodiments and corresponds to a cross-section cut along line AB of FIG. 1a. FIG. 5b is a drawing for explaining a semiconductor package according to embodiments and corresponds to a cross-section cut along line CD of FIG. 1a.

[0090] Referring to FIGS. 5a and 5b, the semiconductor package (1) may include a lower package (10') and an upper package (20). The lower package (10') may be substantially the same as the semiconductor package (10) described in the examples of FIGS. 1a through 1f. The lower package (10') may include a first redistribution substrate (100), solder balls (500), a semiconductor chip (200), a molding film (400), conductive structures (300), and a second redistribution substrate (600). In another example, the lower package (10') may be substantially the same as the semiconductor package (10A) of FIGS. 3a and 3b or the semiconductor package (10B) of FIGS. 4a and 4b.

[0091] The upper package (20) may include an upper semiconductor chip (720), upper bumps (750), and an upper molding film (740). The upper semiconductor chip (720) may be a semiconductor chip (200) of a different type from the semiconductor chip (200). For example, the upper semiconductor chip (720) may be a memory chip, and the semiconductor chip (200) may be a logic chip. The upper semiconductor chip (720) may be mounted on the upper surface of the second rewiring board (600). For example, the upper bumps (750) may be provided between the second rewiring board (600) and the upper semiconductor chip (720). The upper bumps (750) may be connected to the bonding pads (650PG, 650S) and the upper chip pads (730) of the upper semiconductor chip (720), respectively. The upper bumps (750) may include a solder material. Although not illustrated, the upper bumps (750) may further include pillar patterns. The upper semiconductor chip (720) may be connected to the semiconductor chip (200) or solder balls (500) through the second redistribution substrate (600) and the conductive structures (300).

[0092] The upper molding film (740) is provided on the second redistribution substrate (600) and can cover the upper semiconductor chip (720). The upper molding film (740) can be placed directly on the second redistribution substrate (600). The upper molding film (740) may not cover the upper surface of the upper semiconductor chip (720). The upper molding film (740) may include an insulating polymer such as an epoxy-based molding compound.

[0093] The upper package (20) may further include a heat dissipation structure (790). The heat dissipation structure (790) may be disposed on the upper surface of the upper semiconductor chip (720) and on the upper surface of the upper molding film (740). The heat dissipation structure (790) may further extend along the side of the upper molding film (740). The heat dissipation structure (790) may include a heat sink, a heat slug, or a thermal interface material (TIM) layer. The heat dissipation structure (790) may include, for example, a metal.

[0094] Unlike what is described, the upper package (20) does not include a heat dissipation structure (790), and the upper molding film (740) can cover the upper surface of the upper semiconductor chip (720).

[0096] FIG. 6a is a drawing for explaining a semiconductor package according to embodiments and corresponds to a cross-section cut along line AB of FIG. 1a. FIG. 6b is a drawing for explaining a semiconductor package () according to embodiments and corresponds to a cross-section cut along line CD of FIG. 1a.

[0097] Referring to FIGS. 6a and 6b, the semiconductor package (1A) may include a lower package (10'), an upper package (20A), and connecting bumps (675). The lower package (10') may be substantially the same as the semiconductor package (10) described in the examples of FIGS. 1a through 1f. In another example, the lower package (10') may be substantially the same as the semiconductor package (10A) of FIGS. 3a and 3b or the semiconductor package (10B) of FIGS. 4a and 4b.

[0098] The upper package (20A) may include an upper substrate (710), an upper semiconductor chip (720), upper bumps (750'), and an upper molding film (740). The upper substrate (710) is placed on the upper surface of the second redistribution board (600) and may be spaced apart from the upper surface of the second redistribution board (600). The upper substrate (710) may be a printed circuit board or a redistribution layer. The upper bumps (750') are interposed between the upper substrate (710) and the upper semiconductor chip (720) and may be connected to the upper substrate (710) and the upper chip pads (730). Being connected to the upper substrate (710) may mean being electrically connected to the metal wiring within the upper substrate (710). An upper molding film (740) may be provided on the upper substrate (710) to cover the upper semiconductor chip (720).

[0099] Connecting bumps (675) may be interposed between the lower package (10') and the upper package (20A). For example, connecting bumps (675) may be interposed between the second rewiring board (600) and the upper board (710) to be electrically connected to the bonding pads (650PG, 650S) and the upper board (710). Connecting bumps (675) may include solder material. Connecting bumps (675) may further include metal pillar patterns, but are not limited thereto.

[0100] The upper package (20A) may further include a heat dissipation structure (790).

[0102] FIG. 7a is a plan view of a semiconductor package according to embodiments. FIG. 7b is a cross-section cut along the line A'-B' of FIG. 7a. FIG. 7c is a cross-section cut along the line C'-D' of FIG. 7a.

[0103] Referring to FIGS. 7a, 7b, and 7c, a semiconductor package (1B) may include a lower package (11) and an upper package (21B). The lower package (11) may include a first redistribution substrate (100), solder balls (500), a semiconductor chip (200), conductive structures (300), a molding film (400), and a second redistribution substrate (600). The upper package (21B) may include an upper semiconductor chip (720), upper bumps (750), and an upper molding film (740). The upper package (21B) may further include a heat dissipation structure (790).

[0104] The first redistribution board (100) may have a first region (R1) and a second region (R2) in a planar view. The first region (R1) of the first redistribution board (100) may be adjacent to a first side of the first redistribution board (100). The second region (R2) of the first redistribution board (100) may be adjacent to a second side of the first redistribution board (100). For example, the second region (R2) of the first redistribution board (100) may be provided between the first region (R1) and the second side. The second side of the first redistribution board (100) may be opposite to the first side.

[0105] A semiconductor chip (200) may be disposed on the upper surface of a first region (R1) of a first redistribution substrate (100). Conductive structures (300) may be disposed on the upper surface of a second region (R2) of the first redistribution substrate (100).

[0106] The upper semiconductor chip (720) is placed on the second redistribution substrate (600) and may overlap with the first region (R1) and the second region (R2) of the first redistribution substrate (100) in a planar view. At least a portion of the upper semiconductor chip (720) may overlap vertically with the conductive structures (300). The upper chip pads (730) may overlap vertically with the second region (R2) of the first redistribution substrate (100). Accordingly, the length of the electrical path between the upper semiconductor chip (720) and the conductive structures (300) may be further reduced. The semiconductor package (1B) may exhibit improved electrical characteristics.

[0108] FIG. 8a is a top view of a semiconductor package according to embodiments. FIG. 8b is a cross-section cut along the line A''-B'' of FIG. 8a. FIG. 8c is a cross-section cut along the line C''-D'' of FIG. 8a.

[0109] Referring to FIGS. 8A, 8B, and 8C, a semiconductor package (1C) may include a lower package (12) and an upper package (21C). The lower package (12) may include a first rewiring substrate (100), solder balls (11), a first semiconductor chip (201), a second semiconductor chip (202), conductive structures (300), a molding film (400), and a second rewiring substrate (600). Each of the first semiconductor chip (201) and the second semiconductor chip (202) may be the same or similar to the semiconductor chip (200) described in FIG. 1D. The second semiconductor chip (202) may be spaced apart from the first semiconductor chip (201). The second semiconductor chip (202) may be a chip of the same type or different type from the first semiconductor chip (201). First bumps (251) are provided between the first rewiring substrate (100) and the first semiconductor chip (201) so as to be connected to the rewiring pads (150PG, 150S) and the chip pads (230) of the first semiconductor chip (201). Second bumps (252) are provided between the first rewiring substrate (100) and the second semiconductor chip (202) so as to be connected to the rewiring pads (150PG, 150S) and the chip pads (230) of the second semiconductor chip (202). The first bumps (251) and the second bumps (252) may be the same or similar as the bumps (250) described in FIG. 1d.

[0110] The conductive structures (300) may be spaced apart from the first semiconductor chip (201) and the second semiconductor chip (202) and arranged to surround the first semiconductor chip (201) and the second semiconductor chip (202) in a planar view. For example, the conductive structures (300) may be provided between the first semiconductor chip (201) and the second semiconductor chip (202).

[0111] The upper package (21C) may include a first upper semiconductor chip (721), a second upper semiconductor chip (722), first upper bumps (751), second upper bumps (752), and an upper molding film (740). The upper package (21C) may further include a heat dissipation structure (790).

[0112] Each of the first upper semiconductor chip (721) and the second upper semiconductor chip (722) may be identical or similar to the upper semiconductor chip (720) described in the example of FIG. 5a. For example, the first upper semiconductor chip (721) and the second upper semiconductor chip (722) may be mounted on the second rewiring substrate (600). First upper bumps (751) may be provided between the second rewiring substrate (600) and the first upper semiconductor chip (721) to be connected to bonding pads (650PG, 650S) and the first upper chip pads (731) of the first upper semiconductor chip (721). The first upper semiconductor chip (721) may be electrically connected to the first and second semiconductor chips (201, 202) and solder balls (500) through conductive structures (300). The first upper semiconductor chip (721) may be of the same or different type as the first semiconductor chip (201) and the second semiconductor chip (202).

[0113] The second upper semiconductor chip (722) may be spaced apart from the first upper semiconductor chip (721). Second upper bumps (752) are provided between the second rewiring substrate (600) and the second upper semiconductor chip (722) so as to be connected to bonding pads (650PG, 650S) and the second upper chip pads (732) of the second upper semiconductor chip (722). The first upper bumps (751) and the second upper bumps (752) may be the same or similar as the upper bumps (750) described in FIG. 5a. The second upper semiconductor chip (722) may be electrically connected to the first and second semiconductor chips (201, 202) and solder balls (500) through conductive structures (300). The second upper semiconductor chip (722) may be of the same type or different type as the first upper semiconductor chip (721).

[0115] Embodiments of the present invention may be combined with one another. For example, at least two of the semiconductor packages (10) of FIGS. 1a to 1f, the semiconductor packages (10A) of FIGS. 3a and 3b, the semiconductor packages (10B) of FIGS. 4a and 4b, the semiconductor packages (1) of FIGS. 5a and 5b, the semiconductor packages (1A) of FIGS. 6a and 6b, the semiconductor packages (1B) of FIGS. 7a and 7b, and the semiconductor packages (1C) of FIGS. 8a and 8b may be combined with one another. For example, the semiconductor packages (1B) of FIGS. 7a and 7b may include an upper package (20) as described in the example of the semiconductor packages (1A) of FIGS. 5a and 5b.

[0117] FIGS. 9a to 9l are drawings for explaining a method of manufacturing a semiconductor package according to embodiments.

[0118] Referring to FIG. 9a, a first insulating layer (101), an under-bump seed layer (175Z), a first resist pattern (981), and under-bump patterns (170PG, 170S) may be formed on a carrier substrate (910). Forming the first insulating layer (101) may include coating a photosensitive polymer. The first insulating layer (101) may be patterned so that first openings (1011Z) are formed within the first insulating layers (101). The first openings (1011Z) may expose the upper surface of the carrier substrate (910) and the inner walls of the first insulating layer (101). The first insulating layer (101) may be a first sub-insulating layer (1011).

[0119] An under-bump seed layer (175Z) is formed on a carrier substrate (910) to cover the exposed upper surface of the carrier substrate (910) and the first sub-insulating layer (1011). For example, the under-bump seed layer (175Z) can conformally cover the inner walls and the upper surface of the first sub-insulating layer (1011). The under-bump seed layer (175Z) can be formed by a deposition process.

[0120] A first resist pattern (981) is formed on the upper surface of the first insulating layer (101) to cover an under-bump seed layer (175Z). First guide openings (981Z) are formed within the first resist pattern (981) to expose the under-bump seed layer (175Z). The first guide openings (981Z) may overlap vertically with the first openings (1011Z). The widths of the first guide openings (981Z) may be greater than the widths of the corresponding first openings (1011Z).

[0121] Under bump patterns (170PG, 170S) are formed within the first openings (1011Z) and the first guide openings (981Z), respectively, to cover the under bump seed layer (175Z). The under bump patterns (170PG, 170S) can be formed by performing an electroplating process using the under bump seed layer (175Z) as an electrode. The electroplating process may be terminated before the under bump patterns (170PG, 170S) extend onto the upper surface of the first resist pattern (981). Accordingly, a separate planarization process may not be required during the formation of the under bump patterns (170PG, 170S).

[0122] The lower portions of the under-bump patterns (170PG, 170S) may be provided within the first openings (1011Z), and the upper portions of the under-bump patterns may be provided within the first guide openings (981Z). Since the widths of the first guide openings (981Z) are greater than the widths of the first openings (1011Z), the upper portions of the under-bump patterns (170PG, 170S) may have a greater width than the lower portions.

[0123] When the under-bump seed patterns (175) are formed on a single plane and have a flat top surface, it may be difficult to form the under-bump patterns (170PG, 170S) thickly. According to the embodiments, the under-bump seed layer (175Z) may be formed conformally on the bottom surface of the first openings (1011Z), the sidewalls of the first sub-insulating layer (1011), and the top surface. Since the under-bump patterns (170PG, 170S) are formed using the under-bump seed layer (175Z) as an electrode, it may be easy to form the under-bump patterns (170PG, 170S) with a relatively large thickness (T1).

[0124] The under-bump patterns (170PG, 170S) may include signal under-bump patterns (170S) and ground / power under-bump patterns (170PG). Since the under-bump patterns (170PG, 170S) are formed using the first resist pattern (981), the under-bump patterns (170PG, 170S) can be spaced apart from each other without a separate patterning process. Accordingly, the manufacturing process of the under-bump patterns (170PG, 170S) can be simplified.

[0125] Referring to FIG. 9b, the first resist pattern (981) can be removed so that the first portions of the under-bump seed layer (175Z) are exposed. The removal of the first resist pattern (981) can be carried out by a stripping process.

[0126] First portions of the exposed under-bump seed layer (175Z) may be removed by an etching process so that the first sub-insulating layer (1011) is exposed. Second portions of the under-bump seed layer (175Z) may be provided on the lower surfaces (170b) of the under-bump patterns (170PG, 170S) respectively so as not to be exposed to the etching process. Accordingly, the second portions of the under-bump seed layer (175Z) may not be removed. After the etching process, the remaining second portions of the under-bump seed layer (175Z) may form under-bump seed patterns (175). The under-bump seed patterns (175) may be spaced apart from each other and electrically separated.

[0127] Referring to FIG. 9c, a second sub-insulating layer (1012) is formed on the first sub-insulating layer (1011) and the under-bump patterns (170PG, 170S) to cover the under-bump patterns (170PG, 170S).

[0128] The second sub-insulating layer (1012) may be patterned so that second openings (1012Z) can be formed within the second sub-insulating layer (1012). The patterning of the second sub-insulating layer (1012) may be carried out by an exposure process and a development process. The second openings (1012Z) may expose the upper surfaces of the under-bump patterns (170PG, 170S), respectively.

[0129] A first seed layer (135Z), a second resist pattern (982), first ground / power conduction patterns (131PG), and first signal conduction patterns (131S) may be formed on the second sub-insulating layer (1012). First, the first seed layer (135Z) may be formed conformally on the second sub-insulating layer (1012) and within the second openings (1012Z).

[0130] A second resist pattern (982) may be formed on the first seed layer (135Z). The second resist pattern (982) may be patterned to form second guide openings (982Z). The second guide openings (982Z) may each be connected to the second openings (1012Z). The widths of the second guide openings (982Z) may be greater than the widths of the corresponding second openings (1012Z). Each of the second guide openings (982Z) may expose the first seed layer (135Z).

[0131] First ground / power conduction patterns (131PG) and first signal conduction patterns (131S) may be formed within the second openings (1012Z) to cover the first seed layer (135Z). For example, each of the first ground / power conduction patterns (131PG) and the first signal conduction patterns (131S) may fill the corresponding second opening (1012Z). Each of the first ground / power conduction patterns (131PG) and the first signal conduction patterns (131S) may be formed in the lower portions of the corresponding second guide openings (982Z) but may not extend onto the upper surface of the second resist pattern (982). The first ground / power conduction patterns (131PG) and the first signal conduction patterns (131S) may be formed by performing an electroplating process using the first seed layer (135Z) as an electrode. In the process of forming the first ground / power conduction patterns (131PG) and the first signal conduction patterns (131S), a separate flattening process may not be performed.

[0132] The first ground / power conduction patterns (131PG) and the first signal conduction patterns (131S) can be spaced apart from each other. Since the first ground / power conduction patterns (131PG) and the first signal conduction patterns (131S) are formed using the second resist pattern (982), a separate etching process for separating the first ground / power conduction patterns (131PG) and the first signal conduction patterns (131S) may not be required. Accordingly, the formation process of the first ground / power conduction patterns (131PG) and the first signal conduction patterns (131S) can be simplified.

[0133] Referring to FIGS. 9c and FIGS. 9d in turn, the second resist pattern (982) can be removed to expose the upper surfaces of the first portions of the first seed layer (135Z). Subsequently, the exposed first portions of the first seed layer (135Z) can be removed by an etching process to form the first seed pattern (135). The etching process may be a wet etching process. In the etching process, the first ground / power conduction patterns (131PG) and the first signal conduction patterns (131S) may have etch selectivity with respect to the first seed layer (135Z). The second portions of the first seed layer (135Z) may be placed on the lower surfaces of the first ground / power conduction patterns (131PG) or the first signal conduction patterns (131S) so as not to be exposed to the etching process. After the above etching process is completed, the remaining second portions of the first seed layer (135Z) can form a plurality of first seed patterns (135). The plurality of first seed patterns (135) can be separated from each other.

[0134] Referring to FIG. 9e, the process of forming the first insulating layer (101) can be repeated to form a plurality of stacked first insulating layers (101). Second ground / power conduction patterns (132PG), second signal conduction patterns (132S), third ground / power conduction patterns (133PG), third signal conduction patterns (133S), ground / power redistribution pads (150PG), and signal redistribution pads (150S) can be formed on the first ground / power conduction patterns (131PG) and the first signal conduction patterns (131S). For example, first seed patterns (135) can be formed on the lower surfaces of the second ground / power conduction patterns (132PG), second signal conduction patterns (132S), third ground / power conduction patterns (133PG), and third signal conduction patterns (133S). The formation of the second ground / power conduction patterns (132PG) and the second signal conduction patterns (132S) can be performed by the same method as described in the example of the formation of the first ground / power conduction patterns (131PG) and the first signal conduction patterns (131S) of FIG. 9c and 9d. The formation of the third ground / power conduction patterns (133PG) and the third signal conduction patterns (133S) can be performed by the same method as described in the example of the formation of the first ground / power conduction patterns (131PG) and the first signal conduction patterns (131S) of FIG. 9c and 9d, respectively. Accordingly, ground / power conduction patterns (130PG) including first to third ground / power conduction patterns (131PG, 132PG, 133PG) may be formed, and signal conduction patterns (130S) including first to third signal conduction patterns (131S, 132S, 133S) may be formed.

[0135] Third openings (1013Z) may be formed within the uppermost first insulating layer (101). Upper seed pads (655) may each be formed within the third openings (1013Z). The upper seed pads (655) may extend further over the upper surfaces of the uppermost first insulating layer (101). An electroplating process using the upper seed pads (655) as electrodes may be performed to form first redistribution pads (150PG, 150S). Accordingly, a first redistribution substrate (100) may be manufactured. The first redistribution board (100) may include first insulating layers (101), under bump patterns (170PG, 170S), first seed patterns (135), ground / power conduction patterns (130PG), signal conduction patterns (130S), upper seed pads (655), and redistribution pads (150PG, 150S).

[0136] Referring to FIG. 9f, conductive structures (300) may be formed on the redistribution pads (150PG, 150S). For example, forming the conductive structures (300) may be performed by an electroplating process. The conductive structures (300) may include ground / power structures (300PG) and signal structures (300S).

[0137] Referring to FIG. 9g, a semiconductor chip (200) may be mounted on the upper surface of a first redistribution board (100). Mounting the semiconductor chip (200) may include forming bumps (250) between the first redistribution board (100) and the semiconductor chip (200).

[0138] A molding film (400) is formed on the upper surface of the first redistribution substrate (100) to cover the semiconductor chip (200) and the conductive structures (300). The upper surface of the molding film (400) may be provided at a higher level than the upper surfaces of the conductive structures (300).

[0139] Referring to FIG. 9h, a grinding process may be performed on the molding film (400). For example, the grinding process may be carried out by a chemical mechanical polishing process. As a result of the grinding process, the upper surfaces of the conductive structures (300) may be exposed. The ground upper surface of the molding film (400) may be coplanar with the upper surfaces of the conductive structures (300).

[0140] Referring to FIG. 9i, a second insulating layer (601), second seed patterns (615), lower signal redistribution patterns (610S), and lower ground / power redistribution patterns (610PG) may be formed on the molding film (400). For example, the second insulating layer (601) may be formed directly on the upper surface of the molding film (400). Upper openings (609) may be formed within the second insulating layer (601) to expose the upper surfaces of the conductive structures (300), respectively. The second seed patterns (615) may be formed conformally within the upper openings (609) and on the upper surface of the second insulating layer (601). Lower redistribution patterns (610PG, 610S) may be formed within the upper openings (609) and on the upper surface of the second insulating layer (601) to cover the second seed patterns (615). Forming the lower redistribution patterns (610PG, 610S) may be performed by an electroplating process using the second seed patterns (615) as electrodes.

[0141] Referring to FIG. 9j, the process of forming the second insulating layer (601) may be repeated to form a plurality of stacked second insulating layers (601). Second seed patterns (615), upper redistribution patterns (620PG, 620S), upper seed pads (655), and bonding pads (650PG, 650S) may be formed on the lower ground / power redistribution patterns (610PG). Forming the upper redistribution patterns (620PG, 620S) may be performed by an electroplating process using the third seed patterns (625) as electrodes. The method of forming the upper seed pads (655) and bonding pads (650PG, 650S) may be the same or similar as described in the example of forming the seed pads (155) and redistribution pads (150PG, 150S) of FIG. 9e. Accordingly, a second redistribution substrate (600) can be manufactured. The second redistribution substrate (600) may include second insulating layers (601), second seed patterns (615), lower redistribution patterns (610PG, 610S), third seed patterns (625), upper redistribution patterns (620PG, 620S), upper seed pads (655), and bonding pads (650PG, 650S).

[0142] Referring to FIG. 9k, the carrier substrate (910) may be removed so that the lower surface of the first redistribution substrate (100) is exposed. For example, the bottom surface (101b) of the lowest first insulating layer (101) and the lower surfaces (175b') of the under bump seed patterns (175) may be exposed.

[0143] Referring to FIG. 9L, first portions of the exposed under-bump seed patterns (175) can be removed to expose the lower surfaces (170b) of the under-bump patterns (170PG, 170S). The removal of the under-bump seed patterns (175) can be performed by an etching process. The first portions of the under-bump seed patterns (175) may be portions on the lower surfaces (170b) of the under-bump patterns (170PG, 170S). In the etching process, the under-bump patterns (170PG, 170S) and the lower first insulating layer (101) may have etch selectivity with respect to the under-bump seed patterns (175).

[0144] Since the under-bump seed patterns (175) are removed, the lower surfaces (170b) of the under-bump patterns (170PG, 170S) can be placed at a higher level than the bottom surface (101b) of the lowest first insulating layer (101). The level difference between the lower surfaces (170b) of the under-bump patterns (170PG, 170S) and the bottom surface (101b) of the lowest first insulating layer (101) can be substantially the same as the first thickness (T in FIG. 1c) of each of the under-bump seed patterns (175).

[0145] After the above etching process, each of the under-bump seed patterns (175) may have an undercut. The undercut of each under-bump seed pattern (175) may be formed between the sidewall of the corresponding under-bump pattern (170PG, 170S) and the first insulating layer (101). Accordingly, as shown in FIG. 1c, the bottom surface (175b) of the under-bump seed pattern (175) may be positioned at a higher level than the bottom surface (170b) of the corresponding under-bump pattern (170PG, 170S).

[0146] As another example, by controlling the etching process conditions, the bottom surface (175b) of the under bump seed pattern (175) can be positioned at substantially the same level as the bottom surface (170b) of the under bump pattern (170PG, 170S).

[0147] Referring again to FIG. 1d, solder balls (500) are formed on the lower surfaces (170b) of the under bump patterns (170PG, 170S), respectively, so as to be connected to the under bump patterns (170PG, 170S). The manufacturing of the semiconductor package (10) can be completed by the examples described so far.

[0148] For the sake of simplicity of explanation, the manufacturing of a single semiconductor package (1) has been illustrated and described, but the method of manufacturing a semiconductor package of the present invention is not limited to manufacturing at the chip level. For example, the semiconductor package (1) may be manufactured at the chip level, panel level, or wafer level.

[0150] FIGS. 10a to 10c are drawings for explaining a method of manufacturing a semiconductor package according to embodiments. Hereinafter, content that overlaps with what has been previously described is omitted.

[0151] Referring to FIG. 10a, a first redistribution substrate (100), a semiconductor chip (200), conductive structures (300), a molding film (400), and a second redistribution substrate (600) may be formed on a carrier substrate (910). The formation of the first redistribution substrate (100), the semiconductor chip (200), the conductive structures (300), the molding film (400), and the second redistribution substrate (600) may be substantially the same as described in the examples of FIG. 9a to 9j.

[0152] Subsequently, the upper semiconductor chip (720) may be mounted on the second redistribution substrate (600). Mounting the upper semiconductor chip (720) may include forming upper bumps (750). A molding film (400) may be formed on the second redistribution substrate (600) to cover the upper semiconductor chip (720). A heat dissipation structure (790) may be further formed on the upper molding film (740).

[0153] Referring to FIG. 10b, the carrier substrate (910) can be removed so that the bottom surface (101b) of the lowest first insulating layer (101) and the bottom surfaces (175b') of the under bump seed patterns (175) can be exposed.

[0154] Referring to FIG. 10c, first portions of the exposed under-bump seed patterns (175) may be removed to expose the lower surfaces (170b) of the under-bump patterns (170PG, 170S). The removal of the under-bump seed patterns (175) may be substantially the same as described in FIG. 9l. The lower surfaces (175b) of the under-bump seed patterns (175) may be positioned at a higher level than the lower surfaces (170b) of the under-bump patterns (170PG, 170S).

[0155] Referring again to FIG. 5a, solder balls (500) can be attached to the lower surfaces (170b) of the exposed under-bump patterns (170PG, 170S). Accordingly, the manufacturing of the semiconductor package (1) can be completed.

[0156] When the semiconductor package (1) proceeds to the wafer level or panel level, a sawing process may be further performed prior to the attachment process of the solder balls (500). By the sawing process, the semiconductor package at the wafer level may be separated into semiconductor packages (1) at the chip level.

[0158] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments and may be used in various other combinations, modifications, and environments without departing from the essence of the invention.

Claims

Claim 1 A first redistribution substrate comprising a first under-bump pattern, a second under-bump pattern, and a third under-bump pattern; a semiconductor chip disposed on the first redistribution substrate; conductive structures disposed adjacent to the semiconductor chip on the first redistribution substrate, wherein the conductive structures are spaced apart from each other; and a second redistribution substrate on the semiconductor chip and the conductive structures, wherein the third under-bump pattern is insulated from the first and second under-bump patterns, and the conductive structures include: a first conductive structure connected to the first under-bump pattern; and a second conductive structure connected to the second under-bump pattern. A semiconductor package comprising a third conductive structure adjacent to the first and second conductive structures and connected to the third under-bump pattern, wherein the third conductive structure is disposed between the first conductive structure and the second conductive structure, the width of the first under-bump pattern is greater than the width of the third under-bump pattern, and the width of the second under-bump pattern is greater than the width of the third under-bump pattern, and the conductive structures further comprise a fourth conductive structure, wherein the first redistribution substrate further comprises a first shared conductive pattern, and the first shared conductive pattern is electrically connected to the first conductive structure and the fourth conductive structure. Claim 2 A semiconductor package according to claim 1, wherein the upper surface area of ​​the first under-bump pattern is larger than the upper surface area of ​​the third under-bump pattern, and the upper surface area of ​​the second under-bump pattern is larger than the upper surface area of ​​the third under-bump pattern. Claim 3 A semiconductor package according to claim 1, wherein the length of the upper surface of the first under-bump pattern and the length of the upper surface of the second under-bump pattern are greater than the length of the upper surface of the third under-bump pattern. Claim 4 In claim 1, the first under-bump pattern is a semiconductor package having a hole penetrating the interior thereof. Claim 5 A semiconductor package according to claim 1, wherein the first under-bump pattern and the second under-bump pattern are ground / power under-bump patterns, and the third under-bump pattern is a signal under-bump pattern. Claim 6 A semiconductor package according to claim 1, wherein the second redistribution substrate comprises: a first redistribution pattern electrically connected to the first conductive structure; a second redistribution pattern electrically connected to the second conductive structure; and a third redistribution pattern electrically connected to the third conductive structure, wherein the upper surface area of ​​the first redistribution pattern and the upper surface area of ​​the second redistribution pattern are larger than the upper surface area of ​​the third redistribution pattern. Claim 7 In claim 6, the conductive structures further comprise: a semiconductor package including a fifth conductive structure electrically connected to the second redistribution pattern. Claim 8 delete Claim 9 In claim 1, the conductive structures further include a fifth conductive structure, wherein the first redistribution substrate includes a second shared conductive pattern, and the second shared conductive pattern is electrically connected to the second conductive structure and the fifth conductive structure in a semiconductor package. Claim 10 In claim 1, the first rewiring substrate further comprises underbump seed patterns covering the sidewalls of the first to third underbump patterns, and the underbump seed patterns do not cover the lower surfaces of the first to third underbump patterns, forming a semiconductor package. Claim 11 A semiconductor package according to claim 1, wherein none of the conductive structures are provided in a first region between the first conductive structure and the third conductive structure and a second region between the second conductive structure and the second conductive structure. Claim 12 A first redistribution substrate; a semiconductor chip disposed on the first redistribution substrate; conductive structures disposed on the first redistribution substrate and spaced laterally from the semiconductor chip; and a second redistribution substrate on the semiconductor chip and the conductive structures, wherein the conductive structures include a first conductive structure, a second conductive structure, and a third conductive structure adjacent to each other, and the third conductive structure is disposed between the first and second conductive structures and is insulated from the first and second conductive structures, and the second redistribution substrate comprises: a first redistribution pattern electrically connected to the first conductive structure and vertically overlapping with the semiconductor chip; and a second redistribution pattern electrically connected to the second conductive structure. A semiconductor package comprising a third redistribution pattern electrically connected to the third conductive structure, wherein the upper surface area of ​​the first redistribution pattern is larger than the upper surface area of ​​the third redistribution pattern, and the upper surface area of ​​the second redistribution pattern is larger than the upper surface area of ​​the third redistribution pattern, and the first conductive structure and the second conductive structure are ground / power structures, and the third conductive structure is a signal structure. Claim 13 In claim 12, the first rewiring pattern is a semiconductor package having a hole penetrating the interior. Claim 14 A semiconductor package according to claim 12, wherein the conductive structures further comprise a fourth conductive structure and a fifth conductive structure, wherein the first redistribution pattern is electrically connected to the fourth conductive structure, the second redistribution pattern is electrically connected to the fifth conductive structure, and the third redistribution pattern is connected to the third conductive structure in a one-to-one manner. Claim 15 delete Claim 16 In claim 12, the semiconductor package further comprises an upper semiconductor chip mounted on the second rewiring substrate; and an upper molding film provided on the second rewiring substrate and covering the upper semiconductor chip, wherein the upper molding film is directly disposed on the second rewiring substrate. Claim 17 A first redistribution board comprising a first insulating layer, under-bump patterns, under-bump seed patterns, a first ground / power conductive pattern, a second ground / power conductive pattern, and a signal conductive pattern; solder balls disposed on the lower surface of the first redistribution board and connected to the under-bump patterns; a semiconductor chip disposed on the upper surface of the first redistribution board; conductive structures disposed on the upper surface of the first redistribution board and positioned adjacent to the semiconductor chip; a molding film disposed on the upper surface of the first redistribution board and covering the sidewalls of the semiconductor chip and the sidewalls of the conductive structures; and a second redistribution board disposed on the molding film and the conductive structures and electrically connected to the conductive structures, wherein the conductive structures are spaced apart from each other, and the conductive structures include: a first conductive structure connected to the first ground / power conductive pattern; a second conductive structure connected to the second ground / power conductive pattern; and a third conductive structure connected to the signal conductive pattern. A semiconductor package comprising a fourth conductive structure connected to the first ground / power conductive pattern, wherein the third conductive structure is disposed between the first and second conductive structures and is adjacent to the first and second conductive structures, and the under-bump seed patterns cover the side walls of the under-bump patterns and are spaced apart from the lower surfaces of the under-bump patterns. Claim 18 In claim 17, the under-bump patterns comprise: a first ground / power under-bump pattern electrically connected to the first ground / power conductive pattern; a second ground / power under-bump pattern electrically connected to the second ground / power conductive pattern; and a signal under-bump pattern electrically connected to the signal conductive pattern, wherein the width of the upper surface of the first ground / power under-bump pattern and the width of the upper surface of the second ground / power under-bump pattern are greater than the width of the upper surface of the signal under-bump pattern. Claim 19 In claim 17, the second redistribution substrate comprises: a first redistribution pattern electrically connected to the first conductive structure; a second redistribution pattern electrically connected to the second conductive structure; and a third redistribution pattern electrically connected to the third conductive structure, wherein the upper surface area of ​​the first redistribution pattern is larger than the upper surface area of ​​the third redistribution pattern, and the upper surface area of ​​the second redistribution pattern is larger than the upper surface area of ​​the third redistribution pattern. Claim 20 A semiconductor package according to claim 17, wherein the thicknesses of the under-bump patterns are 5 μm to 20 μm.

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