Electronic structure comprising a plurality of interconnected high-k dielectric materials and related electronic device, system and method

Abstract

The electronic structure comprises stacks of alternating dielectric materials and conductive materials within the cell region of the electronic structure. A pillar high-k dielectric material is adjacent to the stacks within the pillar region of the electronic structure. A charge blocking material, a nitride material, a tunnel dielectric material, and a channel material are adjacent to the pillar high-k dielectric material within the pillar region of the electronic structure. A cell high-k dielectric material surrounds the conductive materials within the cell region of the electronic structure. The cell high-k dielectric material is connected to a portion of the pillar high-k dielectric material. Additional electronic structures are disclosed, such as related electronic devices, systems, and methods for forming electronic devices.

Description

Technology Field

[0001] Claim of priority

[0002] This application is an entry into the national phase of international patent application PCT / US2021 / 070404, filed April 19, 2021, designating the Republic of Korea, and published in English as International Patent Publication No. WO 2021 / 222920 on November 4, 2021, which claims the benefit under Clause 8 of the Patent Cooperation Treaty with respect to U.S. patent application No. 16 / 862,150, filed April 29, 2020.

[0003] Technology field

[0004] The embodiments disclosed herein relate to electronic structures and devices and the manufacture of electronic devices. More specifically, the embodiments of the present disclosure relate to electronic structures comprising a number of adjacent high-k dielectric materials, and related electronic devices, methods, and systems comprising electronic structures. Background Technology

[0005] Designers of electronic devices (e.g., semiconductor devices, memory devices) typically want to increase the integration or density of features (e.g., components) within the device by reducing the dimensions of individual features and decreasing the separation distance between neighboring features. Electronic device designers also want to design architectures that provide performance advantages as well as simplified designs that are not only compact. Reducing the dimensions and spacing of features has increased the demands on the methods used to form electronic devices. One solution was to form three-dimensional (3D) electronic devices, such as 3D NAND devices, where memory cells are stacked vertically on a substrate. However, as memory cells are formed closer together and with smaller dimensions, wordline-to-wordline resistance (RC) (the product of resistance and capacitance) increases. Additionally, wordline-to-wordline coupling increases, and issues regarding program erasure and data retention arise.

[0006] An electronic structure is disclosed comprising stacks of alternating dielectric materials and conductive materials within a cell region of the electronic structure. A pillar high-k dielectric material is adjacent to the stacks within the pillar region of the electronic structure. A charge blocking material, a nitride material, a tunnel dielectric material, and a channel material are adjacent to the pillar high-k dielectric material within the pillar region of the electronic structure. A cell high-k dielectric material surrounds the conductive materials within the cell region of the electronic structure. The cell high-k dielectric material is connected to a portion of the pillar high-k dielectric material.

[0007] Another electronic structure is disclosed and includes stacks comprising conductive materials that are adjacent to each other and separated by air gaps. The stacks are located within the cell region of the electronic structure. A cell high-k dielectric material surrounds the conductive materials within the cell region. A pillar high-k dielectric material is adjacent to the stacks within the pillar region of the electronic structure. The pillar high-k dielectric material is connected to a portion of the cell high-k dielectric material. A charge blocking material, a nitride material, a tunnel dielectric material, and a channel material are adjacent to the pillar high-k dielectric material within the pillar region of the electronic structure.

[0008] Additionally, a method for forming an electronic device is disclosed, comprising the step of forming stacks of alternating dielectric materials and nitride materials. A pillar high-k dielectric material is formed adjacent to the alternating dielectric materials and nitride materials. A charge blocking material, a nitride material, a tunnel dielectric material, and a channel material are formed adjacent to the pillar high-k dielectric material within the pillar region of the electronic structure, and an insulating material is formed adjacent to the channel material. The nitride materials are removed to form openings between the dielectric materials, and cell high-k dielectric materials are formed within the openings. A portion of the cell high-k dielectric material is connected to a portion of the pillar high-k dielectric material. A conductive material is formed within the openings to form stacks of alternating dielectric materials and conductive materials.

[0009] An electronic device is also disclosed. The electronic device comprises an array of memory cells, wherein the memory cells comprise stacks of alternating dielectric materials and conductive materials within a cell region of the electronic device, and a pillar high-k dielectric material adjacent to the stacks and within a pillar region of the electronic device. An interlayer poly-dielectric structure and a channel material are adjacent to the pillar high-k dielectric material. The cell high-k dielectric material surrounds the conductive materials within the cell region, and a portion of the cell high-k dielectric material is connected to a portion of the pillar high-k dielectric material. Access lines and bit lines are electrically coupled to the memory cells.

[0010] A system is disclosed and includes a processor operably coupled to an input device and an output device, and an electronic device operably coupled to the processor. The electronic device includes memory cells, and one or more of the memory cells include stacks of alternating dielectric materials and conductive materials within a cell region of the electronic device. A pillar high-k dielectric material, an interlayer poly-dielectric structure, and a channel material are adjacent to the stacks within the pillar region of the electronic device. A cell high-k dielectric material is within the cell region, and a portion of the cell high-k dielectric material is adjacent to a portion of the pillar high-k dielectric material. Brief explanation of the drawing

[0011] FIGS. 1A and FIGS. 1B are cross-sectional views of electronic structures comprising a plurality of high k dielectric materials according to embodiments of the present disclosure. FIGS. 2a and 2b are cross-sectional views of electronic structures comprising a plurality of high k dielectric materials according to other embodiments of the present disclosure. FIGS. 3a and 3b are cross-sectional views of electronic structures comprising a plurality of high k dielectric materials according to other embodiments of the present disclosure. FIGS. 4a and 4b are cross-sectional views of electronic structures comprising a plurality of high k dielectric materials according to embodiments of the present disclosure. FIGS. 51a to 5f are cross-sectional views of electronic structures comprising one or more of a plurality of high-k dielectric materials, air gaps, and storage nodes according to embodiments of the present disclosure. FIGS. 6a to 6f are cross-sectional views illustrating the formation of the electronic structures of FIGS. 1a and 1b. FIGS. 7A and FIGS. 7B are cross-sectional views illustrating the formation of the electronic structures of FIGS. 2A and FIGS. 2B. FIGS. 8a to 8c are cross-sectional views illustrating the formation of the electronic structures of FIGS. 3a and 3b. FIGS. 9a to 9c are cross-sectional views illustrating the formation of the electronic structures of FIGS. 4a and 4b. FIG. 10 is a functional block diagram of an electronic device including electronic structures according to embodiments of the present disclosure. FIG. 11 is a simplified block diagram of a system including electronic structures according to embodiments of the present disclosure. Specific details for implementing the invention

[0012] An electronic device (e.g., device, semiconductor device, memory device) comprising a plurality of contiguous high-k dielectric materials is disclosed. The plurality of high-k dielectric materials exist within an electronic structure of the electronic device as at least one high-k dielectric material (e.g., pillar high-k dielectric material) within a pillar region of the electronic structure and one or more high-k dielectric materials (e.g., cell high-k dielectric material) within a cell region of the electronic structure. The plurality (e.g., two or more) high-k dielectric materials are contiguous with each other and are substantially coextensive along the length of the cell high-k dielectric material. The plurality of high-k dielectric materials exist within the pillar region and the cell region to isolate (e.g., electrically isolate) a conductive material in the electronic structure of the electronic device. By including a portion of the high-k dielectric materials (e.g., pillar high-k dielectric material) within the pillar region, additional space for the conductive material within the cell region is available. The conductive material within the cell region may be configured, for example, as a wordline (e.g., gate) of the electronic device. The conductive material is isolated (e.g., electrically isolated) from other conductive materials within the electronic device by the cell high-k dielectric material and the pillar high-k dielectric material.

[0013] The cell region contains a smaller amount (e.g., volume) of high-k dielectric material than that present in conventional electronic devices where the high-k dielectric material exists only within the cell region. The total amount (e.g., total volume) of high-k dielectric materials within the electronic structure according to the embodiments of the present disclosure includes the total (e.g., combined) volume of the pillar high-k dielectric material and the cell high-k dielectric material. The combined volume of high-k dielectric materials within the electronic structure according to the embodiments of the present disclosure may be substantially equal to or greater than the volume of high-k dielectric material in a conventional electronic device where the high-k dielectric material exists only within the cell region. Since the electronic structure contains high-k dielectric materials within the cell region and the pillar region, and the combined volume of high-k dielectric materials is maintained at least, additional space within the cell region for the conductive material is achieved without adversely affecting electrical performance properties such as wordline-to-wordline resistance, wordline-to-wordline coupling, erasure performance, and data retention of the electronic device containing the electronic structure.

[0014] The pillar high-k dielectric material and the cell high-k dielectric material are adjacent to each other in close proximity to the conductive material of the cell region (e.g., directly adjacent). For example, the pillar high-k dielectric material and the cell high-k dielectric material are laterally adjacent to each other in close proximity to the conductive material (e.g., directly laterally adjacent). The length of the cell high-k dielectric material is substantially in line with the length of the pillar high-k dielectric material, while the length of the pillar high-k dielectric material is greater than the length of the cell high-k dielectric material. The entire length of the cell high-k dielectric material in close proximity to the conductive material is in direct contact with the pillar high-k dielectric material. The conductive material extends between adjacent pillar regions, and the cell high-k dielectric material extends between adjacent pillar regions and surrounds the conductive material. The outer surface of the cell high-k dielectric material is in direct contact with the pillar high-k dielectric material and the dielectric material adjacent perpendicularly to the conductive material, and the inner surface of the cell high-k dielectric material is in direct contact with the conductive material.

[0015] Including high-k dielectric materials within the pillar region and the cell region provides improved electrical properties to electronic devices containing high-k dielectric materials due to the placement of the high-k dielectric materials. For example, wordline-to-wordline resistance between vertically adjacent conductive materials (e.g., wordlines, gates) within an electronic device is reduced because additional space within the cell region, provided by moving a portion of the high-k dielectric material into the pillar region, becomes available for the conductive material. An increased amount of conductive material within the cell region reduces wordline-to-wordline resistance between vertically adjacent conductive materials. Forming high-k dielectric materials within both the pillar region and the cell region can also allow the shape of the conductive materials (e.g., wordlines, gates) to be adjustable. For example, the conductive material may have a substantially rectangular cross-section or a round cross-section. The conductive material may define, for example, the wordlines (e.g., gates) of the electronic device. By forming cell-high k dielectric materials and pillar-high k dielectric materials, the shape of the conductive material can be adjusted by controlling the shape of the cell-high k dielectric materials between vertically adjacent conductive materials. The shape of the conductive material affects the effective gate length of an electronic device containing an electronic structure.

[0016] The following description provides specific details, such as material types, material thicknesses, and process conditions, to provide a detailed description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein may be practiced without these specific details. In practice, the embodiments may be practiced with conventional manufacturing techniques employed in the semiconductor industry. Furthermore, the description provided herein does not constitute a complete description of an electronic device or a complete process flow for manufacturing an electronic device, and the structures described below do not constitute a complete electronic device. Only the process operations and structures necessary to understand the embodiments described herein are described in detail below. Additional operations for forming a complete electronic device may be performed by conventional techniques.

[0017] Unless otherwise indicated, the materials described herein may be formed by conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD) (including sputtering, evaporation, ionization PVD, and / or plasma-enhanced CVD), or epitaxial growth. Alternatively, the materials may be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person skilled in the art. Unless the context otherwise indicates, the removal of the materials may be achieved by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization (e.g., chemical-mechanical planarization), or other known methods.

[0018] The drawings presented herein are for illustrative purposes only and are not to be considered actual representations of any specific material, component, structure, electronic device, or electronic system. For example, variations from the shapes depicted in the drawings are expected as a result of manufacturing techniques and / or tolerances. Accordingly, the embodiments described herein should not be considered limited to specific shapes or regions as depicted, and include, for example, variations in shapes resulting from manufacturing. For example, a region depicted or described as a box shape may have approximate and / or non-linear features, and a region depicted or described as a circle may include features that are somewhat approximate and / or linear. Also, a pointed angle depicted may be circular, and vice versa. Therefore, the regions depicted in the drawings are actually schematic, and their shapes are not intended to depict the exact shape of the region and do not limit the scope of the claims. The drawings are not necessarily proportional. Also, elements common between the drawings may retain the same name.

[0019] As used herein, singular expressions include plural forms unless the context clearly indicates otherwise.

[0020] As used herein, "and / or" includes any combination of one or more of the listed related items and all combinations.

[0021] As used herein, “about” or “approximately” with respect to a numerical value for a specific parameter encompasses the numerical value and any deviation from the numerical value that is understood by a person skilled in the art to be within the acceptable tolerance for the specific parameter. For example, with respect to a numerical value, “about” or “approximately” may include additional numerical values ​​within a range of 90.0 percent to 110.0 percent of the numerical value, such as within a range of 95.0 percent to 105.0 percent, within a range of 97.5 percent to 102.5 percent, within a range of 99.0 percent to 101.0 percent, within a range of 99.5 percent to 100.5 percent, or within a range of 99.9 percent to 100.1 percent.

[0022] As used herein, spatially relative terms such as “~ bottom,” “~ below,” “lower side,” “bottom,” “~ above,” “upper side,” “top,” “front,” “back,” “left,” “right,” etc., may be used for convenience of explanation to describe the relationship of one element or feature to another element(s) or feature(s) when depicted in the drawings. Unless otherwise specified, spatially relative terms are intended to encompass orientations other than those depicted in the drawings of the materials. For example, if the materials are inverted in the drawings, elements described as “below,” “bottom,” “lower,” or “bottom” of other elements or features will be oriented “above” or “top” of other elements or features. Accordingly, the term “~ below” may encompass both up and down orientations depending on the context in which the term is used, which will be obvious to those skilled in the art. Materials can be oriented differently (e.g., rotated 90 degrees, inverted, flipped), and accordingly, spatially relative technical terms used herein can be interpreted.

[0023] As used herein, the term "cell high-k dielectric material" means and includes a high-k dielectric material within the cell region of an electronic structure.

[0024] As used herein, the term “cell region” means and includes a region of electronic structures between neighboring pillar high k dielectric materials, and includes stacks of alternating dielectric materials and conductive materials, cell high k dielectric materials, and optionally an etching stop material. Alternatively, the cell region includes stacks of alternating dielectric materials and nitride materials, cell high k dielectric materials, and optionally an etching stop material during the initial stage of forming electronic structures.

[0025] As used herein, the term “configured” refers to the size, shape, material, composition, and arrangement of at least one of at least one structure and at least one device that enables the operation of at least one of at least one of the structure and at least one device in a predetermined manner.

[0026] As used herein, the term “electronic device” includes, without limitation, semiconductor devices that may or may not incorporate memory, such as logic devices, processor devices, or radio frequency (RF) devices, as well as memory devices. Additionally, an electronic device may include memory in addition to other functions, such as, for example, a so-called “system-on-chip (SoC)” that includes a processor and memory, or an electronic device that includes logic and memory. An electronic device may be a 3D electronic device, for example, a 3D NAND flash memory device.

[0027] As used herein, the term “etching stop material” means and includes a material that is resistant to removal (e.g., etching) with respect to the removal of the nitride material of the stacks of alternating dielectric materials and nitride materials during the fabrication of the stacks. The nitride material of the stacks is selectively removable (e.g., selectively etchable) with respect to the etching stop material. The etching stop material is also selectively removable (e.g., selectively etchable) with respect to the exposed materials during a subsequent process operation (e.g., alternate gate operation).

[0028] As used herein, the term "high-k dielectric material" refers to silicon oxide (SiO₂), such as silicon dioxide (SiO₂). x It means and includes dielectric oxide materials having a dielectric constant greater than the dielectric constant of ). High k dielectric materials may include, but are not limited to, high k oxide materials, high k metal oxide materials, or combinations thereof. By way of example only, high k dielectric materials may be aluminum oxide, gadolinium oxide, hafnium oxide, niobium oxide, tantalum oxide, titanium oxide, zirconium oxide, combinations thereof, or a combination of one or more of the listed high k dielectric materials and silicon oxide.

[0029] As used herein, when an element is referred to as being "on" or "above" another element, it includes the element being directly above, adjacent (e.g., transversely adjacent, vertically adjacent), below, or in direct contact with the other element. Additionally, when an element is indirectly above, adjacent (e.g., transversely adjacent, vertically adjacent), below, or in the vicinity of another element, other elements exist between them. In contrast, when one element is referred to as being "directly" on or "directly" adjacent to another element, no intermediate elements exist.

[0030] As used herein, the term "pillar high-k dielectric material" means and includes high-k dielectric material within the pillar region of an electronic structure.

[0031] As used herein, the term "pillar region" means and includes a region of electronic structure between neighboring cell regions, and includes pillar high-k dielectric materials, charge blocking materials, nitride materials, tunnel dielectric materials, channel materials, and insulating materials.

[0032] As used herein, the term “selectively etchable” means and includes a material that, in response to exposure to a given etching chemical or process condition, exhibits a greater etching rate than other materials exposed to the same etching chemical and / or process conditions. For example, the material may exhibit an etching rate that is at least about 5 times greater than the etching rate of another material, such as about 10 times, about 20 times, or about 40 times greater than the etching rate of another material. Etching chemicals and etching conditions for selectively etching a desired material may be selected by a person skilled in the art.

[0033] As used herein, the term “stack” means and includes a feature having one or more materials adjacent perpendicularly to one another. Stacks may include alternating dielectric materials and conductive materials, such as oxide materials and metallic materials, or alternating oxide materials and polysilicon materials. Alternatively, stacks may include alternating dielectric materials and nitride materials, such as alternating oxide materials and silicon nitride materials.

[0034] As used herein, the term “substantially” with respect to a given parameter, attribute, or condition means and includes the extent to which a person skilled in the art would understand that the given parameter, attribute, or condition is satisfied with a degree of deviation such as within acceptable manufacturing tolerances. For example, depending on a specific parameter, attribute, or condition that is substantially satisfied, the parameter, attribute, or condition may be satisfied by 90.0% or more, 95.0% or more, 99.0% or more, or more precisely, 99.9% or more.

[0035] As used herein, the term “substrate” means and includes a material (e.g., a base material) or a composition on which additional materials are formed. The substrate may be an electronic substrate, a semiconductor substrate, an electronic substrate on which a base semiconductor layer, an electrode, one or more materials, layers, structures, or regions are formed thereon, or a semiconductor substrate on which one or more materials, layers, structures, or regions are formed thereon. Materials on the electronic substrate or semiconductor substrate may include, but are not limited to, semiconductor materials, insulating materials, conductive materials, etc. The substrate may be a conventional silicon substrate or other bulk substrate comprising a semiconductor material layer. As used herein, the term “bulk substrate” means and includes silicon wafers, as well as silicon-on-insulator (“SOI”) substrates such as silicon-on-sapphire (“SOS”) substrates and silicon-on-glass (“SOI”) substrates, epitaxial layers of silicon on a base semiconductor, and other semiconductor or optoelectronic materials such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphate. The substrate may or may not be doped.

[0036] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are based on the principal plane of the structure and are not necessarily limited by the Earth’s gravitational field. The “horizontal” or “lateral” direction is substantially parallel to the principal plane of the structure, while the “vertical” or “longitudinal” direction is substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surface of the structure having a relatively large area compared to the other surfaces of the structure.

[0037] An electronic structure (100) according to embodiments of the present disclosure and comprising a plurality of high-k dielectric materials is illustrated in FIG. 1a and FIG. 1b, wherein FIG. 1b is an enlarged view of the dashed area of ​​FIG. 1a. The electronic structure (100) comprises stacks (105) of alternating dielectric materials (110) and conductive materials (115), optionally an etching stop material (120), a first high-k dielectric material (125) (e.g., pillar high-k dielectric material (125)), a second high-k dielectric material (130) (e.g., cell high-k dielectric material (130)), a charge blocking material (135), a storage node material (140), a tunnel dielectric material (145), a channel material (150), and an insulating material (160) (e.g., a charge material). The pillar high k dielectric material (125) is present in the pillar region (170) of the electronic structure (100), and the cell high k dielectric material (130) is present in the cell region (165) of the electronic structure (100). The pillar region (170) includes pillar high k dielectric materials (125), charge blocking materials (135), storage node materials (140), tunnel dielectric materials (145), channel materials (150), and insulating materials (160). The cell region (165) includes dielectric materials (110), conductive materials (115), cell high k dielectric materials (130), and optionally etching stop materials (120). Depending on the manufacturing stage, the electronic structure (100) includes stacks (105) of alternating dielectric materials (110) and conductive materials (115), or stacks (105) of alternating dielectric materials (110) and nitride materials (675) (e.g., see FIG. 6a).

[0038] The dielectric materials (110) have a length L1, and the conductive materials (115) have a length L2, wherein L1 and L2 may be substantially the same, L1 may be greater than L2, or L1 may be smaller than L2. The dielectric materials (110) of the stacks (105) may be silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials. In some embodiments, the dielectric material (110) is silicon oxide. The conductive material (115) may function as a wordline of an electronic device comprising an electronic structure (100). The conductive materials (115) of the stacks (105) may be any conductive material including but not limited to n-doped polysilicon, p-doped polysilicon, undoped polysilicon, or metal. The locations of the conductive materials (115) correspond to where the nitride materials (675) of the stacks (105) (e.g., see FIG. 6a) are initially present during the manufacture of the electronic structure (100). In some embodiments, the conductive material (115) is n-doped polysilicon. The conductive material (115) is isolated (e.g., electrically isolated) from other conductive materials within the electronic device by the cell high k dielectric material (130) and the pillar high k dielectric material (125). The stacks (105) may include multiple tiers of alternating dielectric materials (110) and conductive materials (115), such as 50 or more tiers, 100 or more tiers, 200 or more tiers, or 500 or more tiers. FIGS. 1a and FIGS. 1b include three layers of alternating dielectric materials (110) and conductive materials (115), but more layers may exist.

[0039] The pillar high k dielectric material (125) exists within the pillar region (170) of the electronic structure (100), and the cell high k dielectric material (130) exists within the cell region (165) of the electronic structure (100). The connecting portions of the pillar high k dielectric material (125) and the cell high k dielectric material (130) are laterally adjacent to each other (e.g., directly laterally adjacent), but are not on the same line along the entire length of the pillar high k dielectric material (125). The connecting portions of the pillar high k dielectric material (125) and the cell high k dielectric material (130) are referred to herein as combined high k dielectric materials (125 / 130). The pillar high k dielectric material (125) is between the cell high k dielectric material (130) and the charge blocking material (135), and a portion of the cell high k dielectric material (130) (e.g., a vertical portion) is between the first high k dielectric material (125) and the conductive materials (115).

[0040] The pillar high k dielectric material (125) extends for a length L3 of the stacks (105) (e.g., substantially the entire length of the stacks (105)) and lies on the charge blocking material (135) (e.g., adjacent laterally, directly adjacent laterally), such as on the side walls (e.g., vertical surfaces) of the charge blocking material (135). The vertical portions of the cell high k dielectric material (130) lie on the conductive material (115) (e.g. adjacent laterally, directly adjacent laterally), such as on the side walls (e.g., vertical surfaces) of the conductive material (115). The portions of the cell high k dielectric material (130) also lie on the horizontal surfaces of the conductive material (115) (e.g. adjacent horizontally, directly adjacent horizontally). As illustrated in the drawing of FIG. 1a, the cell high k dielectric material (130) is on the horizontal and vertical surfaces of the conductive material (115) and substantially surrounds the conductive material (115). The length L4 of the vertical portions of the cell high k dielectric material (130) adjacent to the pillar high k dielectric material (125) is greater than the length L2 of the conductive material (115). Since the cell high k dielectric material (130) substantially surrounds the conductive material (115), additional portions of the cell high k dielectric material (130) extend beyond the length L2 of the conductive material (115). The conductive material (115) includes substantially vertical sidewalls and substantially horizontal surfaces, and as illustrated in FIG. 1a and FIG. 1b, the upper and lower portions of the cell high k dielectric material (130) on the sidewalls of the conductive material (115) extend above and below the upper and lower surfaces of the conductive material (115). The upper and lower portions of the cell high dielectric material (130) on the horizontal surfaces of the conductive material (115) are substantially flat and substantially parallel to each other.The conductive material (115) forms word lines (e.g., gates) having substantially the same dimensions (e.g., substantially the same length L2) at both ends of the conductive material (115) and along the length L2 of the conductive material (115). In other words, the end portions of the conductive material (115) and the middle portions of the conductive material (115) adjacent to the adjacent pillar high dielectric material (125) exhibit substantially the same width L2.

[0041] As most clearly illustrated in FIG. 1b, portions of the pillar high k dielectric material (125) and the cell high k dielectric material (130) are laterally adjacent to and connected to each other with respect to the conductive material (115), while other portions of the pillar high k dielectric material (125) are laterally adjacent to the etching stop material (120) (if present) or the dielectric material (110). The cell high k dielectric material (130) is substantially in alignment with the portion of the pillar high k dielectric material (125), while the length L3 of the pillar high k dielectric material (125) is greater than the length L4 of the cell high k dielectric material (130). The entire length L4 of the cell high k dielectric material (130) is in direct contact with the pillar high k dielectric material (125). The length L4 of the cell high k dielectric material (130) is equal to the length L2 of the conductive material (115) plus twice the thickness of the cell high k dielectric material (130). The first vertical surface of the cell high k dielectric material (130) between the conductive material (115) and the pillar high k dielectric material (125) is in direct contact with the conductive material (115), and the second vertical surface opposite the first vertical surface of the cell high k dielectric material (130) is in direct contact with the pillar high k dielectric material (125). The interfacial properties of the pillar high k dielectric material (125) and the cell high k dielectric material (130) may be sufficient for the combined high k dielectric materials (125, 130) to exhibit desired electrical performance properties of an electronic device comprising an electronic structure (100). If an etching stop material (120) is present, a portion of the pillar high k dielectric material (125) is directly laterally adjacent to the etching stop material (120). The etching stop material (120) can protect the pillar high k dielectric material (125) from removal during a subsequent process operation. If the etching stop material (120) is not present, a portion of the pillar high k dielectric material (125) is directly laterally adjacent to the dielectric material (110).

[0042] Each of the pillar high k dielectric material (125) and the cell high k dielectric material (130) is a dielectric material having a dielectric constant greater than the dielectric constant of silicon dioxide. Each of the pillar high k dielectric material (125) and the cell high k dielectric material (130) may include, but is not limited to, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, combinations thereof, or silicon oxide and one or more of the listed materials. The pillar high k dielectric material (125) and the cell high k dielectric material (130) may be the same material. Alternatively, different materials may be used for each of the pillar high k dielectric material (125) and the cell high k dielectric material (130). By using different materials, the data retention properties and erasure performance properties over time of the electronic device including the electronic structure (100) may be adjusted.

[0043] The thickness of each of the pillar high k dielectric material (125) and the cell high k dielectric material (130) may be about 1 nm to about 10 nm, about 1 nm to about 4 nm, about 1 nm to about 3 nm, about 1 nm to about 2 nm, or about 2 nm to about 4 nm, or about 2 nm to about 3 nm. Alternatively, the thickness of one or more of the pillar high k dielectric material (125) and the cell high k dielectric material (130) may be less than about 1 nm, for example, a single layer thickness. The combined thickness of the pillar high k dielectric material (125) and the cell high k dielectric material (130) may be sufficient to form a substantially continuous material over (e.g., adjacent to) the exposed materials of the electronic structure (100) to protect these materials during subsequent process operations. The thickness of the cell high k dielectric material (130) may be less than about 1 nm, or a few single-layer thickness, depending on the desired performance properties of the electronic device including the electronic structure (100). To provide sufficient space for the conductive materials (115) within the cell region (165) of the electronic structure (100), the cell high k dielectric material (130) may be about 1 nm to about 2 nm thick, and the pillar high k dielectric material (125) may be about 2 nm to about 4 nm thick.

[0044] The cell high k dielectric material (130) may account for a smaller proportion of the total high k dielectric material thickness (the thickness of the cell high k dielectric material (130) and the thickness of the pillar high k dielectric material (125)) to achieve desired performance properties of the electronic device. For example, the total high k dielectric material thickness of the pillar high k dielectric material (125) and the cell high k dielectric material (130) may be minimized to reduce the effect on wordline resistance between vertically adjacent conductive materials (115). The cell high k dielectric material (130) may be formed with a few single-layer thicknesses, and the pillar high k dielectric material (125) may account for the remainder of the total high k dielectric material thickness. If the total high k dielectric material thickness is mostly due to the thickness of the pillar high k dielectric material (125), the effect on the performance properties provided by the combined high k dielectric materials (125 / 130) may be mostly due to the properties of the pillar high k dielectric material (125). The total thickness of the adjacent pillar high k dielectric material (125) and cell high k dielectric material (130) may be about 2 nm to about 20 nm, about 2 nm to about 8 nm, about 2 nm to about 6 nm, about 2 nm to about 4 nm, or about 4 nm to about 8 nm, or about 4 nm to about 6 nm.

[0045] Although the embodiments described and illustrated herein refer to the Phila High K dielectric material (125) and the Cell High K dielectric material (130) as single materials, one or more of the Phila High K dielectric material (125) and the Cell High K dielectric material (130) may comprise multiple materials, such as a stack of High K dielectric materials. Each of the Phila High K dielectric material (125) and the Cell High K dielectric material may have a substantially homogeneous chemical composition or a heterogeneous chemical composition.

[0046] As most clearly illustrated in FIG. 1b, the etching stop material (120) as an option may be located directly between the dielectric material (110) and the pillar high k dielectric material (125) of the stacks (105), for example, between the dielectric material (110) and the pillar high k dielectric material (125). The material of the etching stop material (120) may be selected to be selectively removable (e.g., selectively etchable) with respect to the dielectric material (110) and the pillar high k dielectric material (125). However, during a previously performed process operation in which the nitride material of the stack (105) (e.g., stack nitride material (675)) is removed before forming the cell high k dielectric material (130), for example, during an alternative gate process operation, the etching stop material (120) is not substantially removable. As merely an example, substantially all of the etching stop material (120) may remain during the removal of the nitride material (675). Subsequently with the removal of the nitride material (675), some parts of the etching stop material (120) are selectively removed and other parts of the etching stop material (120) remain before the formation of the cell high-k dielectric material (130) occurs. The etching stop material (120) may include, but is not limited to, silicon oxide, silicon carbonitride, silicon oxycarbide, or a combination thereof.

[0047] A charge blocking material (135) is on a pillar high dielectric material (125) (e.g., adjacent thereto thereto), a storage node material (140) is on the charge blocking material (135), and a tunnel dielectric material (145) is on the storage node material (140). A channel material (150) is on the tunnel dielectric material (145), and an insulating material (160) is between adjacent channel materials (150). The charge blocking material (135) may include silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof, but is not limited thereto. The storage node material (140) may include silicon nitride, silicon oxynitride, or a combination thereof, but is not limited thereto. The tunnel dielectric material (145) may include silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof, but is not limited thereto. In some embodiments, the charge blocking material (135), the storage node material (140), and the tunnel dielectric material (145) form an oxide-nitride-oxide (ONO) structure (e.g., an interlayer polydielectric structure). The channel material (150) may be doped polysilicon, undoped polysilicon, or other material. In some embodiments, the channel material (150) is polysilicon. The insulating material (160) may be a dielectric material comprising, but not limited to, silicon dioxide, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass; titanium dioxide, hafnium oxide, zirconium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, or a combination thereof.

[0048] An electronic structure (100') comprising a plurality of high k dielectric materials (125, 130') according to other embodiments of the present disclosure is illustrated in FIGS. 2a and 2b. The materials, material thicknesses, relative positions of the materials, etc. of the electronic structure (100') are as described above with respect to FIGS. 1a and 1b. The electronic structure (100') differs from the electronic structure (100) in that an etching stop material (120') is present, and the length L4 of the cell high k dielectric material (130') is longer than the length L4 of the cell high k dielectric material (130) in FIGS. 1a and 1b. The cell high k dielectric material (130') has a length L4' proximal to the pillar high k dielectric material (125) and a length L4 distal to the pillar high k dielectric material (125). The length L4' of the cell high k dielectric material (130') in the electronic structure (100') is also longer than the length L4 of the cell high k dielectric material (130) in the electronic structure (100'). The cell high k dielectric material (130') according to the embodiments of the present disclosure in FIG. 2a and 2b extends by a greater distance in the vertical direction than the cell high k dielectric material (130) of the electronic structure (100) in FIG. 1a and 1b. Accordingly, the cell high k dielectric material (130') is connected to a greater proportion of the pillar high k dielectric material (125) (e.g., directly adjacent) compared to the proportion of the connecting high k dielectric materials (125, 130) in the electronic structure (100) of FIG. 1a and 1b. Parts of the etching stop material (120') exist between the ends of the dielectric material (110) and the pillar high dielectric material (125). The length of the etching stop material (120') is shorter than the length of the etching stop material (120) (when present) in the electronic structure (100) of FIG. 1a and FIG. 1b.As illustrated in FIGS. 2a and 2b, the cell high k dielectric material (130') on the vertical sidewalls of the conductive material (115) extends above and below the cell high k dielectric material (130') on the horizontal surfaces of the conductive material (115). Compared to the electronic structure (100) of FIGS. 1a and 1b, portions of the cell high k dielectric material (130') adjacent to the pillar high k dielectric materials (125) protrude above and below the cell high k dielectric material (130') on the horizontal surfaces of the conductive material (115). Similar to the electronic structure (100) of FIGS. 1a and 1b, the conductive material (115) also includes substantially linear sidewalls and substantially horizontal upper and lower surfaces. Accordingly, the conductive material (115) in the electronic structure (100') forms a word line having substantially the same dimensions (e.g., substantially the same length L2) at both ends of the conductive material (115) as at the middle portions of the conductive material (115), for example, similar to the electronic structure (100) of FIG. 1a and FIG. 1b. In both electronic structures (100, 100'), the conductive material (115) has a substantially rectangular cross-section, and its length L2 is substantially uniform between adjacent pillar regions (170).

[0049] An electronic structure (100'') according to other embodiments of the present disclosure and comprising a plurality of high k dielectric materials (125, 130') is illustrated in FIGS. 3a and 3b. The materials, material thicknesses, relative positions of the materials, etc. of the electronic structure (100'') are as described above for the electronic structure (100) in FIGS. 1a and 1b. The electronic structure (100'') differs from the electronic structure (100) in that an etching stop material (120'') is present. The electronic structure (100'') is also different in that the length L4' of the cell high k dielectric material (130'') adjacent to the pillar high k dielectric material (125) is longer than the length L4 of the cell high k dielectric material (130) in FIG. 1a and 1b, and the length L2' of the conductive material (115'') is longer than the length L2 of the conductive material (115) in FIG. 1a and 1b. The length L4' of the cell high k dielectric material (130'') is also longer than the length L4 of the cell high k dielectric material (130'') distal to the pillar high k dielectric material (125). The electronic structure (100'') is also different from the electronic structures (100, 100') in that the conductive material (115'') includes non-linear (e.g., round) surfaces proximal to the pillar region (170). The electronic structure (100'') differs from the electronic structures (100, 100') in that portions of both the conductive material (115'') and the cell high k dielectric material (130'') protrude above and below the horizontal surfaces of the conductive material (115''). For example, portions of the conductive material (115'') and the cell high k dielectric material (130'') adjacent to the pillar high k dielectric materials (125) extend above and below the horizontal surfaces of the conductive material (115''). Accordingly, the conductive materials (115'') and the cell high k dielectric materials (130'') have increased lengths L2', L4', respectively, proximal to the pillar region (170) compared to the lengths of comparable materials of the electronic structures (100, 100'). The effective gate lengths proximate to the pillar high k dielectric materials (125) are increased by increasing the length of the conductive material (115''), but only at locations close to the pillar region (170). The length of the conductive material (115'') at locations distal to the pillar high k dielectric materials (125) (e.g., distal to the pillar region (170)) is length L2. Accordingly, the conductive material (115'') forms a wordline (e.g., gate) having a length L2' at the proximate to the pillar region (170) greater than the length L2 at the distal to the pillar region (170). Accordingly, the effective gate length proximate to the pillar high k dielectric materials (125) is increased without increasing the effective gate length at parts of the conductive material (115) distal to the pillar high k dielectric material (125). By increasing the effective gate length only in proximity to the pillar region (170), the coupling between adjacent conductive materials (115'') is reduced.

[0050] The cell high k dielectric material (130'') is also extended by a greater distance in the vertical direction than the cell high k dielectric material (130) of the electronic structure (100) in FIGS. 1a and 1b. Accordingly, the cell high k dielectric material (130'') is connected to a larger proportion of the pillar high k dielectric material (125) compared to the connected portion in the electronic structure (100) of FIGS. 1a and 1b. The portions of the etching stop material (120'') exist between the cell high k dielectric material (130'') that are vertically adjacent and close to the pillar high k dielectric materials (125). As shown in FIGS. 3a and 3b, the cell high k dielectric material (130'') on the vertical sidewalls of the conductive material (115'') extends above and below the cell high k dielectric material (130'') on the horizontal surfaces (e.g., intermediate portions) of the conductive material (115''). Additionally, portions of the conductive material (115'') adjacent to the pillar high k dielectric materials (125) are substantially identical to or extend upward and downward to the surfaces of the cell high k dielectric material (130'') on the horizontal surfaces of the conductive material (115''). In contrast to the electronic structure (100) of FIGS. 1A and 1B, portions of the cell high k dielectric material (130'') protrude upward and downward from the cell high k dielectric material (130'') on the horizontal surfaces of the conductive material (115'') adjacent to the pillar high k dielectric materials (125). Similar to the electronic structure (100') of FIGS. 2A and 2B, portions of the cell high k dielectric material (130'') adjacent to the pillar high k dielectric materials (125) protrude upward and downward from the horizontal surfaces of the conductive material (115''). Parts of the conductive material (115'') adjacent to the pillar high k dielectric materials (125) also protrude above and below the horizontal surfaces of the conductive material (115'').By increasing the length (L2') of the conductive material (115''), but only at locations close to the pillar region (170), the effective gate length near the pillar high k dielectric material (125) is increased. The gate defined by the conductive material (115'') has a greater length L2' near the pillar high k dielectric materials (125) than near the pillar high k dielectric materials (125). The conductive material (115'') also includes non-linear (e.g., rounded) surfaces near the pillar high k dielectric materials (125), while the surfaces of the intermediate portions of the conductive material (115'') are substantially parallel to each other. The increased lengths L2' and L4' of the conductive material (115'') and the cell high dielectric material (130'') near the pillar region (170), respectively, provide an increased effective gate length to the electronic structure (100'') compared to conventional electronic devices.

[0051] An electronic structure (100''') according to other embodiments of the present disclosure and comprising a plurality of high k dielectric materials (125, 130''') is illustrated in FIG. 4a and FIG. 4b. The materials, material thicknesses, relative positions of the materials, etc. of the electronic structure (100''') are as described above with respect to FIG. 1a and FIG. 1b. The electronic structure (100''') differs from the electronic structure (100) in that an etching stop material (120''') is present, and the width W2 of the etching stop material (120''') is greater than the width W1 of the etching stop material (120) (if present) in FIG. 1a and FIG. 1b. A greater width W2 allows the lengths L2' and L4' of the conductive material (115''') and the cell high k dielectric material (130'''), respectively, to be larger than the lengths L2 and L4 of the conductive material (115''') and the cell high k dielectric material (130'''), respectively. The electronic structure (100''') differs from the electronic structures (100, 100') in that the conductive material (115) includes non-linear (e.g., rounded) surfaces proximal to the pillar high k dielectric material (125). The electronic structure (100''') also differs from the electronic structures (100, 100') in that parts of both the conductive material (115''') and the cell high k dielectric material (130''') protrude above and below the surfaces of the conductive material (115'''). Parts of the conductive material (115''') and the cell high-k dielectric material (130''') adjacent to the pillar region (170) in the electronic structures (100''') extend above and below the horizontal surfaces of the conductive material (115'''). By increasing the length L2' of the conductive material (115''') near the pillar high-k dielectric materials (125), the effective gate length is increased compared to conventional electronic devices without increasing the effective gate length in the middle parts of the conductive material (115''').By increasing the effective gate length only in proximity to the pillar region (170), the coupling between adjacent conductive materials (115''') is reduced. Additionally, the conductive material (115''') defines a gate having different dimensions than in the middle portions of the conductive material (115''') near the pillar high k dielectric materials (125). The electronic structure (100''') differs from the electronic structures (100', 100'') in that the etching stop material (120''') has larger dimensions (e.g., width W2) than the corresponding material of the electronic structures (100, 100', 100''). The greater width of the etching stop material (120''') allows a larger recess (790) (see FIG. 8b) to be formed perpendicularly adjacent to the etching stop material (120'''), where both the conductive material (115''') and the cell high k dielectric material (130''') are ultimately formed. The electronic structure (100''') differs from the electronic structure (100'') in that the initially formed etching stop material (120''') is thicker, so a larger amount of the cell high k dielectric material (130''') and the conductive material (115''') can exist within the recesses (790). The larger dimensions and rounded shape of the recesses (790) allow additional cell high-k dielectric material (130''') and conductive material (115''') to be formed within the recesses (790) compared to the electronic structures (100''). By forming the conductive material (115''') and cell high-k dielectric material (130''') within the recesses (790), non-linear (e.g., rounded) surfaces of the gate are created.

[0052] Parts of the etching stop material (120''') exist between the conductive materials (115''') and the cell high k dielectric materials (130''') that are vertically adjacent to the pillar high k dielectric materials (125). The width W2 of the etching stop material (120''') is greater than the thickness of the cell high k dielectric material (130'''). Accordingly, the sidewalls of the etching stop material (120''') adjacent to the dielectric material (110''') and the sidewalls of the cell high k dielectric material (130''') adjacent to the conductive material (115''') are substantially not aligned. In contrast, the sidewalls of the etching stop material (120) of the electronic structure (100) are substantially aligned with the outer surface of the cell high k dielectric material (130), as can be seen in the electronic structure (100) in FIG. 1a and FIG. 1b. In other words, the vertical sidewalls of the cell high k dielectric material (130''') and the vertical sidewalls of the etching stop material (120''') near the intermediate portions of the cell high k dielectric material (130''') and the conductive material (115''') are not substantially coplanar with each other. The cell high k dielectric material (130''') substantially surrounds the conductive material (115''') in the figure of FIG. 4a. The lengths L2' and L4' of the conductive material (115''') and the cell high k dielectric material (130''') near the pillar region (170), respectively, are greater than the lengths L2 and L4 of the conductive material (115''') and the cell high k dielectric material (130''') near the pillar region (170), respectively. Since the cell high k dielectric material (130''') surrounds the conductive material (115''') and the length of the conductive material (115''') at the proximal end of the pillar high k dielectric material (125) is greater than the length at the middle portions of the conductive material (115'''), the additional portions of the cell high k dielectric material (130''') and the conductive material (115''') extend beyond the length L2 of the conductive material (115''').The conductive material (115''') includes substantially horizontal surfaces and substantially vertical sidewalls in its middle portion. However, as shown in FIGS. 4a and 4b, the upper and lower surfaces of the cell high dielectric material (130''') on the sidewalls of the conductive material (115''') extend above and below the upper and lower surfaces of the middle portions of the conductive material (115''').

[0053] As illustrated in FIGS. 4a and 4b, the length L4 of the cell high k dielectric material (130''') is substantially in line with the length L3 of the pillar high k dielectric material (125), while the length L3 of the pillar high k dielectric material (125) is greater than the length L4' of the cell high k dielectric material (130'''). For example, the entire length L4' of the cell high k dielectric material (130''') adjacent to the conductive material (115''') is in direct contact with the pillar high k dielectric material (125). The first vertical surface of the cell high k dielectric material (130''') is in direct contact with the conductive material (115'''), and the second vertical surface opposite the first vertical surface of the cell high k dielectric material (130''') is in direct contact with the pillar high k dielectric material (125). The conductive material (115''') proximal to the pillar high k dielectric material (125) exhibits a length L2' greater than the length L2 of the middle portion of the conductive material (115'''). In contrast to the electronic structure (100') of FIGS. 2A and 2B, the cell high k dielectric material (130''') and the conductive material (115''') adjacent to the pillar high k dielectric materials (125) exhibit a rounded cross-sectional shape rather than the substantially rectangular cross-sectional shape of the cell high k dielectric material (130') and the conductive material (115') of the electronic structure (100'). Similar to the electronic structure (100'') of FIGS. 3A and 3B, the conductive material (115''') includes rounded surfaces proximal to the pillar high k dielectric material (125).

[0054] The electronic structures (100'', 100''') also have greater effective gate lengths than the electronic structures (100, 100') because the length L2' of the conductive materials (115'', 115''') near the pillar region (170) in the electronic structures (100'', 100''') is greater than the length L2 of the conductive materials (115, 115') near the pillar region (170) in the electronic structures (100, 100'). The increased effective gate lengths of the electronic structures (100'', 100''') are achieved without increasing the length L2 of the intermediate portions of the conductive materials (115'', 115'''). Accordingly, the coupling between vertically adjacent conductive materials (115'', 115''') is not increased. The electronic structures (100'', 100''') also have an increased amount of conductive material (115'', 115''') compared to the electronic structures (100, 100') because the conductive material (115'', 115''') is also present within the recesses (790). Accordingly, in some embodiments, the conductive material (115) near the pillar region (170) exhibits substantially the same dimensions (e.g., length L2) as the conductive material (115) far from the pillar high dielectric material. In other embodiments, the conductive materials (115'', 115''') near the pillar region (170) exhibit a length L2' greater than the length L2 of the conductive material (115'', 115''') far from the pillar region (170).

[0055] Electronic structures (100, 100', 100'', 100'') according to embodiments of the present disclosure may also be used in electronic structures (100A, 100A', 100A'', 100B, 100B', 100B'') comprising one or more of air gaps (1090) (e.g., voids) or storage nodes (1095), as illustrated in FIGS. 5A through 5F. The air gaps (1090) or storage nodes (1095) are incorporated into the electronic structures (100A, 100A', 100A'', 100B, 100B', 100B'') by conventional techniques. FIGS. 51a to 52c illustrate electronic structures (100A (Fig. 51a, FIG. 52a), 100A' (Fig. 51b, FIG. 52b), and 100A'' (Fig. 51c, FIG. 52c)), each of which electronic structure (100A) includes air gaps (1090) in combination with electronic structure (100), electronic structure (100A') includes air gaps (1090) in combination with electronic structure (100'), and electronic structure (100A'') includes air gaps (1090) in combination with electronic structure (100''). The etching stop material (120) may be present in the electronic structures (100A (Fig. 51a), 100A' (Fig. 51b), and 100A'' (Fig. 51c)), or the etching stop material (120) may not be present in the electronic structures (100A (Fig. 52a), 100A' (Fig. 52b), and 100A'' (Fig. 52c)). If the etching stop material (120) is not present, the air gaps (1090) are defined by the horizontal surfaces of the second high-k dielectric material (130) and the vertical surfaces of the etching stop material (120) or the vertical surfaces of the pillar high-k dielectric material (125).FIGS. 5d to 5f illustrate electronic structures (100B (Fig. 5d), 100B' (Fig. 5e), and 100B'' (Fig. 5f)), each electronic structure (100B) includes air gaps (1090) and storage nodes (1095) in combination with electronic structure (100), electronic structure (100B') includes air gaps (1090) and storage nodes (1095) in combination with electronic structure (100'), and electronic structure (100B'') includes air gaps (1090) and storage nodes (1095) in combination with electronic structure (100''). The storage node (1095) is defined by the horizontal surfaces of the pillar high k dielectric material (125'), the charge blocking material (135'), and the nitride material (140) and the vertical surfaces of the tunnel dielectric material (145), and the air gaps (1090) are defined by the horizontal surfaces of the second high k dielectric material (130), the vertical surfaces of the etching stop material (120, 120'', 120'''), and the storage node (1095).

[0056] Accordingly, an electronic structure is disclosed. The electronic structure comprises stacks of alternating dielectric materials and conductive materials within the cell region of the electronic structure. A pillar high-k dielectric material is adjacent to the stacks within the pillar region of the electronic structure. A charge blocking material, a nitride material, a tunnel dielectric material, and a channel material are adjacent to the pillar high-k dielectric material within the pillar region of the electronic structure. A cell high-k dielectric material surrounds the conductive materials within the cell region of the electronic structure. The cell high-k dielectric material is connected to a portion of the pillar high-k dielectric material.

[0057] Accordingly, another electronic structure is disclosed. The electronic structure comprises stacks containing conductive materials that are adjacent to each other and separated by air gaps—the stacks are located within the cell region of the electronic structure. A cell high-k dielectric material surrounds the conductive materials within the cell region. A pillar high-k dielectric material is adjacent to the stacks within the pillar region of the electronic structure. The pillar high-k dielectric material is connected to a portion of the cell high-k dielectric material. A charge blocking material, a nitride material, a tunnel dielectric material, and a channel material are adjacent to the pillar high-k dielectric material within the pillar region of the electronic structure.

[0058] The electronic structure (100) of FIGS. 1a and 1b may be formed as illustrated in FIGS. 6a through 6f. To form the electronic structure (100), alternating dielectric materials (110) and nitride materials (675) of stacks (105) are formed by conventional techniques. The nitride materials (675) may be, for example, silicon nitride. A portion of the dielectric materials (110) and nitride materials (675) is removed (e.g., etched) to form the stacks (105), and adjacent stacks (105) are separated from each other by pillar openings (680), as illustrated in FIG. 6a. The pillar openings (680) are formed by etching the dielectric materials and nitride materials using conventional techniques, such as conventional photolithography and etching techniques. The materials of the stacks (105) may be exposed to an anisotropic etching process, such as a dry plasma etching process or a reactive ion etching process, to form the stacks (105). Conventional etching chemicals and etching conditions may be used to form the stacks (105) and the pillar openings (680). The stacks (105) may be high aspect ratio (HAR) features having an aspect ratio (i.e., ratio of width to depth) of about 5:1 or greater, such as about 5:1 to about 100:1, about 5:1 to about 50:1, about 10:1 to about 40:1, about 10:1 to about 30:1, about 10:1 to about 20:1, about 20:1 to about 50:31, about 20:1 to about 40:1, or about 20:1 to about 30:1. Pillar openings (680) may also exhibit a high aspect ratio. In addition to the stacks (105) being composed of lines (e.g., wordlines), other compositions may be considered.

[0059] An etching stop material (120) (if present) may be formed on the stacks (105), such as on the sidewalls of the stacks (105), as illustrated in FIG. 6b. The etching stop material (120) may be formed by conventional techniques and may be extended by the length L3 of the stack (105). If the etching stop material (120) is not present, a pillar high k dielectric material (125) may be formed on the sidewalls of the nitride materials (675) and dielectric materials (110). The pillar high k dielectric material (125) may be formed on the etching stop material (120), such as on the sidewalls of the etching stop material (120), by conventional techniques as illustrated in FIG. 6c. The pillar high k dielectric material (125) may be extended by the length L3 of the stack (105). Subsequently, a charge blocking material (135), a storage node material (140), and a tunnel dielectric material (110) may be formed sequentially on the pillar high k dielectric material (125), for example on the sidewalls of the pillar high k dielectric material (125), and may be extended for the length of the pillar high k dielectric material (125). A channel material (150) may be formed on the tunnel dielectric material (110), for example on the sidewalls of the tunnel dielectric material (110), and an insulating material (160) (not shown in FIG. 6a through 6f) may be formed within the remaining portion of the openings (680). The charge blocking material (135), the storage node material (140), and the tunnel dielectric material (110) may be formed for the entire length L3 of the stack (105) to form, for example, an ONO structure. The charge blocking material (135), storage node material (140), and tunnel dielectric material (110) can be formed by conventional techniques. The etching stop material (120), pillar high dielectric material (125), charge blocking material (135), storage node material (140), and tunnel dielectric material (110) can be formed conformally, for example, by CVD or ALD.

[0060] As illustrated in FIG. 6d, the nitride materials (675) may be removed (e.g., exposed, etched) to expose the etching stop material (120) (if present) and form openings (685) between vertically adjacent dielectric materials (110) of the stacks (105). The nitride materials (675) may be removed by conventional techniques such as a wet etching process. Conventional etching chemicals and etching conditions may be used to remove the nitride materials (675). The etching chemicals and etching conditions may be selected according to the materials used for the nitride materials (675) and the etching stop material (120) (if present). The etching chemicals and etching conditions may selectively remove the nitride materials (675) without substantially removing the etching stop material (120) (if present) or the dielectric material (110). The etching stop material (120) can protect the pillar high k dielectric material (125) during, for example, a wet etching process. If the etching stop material (120) is not present, the nitride materials (675) can be selectively removed without substantially removing the pillar high k dielectric material (125). Etching chemicals and etching conditions can be selected so that the pillar high k dielectric material (125) is exposed after the nitride materials (675) are removed, with only a minimal portion of the pillar high k dielectric material (125) removed.

[0061] Parts of the etching stop material (120) (if present) can be selectively removed, as illustrated in FIG. 6e, to expose the pillar high k dielectric material (125). Parts of the etching stop material (120) may remain adjacent to the dielectric material (110) (e.g., adjacent laterally). Accordingly, the etching stop material (120) separates the dielectric material (110) from the pillar high k dielectric material (125). Conventional etching chemicals and etching conditions may be used to selectively remove the etching stop material (120). The etching chemicals and etching conditions may be selected so that desired parts of the etching stop material (120) are removed without substantially removing the exposed pillar high k dielectric material (125) and dielectric material (110).

[0062] A cell high k dielectric material (130) may be formed adjacent to (e.g., on top of) the dielectric material (110) and the pillar high k dielectric material (125), as illustrated in FIG. 6f. The cell high k dielectric material (130) may be formed conformally on the exposed horizontal surfaces of the dielectric material (110) and the exposed vertical surfaces of the pillar high k dielectric material (125). The cell high k dielectric material (130) may be formed, for example, by ALD. The cell high k dielectric material (130) is formed within a portion of the openings (685) and is in direct contact with the pillar high k dielectric material (125) along the vertical surfaces of the pillar high k dielectric material (125). If multiple high-k dielectric materials (125, 130) are present at these locations, the total thickness of the high-k dielectric materials (125, 130) at these locations is greater than the thickness of the pillar high-k dielectric material (125) and cell high-k insulating material (130) at other locations.

[0063] By forming the pillar high k dielectric material (125) and the cell high k dielectric material (130) at different stages in the manufacturing process, different high k dielectric materials may be used, which provides increased flexibility in the manufacturing process. However, the pillar high k dielectric material (125) and the cell high k dielectric material (130) may be formed from the same high k dielectric material. Additionally, since the pillar high k dielectric material (125) and the cell high k dielectric material (130) are formed individually, one or more processing operations may be performed on one or more of the high k dielectric materials. For example, the processing operation may be performed after forming the pillar high k dielectric material (125) and before forming the cell high k dielectric material (130), or after forming both the pillar high k dielectric material (125) and the cell high k dielectric material (130). Using different high-k dielectric materials for each of the pillar high-k dielectric material (125) and cell high-k dielectric material (130) also makes it possible to adjust the electrical properties of the electronic device.

[0064] After forming the cell high k dielectric material (130), a conductive material (115) can be formed within the remaining portion of the openings (685') to form an electronic structure (100) (see FIG. 1b). The conductive material (115) can be formed by conventional techniques. The conductive material (115) can substantially fill the remaining portion of the openings (685'). Accordingly, the cell high k dielectric material (130) and the conductive material (115) substantially fill the openings (685) formed following the removal of the nitride materials (675). The conductive material (115) has a substantially rectangular cross-sectional shape.

[0065] By including high-k dielectric materials (125, 130) within the pillar region (170) and within the cell region (165) of the electronic structure (100) according to embodiments of the present disclosure, the amount of conductive material (115) within the openings (685') can be increased compared to the amount of conductive material present in conventional structures in which the high-k dielectric material is present only within the cell region. Accordingly, the electronic structure (100) according to embodiments of the present disclosure provides additional space for the conductive material (115) without negatively affecting the electrical performance properties of the electronic device including the electronic structure (100). Since the high-k dielectric materials (125, 130) are formed individually within different regions of the electronic structure (100), the formation of the high-k dielectric materials (125, 130) can be easily integrated into the formation of the electronic structure (100).

[0066] During the manufacture of the electronic structure (100), one or more of the cell high-k dielectric material (130) and the pillar high-k dielectric material (125) may optionally undergo one or more processing operations. The processing operations may include, but are not limited to, annealing operations that increase the density of the high-k dielectric materials (125, 130), crystallize, oxidize, provide interfacial properties, or change other properties. Only as examples, the cell high-k dielectric material (130) and the pillar high-k dielectric material (125) may undergo an inert annealing operation, a peripheral annealing operation, a radical-based annealing operation, etc. The pillar high-k dielectric material (125) may optionally undergo a processing operation after forming the pillar high-k dielectric material (125) and before forming the cell high-k dielectric material (130). Alternatively, both the pillar high k dielectric material (125) and the cell high k dielectric material (130) may undergo a processing operation as an option, for example, after forming each of the pillar high k dielectric material (125) and the cell high k dielectric material (130), or after forming both the pillar high k dielectric material (125) and the cell high k dielectric material (130). Alternatively, only the cell high k dielectric material (130) may undergo a processing operation(s) as an option, for example, after forming the cell high k dielectric material (130). Since the processing operations can be performed at various stages in the manufacturing process, there is a larger process window for forming an electronic structure (100) comprising the high k dielectric materials (125, 130) according to the embodiments of the present disclosure.Additionally, since processing operations can be performed from the cell region (165) (when the cell high k dielectric material (130) is exposed) or from the pillar region (170) (when the pillar high k dielectric material (125) is exposed), forming an electronic structure (100) comprising high k dielectric materials (125, 130) according to embodiments of the present disclosure can be easily integrated with conventional process flows.

[0067] The electronic structure (100') may be formed as illustrated in FIGS. 6a through 6d and FIGS. 7a and 7b. The stacks (105), etching stop material (120), pillar high k dielectric material (125), charge blocking material (135), storage node material (140), tunnel dielectric material (110), and openings (685) are formed as described above and illustrated in FIGS. 6a through 6d. The etching stop material (120) may be one of the aforementioned materials, except that it is not silicon oxide or silicon nitride. The material for the etching stop material (120) may be optionally etchable with respect to the dielectric material (110) and pillar high k dielectric material (125), such as silicon, metal, silicon oxycarbide, or silicon carbonitride. As illustrated in FIG. 7a, a portion of the etching stop material (120) may be removed to form recesses (790) laterally adjacent to the dielectric material (110). The length of the etching stop material (120') after the formation of the recesses (790) may be smaller than the initial length of the etching stop material (120). The recesses (790) within the etching stop material (120') may be formed using conventional etching chemicals and etching conditions. The etching chemicals and etching conditions may be selected according to the material used as the etching stop material (120). The dimensions of the recesses (790) may be selected by appropriately selecting the etching chemicals and etching conditions. The dimensions of the recesses (790) may be about 1 nm to about 10 nm, for example, about 1 nm to about 4 nm or about 1 nm to about 3 nm. By increasing the dimensions of the recesses (790), the range (e.g., degree) of junction between the high k dielectric materials (125, 130) may be reduced. Parts of the etching stop material (120') remain adjacent to the dielectric material (110) and the pillar high k dielectric material (125) (e.g., adjacent laterally).The profile of the recesses (790) within the etching stop material (120') determines the shape of the resulting gate formed from the conductive material (115).

[0068] A cell high k dielectric material (130') may be formed adjacent to (e.g., above) the dielectric material (110), the pillar high k dielectric material (125), and the recesses (790), as illustrated in FIG. 7b. The cell high k dielectric material (130') may be formed equilaterally as described above and as illustrated in FIG. 6f, except that the cell high k dielectric material (130') is also formed equilaterally within the recesses (790). Accordingly, the cell high k dielectric material (130') is formed on the exposed horizontal surfaces of the dielectric material (110), on the exposed vertical surfaces of the pillar high k dielectric material (125), and within the recesses (790). The cell high k dielectric material (130') may be formed, for example, by ALD. Accordingly, the cell high k dielectric material (130') comes into direct contact with the dielectric material (110), the pillar high k dielectric material (125), and the etching stop material (120'). One or more of the cell high k dielectric material (130') and the pillar high k dielectric material (125) may optionally undergo one or more processing operations as described above.

[0069] A conductive material (115) can be formed on the cell high k dielectric material (130') and within the openings (685') as described above to form the electronic structure (100') of FIG. 2B. The conductive material (115) can substantially fill the remaining portion of the openings (685') and can be formed by conventional techniques. Accordingly, the cell high k dielectric material (130') and the conductive material (115) substantially fill the openings (685'). After forming the conductive material (115) within the openings (685), the cell high k dielectric material (130') comes into direct contact with the pillar high k dielectric material (125) and the conductive material (115) along the vertical surfaces of the pillar high k dielectric material (125). The substantially rectangular resulting shape of the conductive material (115) is defined by the shape of the recesses (790) and the openings (685'). The conductive material (115) can be formed by conventional techniques and can substantially fill the remaining portion of the openings (685'). A portion of the cell high-k dielectric material (130') adjacent to the pillar high-k dielectric material (125) protrudes above and below the conductive material (115). The protruding portions of the cell high-k dielectric material (130') are in direct contact with the dielectric material (110) and the pillar high-k dielectric material (125). Since the cell high-k dielectric material (130') protrudes above and below the conductive material (115), the upper surface of the protruding portions of the cell high-k dielectric material (130') is not in the same plane as the upper surface of the cell high-k dielectric material (130') on the upper horizontal surface of the conductive material (115), and the lower surface of the protruding portions of the cell high-k dielectric material (130') is not in the same plane as the lower surface of the cell high-k dielectric material (130') on the lower horizontal surface of the conductive material (115).

[0070] The electronic structure (100'') may be formed as illustrated in FIGS. 6a through 6d and FIGS. 8a through 8c. Stacks (105), etching stop material (120), pillar high k dielectric material (125), charge blocking material (135), storage node material (140), tunnel dielectric material (110), pillar openings (680), and openings (685) are formed as described above and illustrated in FIGS. 6a through 6d. The etching stop material (120) may be one of the aforementioned materials, except that it is not silicon oxide or silicon nitride. The material for the etching stop material (120) may be optionally etchable with respect to the dielectric material (110) and pillar high k dielectric material (125), such as silicon, metal, silicon oxycarbide, or silicon carbonitride. As illustrated in FIG. 8a, recesses (790) can be formed by removing a portion of the etching stop material (120). The recesses (790) are as described above in relation to FIG. 7a. After forming the recesses (790), a portion of the dielectric material (110) can be removed by conventional techniques. As illustrated in FIG. 8b, a portion of the dielectric material (110) adjacent laterally to the upper and lower surfaces of the etching stop material (120) can be removed, thereby increasing the size of the recesses (790') and openings (685') adjacent to the etching stop material (120) and the pillar high-k dielectric material (125). The resulting shape of the dielectric material (110'') may include rounded surfaces proximal to the etching stop material (120'') and the pillar high-k dielectric material (125). Cell high k dielectric material (130'') and conductive material (115'') can be formed within the openings (685) and within the recesses (790) to form an electronic structure (100'') as shown in FIG. 8c and FIG. 3b.The shape of the dielectric material (110'') affects the resulting shape of the cell high dielectric material (130'') and the conductive material (115'') of the electronic structure (100'').

[0071] Alternatively, the electronic structure (100'') can be formed starting with stacks (105) having a dielectric material (110) with a greater thickness than the nitride materials (675). The electronic structure (100'') can be formed as illustrated in FIGS. 6a through 6d and FIG. 7a, except that the dielectric material (110) has a greater width than the nitride material (675). In other words, the dielectric materials (110) and the nitride material (675) of the stacks (105) exhibit different widths relative to each other, rather than being substantially the same widths as illustrated in FIGS. 6a through 6d and FIG. 7a. The stacks (105), etching stop material (120), pillar high k dielectric material (125), charge blocking material (135), storage node material (140), tunnel dielectric material (110), and pillar openings (680) are formed as described above and illustrated in FIGS. 6a through 6d. The etching stop material (120) may be any of the aforementioned materials, except that the etching stop material (120) is not silicon oxide or silicon nitride. The recesses (790) within the etching stop material (120) may be formed as described above and illustrated in FIG. 7a. After forming the recesses (790), a portion of the dielectric material (110) adjacent to the pillar high k dielectric materials (125) is removed to increase the size of the openings (685) adjacent to the pillar high k dielectric material (125). The dielectric materials (110) can be removed by conventional techniques. The resulting shape of the dielectric materials (110'') may include rounded surfaces proximal to the filament high dielectric material (125), similar to that shown in FIG. 8b.Cell high k dielectric material (130'') and conductive material (115'') can be formed within the openings (685) and within the recesses (790) to produce an electronic structure similar to the electronic structure (100'') shown in FIG. 3b, except that the dielectric materials (110'') and conductive materials (115'') of the stacks (105) have different widths.

[0072] The electronic structure (100''') may be formed as illustrated in FIGS. 6a to 6d and FIGS. 9a to 9c. The stacks (105), etching stop material (120), pillar high-k dielectric material (125), charge blocking material (135), storage node material (140), tunnel dielectric material (110), and pillar openings (680) are formed as described above and illustrated in FIGS. 6a to 6d, except that the etching stop material (120) has a greater thickness W2 than in FIGS. 6a to 6d. The etching stop material (120) may be one of the aforementioned materials, except that it is not silicon oxide or silicon nitride. The material for the etching stop material (120) may be selectively etchable with respect to the dielectric material (110) and the pillar high-k dielectric material (125), such as silicon, metal, silicon oxycarbide, or silicon carbonitride. As shown in FIG. 9a, recesses (790) may be formed by removing a portion of the etching stop material (120). The recesses (790) are as described above in relation to FIG. 7a. A portion of the dielectric material (110) adjacent to the pillar high-k dielectric materials (125) may be removed by conventional techniques. As illustrated in FIG. 9b, a portion of the dielectric material (110) adjacent laterally to the end surfaces of the etching stop material (120') can be removed, thereby increasing the size of the recesses (790) and openings (685) adjacent to the etching stop material (120''') and the pillar high k dielectric material (125). The resulting shape of the dielectric material (110''') may include rounded surfaces proximal to the etching stop material (120''') and the pillar high k dielectric material (125). The cell high k dielectric material (130''') and the conductive material (115''') can be formed within the openings (685) and within the recesses (790) to form an electronic structure (100''') as illustrated in FIG. 9c and FIG. 4b.

[0073] Accordingly, a method for forming a semiconductor device is disclosed. The method comprises the step of forming stacks of alternating dielectric materials and nitride materials. A pillar high-k dielectric material is formed adjacent to the alternating dielectric materials and nitride materials. A charge blocking material, a nitride material, a tunnel dielectric material, and a channel material are formed adjacent to the pillar high-k dielectric material, and an insulating material is formed adjacent to the channel material. The nitride materials are removed to form openings between the dielectric materials, and cell high-k dielectric materials are formed within the openings. A portion of the cell high-k dielectric material is connected to a portion of the pillar high-k dielectric material. A conductive material is formed within the openings to form stacks of alternating dielectric materials and conductive materials.

[0074] One or more of the electronic structures (100, 100', 100'', 100''', 100A, 100A', 100A'', 100B, 100B', 100B'') according to embodiments of the present disclosure may exist within an electronic device that may include, but is not limited to, a 3D NAND flash memory device. The electronic device may exist within a memory array (1000), as schematically illustrated in FIG. 10. The memory array (1000) includes a memory array (1002) of memory cells and a control logic component (1004). Electronic structures (100, 100', 100'', 100''', 100A, 100A', 100A'', 100B, 100B', 100B'') according to embodiments of the present disclosure include a plurality of memory cells. A control logic component (1004) may be configured to operably interact with a memory array (1002) of memory cells to read, write, or refresh any or all memory cells within the memory array (1002) of memory cells. Memory cells of the memory array (1000) are coupled to access lines (e.g., conductive materials (115, 115'', 115''')), and the access lines are coupled to control gates of the memory cells. A string of memory cells of the memory array (1000) is coupled serially between a source line and a data line (e.g., a bit line). Memory cells are positioned between access lines and data lines. Access lines may make electrical contact with, for example, conductive materials (115', 115'', 115''') of stacks (105), and data lines may make electrical contact with electrodes (e.g., top electrodes) of stacks (105). Data lines may be placed directly over rows or columns of memory cells and may make contact with their top electrodes. Each of the access lines may extend in a first direction and may connect rows of memory cells.Each of the data lines may extend in a second direction that is at least substantially perpendicular to the first direction and may connect columns of memory cells. The voltage applied to the access lines and data lines may be controlled so that an electric field can be selectively applied at the intersection of at least one access line and at least one bit line, thereby allowing the memory cells to be selectively operated. Additional process operations for forming a memory array (1000) comprising electronic structures (100, 100', 100'', 100''', 100A, 100A', 100A'', 100B, 100B', 100B'') are performed by the prior art.

[0075] Accordingly, an electronic device is disclosed. The electronic device comprises an array of memory cells, wherein the memory cells comprise stacks of alternating dielectric materials and conductive materials within a cell region of the electronic device, and a pillar high-k dielectric material adjacent to the stacks within a pillar region of the electronic device. An interlayer poly-dielectric structure and a channel material are adjacent to the pillar high-k dielectric material. The cell high-k dielectric material surrounds the conductive materials within the cell region, and a portion of the cell high-k dielectric material is connected to a portion of the pillar high-k dielectric material. Access lines and bit lines are electrically coupled to the memory cells.

[0076] As illustrated in FIG. 11, a system (1100) is also disclosed, which includes one or more electronic structures (100, 100', 100'', 100''', 100A, 100A', 100A'', 100B, 100B', 100B'') according to embodiments of the present disclosure. FIG. 11 is a simplified block diagram of a system (1100) implemented according to one or more embodiments described herein. The system (1100) may include, for example, a computer or computer hardware component, a server or other networking hardware component, a mobile phone, a digital camera, a personal information terminal (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as an iPad® or SURFACE® tablet, an e-book, a navigation device, etc. The system (1100) includes at least one memory device (1102), which includes electronic structures (100, 100', 100'', 100''', 100A, 100A', 100A'', 100B, 100B', 100B'') as described above. The system (1100) may further include at least one processor (1104), such as a microprocessor, to control the processing of system functions and requests in the system (1100). The processor (1104) and other subcomponents of the system (1100) may include memory cells. The processor (1104) may optionally include one or more memory arrays (1000) as described above.

[0077] Depending on the functions performed by the system (1100), various other devices may be coupled to the processor (1104). For example, an input device (1106) may be coupled to the processor (1104) to input information into the electronic system (1100) by a user, such as, for example, a mouse or other pointing device, a button, a switch, a keyboard, a touchpad, a light pen, a digitizer and stylus, a touch screen, a voice recognition system, a microphone, a control panel, or a combination thereof. An output device (1108) for outputting information (e.g., visual or audio output) to a user may also be coupled to the processor (1104). The output device (1108) may include an LCD display, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a 3D projection, an audio display, or a combination thereof. The output device (1108) may also include a printer, an audio output jack, a speaker, etc. In some embodiments, the input device (1106) and the output device (1108) may include a single touchscreen device that can be used to input information into the electronic system (1100) and output visual information to a user. One or more input devices (1106) and output devices (1108) may electrically communicate with at least one of a memory device (1102) and a processor device (1104). At least one memory device (1102) and a processor device (1104) may also be used in a system on chip (SoC).

[0078] Accordingly, a system is disclosed. The system comprises a processor operably coupled to an input device and an output device, and an electronic device operably coupled to the processor. The electronic device comprises memory cells, and one or more of the memory cells comprise stacks of alternating dielectric materials and conductive materials within a cell region of the electronic device. A pillar high-k dielectric material, an interlayer poly-dielectric structure, and a channel material are adjacent to the stacks within the pillar region of the electronic device. A cell high-k dielectric material is within the cell region, and a portion of the cell high-k dielectric material is adjacent to a portion of the pillar high-k dielectric material.

[0079] Additional non-limiting exemplary embodiments of the present disclosure are presented below.

[0080] Example 1. As an electronic structure, stacks comprising alternating dielectric materials and conductive materials within the cell regions of the electronic structure;

[0081] Pillar high k dielectric material adjacent to stacks and within the pillar region of the electronic structure;

[0082] Charge blocking material, nitride material, tunnel dielectric material, and channel material adjacent to the pillar of the high-k dielectric material within the pillar region of the electronic structure; and

[0083] An electronic structure comprising a cell high-k dielectric material that surrounds conductive materials within a cell region of the electronic structure and is connected to a portion of a pillar of the high-k dielectric material.

[0084] Example 2. The electronic structure in Example 1, wherein the pillar high k dielectric material and the cell high k dielectric material separate the stacks from the channel material.

[0085] Example 3. An electronic structure in which, in Example 1 or Example 2, the total thickness of the pillar high k dielectric material and the cell high k dielectric material is about 2 nm to about 20 nm.

[0086] Example 4. An electronic structure in which, in any one of Examples 1-3, the connecting pillar high k dielectric material and cell high k dielectric material are adjacent to the conductive materials of the stacks.

[0087] Example 5. An electronic structure in which, in any one of Examples 1-4, the pillar high k dielectric material is close to the dielectric materials of the stacks and the conductive materials of the stacks.

[0088] Example 6. An electronic structure in any one of Examples 1-5, wherein the cell high k dielectric material is not in close proximity to the vertical surfaces of the dielectric materials of the stacks.

[0089] Example 7. An electronic structure comprising, in any one of Examples 1-6, an etching stop material between the dielectric materials of the stacks and the pillar high-k dielectric material.

[0090] Example 8. An electronic structure in any one of Examples 1-7, wherein the length of the pillar high k dielectric material is substantially in line with the length of the stacks.

[0091] Example 9. An electronic structure in any one of Examples 1-8, wherein the Phila High k dielectric material and the Cell High k dielectric material comprise materials of different chemical compositions.

[0092] Example 10. An electronic structure in which, in any one of Examples 1-9, the Phila High K dielectric material and the Cell High K dielectric material have the same chemical composition.

[0093] Example 11. An electronic structure in which, in any one of Examples 1-10, the surfaces of the cell high k dielectric material are substantially planar.

[0094] Example 12. An electronic structure in any one of Examples 1-11, wherein a portion of the cell high-k dielectric material connected to the pillar high-k dielectric material protrudes above the upper horizontal surface of the conductive materials of the stacks and protrudes below the lower horizontal surface of the conductive materials of the stacks.

[0095] Example 13. An electronic structure in any one of Examples 1-11, wherein a portion of the cell high-k dielectric material connected to the pillar high-k dielectric material protrudes above the upper horizontal surface of the cell high-k dielectric material and protrudes below the lower horizontal surface of the cell high-k dielectric material.

[0096] Example 14. An electronic structure in any one of Examples 1-11, wherein a portion of the conductive material of the stacks adjacent to the pillar region protrudes above the upper horizontal surface of the conductive material of the stacks and protrudes below the lower horizontal surface of the conductive material of the stacks.

[0097] Example 15. An electronic structure in which, in any one of Examples 1-14, the conductive materials of the stacks substantially comprise a rectangular cross-sectional shape.

[0098] Example 16. An electronic structure in any one of Examples 1-14, wherein the conductive materials of the stacks comprise a rounded cross-sectional shape proximal to the pillar region.

[0099] Example 17. An electronic structure in any one of Examples 1-14, wherein the conductive materials of the stacks and the cell high-k dielectric material comprise a rounded cross-sectional shape proximal to the pillar region.

[0100] Example 18. An electronic structure in which, in any one of Examples 1-17, the conductive materials of the stacks exhibit a greater width at the proximal end of the pillar high k dielectric material than at the distal end of the pillar high k dielectric material.

[0101] Example 19. An electronic structure comprising: stacks of conductive materials adjacent to each other and separated by air gaps — the stacks are located within the cell region of the electronic structure —; a cell high k dielectric material surrounding the conductive materials within the cell region; a pillar high k dielectric material adjacent to the stacks and connected to a portion of the cell high k dielectric material — the pillar high k dielectric material is located within the pillar region of the electronic structure —; and a charge blocking material, a nitride material, a tunnel dielectric material, and a channel material adjacent to the pillar high k dielectric material and located within the pillar region.

[0102] Example 20. An electronic structure in which the conductive materials of the stacks in Example 19 are adjacent perpendicular to each other.

[0103] Example 21. An electronic structure in which the pillar high k dielectric material of Example 19 or Example 20 is laterally adjacent to the stacks.

[0104] Example 22. An electronic structure in which, in any one of Examples 19-21, the cell high k dielectric material is laterally adjacent to the conductive materials of the stacks.

[0105] Example 23. An electronic structure comprising, in any one of Examples 19-22, further comprising storage nodes adjacent to air gaps.

[0106] Example 24. A method for forming an electronic device, comprising: forming stacks of alternating dielectric materials and nitride materials; forming a pillar high k dielectric material adjacent to the alternating dielectric materials and nitride materials; forming a charge blocking material, a nitride material, a tunnel dielectric material, and a channel material adjacent to the pillar high k dielectric material; forming an insulating material adjacent to the channel material; removing the nitride materials to form openings between the dielectric materials; forming a cell high k dielectric material within the openings — wherein a portion of the cell high k dielectric material is connected to a portion of the pillar high k dielectric material —; and forming a conductive material within the openings to form stacks of alternating dielectric materials and conductive materials.

[0107] Example 25. The method of Example 24, wherein the step of forming a conductive material within the openings to form stacks of alternating dielectric materials and conductive materials comprises the step of forming the conductive materials of the stacks having a substantially rectangular cross-sectional shape.

[0108] Example 26. A method in Example 24 or Example 25, further comprising the step of forming an etching stop material adjacent to stacks of alternating dielectric materials and nitride materials before forming a pillar high-k dielectric material adjacent to alternating dielectric materials and nitride materials.

[0109] Example 27. The method of Example 26, further comprising the step of removing a portion of the etching stop material to form recesses adjacent to the dielectric materials.

[0110] Example 28. A method in any one of Examples 24-27, wherein the step of forming a cell high k dielectric material in the openings comprises the step of forming a cell high k dielectric material in the openings and in the recesses.

[0111] Example 29. A method in any one of Examples 24-28, wherein the step of forming a conductive material in the openings to form stacks of alternating dielectric materials and conductive materials comprises the step of forming a conductive material in the openings and in the recesses.

[0112] Example 30. The method of Example 24, wherein the step of forming a conductive material in the openings and in the recesses comprises the step of forming a conductive material of stacks having a rounded cross-sectional shape proximal to the pillar high k dielectric material.

[0113] Example 31. An electronic device comprising an array of memory cells ― memory cells comprising: stacks of alternating dielectric materials and conductive materials within a cell region of the electronic device; a pillar high-k dielectric material adjacent to the stacks and within a pillar region of the electronic device; an interlayer poly-dielectric structure and channel material adjacent to the pillar high-k dielectric material; and a cell high-k dielectric material surrounding conductive materials within the cell region, and a portion of the cell high-k dielectric material adjacent to a portion of the pillar high-k dielectric material ―; and access lines and bit lines electrically coupled to the memory cells.

[0114] Example 32. A system comprising: a processor operably coupled to an input device and an output device; and an electronic device operably coupled to the processor ―the electronic device comprises memory cells, wherein one or more of the memory cells comprise: stacks of alternating dielectric materials and conductive materials within a cell region of the electronic device; a pillar high-k dielectric material, an interlayer poly-dielectric structure, and a channel material adjacent to the stacks and within a pillar region of the electronic device; and a cell high-k dielectric material within the cell region, and a portion of the cell high-k dielectric material adjacent to a portion of the pillar high-k dielectric material ―.

[0115] Although specific exemplary embodiments have been described in connection with the drawings, those skilled in the art will recognize and understand that the embodiments covered by this disclosure are not limited to those explicitly shown and described herein. More precisely, many additions, deletions, and modifications to the embodiments described herein may be made without departing from the scope of the embodiments covered by this disclosure, such as those claimed below, including legal equivalents. Furthermore, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being covered within the scope of this disclosure.

Claims

Claim 1 An electronic structure comprising: stacks including alternating dielectric materials and conductive materials within a cell region of the electronic structure; a pillar high-k dielectric material adjacent to the stacks and extending through a pillar region of the electronic structure; a charge blocking material, a nitride material, a tunnel dielectric material, and a channel material adjacent to the pillar high-k dielectric material within the pillar region of the electronic structure and extending through the pillar region; and a cell high-k dielectric material surrounding the conductive materials within the cell region of the electronic structure and connected to a portion of the pillar high-k dielectric material within the pillar region. Claim 2 An electronic structure according to claim 1, wherein the pillar high k dielectric material and the cell high k dielectric material separate the stacks from the channel material. Claim 3 An electronic structure according to claim 1, wherein the total thickness of the Phila High k dielectric material and the Cell High k dielectric material is about 2 nm to about 20 nm. Claim 4 An electronic structure according to claim 1, wherein the adjacent pillar high k dielectric material and the cell high k dielectric material are adjacent to the conductive materials of the stacks. Claim 5 In claim 1, the above-mentioned pillar high k dielectric material is an electronic structure that is close to the dielectric materials of the stacks and the conductive materials of the stacks. Claim 6 In paragraph 5, the cell high k dielectric material is an electronic structure that does not approach the vertical surfaces of the dielectric materials of the stacks. Claim 7 An electronic structure according to any one of claims 1 to 6, further comprising an etching stop material between the dielectric materials of the stacks and the pillar high-k dielectric material. Claim 8 An electronic structure according to claim 1, wherein the length of the above-mentioned pillar high k dielectric material is substantially coextensive with the length of the above-mentioned stacks. Claim 9 An electronic structure according to claim 1, wherein the above-mentioned Phila High K dielectric material and the above-mentioned Cell High K dielectric material comprise materials of different chemical compositions. Claim 10 An electronic structure according to claim 1, wherein the Phila High K dielectric material and the Cell High K dielectric material have the same chemical composition. Claim 11 An electronic structure according to claim 1, wherein the surfaces of the cell high k dielectric material are substantially planar. Claim 12 An electronic structure according to claim 1, wherein a portion of the cell high k dielectric material adjacent to the pillar high k dielectric material protrudes above the upper horizontal surface of the conductive materials of the stacks and protrudes below the lower horizontal surface of the conductive materials of the stacks. Claim 13 An electronic structure according to claim 1, wherein a portion of the cell high k dielectric material connected to the pillar high k dielectric material protrudes above the upper horizontal surface of the cell high k dielectric material and protrudes below the lower horizontal surface of the cell high k dielectric material. Claim 14 An electronic structure according to claim 1, wherein a portion of the conductive materials of the stacks adjacent to the pillar region protrudes above the upper horizontal surface of the conductive materials of the stacks and protrudes below the lower horizontal surface of the conductive materials of the stacks. Claim 15 An electronic structure according to claim 1, wherein the conductive materials of the stacks substantially comprise a rectangular cross-sectional shape. Claim 16 An electronic structure according to claim 1, wherein the conductive materials of the stacks include a rounded cross-sectional shape proximal to the pillar region. Claim 17 An electronic structure according to claim 1, wherein the conductive materials of the stacks and the cell high-k dielectric material comprise a round cross-sectional shape proximal to the pillar region. Claim 18 An electronic structure according to claim 1, wherein the conductive materials of the stacks exhibit a greater width at the proximal end of the pillar high k dielectric material than at the distal end of the pillar high k dielectric material. Claim 19 An electronic structure comprising: stacks of conductive materials adjacent to each other and separated by air gaps ― said stacks are located within a cell region of the electronic structure ―; a cell high k dielectric material surrounding said conductive materials within the cell region; a pillar high k dielectric material adjacent to a portion of the cell high k dielectric material extending through said stacks within a pillar region of the electronic structure ― said cell high k dielectric material has a greater width at the proximal end of the pillar high k dielectric material than at the distal end of the pillar high k dielectric material ―; and a charge blocking material, a nitride material, a tunnel dielectric material, and a channel material adjacent to said pillar high k dielectric material and extending through said pillar region. Claim 20 In paragraph 19, the electronic structure wherein the conductive materials of the stacks are adjacent to each other perpendicularly. Claim 21 In claim 19, the above-mentioned pillar high k dielectric material is an electronic structure that is laterally adjacent to the stacks. Claim 22 In claim 19, the cell high k dielectric material is an electronic structure that is laterally adjacent to the conductive materials of the stacks. Claim 23 An electronic structure according to any one of claims 19 to 22, further comprising storage nodes adjacent to the air gaps. Claim 24 A method for forming an electronic device comprising: forming stacks of alternating dielectric materials and nitride materials; forming a pillar high k dielectric material adjacent to the alternating dielectric materials and nitride materials and extending through the stacks; forming a charge blocking material, a nitride material, a tunnel dielectric material, and a channel material extending through the stacks and adjacent to the pillar high k dielectric material; forming an insulating material extending through the stacks and adjacent to the channel material; removing the nitride materials to form openings between the dielectric materials; forming a cell high k dielectric material within the openings ― wherein a portion of the cell high k dielectric material is connected to a portion of the pillar high k dielectric material ―; and forming a conductive material within the openings to form stacks of alternating dielectric materials and conductive materials. Claim 25 In claim 24, the step of forming a conductive material within the openings to form stacks of alternating dielectric materials and conductive materials comprises the step of forming the conductive materials of the stacks having a substantially rectangular cross-sectional shape. Claim 26 A method according to claim 24, further comprising the step of forming an etching stop material adjacent to and extending through the stacks of the alternating dielectric materials and nitride materials before forming the pillar high-k dielectric material adjacent to the alternating dielectric materials and nitride materials. Claim 27 A method according to claim 26, further comprising the step of removing a portion of the etching stop material to form recesses adjacent to the dielectric materials. Claim 28 A method according to claim 27, wherein the step of forming a cell high k dielectric material within the openings comprises the step of forming the cell high k dielectric material within the openings and within the recesses. Claim 29 A method according to claim 27, wherein the step of forming a conductive material within the openings to form stacks of alternating dielectric materials and conductive materials comprises the step of forming the conductive material within the openings and within the recesses. Claim 30 In claim 29, the step of forming the conductive material within the openings and within the recesses comprises the step of forming the conductive material of the stacks having a rounded cross-sectional shape proximal to the pillar high k dielectric material. Claim 31 As an electronic device, an array of memory cells ― said memory cells: stacks of alternating dielectric materials and conductive materials within a cell region of said electronic device; a pillar high-k dielectric material adjacent to said stacks and extending through a pillar region of said electronic device; an interlayer poly-dielectric structure and channel material extending through the pillar region and adjacent to said pillar high-k dielectric material; a cell high-k dielectric material surrounding said conductive materials within said cell region; and a portion of said pillar high-k dielectric material connected to under An electronic device comprising: a portion of the cell high-k dielectric material protruding above the upper horizontal surface and below the lower horizontal surface of the conductive materials; and access lines and bit lines electrically coupled to the memory cells. Claim 32 A system comprising: a processor operably coupled to an input device and an output device; and an electronic device operably coupled to the processor, wherein the electronic device comprises memory cells, and one or more of the memory cells comprise: stacks of alternating dielectric materials and conductive materials within a cell region of the electronic device; a pillar high-k dielectric material, an interlayer poly-dielectric structure, and a channel material adjacent to the stacks and extending through a pillar region of the electronic device; and a cell high-k dielectric material within the cell region, and a portion of the cell high-k dielectric material within the cell region adjacent to a portion of the pillar high-k dielectric material within the pillar region.

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