Interposer and electronic device including the same

Abstract

An electronic device is disclosed. The electronic device comprises: a housing; a first substrate and a second substrate disposed within the housing and disposed to face each other in a first direction; and an interposer extending to surround an internal space between the first substrate and the second substrate, electrically connecting the first substrate and the second substrate, and including vias extending in the first direction, wherein the interposer comprises a first portion forming an outer surface and a second portion forming an inner surface facing the internal space and surrounded by the first portion, and wherein the first portion is configured to shield the second portion and the internal space; wherein the vias included in the first portion are all ground vias and are spaced apart from each other by a first interval, and the vias included in the second portion may include signal vias and a number of ground vias smaller than the number of signal vias and be spaced apart from each other by a second interval greater than or equal to the first interval. In addition to this, various embodiments as identified from the specification are possible.

Description

Technology Field

[0001] The embodiments disclosed in this document relate to an interposer and an electronic device including the same. Background Technology

[0002] As the functions integrated into electronic devices become increasingly diverse, the clock frequencies of electrical components are rising and data transmission speeds are accelerating. Electrical components operating at high frequencies can cause electromagnetic interference (EMI) or lead to problems caused by electrostatic discharge (ESD). This can result in malfunctions of electronic devices or lead to issues with RF immunity.

[0003] An electronic device may include two or more substrates on which electrical components are mounted. The two or more substrates may be arranged to overlap each other. The electronic device may include an interposer for electrically connecting the two or more substrates. The interposer may be provided to surround the facing regions of each of the two substrates. The interposer may be configured to electrically connect the circuits contained in each and to shield the regions surrounded by the interposer. The problem to be solved

[0004] According to the embodiments disclosed in this document, we intend to provide an interposer that improves shielding performance by utilizing some vias without including a separate side plating area, and an electronic device including the same. means of solving the problem

[0005] An electronic device according to one embodiment disclosed in this document comprises: a housing; a first substrate and a second substrate disposed inside the housing and disposed to face each other in a first direction; and an interposer extending to surround an internal space between the first substrate and the second substrate, electrically connecting the first substrate and the second substrate, and including vias extending in the first direction, wherein the interposer includes a first portion forming an outer surface and a second portion forming an inner surface facing the internal space and surrounded by the first portion, and the first portion is configured to shield the second portion and the internal space; wherein the vias included in the first portion are all ground vias and are spaced apart from each other by a first interval, and the vias included in the second portion include signal vias and a number of ground vias smaller than the number of signal vias and may be spaced apart from each other by a second interval greater than or equal to the first interval. Effects of the invention

[0006] The interposer according to the embodiments disclosed in this document can be manufactured without a separate plating process, thereby reducing production costs. In addition, the interposer can provide improved shielding performance by including a fence structure containing vias. Furthermore, various effects that can be identified directly or indirectly through this document may be provided. Brief explanation of the drawing

[0007] FIG. 1 is a front perspective view of an electronic device according to one embodiment. FIG. 2 is a rear perspective view of an electronic device according to one embodiment. FIG. 3 is an exploded perspective view of an electronic device according to one embodiment. FIG. 4 is a drawing illustrating an electronic device according to one embodiment. FIG. 5 is a drawing illustrating an interposer of an electronic device according to one embodiment. FIG. 6 is a plan view of an interposer according to one embodiment. FIG. 7a is a cross-sectional view of an interposer according to one embodiment. FIG. 7b is a cross-sectional view of an interposer according to one embodiment. FIG. 8 is a plan view of an interposer according to one embodiment. FIG. 9a is a cross-sectional view of a second structure of an interposer according to one embodiment. FIG. 9b is a cross-sectional view of a third structure of an interposer according to one embodiment. FIG. 10 is a plan view of an interposer according to one embodiment. FIG. 11a is a cross-sectional view of a first part of an interposer according to one embodiment. FIG. 11b is a cross-sectional view of a first part of an interposer according to one embodiment. FIG. 12a is a drawing showing a portion of the surface of a first part of an interposer according to various embodiments. FIG. 12b is a drawing showing a portion of the surface of a first part of an interposer according to various embodiments. FIG. 13a is a drawing showing a portion of the surface of a first part of an interposer according to various embodiments. FIG. 13b is a drawing showing a portion of the surface of a first part of an interposer according to various embodiments. FIG. 13c is a drawing showing a portion of the surface of a first part of an interposer according to various embodiments. FIG. 14a is a drawing showing a portion of the surface of a first part of an interposer according to various embodiments. FIG. 14b is a drawing showing a portion of the surface of a first part of an interposer according to various embodiments. FIG. 15 is a drawing illustrating an interposer according to various embodiments. FIGS. 16a, FIGS. 16b, and FIGS. 16c are drawings illustrating the arrangement of ground vias according to various embodiments. FIG. 17 is a block diagram of an electronic device in a network environment according to various embodiments. In relation to the description of the drawings, the same or similar reference numerals may be used for identical or similar components. Specific details for implementing the invention

[0008] Hereinafter, various embodiments of the present invention are described with reference to the accompanying drawings. However, this is not intended to limit the present invention to specific embodiments and should be understood to include various modifications, equivalents, and / or alternatives of the embodiments of the present invention.

[0009] FIG. 1 is a front perspective view of an electronic device (100) according to one embodiment. FIG. 2 is a rear perspective view of an electronic device (100) according to one embodiment. FIG. 3 is an exploded perspective view of an electronic device (100) according to one embodiment.

[0010] Referring to FIGS. 1 and 2, the electronic device (100) may include a housing (110) comprising a first surface (or front) (110A), a second surface (or rear) (110B), and a side (110C) surrounding the space between the first surface (110A) and the second surface (110B).

[0011] In another embodiment (not shown), the housing (110) may refer to a structure forming some of the first surface (110A), the second surface (110B), and the side (110C).

[0012] In one embodiment, the first surface (110A) may be formed by a front plate (102) (e.g., the front plate (120) of FIG. 3) in which at least a portion is substantially transparent. The front plate (102) may comprise a glass plate or a polymer plate comprising various coating layers. In one embodiment, the second surface (110B) may be formed by a rear plate (111) (e.g., the rear plate (180) of FIG. 3) in which it is substantially opaque. The rear plate (111) may be formed by, for example, coated or colored glass, ceramic, polymer, metal (e.g., aluminum, stainless steel (STS), or magnesium), or a combination of at least two of the above materials. The side surface (110C) may be formed by a side bezel structure (118) comprising metal and / or polymer, which is combined with the front plate (102) and the rear plate (111).

[0013] In another embodiment, the rear plate (111) and the side bezel structure (118) may be formed integrally and may include the same material (e.g., a metallic material such as aluminum).

[0014] In the illustrated embodiment, the front plate (102) may include two first regions (110D) that are curved and seamlessly extended from a portion of the first surface (110A) toward the rear plate (111). The first regions (110D) may be located at both ends of the long edge of the front plate (102).

[0015] In the illustrated embodiment, the rear plate (111) may include two second regions (110E) that are curved and seamlessly extended from a portion of the second surface (110B) toward the front plate (102). The second regions (110E) may be included at both ends of the long edge of the rear plate (111).

[0016] In another embodiment, the front plate (102) (or rear plate (111)) may include only one of the first regions (110D) (or second regions (110E)). Also, in another embodiment, the front plate (102) (or rear plate (111)) may not include some of the first regions (110D) (or second regions (110E)).

[0017] In one embodiment, the side bezel structure (118) may have a first thickness (or width) in a side direction (e.g., short side) that does not include the first regions (110D) or second regions (110E) as described above when viewed from the side of the electronic device (100), and may have a second thickness that is thinner than the first thickness in a side direction (e.g., long side) that includes the first regions (110D) or second regions (110E).

[0018] In one embodiment, the electronic device (100) may include at least one of a display (101), an audio module (103, 104, 107), a sensor module (not shown), a camera module (105, 112), a key input device (117), a light-emitting element (not shown), and a connector hole (108). In another embodiment, the electronic device (100) may omit at least one of the components (e.g., a key input device (117) or a light-emitting element (not shown)) or additionally include other components.

[0019] In one embodiment, the display (101) may be exposed through at least a portion of the front plate (102). For example, at least a portion of the display (101) may be exposed through the front plate (102), which includes the first surface (110A) and the first area (110D) of the side (110C).

[0020] In one embodiment, the shape of the display (101) may be formed substantially identical to the adjacent outer shape of the front plate (102). In another embodiment (not shown), in order to expand the exposed area of ​​the display (101), the gap between the outer edge of the display (101) and the outer edge of the front plate (102) may be formed generally identical.

[0021] In one embodiment, the surface of the housing (110) (or the front plate (102)) may include a display area in which the display (101) is visually exposed and content is displayed through pixels. For example, the display area may include a first surface (110A) and a first area (110D) on the side.

[0022] In another embodiment (not shown), the display area (110A, 110D) may include a sensing area (not shown) configured to acquire the user's biometric information. Here, the meaning of "the display area (110A, 110D) includes a sensing area" can be understood as at least a portion of the sensing area being overlapped with the display area (110A, 110D). For example, the sensing area (not shown) may mean an area that can display content by the display (101) just like other areas of the display area (110A, 110D) and additionally acquire the user's biometric information (e.g., fingerprint).

[0023] In one embodiment, the display area (110A, 110D) of the display (101) may include a camera area (106). For example, the camera area (106) may be an area through which light reflected from a subject and received by the first camera module (105) passes. For example, the camera area (106) may include an area through which the optical axis of the first camera module (105) passes. Here, the meaning of "the display area (110A, 110D) includes the camera area (106)" can be understood as at least a portion of the camera area (106) being overlapped with the display area (110A, 110D). For example, the camera area (106) may display content by the display (101) just like other areas of the display area (110A, 110D).

[0024] In various embodiments (not shown), the screen display area (110A, 110D) of the display (101) may include an area where a first camera module (105) (e.g., a punch-hole camera) can be visually exposed. For example, at least a portion of the edge of the area where the first camera module (105) is exposed may be surrounded by the screen display area (110A, 110D). In one embodiment, the first camera module (105) may include a plurality of camera modules.

[0025] In one embodiment, the display (101) may include at least one of an audio module (103, 104, 107), a sensor module (not shown), a camera module (e.g., a first camera module (105)), and a light-emitting element (not shown) on the back surface of a screen display area (110A, 110D). For example, the electronic device (100) may be positioned such that a camera module (e.g., a first camera module (105)) faces the first surface (110A) and / or the side (110C) (e.g., at least one surface of the first area (110D)) on the back surface (e.g., a surface facing the -Z axis direction). For example, the first camera module (105) may not be visually exposed to the screen display area (110A, 110D) and may include a hidden under-display camera (UDC).

[0026] In another embodiment (not shown), the display (101) may include a touch detection circuit, a pressure sensor capable of measuring the intensity (pressure) of the touch, and / or a digitizer for detecting a magnetic field type stylus pen, or may be disposed adjacently.

[0027] In one embodiment, the audio module (103, 104, 107) may include a microphone hole (103, 104) and a speaker hole (107).

[0028] In one embodiment, the microphone holes (103, 104) may include a first microphone hole (103) formed in a part of the side (110C) and a microphone hole (104) formed in a part of the second surface (110B). The microphone holes (103, 104) may have a microphone placed inside the housing (110) to acquire external sound. The microphone may include a plurality of microphones to detect the direction of the sound. In one embodiment, the second microphone hole (104) formed in a part of the second surface (110B) may be placed adjacent to the camera module (105, 112). For example, the second microphone hole (104) may acquire sound when the camera module (105, 112) is running or when other functions are running.

[0029] In one embodiment, the speaker hole (107) may include a call receiver hole (not shown). The speaker hole (107) may be formed in a part of the side (110C) of the electronic device (100). In another embodiment, the speaker hole (107) may be implemented as a single hole with the microphone hole (103). Although not shown, the call receiver hole (not shown) may be formed in another part of the side (110C). For example, the call receiver hole (not shown) may be formed in another part of the side (110C) facing the part of the side (110C) where the speaker hole (107) is formed (e.g., the part facing the -Y-axis direction) (e.g., the part facing the +Y-axis direction).

[0030] In one embodiment, the electronic device (100) may include a speaker that is fluidly connected to a speaker hole (107). In another embodiment, the speaker may include a piezo speaker in which the speaker hole (107) is omitted.

[0031] In one embodiment, a sensor module (not shown) may generate an electrical signal or data value corresponding to an internal operating state of the electronic device (100) or an external environmental state. In one embodiment, a sensor module (not shown) may be placed on at least a portion of a first surface (110A), a second surface (110B), or a side (110C) of a housing (110) (e.g., first regions (110D) and / or the second regions (110E)), and may be placed on the back surface of a display (101) (e.g., a fingerprint sensor). For example, at least a portion of the sensor module (not shown) may be placed below the display area (110A, 110D) so as not to be visually exposed, and may form a sensing area (not shown) on at least a portion of the display area (110A, 110D). For example, the sensor module (not shown) may include an optical fingerprint sensor. In some embodiments (not shown), the fingerprint sensor may be placed on the first surface (110A) (e.g., screen display area (110A, 110D)) as well as the second surface (110B) of the housing (110). For example, the sensor module may include at least one of a proximity sensor, an HRM sensor, a fingerprint sensor, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0032] In one embodiment, the key input device (117) may be placed on the side (110C) of the housing (110) (e.g., first areas (110D) and / or second areas (110E)). In another embodiment, the electronic device (100) may not include some or all of the key input device (117), and the key input device (117) not included may be implemented in other forms, such as soft keys, on the display (101). In another embodiment, the key input device may include a sensor module (not shown) forming a sensing area (not shown) included in the display area (110A, 110D).

[0033] In one embodiment, the connector hole (108) may accommodate a connector. The connector hole (108) may be positioned on the side (110C) of the housing (110). For example, the connector hole (108) may be positioned on the side (110C) adjacent to at least a portion of an audio module (e.g., microphone hole (103) and speaker hole (107)). In another embodiment, the electronic device (100) may include a first connector hole (108) capable of accommodating a connector (e.g., USB connector) for transmitting / receiving power and / or data to / from an external electronic device, and / or a second connector hole (not shown) capable of accommodating a connector (e.g., earphone jack) for transmitting / receiving audio signals to / from an external electronic device.

[0034] In one embodiment, the electronic device (100) may include a light-emitting element (not shown). For example, the light-emitting element (not shown) may be placed on a first surface (110A) of the housing (110). The light-emitting element (not shown) may provide state information of the electronic device (100) in the form of light. In another embodiment, the light-emitting element (not shown) may provide a light source that is linked to the operation of the first camera module (105). For example, the light-emitting element (not shown) may include an LED, an IR LED, and / or a xenon lamp.

[0035] In one embodiment, the camera module (105, 112) may include a first camera module (105) configured to receive light through a camera area (106) of a first surface (110A) of the electronic device (100) (e.g., under display camera), a second camera module (112) configured to receive light through a part of a second surface (110B) (e.g., rear camera area (184) of FIG. 3), and / or a flash (113).

[0036] In one embodiment, the first camera module (105) may include an under-display camera (UDC) positioned on the back surface of the display (101). For example, the first camera module (105) may be positioned on a part of the display (101), or the optical axis of the lens may be positioned to pass through the display area (110A, 110D) of the display. In various embodiments, the first camera module (105) may be configured to receive light through a camera area (106) included in the display area (110A, 110D). For example, the camera area (106) may be configured to display content, just like other areas of the display area (110A, 110D), when the first camera module (105) is not in operation. For example, when the first camera module (105) is in operation, the camera area (106) does not display content, and the first camera module (105) can receive light through the camera area (106).

[0037] In various embodiments (not shown), the first camera module (105) (e.g., a punch-hole camera) may be exposed through a portion of the display area (110A, 110D) of the display (101). For example, the first camera module (105) may be exposed to a portion of the screen display area (110A, 110D) through an opening formed in a portion of the display (101).

[0038] In one embodiment, the second camera module (112) may include a plurality of camera modules (e.g., dual camera, triple camera, or quad camera). However, the second camera module (112) is not necessarily limited to including a plurality of camera modules and may include a single camera module.

[0039] In one embodiment, the first camera module (105) and / or the second camera module (112) may include one or more lenses, an image sensor, and / or an image signal processor. The flash (113) may include, for example, a light-emitting diode or a xenon lamp. In another embodiment, two or more lenses (infrared camera, wide-angle and telephoto lenses) and image sensors may be arranged inside the housing so as to face the direction in which one side of the electronic device (100) (e.g., the second side (110B)) faces.

[0040] Referring to FIG. 3, the electronic device (100) may include a side bezel structure (118), a first support member (140) (e.g., a bracket), a front plate (120) (e.g., the front plate (102) of FIG. 1), a display (130) (e.g., the display (101) of FIG. 1), a printed circuit board (150) (e.g., a printed circuit board (PCB), a flexible PCB (FPCB), or a rigid-flexible PCB (RFPCB)), a battery (152), a second support member (160) (e.g., a rear case), an antenna (170), and a rear plate (180) (e.g., the rear plate (111) of FIG. 2). In some embodiments, the electronic device (100) may omit at least one of the components (e.g., the first support member (140), or the second support member (160)) or additionally include other components. At least one of the components of the electronic device (100) may be identical or similar to at least one of the components of the electronic device (100) of FIG. 1 or FIG. 2, and redundant descriptions are omitted below.

[0041] In one embodiment, the first support member (140) may be disposed inside the electronic device (100) and connected to the side bezel structure (118), or may be formed integrally with the side bezel structure (118). The first support member (140) may be formed, for example, from a metal material and / or a non-metal (e.g., polymer) material. A display (130) may be attached or positioned on one side of the first support member (140), and a printed circuit board (150) may be attached or positioned on the other side.

[0042] In one embodiment, a processor, memory, and / or interface may be disposed on the printed circuit board (150). The processor may include, for example, one or more of a central processing unit, an application processor, a graphics processing unit, an image signal processor, a sensor hub processor, or a communication processor.

[0043] In one embodiment, the memory may include, for example, volatile memory or non-volatile memory.

[0044] In one embodiment, the interface may include, for example, an HDMI (high definition multimedia interface), a USB (universal serial bus) interface, an SD card interface, and / or an audio interface. The interface may, for example, electrically or physically connect the electronic device (100) to an external electronic device and may include a USB connector, an SD card / MMC connector, or an audio connector.

[0045] In one embodiment, the battery (152) is a device for supplying power to at least one component of the electronic device (100) and may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. At least a portion of the battery (152) may be disposed substantially coplanar with, for example, the printed circuit board (150). The battery (152) may be disposed integrally inside the electronic device (100) or may be disposed detachably from the electronic device (100).

[0046] In one embodiment, the antenna (170) may be positioned between the rear plate (180) and the battery (152). The antenna (170) may include, for example, a near field communication (NFC) antenna, a wireless charging antenna, and / or a magnetic secure transmission (MST) antenna. The antenna (170) may, for example, communicate near-field with an external device or wirelessly transmit and receive power required for charging. In another embodiment, the antenna structure may be formed by a side bezel structure (118) and / or a part or combination thereof of the first support member (140).

[0047] In one embodiment, the first camera module (105) may be coupled to the back surface of the display (130) to receive light through the camera area (106) of the front plate (120). For example, at least a portion of the first camera module (105) may be placed on the first support member (140). For example, the image sensor of the first camera module (105) may receive light that has passed through the camera area (106) and the pixel array included in the display (130). For example, the camera area (106) may overlap at least partially with the display area where content is displayed. For example, the optical axis (OA) of the first camera module (105) may pass through a portion of the display (130) and the camera area (106) of the front plate (120). For example, the portion may include a pixel array comprising a plurality of light-emitting elements. In one embodiment, a portion of the display (130) facing the first camera module (105) may be formed as a transparent area having a specified transmittance as part of the display area where content is displayed. In one embodiment, the transparent area may be formed to have a transmittance in the range of about 5% to about 25%. In one embodiment, the transparent area may be formed to have a transmittance in the range of about 25% to about 50%. In one embodiment, the transparent area may be formed to have a transmittance of about 50% or more. Such a transparent area may include an area that overlaps with the effective area (e.g., field of view (FOV)) of the first camera module (105) through which light passes to form an image with an image sensor to generate an image. For example, the transparent area of ​​the display (130) may include an area with a lower pixel density and / or wiring density than the surrounding area.

[0048] In one embodiment, the second camera module (112) may be positioned so that the lens is exposed to a rear camera area (184) of the rear plate (180) of the electronic device (100) (e.g., rear (110B) of FIG. 2). The rear camera area (184) may be formed on at least a portion of the surface of the rear plate (180) (e.g., rear (110B) of FIG. 2). In one embodiment, the second camera area (184) may be formed at least partially transparent so that the second camera module (112) receives external light through the second camera area (184).

[0049] In one embodiment, at least a portion of the rear camera area (184) may protrude a predetermined height from the surface of the rear plate (180). However, it is not necessarily limited thereto, and the rear camera area (184) may form a plane substantially identical to the surface of the rear plate (180).

[0051] FIG. 4 is a drawing illustrating an electronic device according to one embodiment.

[0052] Referring to FIG. 4, the electronic device (100) may include an interposer (200) (e.g., a shielding member) that electrically connects a first substrate (150) (e.g., a printed circuit board (150) of FIG. 3) and a second substrate (190). In one embodiment, the interposer (200) may form a shielding space (209) capable of shielding noise generated between the first substrate (150) and the second substrate (190) or introduced from the outside. In one embodiment, the interposer (200) may be provided in various shapes. For example, the interposer (200) may be provided in a polygonal shape. The interposer (200) may be provided in a ring shape that surrounds the shielding space (209). The shielding space (209) may include a portion of the first substrate (150) and a portion of the second substrate (190). The form of the interposer (200) disclosed in this document is not limited to that shown in the drawings.

[0053] In one embodiment, the first substrate (150) (e.g., the printed circuit board (150) of FIG. 3) may include one or more electrical elements (152, 154), a signal line electrically connecting the electrical elements (152, 154), and a ground. In one embodiment, the one or more electrical elements (152, 154) may include a first electrical element (152) located inside the shielding space (209) and a second electrical element (154) located outside the shielding space (209). In one embodiment, the first substrate (150) may include a first upper surface (1501) facing the second lower surface (1902) of the second substrate (190), and a first lower surface (1502) opposite to the first upper surface (1501). Referring to the drawing, a portion of the first upper surface (1501) of the first substrate (150) may be included in the shielding space (209). The first electric element (152) and the second electric element (154) may be placed on the first upper surface (1501).

[0054] In one embodiment, the second substrate (190) may be positioned in a first direction of the first substrate (150). For example, the second substrate (190) may be positioned on the first upper surface (1501) of the first substrate (150) or below the first lower surface (1502) of the first substrate (150). The position of the second substrate (190) may vary depending on the type and / or function of the third electrical element (192) mounted on the second substrate (190). The third electrical element (192) may be positioned inside the shielding space (209). Referring to the drawings, the third electrical element (192) may be positioned on the second lower surface (1902) of the second substrate (190). The second substrate (190) may include a second lower surface (1902) facing the first upper surface (1501) of the first substrate (150), and a second upper surface (1901) opposite to the second lower surface (1902). Referring to the drawings, at least a portion of the second lower surface (1902) of the second substrate (190) may be included in the shielding space (209).

[0055] In one embodiment, the interposer (200) may be extended to surround a shielding space (209) defined between the first substrate (150) and the second substrate (190). For example, the interposer (200) may include a second surface (202) that is at least partially in contact with a first upper surface (1501) of the first substrate (150), a first surface (201) that is at least partially in contact with a second lower surface (1902) of the second substrate (190), and sides (203, 204) that surround the space between the first surface (201) and the second surface (202).

[0056] In one embodiment (not shown), the interposer (200) can connect a flexible circuit board and a main circuit board (e.g., a first board (150)). For example, the second board (190) may be a flexible circuit board. For example, the interposer (200) may be a conductive member connecting the junction of the flexible circuit board and the main circuit board. In one embodiment, the interposer (200) may include a plurality of vias (e.g., a plurality of vias (Vs, V1, V2, V3) of FIG. 6)) and may be arranged coaxially with the junction of the flexible circuit board. Additionally, during the bonding process of the flexible circuit board and the main circuit board (e.g., a hot bar process), a conductive material such as lead may be bonded to the plurality of vias to form a signal transmission structure between the flexible circuit board and the main circuit board.

[0057] In various embodiments, the second substrate (190) may be formed in various sizes. For example, the second substrate (190) may be formed in the same size as the first substrate (150), or the second substrate (190) may be formed smaller than the first substrate (150), or the second substrate (190) may be formed larger than the first substrate (150). The second substrate (190) may be formed in a shape corresponding to the shape of the interposer (200). The shapes of the first substrate (150) and the second substrate (190) shown in the drawings are merely examples, and each substrate may be formed in various shapes.

[0058] In one embodiment, each of the first electric element (152), the second electric element (154), and the third electric element (192) may include an integrated circuit, an active element, or a passive element. For example, the first electric element (152) and the third electric element (192) placed inside a shielded space may include electric elements that require shielding due to higher noise vulnerability compared to the second electric element (154), or electric elements that generate more noise. For example, the first electrical element (152) may include a processor (e.g., the processor (1720) of FIG. 17) (e.g., an application processor (AP) and / or a call processor (CP)), memory (e.g., the memory (1730) of FIG. 17), and a power management circuit (e.g., the power management module (1788) of FIG. 17). Additionally, the third electrical element (192) may include an RF circuit (e.g., the communication module (1790) of FIG. 17), an NFC chip, a UWB chip, a sensor circuit (e.g., the sensor module (1776) of FIG. 17), a transceiver, a wireless communication module (e.g., a WiFi module), and a connector module for connection with an external electronic device (e.g., the connection terminal (1778) of FIG. 17). The connector module may include a Type-C connector, a display connector, and / or a battery connector.

[0059] In one embodiment, the interposer (200) may include a plurality of signal vias (e.g., signal vias (Vs) of FIG. 6) (e.g., power interface, USB interface, MIPI interface, RF interface, through-electrodes, wiring) and grind vias (e.g., ground vias (V1, V2, V3) of FIG. 6) (e.g., ground (GND) terminal). For example, the first substrate (150) and the second substrate (190) may be electrically connected by the interposer (200), and the first substrate (150) may transmit a digital signal related to the RF (radio frequency) band to the second substrate (190) through the interposer (200).

[0060] According to one embodiment, some electrical components are placed on the second substrate (190), thereby allowing the internal space of the electronic device (100) to be utilized efficiently. According to one embodiment, since the interposer (200) performs a shielding function in addition to electrically connecting the first substrate (150) and the second substrate (190), a separate shield can may not be required.

[0062] FIG. 5 is a drawing illustrating an interposer of an electronic device according to one embodiment.

[0063] Referring to FIG. 5, the interposer (200) may be extended in a closed form to surround the internal space (209). In one embodiment, the extension direction (E) of the interposer (200) may be a direction substantially perpendicular to the z-axis (e.g., the z-axis in FIG. 1 and FIG. 2) (e.g., the x-axis and y-axis in FIG. 1 and FIG. 2). In another embodiment, the extension direction (E) of the interposer (200) may include a direction formed on the xy-plane in addition to the illustrated direction. For example, the extension direction (E) may include a diagonal direction in the xy-plane. For example, the extension direction (E) may include any direction formed by the combination of an x-axis direction vector and a y-axis direction vector. The interposer (200) may include a straight section that extends substantially in a straight line and a curved section that extends in a curve. In one embodiment, an electric element (e.g., the first electric element (152) and the third electric element (192) of FIG. 4) mounted on the first substrate (150) and / or the second substrate (190) may be located in the internal space (209).

[0064] In one embodiment, the interposer (200) may include a first surface (201), a second surface (202), an outer surface (203), and an inner surface (204). The inner surface (204) may be a surface facing the inner space (209). The outer surface (203) may be a surface facing the outside of the interposer (200).

[0065] In one embodiment, the first surface (201) of the interposer (200) may include an insulating first cover layer (e.g., the first cover layer (230a) of FIG. 7a) and a conductive pad (e.g., the first pad (310), the second pad (320) of FIG. 7a) formed in an open area of ​​the first cover layer (230a). For example, the conductive pad included in the first surface (201) may be electrically connected by at least partially contacting the conductive area of ​​the second substrate (190). For example, the conductive pad included in the first surface (201) may be joined to the conductive area of ​​the second substrate (190) through soldering.

[0066] In one embodiment, the second surface (202) of the interposer (200) may include an insulating second cover layer (e.g., the second cover layer (230b) of FIG. 7a) and a conductive pad (e.g., the first pad (310), the second pad (320) of FIG. 7a) formed in an open area of ​​the second cover layer (230b). For example, the conductive pad included in the second surface (202) may be electrically connected by at least partially contacting the conductive area of ​​the first substrate (150). For example, the conductive pad included in the second surface (202) may be joined to the conductive area of ​​the first substrate (150) through soldering.

[0067] In one embodiment, the interposer (200) may be formed with a structure comprising a plurality of layers. For example, the interposer (200) may include a plurality of insulating portions comprising an insulating material. For example, the insulating material may include PPG (preimpregnated materials) (e.g., insulating resin), and a copper clad laminate may be disposed between the insulating materials.

[0069] FIG. 6 is a plan view of an interposer according to one embodiment. FIG. 7a is a cross-sectional view of an interposer according to one embodiment. FIG. 7b is a cross-sectional view of an interposer according to one embodiment.

[0070] Referring to FIG. 6, the interposer (200) may include a plurality of vias (Vs, V1, V2, V3). The plurality of vias (Vs, V1, V2, V3) may include signal vias (Vs) connecting signal lines of a first substrate (e.g., the first substrate (150) of FIG. 4) and a second substrate (e.g., the second substrate (190) of FIG. 4), respectively, and ground vias (V1, V2, V3) connecting ground regions of the first substrate (150) and the second substrate (190) respectively. In various embodiments, the ground vias disclosed herein may include vias (V4 to V11) shown in FIG. 8 to 15 in addition to the vias (V1, V2, V3) shown in FIG. 6 to 7b.

[0071] In one embodiment, the interposer (200) may fill the interior of at least one via (Vs, V1, V2, V3) with a conductive material (or conductive material) through hole plugging, but is not limited thereto.

[0072] In one embodiment (not shown), the shape of the plurality of vias (Vs, V1, V2, V3) is not limited to that shown in the drawing. For example, at least some of the plurality of vias (Vs, V1, V2, V3) may be formed in a slot shape. For example, the slot-shaped via may be formed in an opening shape having a length in the extension direction (E). For example, the slot-shaped via may be formed by performing continuous hole plugging so that the plurality of vias (Vs, V1, V2, V3) shown are not spaced apart from each other.

[0073] Referring to FIG. 6, the interposer (200) may include a plurality of pads (310, 320) formed on a surface and electrically connected to each of the signal vias (Vs) and ground vias (V1, V2, V3). Each of the plurality of pads (310, 320) may be connected to one or more vias. When viewed from above (e.g., in the z-axis direction) of the surface of the interposer (200) (e.g., a first surface (201) or a second surface (202)), each of the plurality of pads (310, 320) may overlap with at least one via.

[0074] In one embodiment, the pads connected to the signal vias (Vs) may each be electrically connected to a signal line of the first substrate (150) or the second substrate (190). In one embodiment, the pads connected to the ground vias (V1, V2, V3) may each be electrically connected to a ground area of ​​the first substrate (150) or the second substrate (190).

[0075] In various embodiments, the first portion (P1) in which the ground vias (V1, V2) are arranged is not necessarily limited to being defined in the first column (C1). For example, the first portion (P1) of the interposer (200) may be partially provided for antenna connection. In this case, a portion of the ground vias (V1, V2) may be located in the second column (C2) or the third column (C3) and may form a fence with the ground vias (V1, V2) arranged in the first column (C1). The signal vias (Vs) and internal space of the interposer (200) may be located inside the fence, and the vias provided for antenna connection may be located outside the fence.

[0077] Referring to FIG. 7a, a plurality of vias (V1, V2, V3) may be extended in the z-axis direction to penetrate the insulating layer (210). For example, the length direction of each of the plurality of vias (V1, V2, V3) may be defined as a direction substantially parallel to the z-axis.

[0078] In one embodiment, the interposer (200) may include a first portion (P1) and a second portion (P2) surrounded by the first portion (P1). The first portion (P1) may be defined along the outer surface (203) of the interposer (200). In one embodiment, the first portion (P1) may be configured to shield the inner space (209) surrounded by the interposer (200) and the second portion (P2) of the interposer (200). For example, the first portion (P1) may prevent or reduce noise generated from the inner space (209) or the second portion (P2) from leaking out of the interposer (200), and prevent or reduce noise generated from the outside from flowing into the inner space (209) or the second portion (P2) of the interposer (200).

[0079] In one embodiment, the first part (P1) of the interposer (200) may include ground vias (V1, V2, V3). For example, only ground vias (V1, V2, V3) may be placed in the first part (P1) and signal vias (Vs) may not be placed. In another embodiment (not shown), the first part (P1) of the interposer (200) may include ground vias (V1, V2, V3) and signal vias (Vs), and the area where the ground vias (V1, V2, V3) are placed may be formed wider than the area where the signal vias (Vs) are placed.

[0080] In various embodiments, the second part (P2) of the interposer (200) may include signal vias (Vs) and ground vias. In the second part (P2) of the interposer (200), the number of signal vias (Vs) may be greater than the number of ground vias. In one embodiment, the sizes of the signal vias (Vs) and ground vias may be formed differently from each other. For example, the signal vias (Vs) may be formed with a first size (diameter) when viewed in the z-axis direction, and the ground vias may be formed with a second size (diameter) smaller than the first size (diameter). For example, the interposer (200) may be machined into different shapes based on the size and / or number of drills in the process of forming at least one via (Vs, V1, V2, V3). However, drilling is merely one example of a processing method for forming at least one via (Vs, V1, V2, V3), and at least one via (Vs, V1, V2, V3) may be formed by laser processing or punching.

[0081] In one embodiment, the second part (P2) of the interposer (200) may be provided such that the first area, which is the area where signal vias (Vs) are placed, has a larger area than the second area, which is the area where ground vias are placed. For example, if the size (diameter) of the signal vias (Vs) placed in the first area is larger than the size (diameter) of the ground vias placed in the second area, the first area has a larger area than the second area, and the number of signal vias (Vs) in the first area and the number of ground vias in the second area may be placed equal to each other.

[0082] In one embodiment, the second portion (P2) of the interposer (200) may be provided such that the first area, which is an area where signal vias (Vs) are placed, and the second area, which is an area where ground vias are placed, have substantially the same area. For example, if the size (diameter) of the signal vias (Vs) placed in the first area is larger than the size (diameter) of the ground vias placed in the second area, the first area has substantially the same area as the second area, and the number of signal vias (Vs) in the first area may be less than the number of ground vias in the second area.

[0083] In various embodiments, when viewed from above from the surface (201, 202) of the interposer (200), the area occupied by the first part (P1) may be smaller than the area occupied by the second part (P2). The number of vias (e.g., ground vias) included in the first part (P1) may be smaller than the number of vias included in the second part (P2). Thus, the interposer (200) according to one embodiment may provide a greater number of signal vias compared to a conventional interposer of the same size. For example, in a conventional interposer, the area of ​​the first part (P1) and the area of ​​the second part (P2) are substantially the same. The interposer (200) according to the embodiments may increase the total number of vias formed in the interposer (200) by reducing the area of ​​the first part (P1) and increasing the area of ​​the second part (P2) compared to a conventional interposer. For example, the increased vias can be used primarily as signal vias (Vs) to perform more signal processing. As another example, by using the ground vias included in the first part (P1) to provide a shielding function (e.g., shield can) of the interposer (200), the ground vias placed in the second part of the existing interposer can be used as signal vias. Thus, the interposer (200) can provide a larger number of signal vias (Vs).

[0084] In one embodiment, vias (V1, V2, V3, Vs) provided in the interposer (200) may form multiple rows. The rows of the interposer (200) may be defined substantially along the extension direction (E). For example, referring to the drawings, the interposer (200) may be defined with a first row (C1) adjacent to the outer surface (203), a third row (C3) adjacent to the inner surface (204), and a second row (C2) between the first row (C1) and the third row (C3). However, the interposer (200) is not necessarily limited to including three rows. For example, the interposer (200) may include three or more rows. In one embodiment, ground vias (V1, V2, V3) may be placed in the first row (C1) adjacent to the outer surface (203) of the interposer (200) for shielding performance. Signal vias (Vs) may be placed in the second column and / or the third column. In various embodiments, some ground vias may be placed in the second column (C2) and / or the third column (C3). For example, the first part (P1) of the interposer (200) may include ground vias (V1, V2, V3) placed in the first column (C1) of the interposer (200).

[0085] Referring to FIGS. 7a and 7b, the interposer (200) may include an insulating layer (210), a first conductive layer (220a) and a second conductive layer (220b) disposed on both sides of the insulating layer (210), and a first cover layer (230a) and a second cover layer (230b) disposed on the surface of each conductive layer (220a, 220b). For example, the first conductive layer (220a) may be disposed between the first cover layer (230a) and the insulating layer (210). For example, the second conductive layer (220b) may be disposed between the second cover layer (230b) and the insulating layer (210). For example, the first cover layer (230a) may form the first surface (201) of the interposer (200), and the second cover layer (230b) may form the second surface (202) of the interposer (200). In one embodiment, the first conductive layer (220a) and the second conductive layer (220b) may each include a first pad (310), a second pad (320), and a first conductive pattern (221). In one embodiment, a filling material may be filled inside the vias (V1, V2, V3, Vs) of the interposer (200). For example, the inner wall of the via hole may be plated first, and the vias (V1, V2, V3, Vs) may be formed by filling the inside of the plated via hole with a filling material (e.g., dielectric material). In one embodiment, the filling member may be formed by filling the space between vias (V1, V2, V3, Vs) with a dielectric material in a paste or ink state (e.g., PSR ink (photo imageable solder resist mask ink)) and then curing it. For example, the filling member may prevent electrical short circuits between adjacent vias (V1, V2, V3, Vs). Referring to FIGS. 7a and 7b, each of the ground vias (V1, V2, V3) may overlap with pads (311, 312, 320) when viewed from the z-axis direction toward the first surface (201) or the second surface (202).However, the relationship between the ground vias (V1, V2, V3) and the pads (311, 312, 320) is not limited to what is illustrated. For example, the ground vias (V1, V2, V3) may overlap with a portion of the cover layer (230a, 230b) (e.g., an insulating coating area) when viewed from the z-axis direction toward the first surface (201) or the second surface (202). For example, the insulating coating area may include a solder resist.

[0086] Referring to FIG. 6 and FIG. 7a, the first portion (P1) may include a first structure (301). In one embodiment, the first structure (301) may include a first via (V1) and a second via (V2), and a first pad (310) formed on the surface of the interposer (200) and in contact with the first via (V1) and the second via (V2). The first pad (310) may overlap to cover each of the first via (V1) and the second via (V2) when viewed from above (e.g., in the z-axis direction) of the surface of the interposer (200). For example, the first pad (310) may have an area larger than the first via hole (e.g., the first via (V1)) and the second via hole (e.g., the second via (V2)) so as to completely cover the first via (V1) and the second via (V2).

[0087] Referring to FIGS. 6 and FIGS. 7a, the first pad (310) may include a covering first region (311) in contact with the end of the first via (V1), a second region (312) in contact with the end of the second via (V2), and a third region (313) connecting the first region (311) and the second region (312). In one embodiment, the end of the first via (V1) and the end of the second via (V2) may include a conductive region defined by a conductive material filled in the via hole, formed on the surface of the insulating layer (210). For example, the first region (311) may be formed larger than the size of the first via hole to cover the conductive region formed by the first via (V1) being exposed to the surface of the insulating layer (210). For example, the second region (312) may be formed larger than the size of the second via hole to cover the conductive region formed by the second via (V2) being exposed to the surface of the insulating layer (210). In one embodiment, the conductive material may include copper (Cu), lead (Pb), silver (Ag), nickel (Ni), aluminum (Al), tin (Sn), stainless steel and / or a combination thereof.

[0089] In various embodiments, the first region (311) and the second region (312) are formed in a substantially circular shape, and the third region (313) may have a width smaller than the diameter defined in the first region (311) and the second region (312). Here, the width may be a distance measured in a direction substantially perpendicular to the extension direction (E) of the interposer (200). In various embodiments, the width of the third region (313) may be smaller than the maximum width (e.g., diameter) of the first region (311) or the second region (312). In various embodiments, the first pad (310) may be formed in a dumbbell shape.

[0090] In one embodiment, the shapes of the vias (V1, V2, V3, Vs) and the pads (310, 320) corresponding to the vias can be formed in various ways. For example, the first pad (310) and / or the second pad (320) may be formed in a circular, elliptical, or polygonal shape. The first pad (310) and / or the second pad (320) may be formed in the same size or different sizes. The first pad (310) and / or the second pad (320) may be arranged with a constant or non-constant spacing. Furthermore, those skilled in the art will understand that the same applies to the shapes and / or spacing of the pads arranged in the second part (P2).

[0091] Referring to FIG. 6, the first region (311), the second region (312), and the third region (313) are all formed on the surface of the interposer (200) and can at least partially contact the surface of the first substrate (150) or the second substrate (190). In one embodiment, the interposer (200) includes the third region (313), thereby increasing the contact area with the substrates (150, 190), and the interposer (200) can be more firmly bonded to the substrates (150, 190) due to the increased area.

[0092] Referring to FIG. 6 and FIG. 7b, the first portion (P1) may include a third via (V3) and a second pad (320) in contact with the third via (V3). The second pad (320) may overlap to cover the third via (V3) when viewed from above (e.g., in the z-axis direction) on the surface of the interposer (200) (e.g., the first surface (201) or the second surface (202)). For example, the second pad (320) may have an area larger than the third via hole to completely cover the third via (V3). Referring to FIG. 7b, the third via (V3) and the second pad (320) may be electrically connected to the first structure (301) through a first conductive pattern (221) included in the conductive layers (220a, 220b). For example, the first conductive pattern (221) may be formed on the surface of the insulating layer (210) and may be positioned between the first cover layer (230a) and the insulating layer (210), and between the second cover layer (230b) and the insulating layer (210). The second pad (320) may be formed to cover a conductive area defined by the third via (V3). The second pad (320) may include a substantially circular border when viewed from above on the surface of the interposer (200) (e.g., the first surface (201) or the second surface (202)). In one embodiment, the second pad (320) may be surface mounted (SMT) on the ground area of ​​the first substrate (150) or the second substrate (190). In one embodiment, the first pad (310) and / or the second pad (320) may be connected to the first substrate (150) or the second substrate (190) by a solder ball, a solder wall, and / or an underfill resin. In one embodiment, the solder wall may be formed of the same material as the solder ball. For example, the solder wall and / or the solder ball may include at least one of tin, lead, silver, copper, and zinc.

[0093] Referring to FIG. 6, the interposer (200) may include a first conductive pattern (221) for electrically connecting a first structure (301) and a third via (V3). In various embodiments, when the interposer (200) includes a plurality of first structures (301) and third vias (V3), the first conductive pattern (221) may electrically connect adjacent first structures (301) or adjacent third vias (V3). In one embodiment, the first conductive pattern (221) may not be exposed to the surface of the interposer (200) (e.g., the first surface (201) or the second surface (202)) because it is covered by a cover layer (230a, 230b). Referring to FIGS. 6 and FIGS. 7b, the first structures (301) located on both sides of the third via (V3) can be electrically connected by the first conductive pattern (221).

[0094] In one embodiment, the mounting area of ​​the first substrate (150) and the second substrate (190) can be efficiently utilized by covering the first conductive pattern (221) with the cover layer (230a, 230b). For example, a ground pad does not necessarily need to be placed in the area of ​​the first substrate (150) and the second substrate (190) facing the first conductive pattern (221), and a pattern carrying a signal other than a ground signal may be located therein. For example, the signal line may be electrically insulated from the first conductive pattern (221) by the cover layer (230a, 230b). For example, a solder resist may be formed on the cover layer (230a, 230b). For example, the solder resist may be formed in the remaining area excluding the area where solder (e.g., solder ball, solder wall) is formed. Additionally, the solder resist may be placed around at least one of the first pad (310) and the second pad (320). For example, the solder resist may serve to protect the interposer (200) from external shocks, moisture, or contaminants.

[0095] In various embodiments, although not shown in the drawings, the first conductive pattern (221) may be extended along the outer surface (203) of the interposer (200) to connect all ground vias included in the first portion (P1) (e.g., first column (C1)). In various embodiments, a portion of the first conductive pattern (221) may form a portion of the pad (e.g., third portion (313)) or be covered by a cover layer (230a, 230b).

[0096] According to one embodiment, the first portion (P1) may include pads (310, 320) configured in various shapes, vias (V1, V2, V3), and a first conductive pattern (221) extended to correspond to the first portion (P1). The first conductive pattern (221) may connect the vias (V1, V2, V3) so that a ground signal is applied to all of the vias (V1, V2, V3) included in the first portion (P1). The first conductive pattern (221) may be covered by a cover layer (230a, 230b) or may form a part (e.g., a third region (313)) of a pad (e.g., the first pad (310)).

[0098] FIG. 8 is a plan view of an interposer according to one embodiment. FIG. 9a is a cross-sectional view of a second structure of an interposer according to one embodiment. FIG. 9b is a cross-sectional view of a third structure of an interposer according to one embodiment.

[0099] Hereinafter, in describing FIGS. 8, 9a, and 9b, content that overlaps with content described in FIGS. 6, 7a, and 7b will be omitted.

[0100] Referring to FIGS. 8 and 9a, a first portion (P1) of the interposer (200) may include a second structure (302). In one embodiment, the second structure (302) may include a third pad (330), a fourth via (V4), a fifth via (V5), and a sixth via (V6) located on a surface of the interposer (200) (e.g., a first surface (201) or a second surface (202)). A ground signal may be applied to the third pad (330), the fourth via (V4), the fifth via (V5), and the sixth via (V6).

[0101] In one embodiment, the third pad (330) may include a first region (331) and a second region (332) that are spaced apart from each other and have a substantially circular or arc-shaped edge, and a third region (333) connecting the first region (331) and the second region (332). In one embodiment, the first region (331), the second region (332), and the third region (333) may at least partially contact the surface of the first substrate (150) or the second substrate (190). For example, the first region (331), the second region (332), and the third region (333) may be surface-mounted on the first substrate (150) or the second substrate (190). For example, the first region (331), the second region (332), and the third region (333) may be bonded to the first substrate (150) or the second substrate (190) through a conductive material (e.g., including at least one of tin, lead, silver, copper, and zinc). For example, the conductive material may include solder balls, solder walls, and / or underfill resins.

[0102] In one embodiment, the interposer (200) includes a third region (333), thereby increasing the contact area with the substrates, and the interposer (200) can be more firmly bonded to the substrates due to the increased area.

[0103] In one embodiment, the fourth via (V4) may overlap with and contact the first region (331) of the third pad (330) when viewed from above on the surface of the interposer (200) (e.g., the first surface (201) or the second surface (202)). For example, the first region (331) of the third pad (330) may have an area larger than the size of the fourth via hole. In one embodiment, the fifth via (V5) may overlap with and contact the second region (332) of the third pad (330) when viewed from above on the surface of the interposer (200) (e.g., the first surface (201) or the second surface (202)). For example, the second region (332) of the third pad (330) may have an area larger than the size of the fifth via hole. In one embodiment, the sixth via (V6) may at least partially overlap and contact the third region (333) of the third pad (330) when viewed from above on the surface of the interposer (200) (e.g., the first surface (201) or the second surface (202)).

[0104] In various embodiments, the first region (331) and the second region (332) are formed in a substantially circular shape, and the third region (333) may have a width smaller than the diameter defined in the first region (331) and the second region (332). Here, the width may be a distance measured in a direction substantially perpendicular to the extension direction (E) of the interposer (200). In various embodiments, the width of the third region (333) may be smaller than the maximum width (e.g., diameter) of the first region (331) or the second region (332).

[0105] In various embodiments, the second structure (302) may be understood to further include an additional via (e.g., a sixth via (V6)) between the first via (V1) and the second via (V2) of the first structure (301). The second structure (302) may include vias (V4, V5, V6) arranged at smaller intervals, thereby providing improved shielding performance.

[0106] Referring to FIGS. 8 and 9b, a first part (P1) of the interposer (200) may include a third structure (303). The third structure (303) may include a second structure (302), a seventh via (V7), an eighth via (V8), a fourth region (334), and a fifth region (335). A ground signal is applied to the third structure (303), and the third structure (303) may shield the second part (P2) of the interposer (200) and the internal space (209) surrounded by the interposer (200) by forming a shielding wall together with other vias included in the first part (P1) and other structures (e.g., first structure (301), second structure (302)).

[0107] In one embodiment, the fourth region (334) may have a substantially circular or arc-shaped edge, similar to the first region (331) or the second region (332), and may come into contact with the end of the seventh via (V7). The fourth region (334) may have an area larger than the size of the seventh via hole to completely cover the seventh via (V7) when viewed from above on the surface of the interposer (200) (e.g., the first surface (201), or the second surface (202)). In one embodiment, the fifth region (335) may connect the fourth region (334) and the second region (332). In one embodiment, the interposer (200) includes a fifth region (335) so that the contact area with the substrates (150, 190) is increased, and the interposer (200) can be more firmly bonded to the substrates (150, 190) by the increased area. In various embodiments, the fourth region (334) is formed in a substantially circular shape, and the fifth region (335) may have a width smaller than the diameter defined in the fourth region (334).

[0108] In one embodiment, the seventh via (V7) may overlap with and contact the fourth region (334) of the third pad (330) when viewed from above on the surface of the interposer (200) (e.g., the first surface (201) or the second surface (202)). In one embodiment, the eighth via (V8) may overlap with and contact the fifth region (335) of the third pad (330) at least partially when viewed from above on the surface of the interposer (200) (e.g., the first surface (201) or the second surface (202)).

[0109] In various embodiments, the third structure (303) may be understood as being provided in a form where two second structures (302) share one via (e.g., fifth via (V5)). The third structure (303) may increase the contact area of ​​the first substrate (150) or the second substrate (190) by extending the third pad (330) longer than the second structure (302). Through the increased area, the interposer (200) and the substrates (150, 190) may be more firmly bonded. Additionally, the third structure (303) may further include eighth vias (V8) and sixth vias (V6) compared to the first structure (301), thereby reducing the spacing between the vias and providing improved shielding performance through the reduced spacing.

[0110] In various embodiments, the second structure (302) and the third structure (303) may be electrically connected through a second conductive pattern (222) formed in the conductive layer (220a, 220b) and covered by the cover layer (230a, 230b).

[0111] In various embodiments, the second structure (302) and the third structure (303) may be connected in various shapes in addition to the shape extending in the extension direction (E) from the first part (P1). For example, the second structure (302) and the third structure (303) may be formed in a zigzag shape. When viewed from the z-axis direction, the fourth via (V4), the fifth via (V5), and the seventh via (V7) of the third structure (303) are formed in substantially the same extension direction (E), and the sixth via (V6) and the eighth via (V8) may be positioned above or below the extension direction (E) of the fourth via (V4), the fifth via (V5), and the seventh via (V7). For example, the spacing between each of the fourth via (V4), the fifth via (V5), and the seventh via (V7) may be 0.6 mm to 0.8 mm, and the spacing between the fourth via (V4) and the sixth via (V6) may be 0.15 mm to 0.17 mm.

[0112] Referring to FIG. 8, the spacing (d2) between vias included in the first part (P1) may be smaller than or equal to the spacing (d1, d3) between vias included in the second part (P2). For example, since the vias included in the second part (P2) (e.g., signal vias) transmit independent signals, they may be required to be electrically isolated from each other. Therefore, the vias included in the second part (P2) may be spaced apart by a sufficient distance so that each pad can be physically separated, taking into account the area of ​​the pads. Meanwhile, since all the vias included in the first part (P1) are ground vias, the same ground signal is applied, so they may be placed relatively closer together. For example, the pads included in the first part (P1) may overlap or be connected to each other. For example, the vias included in the first part (P1) may be spaced apart by a second spacing (d2) of 0.2 mm or less. At this time, the second interval (d2) may be the interval between the outlines of the vias.

[0113] In various embodiments, any of the vias included in the second part (P2) may be spaced apart by a third gap (d3) from another adjacent via located in the extension direction. In various embodiments, any of the vias included in the second part (P2) may be spaced apart by a first gap (d1) from another adjacent via located in a direction other than the extension direction. For example, the first gap (d1) may be 0.5 mm to 0.8 mm apart. The third gap (d3) may be 0.6 mm to 0.8 mm apart. The first gap (d1) may be smaller than the third gap (d3). The first gap (d1) and the third gap (d3) may be the gap between the centers of the vias.

[0114] Referring to FIG. 8, a pad connected to a via included in the first part (P1) (e.g., sixth via (V6), seventh via (V7), eighth via (V8)) and a pad connected to a via included in the second part (P2) may be spaced apart from each other by a fourth gap (d4). For example, the fourth gap (d4) may be a distance to prevent short circuits between ground vias and signal vias. In this case, the fourth gap (d4) may be a gap measured in a direction substantially perpendicular to the extension direction (E) and the z-axis (e.g., the width (w) direction of the interposer (200)). The fourth gap (d4) may be 0.12 mm to 0.18 mm. The fourth gap (d4) may be a gap between the outlines of the pads. Referring to FIG. 8, the width (w) of the interposer may be 1.5 mm to 2 mm.

[0115] Referring to FIG. 8, a via or pad adjacent to the outer surface (203) may be spaced apart from the outer surface (203) by a fifth gap (d5) in the width direction. For example, the fifth gap (d5) may be the gap between the pad and the outer surface. For example, the fifth gap (d5) may be 0.2 mm to 0.3 mm. Referring to FIG. 8, a via or pad adjacent to the inner surface (204) may be spaced apart from the inner surface (204) by a sixth gap (d6) in the width direction. For example, the sixth gap (d6) may be the gap between the pad and the inner surface. For example, the sixth gap (d6) may be 0.2 mm to 0.3 mm.

[0117] FIG. 10 is a plan view of an interposer according to one embodiment. FIG. 11a is a cross-sectional view of a first portion of an interposer according to one embodiment. FIG. 11b is a cross-sectional view of a first portion of an interposer according to one embodiment.

[0118] Hereinafter, in describing FIGS. 10, FIGS. 11a, and FIGS. 11b, content that overlaps with content described in FIGS. 6, FIGS. 7a, FIGS. 7b, FIGS. 8, FIGS. 9a, and FIGS. 9b will be omitted.

[0119] Referring to FIGS. 10 and FIGS. 11a, the first part (P1) may include a fourth structure (304). In one embodiment, the fourth structure (304) may include a seconda structure (302a), a secondb structure (302b), a ninth via (V9), and a third conductive pattern (223). The third conductive pattern (223) may electrically connect the seconda structure (302a), the secondb structure (302b), and the ninth via (V9). Each of the seconda structure (302a) and the secondb structure (302b) may be substantially identical to the second structure (302) shown in FIGS. 8 and FIGS. 9a. For example, each of the 2a structure (302a) and the 2b structure (302b) includes a third pad (330), a fourth via (V4), a fifth via (V5), and a sixth via (V6), and the third pad (330) may include a first region (331), a second region (332), and a third region (333).

[0120] Referring to FIG. 11a, the ninth via (V9) may be formed between the first cover layer (230a) and the second cover layer (230b), unlike the fourth via (V4) through the eighth via (V8). For example, when viewed from above, the ninth via (V9) may not be exposed to the surface of the interposer (200) by being covered by the first insulating region (231) of the first cover layer (230a) or the second cover layer (230b). For example, other vias (e.g., fourth to sixth vias (V4–V6)) may be covered by a conductive pad (e.g., third pad (330)) when viewed from above on the surface of the interposer (200) (e.g., first surface (201) or second surface (202)). In this way, the ninth via (V9) may not be in direct contact with the first substrate (150) or the second substrate (190). Referring to FIG. 11a, the fourth via (V4), the fifth via (V5), and the sixth via (V6) may at least partially overlap with a pad forming part of the surface of the interposer (200) when viewed along the longitudinal direction of the via (e.g., z-axis direction). Referring to FIG. 11a, the ninth via (V9) may overlap with the cover layer (230a, 230b) without overlapping with the conductive pad forming part of the surface of the interposer (200) (e.g., first surface (201), or second surface (202)) when viewed in the longitudinal direction of the via (e.g., z-axis direction). The ninth via (V9) may overlap at least partially with the third conductive pattern (223) when viewed in the longitudinal direction of the via (e.g., z-axis direction). The ninth via (V9) may come into at least partial contact with the third conductive pattern (223). In one embodiment, a first insulating region (231) may be located between the second region (332) included in the seconda structure (302a) and the first region (331) included in the secondb structure (302b).Accordingly, the 2a structure (302a) and the 2b structure (302b) are not connected through a pad, but can be connected through a third conductive pattern (223) included in the internal conductive layer (220a, 220b).

[0121] In one embodiment, the ninth via (V9) can be electrically connected to the fourth via (V4) included in the secondb structure (302b) and the fifth via (V5) included in the seconda structure (302a), respectively, by the third conductive pattern (223). Referring to FIG. 11a, the ninth via (V9) can be positioned between the seconda structure (302a) and the secondb structure (302b), which are spaced apart from each other, to form a denser shielding wall and provide improved shielding performance.

[0122] In one embodiment, the third conductive pattern (223) may be covered by the first insulating region (231) of the cover layer (230a, 230b), just like the ninth via (V9). The third conductive pattern (223) may be placed between the insulating layer (210) and the cover layer (230a, 230b) and may extend along the extension direction (E) of the interposer (200). The third conductive pattern (223) may extend from the fourth via (V4) included in the 2b structure (302b) through the ninth via (V9) to the fifth via (V5) included in the 2a structure (302a). For example, the third conductive pattern (223) may not be exposed to the surface of the interposer (200) (e.g., the first surface (201) or the second surface (202)).

[0123] In one embodiment, the third conductive pattern (223) is covered by the first insulating region (231) of the cover layer (230a, 230b), thereby allowing the mounting regions of the first substrate (150) and the second substrate (190) to be utilized efficiently. For example, a ground pad does not necessarily need to be placed in the region of the first substrate (150) and the second substrate (190) facing the third conductive pattern (223), and a pattern through which a signal other than a ground signal flows may be placed. For example, the signal line may be electrically insulated from the third conductive pattern (223) by the cover layer (230a, 230b).

[0124] Referring to FIG. 10 and FIG. 11b, the first portion (P1) may further include a 10 via (V10), a 11 via (V11), and a 4 pad (340) spaced apart from the 4 structure (304). In various embodiments, the 10 via (V10) and the 4 pad (340) may be referred to as the 3 via (V3) and the 2 pad (320) of FIG. 7b. For example, the 4 pad (340) may have an area larger than the 10 via hole so as to contact the z-axis end of the 10 via (V10) and completely cover the end of the 10 via (V10). In one embodiment, a 2-insulating region (232) may be located between the 4 pad (340) and the 2-region (332) of the 2-b structure (302b) adjacent to the 4 pad (340).

[0125] Referring to FIG. 11b, the 10th via (V10) may be electrically connected to an adjacent via of the 4th structure (304) (e.g., the 5th via (V5) of the 2b structure (302b)) by the 4th conductive pattern (224). The 4th conductive pattern (224) may be contained within the conductive layer (220a, 220b) and covered by the second insulating region (232) of the cover layer (230a, 230b) so as not to be exposed to the surface of the interposer (200) (e.g., the first surface (201) or the second surface (202)).

[0126] Referring to FIG. 11b, the 11th via (V11) may be located between the 10th via (V10) and an adjacent via of the 4th structure (304) (e.g., the 5th via (V5) of the 2b structure (302b). The 11th via (V11) may be positioned to overlap at least partially with the 4th conductive pattern (224) and to contact the 4th conductive pattern (224). By having the 11th via (V11) located between the 10th via (V10) and the 5th via (V5), the interposer (200) can provide a denser shielding wall.

[0127] Referring to FIG. 11b, the mounting area of ​​the first substrate (150) and the second substrate (190) can be efficiently utilized by covering the fourth conductive pattern (224) and the first via (V11) with cover layers (230a, 230b). For example, a ground pad does not necessarily need to be placed in the area facing the fourth conductive pattern (224) among the first substrate (150) and the second substrate (190), and a pattern through which other signals flow may be placed. For example, the signal line may be electrically insulated from the fourth conductive pattern (224) and the first via (V11) by the cover layers (230a, 230b).

[0128] Referring to FIG. 10, the spacing (d2) between vias (e.g., ground vias) included in the first part (P1) may be smaller than or equal to the spacing (d1) between vias (e.g., signal vias) included in the second part (P2). For example, since all vias included in the first part (P1) are ground vias, they may be connected by a single pad or by a third conductive pattern (223) and / or a fourth conductive pattern (224) included in the conductive layer (220a, 220b). Thus, the vias included in the first part (P1) may be located closer together than the vias included in the second part (P2). In various embodiments, the vias included in the second part (P2) may be spaced apart from each other by a spacing of 0.5 mm to 0.8 mm, and the vias included in the first part (P1) may be spaced apart from each other by a spacing of 0.2 mm or less. In various embodiments, the third gap (d3), fourth gap (d4), fifth gap (d5), sixth gap (d6), and width (w) shown in FIG. 8 may be defined substantially the same as the interposer (200) shown in FIG. 10.

[0129] According to one embodiment, a first portion (P1) of the interposer (200) may include various types of shielding structures (301, 302, 303, 304) including at least one ground via. The at least one ground via may be electrically connected to each other through a pad (e.g., first pad (310), third pad (330)) formed on the surface of the interposer (200), or through a conductive layer (220a, 220b) located under a cover layer (230a, 230b). For example, when the ground vias or shielding structures (301, 302, 303, 304) are connected through a pad (e.g., first pad (310), third pad (330)), the contact area between the interposer (200) and the substrates (150, 190) is increased, thereby providing a robust connection. For example, when ground vias or shielding structures (301, 302, 303, 304) are connected through a conductive layer (220a, 220b), the mounting area of ​​the substrates (150, 190) can be utilized efficiently. Additionally, unlike signal vias, ground vias do not pose a risk of short circuits to each other, so they are spaced more closely together than signal vias, which can provide improved shielding performance. Such close spacing of ground vias can provide shielding performance capable of replacing the plating area provided on the side of a conventional interposer (200).

[0131] FIG. 12a is a drawing showing a portion of the surface of a first part of an interposer according to various embodiments. FIG. 12b is a drawing showing a portion of the surface of a first part of an interposer according to various embodiments.

[0132] Referring to FIGS. 12a and 12b, a first portion of the interposer (200) may include first vias (401) and second vias (402) to which a ground signal is applied. Each of the first vias (401) and second vias (402) may be extended in the z-axis direction.

[0133] In one embodiment, the first vias (401) may be defined as vias that completely overlap the conductive first pad (410) when viewed in the z-axis direction. For example, the first pad (410) may be located in the z-axis direction of each of the first vias (401). For example, the first pad (410) may be a pad having a substantially circular or arc-shaped edge.

[0134] In one embodiment, the second vias (402) may be defined as vias that are covered by an insulating cover layer and are not exposed to the outside when viewed in the z-axis direction. For example, a cover layer (e.g., the cover layer (230a, 230b) of FIG. 11a) may be located in the z-axis direction of each of the second vias (402).

[0135] In one embodiment, the first vias (401) may be surface mounted (SMT) to the first substrate (150) or the second substrate (190) through the first pad (410). For example, the first vias (401) may be electrically connected to the ground area of ​​the first substrate (150) or the second substrate (190) through the first pad (410). In one embodiment, the first pad (410) may be connected to the first substrate (150) or the second substrate (190) by a solder ball, a solder wall, and / or an underfill resin. In one embodiment, the solder wall may be formed of the same material as the solder ball. For example, the solder wall and / or solder ball may include at least one of tin, lead, silver, copper, and zinc.

[0136] In one embodiment, the second via (402) may be located between the first vias (401) when viewed in the extension direction (E) of the interposer (200). Referring to FIG. 12a, the second via (402) may include two or more vias. In one embodiment, the second vias (402) may be electrically connected to the first vias (401) through a conductive pattern (e.g., the third conductive pattern (223) of FIG. 11a) included in a conductive layer (e.g., the cover layer (230a, 230b) of FIG. 11a) located below the cover layer (e.g., the cover layer (230a, 230b) of FIG. 11a). For example, the second vias (402) can be electrically insulated from the circuit of the first substrate (150) or the second substrate (190) by a cover layer (e.g., the cover layer (230a, 230b) of FIG. 11a).

[0137] In various embodiments, referring to FIG. 12b, the second via (402) may be provided in a form where two vias are at least partially overlapping. For example, the second via (402) of FIG. 12b may include a single connected via hole and a conductive material filled in the via hole. The via hole may have a figure-eight shape. In various embodiments, referring to FIG. 12b, the second via (402) may have a shape that is longer in the width direction substantially perpendicular to the extension direction (E) than in the extension direction (E). For example, the second via (402) may have a form where two second via holes are partially overlapping in the width direction.

[0139] FIG. 13a is a drawing illustrating a portion of the surface of a first part of an interposer according to various embodiments. FIG. 13b is a drawing illustrating a portion of the surface of a first part of an interposer according to various embodiments. FIG. 13c is a drawing illustrating a portion of the surface of a first part of an interposer according to various embodiments.

[0140] Referring to FIGS. 13a and 13b, a first portion of the interposer (200) may include first vias (401) and third vias (403) to which a ground signal is applied, and first pads (411, 412) formed on the surface of the interposer (200) and covering at least partially each of the first vias (401) and third vias (403). Each of the first vias (401) and third vias (403) may be extended in the z-axis direction.

[0141] FIGS. 13a and FIGS. 13b may be variations of the second structure (302) shown in FIGS. 8. For example, the first vias (401) may be referred to as the fourth via (V4) and the fifth via (V5) of FIGS. 8. The first pads (411, 412) may be referred to as the third pad (330) of FIGS. 8.

[0142] In one embodiment, the first vias (401) may be defined as vias that are completely overlapped by the first conductive pads (411, 412) when viewed in the z-axis direction. For example, in the z-axis direction of the first vias (401), a first region (411) of the first conductive pads (411, 412) having a substantially circular or arc-shaped border may be located.

[0143] In one embodiment, the third via (403) may be defined as a via that overlaps at least partially with the cover layer (e.g., the cover layer (230a, 230b) of FIG. 9a) when viewed in the z-axis direction. For example, some regions of the third via (403) may overlap with the second region (412) of the first pad (411, 412) which is conductive, and other regions may overlap with the insulating cover layer (230a, 230b).

[0144] In one embodiment, the first region (411) and the second region (412) of the first pad (411, 412) may be surface-mounted on the first substrate (150) or the second substrate (190) and electrically connected to the ground region of the first substrate (150) or the second substrate (190). In one embodiment, the first pad (411, 412) may be connected to the first substrate (150) or the second substrate (190) by a solder ball, a solder wall, and / or an underfill resin. In one embodiment, the solder wall may be formed of the same material as the solder ball. For example, the solder wall and / or solder ball may include at least one of tin, lead, silver, copper, and zinc.

[0145] In one embodiment, the third via (403) may be located between the first vias (401) when viewed in the extension direction (E) of the interposer (200). The third via (403) may be in at least partial contact with the second region (412) of the first pads (411, 412). Referring to FIG. 13a, the third via (403) may include two or more vias. In one embodiment, the third vias (403) may be electrically connected to the first vias (401) through a conductive pattern included in a conductive layer (e.g., the conductive layer (220a, 220b) of FIG. 9a) located below a cover layer (e.g., the cover layer (230a, 230b) of FIG. 9a) and / or the second region (412) of the first pads (411, 412).

[0146] In various embodiments, referring to FIG. 13b, the third via (403) may be provided in a form where two vias are at least partially overlapping. For example, the third via (403) of FIG. 13b may include a single connected via hole and a conductive material filled in the via hole. The via hole may have a figure-eight shape. In various embodiments, referring to FIG. 13b, the third via (403) may have a shape that is longer in the width direction substantially perpendicular to the extension direction (E) than in the extension direction (E). For example, the third via (403) may have a form where two third via holes are partially overlapping in the width direction. Referring to FIG. 13c, the first part of the interposer (200) may be provided in a form where the third vias (403) are arranged in at least two columns (C1, C2). The first row (C1) may be defined as the row closest to the outer surface (203), and the second row (C2) may be defined as the row adjacent to the first row (C1). The third vias (403) may be ground vias electrically connected to each other through a conductive layer (e.g., the conductive layer (220a, 220b) of FIG. 11a). The third vias (403) may not be directly connected to a pad (e.g., the first pad (411, 412)) formed on the surface (201, 202) of the interposer (200). For example, the third vias (403) may be superimposed on a cover layer (e.g., the cover layer (230a, 230b) of FIG. 11a) in the z-axis direction. In various embodiments, the third vias (403) are not directly connected to the pads, so there is no short circuit problem, and they can be spaced more closely than the first vias (401) or the second vias (402). This allows for further improvement in the shielding performance of the interposer (200).

[0148] FIG. 14a is a drawing showing a portion of the surface of a first part of an interposer according to various embodiments. FIG. 14b is a drawing showing a portion of the surface of a first part of an interposer according to various embodiments.

[0149] The interposer illustrated in FIG. 14a can be understood as the interposer (200) illustrated in FIG. 13a with a third region (413) added thereto. The interposer (200) illustrated in FIG. 14b can be understood as the interposer (200) illustrated in FIG. 13b with a third region (413) added thereto. In describing FIG. 14a and FIG. 14b, details identical to those described in FIG. 13a and FIG. 13b are omitted.

[0150] Referring to FIG. 14a and FIG. 14b, the first pad (411, 412, 413) may further include a third region (413). The third region (413) may be provided in a form that overlaps the third via (403) when viewed in the z-axis direction. The border of the third region (413) may be formed partially circular or elliptical. The third region (413) may extend from the second region (412) and / or the first region (411). By the interposer (200) further including the third region (413), the contact area with the substrate (150, 190) is increased, which can provide a solid bond between the interposer (200) and the substrate (150, 190).

[0152] FIG. 15 is a drawing illustrating an interposer according to various embodiments.

[0153] Referring to FIG. 15, a first portion (P1) of the interposer (200) may include a plurality of ground vias (501, 502, 503). The interposer (200) may be configured such that a first surface (201) contacts the second substrate (190) and a second surface (202) contacts the first substrate (150). The ground vias (501, 502, 503) may electrically connect the ground regions of the first substrate (150) and the second substrate (190) through conductive pads (510) formed on the first surface (201) and conductive pads (520, 530) formed on the second surface (202). Multiple ground vias (501, 502, 503) may be electrically connected to each other through a conductive layer (220a, 220b) or a conductive pad (510, 520, 530). In one embodiment, a conductive pad (510) formed on a first surface (201) and a conductive pad (520, 530) formed on a second surface (202) may be provided to face each other at least partially when viewed in the z-axis direction (e.g., the length direction of the via).

[0154] For example, a first conductive pad (510) may be formed on the first surface (201) of the interposer (200), and a second conductive pad (520) and a third conductive pad (530) may be formed on the second surface (202). Referring to FIG. 15, when viewed in the z-axis direction, the first region (511) of the first conductive pad (510) may face the first region (521) of the second conductive pad (520), the second region (512) of the first conductive pad (510) may face the third conductive pad (530), and the third region (513) of the first conductive pad (510) may face the insulating region (234) formed in the second cover layer (230b). Referring to FIG. 15, the first region (521) of the second conductive region (520) faces the first region (511) of the first conductive pad (510), and the second region (522) of the second conductive pad (520) faces the insulating region (235) formed in the first cover layer (230a).

[0155] For example, referring to FIGS. 6 through 11, a pad located on the first surface (201) and a pad located on the second surface (202) may be provided at substantially the same location. On the other hand, referring to FIG. 15, a conductive pad (510) provided on the first surface (201) and a conductive pad (520, 530) provided on the second surface (202) may be formed staggered such that some areas face each other and other areas do not face each other. Thus, the bonding areas of the interposer (200), the first substrate (150), and the second substrate (190) may be provided partially staggered. Such a bonding structure can improve the bonding strength between the interposer (200) and the substrates (150, 190). For example, when a stress (e.g., shear stress, F) acting in the extension direction (E) and opposite directions is applied to each of the first substrate (150) and the second substrate (190), it can have an effect similar to substantially increasing the contact area by the staggered conductive pads.

[0156] In various embodiments, the first portion (P1) of the interposer (200) includes ground vias (501, 502, 503), and the ground vias may include a first via (501) located between a conductive pad of the first surface (201) and a conductive pad of the second surface (202) when viewed in the first direction (e.g., z-axis direction), a second via (502) located between a conductive pad of the first surface (501) and an insulating region (234) of the second surface (202), and a third via (503) located between an insulating region (235) of the first surface (201) and a conductive pad of the second surface (202). In various embodiments, the vias may include a ninth via (V9) located between an insulating region of the first surface (201) (e.g., the first insulating region (231) of FIG. 11a) and an insulating region of the second surface (202) (e.g., the second insulating region (232) of FIG. 11a), with reference to FIG. 11a.

[0158] FIGS. 16a, FIGS. 16b, and FIGS. 16c are drawings illustrating the arrangement of ground vias according to various embodiments.

[0159] Referring to FIGS. 16a, 16b, and 16c, a first portion (P1) of the interposer (200) may include ground vias (601, 602). The ground vias (601, 602) may include first vias (601) and second vias (602). The first vias (601) may be defined as vias directly connected to a pad (611) located on the surface (201, 202) of the interposer (200). For example, when viewed from above on the surface (201, 202) of the interposer (200), the first vias (601) may overlap with the pad (611). The second vias (602) may be defined as vias that overlap the cover layer (e.g., the cover layer (230a, 230b) of FIG. 15) of the surface (201, 202) of the interposer (200). The first vias (601) provide physical / electrical connection between the interposer (200) and the substrate (150, 190) through the pad (611), and the second vias (602) may be placed in the space between the first vias (601) to improve shielding performance. The first vias (601) and the second vias (602) may be electrically connected through a conductive pattern included in the conductive layer.

[0160] In various embodiments, the second vias (602) may be referred to as the ninth via (V9) of FIG. 11a or the second via (502) or third via (503) of FIG. 15.

[0161] Referring to FIGS. 16a, 16b, and 16c, the first vias (601) and the second vias (602) may be arranged in a zigzag pattern. For example, the first vias (601) may be arranged in the extension direction (E), and the second vias (602) may be arranged in the extension direction (E), but may be placed either inside or outside of the first vias (601). In describing the drawings, the direction facing the outer surface (203) and substantially perpendicular to the extension direction (E) is defined as the outer direction, and the opposite direction is defined as the inner direction.

[0162] Referring to FIG. 16a, each of the first vias (601) and the second vias (602) may be arranged in the extension direction (E). The second vias (602) may be positioned between the first vias (601) when viewed in the extension direction (E), but closer to the outer surface (203) than the first vias (601).

[0163] Referring to FIG. 16b, the first vias (601) and the second vias (602) can each be arranged in the extension direction (E). The second vias (602) can be positioned between the first vias (601) when viewed in the extension direction (E), but can be positioned closer to the inner direction than the first vias (601).

[0164] Referring to FIG. 16c, the first vias (601) are arranged in the extension direction (E), and the second vias (602) are located between the first vias (601) when viewed in the extension direction (E), but may be positioned inward or outward relative to the first vias (601). For example, one second via may be located outward relative to two adjacent first vias (601), and another second via adjacent to one second via may be located inward relative to two adjacent first vias (601).

[0166] According to one embodiment of the present document, at least one via (V1–V9, 401, 402, 403, 501, 502, 503) shown in FIGS. 6 to 16 may be a conductive hole drilled to electrically connect different substrates (e.g., a first substrate (150), a second substrate (190)). At least one via may include, for example, a plated through hole (PTH).

[0167] The interposer (200) according to the embodiments disclosed in this document has a plurality of ground vias concentrated in a first portion and the ground vias are connected to each other in various forms, so that, unlike conventional interposers, it can provide sufficient shielding performance without a side plating area. In addition, the plating process, which requires relatively high costs, is omitted, so the production cost of the interposer can be significantly reduced.

[0169] FIG. 17 is a block diagram of an electronic device in a network environment according to various embodiments.

[0170] Referring to FIG. 17, in a network environment (1700), an electronic device (1701) may communicate with an electronic device (1702) through a first network (1798) (e.g., a short-range wireless communication network) or with an electronic device (1704) or a server (1708) through a second network (1799) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (1701) may communicate with the electronic device (1704) through a server (1708). According to one embodiment, the electronic device (1701) may include a processor (1720), memory (1730), input module (1750), sound output module (1755), display module (1760), audio module (1770), sensor module (1776), interface (1777), connection terminal (1778), haptic module (1779), camera module (1780), power management module (1788), battery (1789), communication module (1790), subscriber identification module (1796), or antenna module (1797). In some embodiments, at least one of these components (e.g., connection terminal (1778)) may be omitted from the electronic device (1701), or one or more other components may be added. In some embodiments, some of these components (e.g., sensor module (1776), camera module (1780), or antenna module (1797)) may be integrated into a single component (e.g., display module (1760)).

[0171] The processor (1720) can, for example, execute software (e.g., program (1740)) to control at least one other component (e.g., hardware or software component) of the electronic device (1701) connected to the processor (1720) and perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (1720) can store commands or data received from other components (e.g., sensor module (1776) or communication module (1790)) in volatile memory (1732), process the commands or data stored in volatile memory (1732), and store the resulting data in non-volatile memory (1734). According to one embodiment, the processor (1720) may include a main processor (1721) (e.g., a central processing unit or an application processor) or an auxiliary processor (1723) that can operate independently or together with it (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor). For example, if the electronic device (1701) includes a main processor (1721) and an auxiliary processor (1723), the auxiliary processor (1723) may be configured to use less power than the main processor (1721) or to be specialized for a specified function. The auxiliary processor (1723) may be implemented separately from the main processor (1721) or as part thereof.

[0172] The auxiliary processor (1723) may control at least some of the functions or states associated with at least one component of the electronic device (1701) (e.g., display module (1760), sensor module (1776), or communication module (1790)) on behalf of the main processor (1721) while the main processor (1721) is in an inactive (e.g., sleep) state, or together with the main processor (1721) while the main processor (1721) is in an active (e.g., application execution) state. According to one embodiment, the auxiliary processor (1723) (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module (1780) or communication module (1790)). According to one embodiment, the auxiliary processor (1723) (e.g., neural network processing unit) may include a hardware structure specialized for processing an artificial intelligence model. The artificial intelligence model may be generated through machine learning. Such learning may be performed, for example, on the electronic device (1701) itself where the artificial intelligence is performed, or through a separate server (e.g., server (1708)). The learning algorithm may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model may include a plurality of artificial neural network layers.An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially.

[0173] The memory (1730) can store various data used by at least one component of the electronic device (1701) (e.g., processor (1720) or sensor module (1776)). The data may include, for example, input data or output data for software (e.g., program (1740)) and related commands. The memory (1730) may include volatile memory (1732) or non-volatile memory (1734).

[0174] The program (1740) may be stored as software in memory (1730) and may include, for example, an operating system (1742), middleware (1744), or an application (1746).

[0175] The input module (1750) can receive commands or data to be used for a component of the electronic device (1701) (e.g., processor (1720)) from outside the electronic device (1701) (e.g., user). The input module (1750) may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0176] The sound output module (1755) can output a sound signal to the outside of the electronic device (1701). The sound output module (1755) may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as multimedia playback or recording playback. The receiver may be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part thereof.

[0177] The display module (1760) can visually provide information to an external (e.g., user) of the electronic device (1701). The display module (1760) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling said device. According to one embodiment, the display module (1760) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of the force generated by said touch.

[0178] The audio module (1770) can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module (1770) can acquire sound through the input module (1750) or output sound through the sound output module (1755) or an external electronic device (e.g., electronic device (1702)) (e.g., speaker or headphones) connected directly or wirelessly to the electronic device (1701).

[0179] The sensor module (1776) can detect the operating state of the electronic device (1701) (e.g., power or temperature) or the external environmental state (e.g., user state) and generate an electrical signal or data value corresponding to the detected state. According to one embodiment, the sensor module (1776) may include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0180] The interface (1777) may support one or more specified protocols that can be used for the electronic device (1701) to be connected directly or wirelessly to an external electronic device (e.g., electronic device (1702)). According to one embodiment, the interface (1777) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0181] The connection terminal (1778) may include a connector through which the electronic device (1701) can be physically connected to an external electronic device (e.g., electronic device (1702)). According to one embodiment, the connection terminal (1778) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0182] The haptic module (1779) can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that can be perceived by the user through tactile or kinesthetic senses. According to one embodiment, the haptic module (1779) may include, for example, a motor, a piezoelectric element, or an electric stimulation device.

[0183] The camera module (1780) can capture still images and video. According to one embodiment, the camera module (1780) may include one or more lenses, image sensors, image signal processors, or flashes.

[0184] The power management module (1788) can manage power supplied to the electronic device (1701). According to one embodiment, the power management module (1788) can be implemented, for example, as at least part of a power management integrated circuit (PMIC).

[0185] The battery (1789) can supply power to at least one component of the electronic device (1701). According to one embodiment, the battery (1789) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0186] The communication module (1790) can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between an electronic device (1701) and an external electronic device (e.g., electronic device (1702), electronic device (1704), or server (1708)), and the performance of communication through the established communication channel. The communication module (1790) may include one or more communication processors that operate independently of the processor (1720) (e.g., application processor) and support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (1790) may include a wireless communication module (1792) (e.g., cellular communication module, short-range wireless communication module, or GNSS (global navigation satellite system) communication module) or a wired communication module (1794) (e.g., LAN (local area network) communication module, or power line communication module). The corresponding communication module among these communication modules can communicate with an external electronic device (1704) via a first network (1798) (e.g., a short-range communication network such as Bluetooth, WiFi (wireless fidelity) direct, or IrDA (infrared data association)) or a second network (1799) (e.g., a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (1792) can identify or authenticate the electronic device (1701) within a communication network such as the first network (1798) or the second network (1799) using subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module (1796).

[0187] The wireless communication module (1792) can support 5G networks and next-generation communication technologies following 4G networks, for example, new radio access technology. NR access technology can support high-speed transmission of high-capacity data (enhanced mobile broadband (eMBB)), minimization of terminal power and connection of multiple terminals (massive machine type communications (mMTC)), or high reliability and low latency (ultra-reliable and low-latency communications (URLLC)). The wireless communication module (1792) can support a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate, for example. The wireless communication module (1792) can support various technologies for securing performance in the high-frequency band, such as beamforming, massive MIMO (multiple-input and multiple-output), full-dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large-scale antenna. The wireless communication module (1792) can support various requirements specified in the electronic device (1701), external electronic device (e.g., electronic device (1704)), or network system (e.g., second network (1799)). According to one embodiment, the wireless communication module (1792) can support a Peak data rate (e.g., 20 Gbps or more) for eMBB realization, loss coverage (e.g., 164 dB or less) for mMTC realization, or U-plane latency (e.g., downlink (DL) and uplink (UL) each 0.5 ms or less, or round trip 1 ms or less) for URLLC realization.

[0188] An antenna module (1797) can transmit a signal or power to or from an external source (e.g., an external electronic device). According to one embodiment, the antenna module (1797) may include an antenna comprising a radiator made of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (1797) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as a first network (1798) or a second network (1799), may be selected from the plurality of antennas, for example, by a communication module (1790). A signal or power may be transmitted or received between the communication module (1790) and an external electronic device through the selected at least one antenna. According to some embodiments, in addition to the radiator, other components (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as part of the antenna module (1797).

[0189] According to various embodiments, the antenna module (1797) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., bottom surface) of the printed circuit board and capable of supporting a specified high frequency band (e.g., mmWave band), and a plurality of antennas (e.g., array antennas) disposed on or adjacent to a second surface (e.g., top surface or side surface) of the printed circuit board and capable of transmitting or receiving a signal of the specified high frequency band.

[0190] At least some of the above components can be connected to each other via a communication method between peripheral devices (e.g., bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)) and exchange signals (e.g., commands or data) with each other.

[0191] According to one embodiment, commands or data may be transmitted or received between the electronic device (1701) and an external electronic device (1704) through a server (1708) connected to a second network (1799). Each of the external electronic devices (1702, or 1704) may be the same or a different type of device as the electronic device (1701). According to one embodiment, all or part of the operations performed on the electronic device (1701) may be performed on one or more of the external electronic devices (1702, 1704, or 1708). For example, if the electronic device (1701) needs to perform a function or service automatically or in response to a request from a user or another device, the electronic device (1701) may request one or more external electronic devices to perform at least part of the function or service instead of performing the function or service itself or additionally. One or more external electronic devices that receive the above request may execute at least part of the requested function or service, or additional function or service related to the request, and transmit the result of the execution to the electronic device (1701). The electronic device (1701) may provide the result as is or additionally processed as at least part of the response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device (1701) may provide ultra-low latency services using, for example, distributed computing or mobile edge computing. In another embodiment, the external electronic device (1704) may include an Internet of Things (IoT) device. The server (1708) may be an intelligent server using machine learning and / or neural networks.According to one embodiment, an external electronic device (1704) or server (1708) may be included within the second network (1799). The electronic device (1701) may be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0192] An electronic device (100) according to embodiments disclosed in this document comprises: a housing (110); a first substrate (150) and a second substrate (190) disposed inside the housing (110) and disposed to face each other in a first direction (z-axis); and an interposer (200) that extends to surround an internal space (209) between the first substrate (150) and the second substrate (190), electrically connects the first substrate (150) and the second substrate (190), and includes vias that extend in the first direction; the interposer (200) includes a first part (P1) forming an outer surface (203) and a second part (P2) that forms an inner surface (204) facing the internal space (209) and is surrounded by the first part (P1), and the first part (P1) is configured to shield the second part (P2) and the internal space (209); wherein the vias included in the first part (P1) are all ground vias and are spaced apart from each other by a first interval, and the vias included in the second part (P2) include signal vias and a smaller number of ground vias than the signal vias, and are spaced apart from each other They can be spaced apart by a second interval greater than or equal to the first interval mentioned above.

[0193] In various embodiments, the first portion (P1) comprises a first via (V1, V4), a second via (V2, V5) spaced apart from the first via (V1, V4) in the extension direction (E) of the interposer (200), and a first pad (310, 330) connected to the first via (V1, V4) and the second via (V2, V5), and when viewed in the first direction, the first pad (310, 330) comprises a first region (311, 331) covering the end of the first via (V1, V4), a second region (312, 332) covering the end of the second via (V2, V5), and a third region (313, 333) connecting the first region (311, 331) and the second region (312, 332).

[0194] In various embodiments, the first pad (310) may be formed on the first surface (201) and the second surface (202) of the interposer (200), respectively, and configured to be mounted on the first substrate (150) and the second substrate (190), respectively.

[0195] In various embodiments, the first portion (P1) further includes a third via (V6) located between the first via (V4) and the second via (V5) and connected to the third region (333), and when viewed in the first direction, the third via (V6) may overlap at least partially with the third region (333).

[0196] In various embodiments, the first region (311, 331) may have a substantially circular or arc-shaped border and an area larger than the size of the first via hole of the first via (V1, V4), and the second region (312, 332) may have a substantially circular or arc-shaped border and an area larger than the size of the second via hole of the second via (V2, V5).

[0197] In various embodiments, the width of the third region (313, 333) is smaller than the maximum width of the first region (311, 331) or the second region (312, 332), and the width may be defined as a distance measured in a direction perpendicular to the extension direction (E) of the interposer (200).

[0198] In various embodiments, the first portion (P1) includes a fourth via (V10) spaced apart from the second via (V5) and a second pad (340) connected to the fourth via (V10), and an insulating region (232) of the cover layer (230) is formed between the second pad (340) and the second region (332) of the first pad (330), and the fourth via (V10) and the second via (V5) can be electrically connected through a conductive pattern (224) placed below the insulating region (232).

[0199] In various embodiments, the first portion (P1) further includes a fifth via (V11) located between the fourth via (V10) and the second via (V5) and in contact at least partially with the conductive pattern (224), and when the interposer (200) is viewed from the first direction, the fifth via (V11) may be obscured by the insulating region (232).

[0200] In various embodiments, the first substrate (150) or the second substrate (190) includes a first mounting area facing the first pad (310, 330) and the second pad (340) of the interposer (200), and a second mounting area facing the insulating area (231, 232) of the interposer (200), wherein the first mounting area is formed as a ground area and the second mounting area may include a pattern through which a signal other than a ground signal flows.

[0201] In various embodiments, the third via (V6) may include two or more third vias (402, 403) arranged in the width direction (W) perpendicular to the extension direction (E) of the interposer.

[0202] In various embodiments, the third via (402, 403) is formed to be longer in the width direction perpendicular to the extension direction than in the extension direction, and the third via hole of the third via may have a shape in which two via holes partially overlap.

[0203] In various embodiments, the fifth via (V11) may include two or more fifth vias (402, 403) arranged in the width direction (W) perpendicular to the extension direction (E) of the interposer.

[0204] In various embodiments, the fifth via (402, 403) is formed to be longer in the width direction perpendicular to the extension direction than in the extension direction, and the fifth via hole of the fifth via may have a shape in which two via holes partially overlap.

[0205] In various embodiments, the first gap may be 0.2 mm or less, and the second gap may be 0.5 mm to 0.8 mm.

[0206] In various embodiments, when the interposer is viewed from the first direction, the area occupied by the first part may be smaller than the area occupied by the second part.

[0207] In various embodiments, the number of vias included in the first part may be smaller than the number of vias included in the second part.

[0208] In various embodiments, the interposer (200) comprises a first surface (201) in contact with the first substrate (150) and a second surface (202) in contact with the second substrate (190), the first surface comprises a first conductive pad (510) coupled to the first substrate and a first insulating region (235) surrounding the first conductive pad, and the second surface comprises a second conductive pad (520, 530) coupled to the second substrate and a second insulating region (234) surrounding the second conductive pad, and vias included in the first portion (P1) include a first via (501) located between the first conductive pad (510) and the second conductive pad (521, 530) when viewed in the first direction, and a second via located between the first conductive pad (510) and the second insulating region (234). It may include a via (502), a third via (503) located between the first insulating region (235) and the second conductive pad (522), and a fourth via (V9, V11) located between the first insulating region (235) and the second insulating region (234).

[0209] In various embodiments, when viewed in the first direction, the first region of the first conductive pad (510) may partially face the second conductive pad (520), and when viewed in the first direction, the second region of the first conductive pad (510) may face the second insulating region (234).

[0210] In various embodiments, the first substrate includes a first conductive region soldered to the first conductive pad, and the second substrate includes a second conductive region soldered to the second conductive pad, and the first conductive region and the second conductive region may be at least partially offset when viewed in the first direction.

[0211] In various embodiments, the interposer (200) comprises an insulating cover layer (230) forming a surface (201, 202) of the interposer and a conductive layer (220) disposed below the cover layer, and the conductive layer may include a conductive pattern that extends to correspond to the first portion (P1) and is connected to each of the vias included in the first portion (P1).

[0212] The electronic device according to the various embodiments disclosed in this document may be a device of various forms. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device according to the embodiments of this document is not limited to the devices described above.

[0213] The various embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of said embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of said items unless the relevant context clearly indicates otherwise. In this document, each of phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B, or C" may include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. Terms such as “first,” “second,” or “first” or “second” may be used simply to distinguish a component from another component and do not limit the components in any other aspect (e.g., importance or order). Where any (e.g., first) component is referred to as “coupled” or “connected” to another (e.g., second) component, with or without the terms “functionally” or “communicationally,” it means that said component may be connected to said other component directly (e.g., wired), wirelessly, or through a third component.

[0214] The term “module” as used in the various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A module may be a component formed integrally, or a minimum unit of said component or a part thereof that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0215] Various embodiments of the present document may be implemented as software (e.g., program (1740)) comprising one or more instructions stored in a storage medium (e.g., internal memory (1736) or external memory (1738)) readable by a machine (e.g., electronic device (1701)). For example, a processor (e.g., processor (1720)) of the machine (e.g., electronic device (1701)) may call at least one of the one or more instructions stored from the storage medium and execute it. This enables the machine to be operated to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The storage medium readable by the machine may be provided in the form of a non-transitory storage medium. Here, 'non-temporary' simply means that the storage medium is a tangible device and does not contain a signal (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily.

[0216] According to one embodiment, the method according to the various embodiments disclosed herein may be provided by being included in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or distributed online (e.g., download or upload) through an application store (e.g., Play Store™) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0217] According to various embodiments, each component (e.g., module or program) of the components described above may include a singular or multiple entities, and some of the multiple entities may be separated and placed in other components. According to various embodiments, one or more of the components or operations among the aforementioned components may be omitted, or one or more other components or operations may be added. Generally or additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the corresponding component among the multiple components prior to integration. According to various embodiments, operations performed by the module, program, or other components may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

Claim 1 An electronic device comprising: a housing; a first substrate and a second substrate disposed within the housing and disposed to face each other; and an interposer extending to surround an internal space between the first substrate and the second substrate and electrically connected to the first substrate and the second substrate, wherein the interposer comprises a first portion forming an outer portion and a second portion forming an inner portion facing the internal space and surrounded by the first portion, wherein the first portion is configured to at least partially and electrically shield the second portion and the internal space from the outside of the interposer, and the interposer comprises signal vias for transmitting signals between the first substrate and the second substrate and ground vias connected to ground, wherein the number of ground vias included in the first portion is greater than the number of signal vias included in the first portion, and the number of signal vias included in the second portion is greater than the number of ground vias included in the second portion. Claim 2 An electronic device according to claim 1, wherein the first portion comprises a first via, a second via spaced apart from the first via in an extending direction of the interposer, and a first pad connected to the first via and the second via, and the first pad comprises a first region covering an end of the first via, a second region covering an end of the second via, and a third region extending between the first region and the second region. Claim 3 An electronic device according to claim 2, wherein the first pad is formed on one surface of the interposer facing the first substrate and is positioned to be in contact with the first substrate. Claim 4 An electronic device according to claim 2, wherein the first portion further comprises a third via located between the first via and the second via, and when viewed in a direction perpendicular to the first substrate, the third via at least partially overlaps the third region. Claim 5 An electronic device according to claim 2, wherein the area of ​​the first region is larger than the area of ​​the end of the first via, and the area of ​​the second region is larger than the area of ​​the end of the second via. Claim 6 An electronic device according to claim 2, wherein, when viewed in a direction perpendicular to the first substrate, the width of the third region is smaller than the maximum width of the first region or the second region. Claim 7 An electronic device according to claim 4, wherein the first portion comprises a fourth via spaced apart from the second via and a second pad connected to the fourth via, an insulating region of a cover layer is formed between the second pad and the second region of the first pad, and the fourth via and the second via are electrically connected through a conductive pattern disposed below the insulating region. Claim 8 An electronic device according to claim 7, wherein the first portion further comprises a fifth via located between the fourth via and the second via and in at least partial contact with the conductive pattern, and when the interposer is viewed in a direction perpendicular to the first substrate, the fifth via is obscured by the insulating region. Claim 9 An electronic device according to claim 8, wherein the first substrate or the second substrate comprises a first mounting region facing the first pad and the second pad of the interposer, and a second mounting region facing the insulating region of the interposer, wherein the first mounting region is formed as a ground region and the second mounting region comprises a pattern through which a signal other than a ground signal flows. Claim 10 An electronic device according to claim 4, wherein the third via comprises two or more third vias arranged in a width direction perpendicular to the extension direction of the interposer. Claim 11 An electronic device according to claim 4, wherein the third via is formed to be longer in the width direction perpendicular to the extension direction than in the extension direction of the interposer, and the third via hole of the third via has a shape in which two via holes partially overlap. Claim 12 An electronic device according to claim 8, wherein the fifth via comprises two or more fifth vias arranged in a width direction perpendicular to the extension direction of the interposer. Claim 13 An electronic device according to claim 8, wherein the fifth via is formed to be longer in the width direction perpendicular to the extension direction than in the extension direction, and the fifth via hole of the fifth via has a shape in which two via holes partially overlap. Claim 14 An electronic device according to claim 1, wherein the ground vias of the first portion are spaced apart by a first interval, and the ground vias of the second portion are spaced apart by a second interval greater than or equal to the first interval. Claim 15 An electronic device according to claim 1, wherein, when the interposer is viewed in a direction perpendicular to the first substrate, the area occupied by the first part is smaller than the area occupied by the second part. Claim 16 An electronic device according to claim 1, wherein the number of ground vias included in the first part is smaller than the number of ground vias included in the second part, which occupies a larger area than the first part. Claim 17 An electronic device according to claim 1, wherein the interposer comprises a first surface in contact with the first substrate and a second surface in contact with the second substrate, the first surface comprises a first conductive pad coupled to the first substrate and a first insulating region surrounding the first conductive pad, the second surface comprises a second conductive pad coupled to the second substrate and a second insulating region surrounding the second conductive pad, and the ground vias included in the first portion comprise, when viewed in a first direction perpendicular to the first substrate, a first via located between the first conductive pad and the second conductive pad, a second via located between the first conductive pad and the second insulating region, a third via located between the first insulating region and the second conductive pad, and a fourth via located between the first insulating region and the second insulating region. Claim 18 An electronic device according to claim 17, wherein, when viewed in the first direction, a first region of the first conductive pad partially faces the second conductive pad, and when viewed in the first direction, a second region of the first conductive pad faces the second insulating region. Claim 19 An electronic device according to claim 18, wherein the first substrate comprises a first conductive region soldered to the first conductive pad, and the second substrate comprises a second conductive region soldered to the second conductive pad, and the first conductive region and the second conductive region are at least partially offset when viewed in the first direction. Claim 20 An electronic device according to claim 1, wherein the interposer comprises an insulating cover layer forming the surface of the interposer and a conductive layer disposed below the cover layer, and the conductive layer comprises a conductive pattern extending to correspond to the first portion and connected to each of the ground vias included in the first portion.

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