Low-power driving method and apparatus for a display device with in-pixel memory based on data change detection

Abstract

A low-power driving method and device through data change detection in a display device equipped with pixel embedded memory are disclosed. The method of operation of the display device includes the steps of receiving a command from a host indicating that current frame data and previous frame data are identical; a display driver IC deactivating a frame data transmission path and maintaining an internal synchronization signal generated based on previous frame data; and a display panel performing a display operation based on the internal synchronization signal and previous frame data stored in the pixel embedded memory.

Description

Technology Field

[0001] The technical field relates to driving technology, specifically to a method and apparatus for enabling low-power driving through data change detection in a display device equipped with in-pixel memory. The present invention relates to a method and apparatus suitable for miniaturization in portable display devices such as smartphones, smartwatches, augmented reality (AR), mixed reality (MR), and extended reality (XR) devices, which can reduce power consumption and minimize data transmission volume. Background Technology

[0002] Display devices can be applied to a wide range of fields, from small mobile devices to large outdoor displays. In particular, displays are being utilized in even more diverse fields, such as various devices in vehicles, AR (Augmented Reality), MR (Mixed Reality), and XR (Extended Reality) devices.

[0003] Display systems require high-resolution displays, and at the same time, miniaturization and low-power operation may be essential. In the case of display driving, power consumption may increase because the system operates by newly recording, saving, and scanning the entire image frame even when there is no image change or when there is an image change only in a part of the screen.

[0004] For example, in the case of AR devices, low-power operation through partial display control may be required because applications displaying simple information such as text or indicators may be primarily used.

[0005] Meanwhile, a display system according to the prior art uses a method of storing frame data transmitted from a host processor (AP) in a frame memory within a display driver IC (DDIC) and then outputting it to a display panel. However, as high-resolution displays have become commonplace, the size of frame data has increased rapidly, which can lead to problems such as a significant increase in the physical size of the frame memory and power consumption.

[0006] In particular, in ultra-small display devices such as AR / MR / XR devices, the size of the frame memory can act as a major constraint on the miniaturization of the display driving circuit.

[0007] In addition, as artificial intelligence capabilities are integrated into mobile devices, the processing burden on Application Processors (APs) is increasing, and efficient methods to alleviate this may be required. The problem to be solved

[0008] The technical problem of the present invention is to provide a method and apparatus that enable the miniaturization of a driving circuit in a display device requiring ultra-small and low-power driving through the embodiments.

[0009] Another technical objective of the present invention is to provide a method and apparatus capable of minimizing image data traffic transmitted from a host and reducing power consumption.

[0010] These tasks are exemplary and do not limit the scope of the invention. means of solving the problem

[0011] A method of operation of a display device including a display driver IC and a display panel according to one embodiment comprises: receiving a command from a host indicating that current frame data and previous frame data are identical; the display driver IC deactivating a frame data transmission path and maintaining an internal synchronization signal generated based on previous frame data; and the display panel performing a display operation based on the internal synchronization signal and previous frame data stored in a pixel embedded memory.

[0012] The above command may be a Panel Self Refresh (PSR) command.

[0013] The above command may be transmitted via the eDP (Embedded DisplayPort) protocol.

[0014] Disabling the above frame data transmission path may include disabling the reception of frame data from the host and disabling internal data transmission, excluding the synchronization signal generation control signal of the display driver IC.

[0015] The above-mentioned in-pixel memory may be Static Random Access Memory (SRAM) embedded in each pixel.

[0016] The above host can determine that there is no change in frame data by comparing the hash values ​​of the previous frame data and the current frame data.

[0017] After receiving a command indicating that there is no change in frame data, the above display driver IC enters Low Power Mode, and after a preset time has elapsed, it can transmit an interrupt signal to the host to check whether to transmit frame data.

[0018] A method of operation of a display device according to another embodiment includes the step of receiving a sync signal from a host without frame data; the step of a display driver IC deactivating a frame data transmission path and synchronizing an internal sync signal generated based on previous frame data with the sync signal received from the host; and the step of a display panel refreshing a screen based on the updated internal sync signal and previous frame data stored in a pixel embedded memory.

[0019] The step of receiving the synchronization signal may include: a step of determining whether frame data has been received if the synchronization signal is received at the current frame data transmission time; and a step of determining that the synchronization signal has been received without the frame data if the frame data is not received within a preset time.

[0020] A display driving device according to one embodiment includes: a receiving interface that receives a command from a host indicating no change in frame data; an interface control unit that generates a control signal instructing to disable a frame data transmission path connected to the receiving interface and to maintain an internal synchronization signal generated based on previous frame data; and a logic controller that, upon receiving the control signal, controls the display panel to refresh the screen of the display panel based on the internal synchronization signal and the previous frame data stored in the pixel embedded memory.

[0021] The above display driving device may not require a frame memory for storing frame data.

[0022] A display driving device according to another embodiment includes: a receiving interface that receives a sync signal without frame data from a host; an interface control unit that generates a control signal instructing to disable a frame data transmission path connected to the receiving interface and to synchronize an internal sync signal generated based on previous frame data with the sync signal received from the host; and a logic controller that, upon receiving the control signal, controls the display panel to refresh the screen of the display panel based on the updated internal sync signal and the previous frame data stored in the pixel embedded memory.

[0023] A driving method for a display device according to another embodiment includes: receiving current frame data from a host; comparing an attribute value for the current frame data with an attribute value for the previous frame data; deactivating a frame data transmission path when the attribute value for the current frame data and the attribute value for the previous frame data are the same; and refreshing a screen based on the previous frame data stored in a pixel built-in memory.

[0024] If the above attribute value is a hash value, the hash value for the current frame data can be calculated and compared with the hash value of the previous frame data.

[0025] If the above attribute value is a frame number or metadata, the attribute value for the current frame data is received from the host, and whether they are the same can be determined by comparing the frame number or metadata of the current frame data with that of the previous frame data.

[0026] The display driver IC can update an internal synchronization signal generated based on the previous frame data based on a synchronization signal included in the current frame data when the attribute value for the current frame data and the attribute value for the previous frame data are the same.

[0027] A display driving device according to another embodiment includes: a receiving interface for receiving current frame data from a host; a comparator that determines whether the attribute value of the current frame data is the same by comparing the attribute value of the previous frame data stored in an attribute value memory and, if the attribute value of the current frame data and the attribute value of the previous frame data are the same, generates a control signal that instructs to disable the frame data transmission path; and a logic controller that controls the display panel to refresh the screen based on the previous frame data stored in the pixel embedded memory upon receiving the control signal.

[0028] A method of operation of a display device according to another embodiment comprises: receiving a low-power mode command from a host; after receiving the low-power mode command, the display driver IC enters a low-power mode; receiving information from the host indicating no change to the entire frame data or a change to some data; and updating a screen according to the information received from the host, wherein the information indicating a change to some data includes image data of the changed area and location information for the changed area, and the step of updating the screen includes updating the changed image data in a pixel embedded memory corresponding to the location information; and the display panel updating the screen based on data stored in the pixel embedded memory.

[0029] A display driving device according to another embodiment includes: a receiving interface that receives a low-power mode command from a host; a comparator that is activated to perform a comparison operation upon receiving the low-power mode command and compares an attribute value for current frame data with an attribute value for previous frame data; and a logic controller that controls the display panel to refresh the screen of the display panel using the previous frame data stored in the pixel embedded memory when the attribute value for current frame data and the attribute value for previous frame data are the same. Effects of the invention

[0030] According to an embodiment of the present invention, by storing frame data transmitted from a host processor in the internal pixel memory of a display panel, the frame memory is not necessarily required. Therefore, miniaturization and low power consumption of the driving circuit are possible through the elimination of the frame memory.

[0031] In addition, it has the effect of minimizing image data traffic between the host and the display driving circuit and improving system processing speed.

[0032] In addition, display efficiency can be improved by reducing data traffic and power consumption of the entire system.

[0033] In addition, the operational load of the AP (Application Processor) can be reduced by minimizing processing for image processing and transmission. Brief explanation of the drawing

[0034] FIG. 1 is a drawing for explaining an example of a display system according to the prior art. FIG. 2 is a drawing for explaining an example of a display system according to one embodiment. FIG. 3 is a drawing for explaining another example of a display system according to one embodiment. FIG. 4 is a drawing for explaining an example of a display driving device according to one embodiment. FIG. 5 is a diagram illustrating the configuration of a logic controller according to one embodiment. FIG. 6 is a drawing for explaining an example of a method of operating a display device according to one embodiment. FIGS. 7 and FIGS. 8 are drawings for illustrating an example of a frame data comparison method according to one embodiment. FIG. 9 is a drawing for explaining another example of a display device operation method according to one embodiment. FIG. 10 is a drawing for explaining another example of a display device operation method according to one embodiment. FIGS. 11 and FIGS. 12 are drawings for explaining a timing signal and a display control according to one embodiment. FIG. 13 is a diagram illustrating the pixel operation of a display panel according to one embodiment. FIG. 14 is a flowchart illustrating a display control method for low-power driving according to one embodiment. FIGS. 15 and 16 are drawings for illustrating an example of a pixel driving circuit according to one embodiment. FIG. 17 is a drawing for explaining another example of a display system according to one embodiment. Specific details for implementing the invention

[0035] Structural or functional descriptions are provided merely for the purpose of illustrating embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and are not limited to the embodiments described herein.

[0036] Embodiments according to the concept of the present invention may be subject to various modifications and may take various forms; therefore, embodiments are illustrated in the drawings and described in detail in this specification. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosed forms, and includes modifications, equivalents, or substitutions that fall within the spirit and scope of the present invention.

[0037] Terms such as "first" or "second" may be used to describe various components, but said components should not be limited by said terms. For the sole purpose of distinguishing one component from another, for example, without departing from the scope of rights according to the concept of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component.

[0038] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. Conversely, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between. Expressions describing the relationships between components, such as "between," "exactly between," or "directly adjacent to," should be interpreted in the same way.

[0039] The terms used herein are used merely to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as “comprising” or “having” are intended to specify the existence of the described features, numbers, steps, actions, components, parts, or combinations thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0040] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification.

[0042] Hereinafter, embodiments will be described in detail with reference to the attached drawings. However, the scope of the patent application is not limited or restricted by these embodiments. Identical reference numerals provided in each drawing indicate identical components. In this specification, the term "display device" may collectively refer to a display driver IC and a display.

[0044] FIG. 1 is a drawing for explaining an example of a display system according to the prior art.

[0045] Referring to FIG. 1, the display system includes a host (110), a display driver IC (120), and a display panel (130).

[0046] The host (110) can be implemented as a system on chip (SoC), an application processor (AP), or a mobile AP.

[0047] The host (110) can transmit frame data to the display driver IC (120).

[0048] Referring to FIG. 1, the display driver IC (120) includes a frame memory (125).

[0049] The frame memory (125) stores current frame data and is used when updating the panel. Therefore, the structure according to the prior art is a structure in which the frame memory (125) is essentially required.

[0050] However, in a micro-display environment such as an AR (augmented reality) device, the frame memory (125) inside the display driver IC (120) limits the area of ​​the active area and causes an increase in the size of the control logic, making it difficult to miniaturize.

[0051] In addition, frequent refresh operations of the panel using frame memory (125) can cause increased power consumption.

[0053] FIG. 2 is a drawing for explaining an example of a display system according to one embodiment.

[0054] Referring to FIG. 2, a display system according to one embodiment includes a host (210), a display driver IC (220), and a pixel embedded memory type display panel (230). Hereinafter, the 'pixel embedded memory type display panel' may simply be referred to as a 'display panel'.

[0055] In this specification, 'display driver IC' may be referred to as 'DDIC', 'backplane hardware logic', 'display driving device', or 'display control device'. Additionally, 'display driver IC' and 'display panel' may be collectively referred to as 'display device' or 'display module'.

[0056] Unlike FIG. 1, the display system according to one embodiment has a structure in which the frame memory is removed and a digital pixel embedded memory is utilized to store 1 to 10 bits of grayscale data.

[0057] A display system according to one embodiment has a structure that does not necessarily include a frame memory for storing frame data in a display driver IC (220). Accordingly, a display driving device according to one embodiment can be designed to operate without a frame memory.

[0058] The host (210) may include a processor and may run firmware or software to support a video stream interface.

[0059] The host (210) can control the display driver IC (220). The host (210) can support a video stream interface.

[0060] The host (210) or display driver IC (220) may include a detection and control block (215, 225) that detects whether image data is updated on a frame-by-frame basis and performs a control operation accordingly.

[0061] When the host (210) determines whether to update the frame data, the detection and control block (215) can perform an error check on the data of the current frame F(t+1) based on the data of the previous frame F(t).

[0062] Additionally, when the display driver IC (220) determines whether the frame data is updated, the detection and control block (225) can perform an error check on the data of the current frame F(t+1) based on the data of the previous frame F(t).

[0063] For example, error checking methods such as parity checking, checksum checking, Cyclic Redundancy Check (CRC), Secure Hash Algorithm (SHA), and Hamming code checking can be used.

[0064] A display panel (230) may be a panel composed of multiple pixels, wherein a plurality of light-emitting elements and a pixel circuit driving the light-emitting elements form individual pixels. Each pixel included in the display panel (230) may include an internal memory (231) capable of storing digital data internally. The internal memory (231) may be referred to as a 'pixel internal memory'. The pixel internal memory can store image data and may be implemented as a DRAM, SRAM, flip-flop, latch, or shift register.

[0065] The display panel (230) may include a plurality of pixels arranged in a predetermined pattern, for example, a matrix type, a zigzag type, or various other patterns. The pixels emit a single color, for example, one of red, blue, green, or white. The pixels may also emit a color other than red, blue, green, or white.

[0066] Pixels can operate on a frame basis. A single frame may consist of multiple subframes. Each subframe may include a data write period and an emission period. During the data write period, a predetermined number of bits of digital data may be stored in the memory contained within the pixel. During the emission period, the digital data of a predetermined number of bits stored is read in synchronization with a clock signal, and the digital data is converted into a PWM signal so that the pixel can express a grayscale. The emission period of a subframe may be the sum of the times allocated to each bit of the digital data.

[0068] FIG. 3 is a drawing for explaining another example of a display system according to one embodiment.

[0069] The example illustrated in FIG. 3 shows an example of detecting whether frame data is updated in the host (310).

[0070] The host (310) may include a host control unit (311) and a transmission interface (313). Meanwhile, the host (310) according to one embodiment may include an application processor (AP), an AP buffer, and a display controller as shown in FIG. 17.

[0071] The host control unit (311) may include a processor and may run firmware or software to support a video stream interface.

[0072] The transmission interface (313) can perform interface functions that support a video stream interface. The transmission interface (313) can support MIPI, eDP, or a high-speed serial interface.

[0073] The transmission interface (313) can transmit image data, video data, and timing signals to the display driving device (320). At this time, the timing signal may include at least one of a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal, and a data enable signal.

[0074] The arrows shown as dotted lines in Fig. 3 indicate that the path may not be used for its intended purpose if there is no change in data. For example, video stream transmission labeled 'DPAC' may not be performed if there is no change in frame data.

[0075] The display driving device (320) includes a receiving interface (321), an interface control unit (301), and a logic controller (323). The display driving device (320) may further include a panel interface (333).

[0076] The receiving interface (321) can receive a video stream and a timing signal transmitted from the host (310). In FIG. 3, the timing signal is represented as 'CLKm'. The timing signal may be a clock signal. The receiving interface (321) can recover data (DATA) using the clock signal, and the clock signal may be bypassed to the logic controller (323).

[0077] The receiving interface (321) can receive a command (hereinafter simply referred to as 'command') from the host (310) indicating that there is no change to the frame data. Additionally, the receiving interface (321) can receive a timing signal that reflects display position information requiring an update in the entire frame data. At this time, the receiving interface (321) may also receive frame data corresponding to the timing signal.

[0078] In one embodiment, the receiving interface (321) can recover a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (DE), and data (DATA) from a video stream. In this case, the vertical sync signal and the horizontal sync signal may be received separately from the video stream. The clock signal may be bypassed to the logic controller (323), but is not limited thereto. In this case, the data enable signal (DE) is an indicator signal indicating valid data, and the data is valid when the data enable signal (DE) is enabled and invalid when it is disabled.

[0079] The 'command' may be a command indicating that the current frame data and the previous frame data are identical. In this case, the command may be, for example, a Panel Self Refresh (PSR) command. The command may be transmitted via the eDP (Embedded DisplayPort) protocol.

[0080] When a command is received by the receiving interface (321), the interface control unit (301) can disable the frame data transmission path connected to the receiving interface (321).

[0081] At this time, the frame data transmission path connected to the receiving interface (321) includes the arrow labeled 'DATA' in FIG. 3. When no frame data change is received from the host (310), the receiving interface (321) may stop receiving the video stream and block the data transmission path inside the display driving device (320).

[0082] If there is no change in the frame data, the interface control unit (301) can generate a control signal that instructs to maintain an internal synchronization signal generated based on the previous frame data.

[0083] The control signal can be transmitted from the interface control unit (301) to the logic controller (323). In FIG. 3, the control signal is represented as 'CTL'. The reason the path for transmitting the control signal is shown as a dotted line is to indicate that the path is used only when there is no change in frame data.

[0084] When the logic controller (323) receives a control signal, it can control the panel interface (333) and the display panel to refresh the screen of the display panel based on an internal synchronization signal generated based on previous frame data and previous frame data stored in the pixel built-in memory. In FIG. 3, the internal synchronization signal is represented as 'i-Sync'.

[0085] The panel interface (333) can transmit video data input during the enable interval of the timing signal to the display panel to write to the corresponding pixel location within the display panel.

[0086] The panel interface (333) can transmit an internal synchronization signal generated based on previous frame data to the display panel so that the screen of the display panel is refreshed using previous frame data stored in the pixel internal memory when there is no change in frame data.

[0087] The panel interface (333) may include a line buffer or a shift register.

[0088] The panel interface (333) can write analog signals corresponding to display data and can scan the written signals and transmit them to data lines provided in the display panel.

[0089] Referring to FIG. 3, the display driving device (320) has a structure that does not necessarily include a frame memory for storing frame data.

[0090] Meanwhile, in one embodiment, the host (310) may transmit only a sync signal to the receiving interface (321) without transmitting frame data, instead of a command indicating no frame change.

[0091] In this embodiment, the receiving interface (321) receives a synchronization signal from the host (310) without frame data, and the interface control unit (301) disables the frame data transmission path and generates a control signal to synchronize the previously generated internal synchronization signal with the synchronization signal received from the host.

[0092] The generated control signal is transmitted to the logic controller (323), and the logic controller (323) can control the panel interface (333) and the display panel to update the screen based on the updated internal synchronization signal and the previous frame data stored in the pixel internal memory.

[0093] In FIG. 3, the internal synchronization signal (i-Sync) is updated in a form synchronized with the received synchronization signal (Sync Signal) and is transmitted to the display panel through the panel interface (333) to update the screen.

[0094] This method allows the screen to be updated without transmitting frame data, thereby reducing unnecessary data transmission and providing the effect of reducing data traffic between the AP and the DDIC.

[0096] FIG. 4 is a drawing for explaining an example of a display driving device according to one embodiment.

[0097] The example illustrated in FIG. 4 shows an example of detecting whether frame data is updated in a display driving device (400).

[0098] Referring to FIG. 4, the display driving device (400) includes a receiving interface (410), a comparator (420), and a logic controller (430). It may further include an attribute value memory (460), a path control unit (421), and a panel interface (440).

[0099] The receiving interface (410) receives the current frame data.

[0100] The receiving interface (410) can receive a video stream and a timing signal transmitted from a host. In FIG. 4, the timing signal is represented as 'CLKm'. The timing signal may be a clock signal. The receiving interface (410) can recover data (DATA) using the clock signal, and the clock signal may be bypassed to a logic controller (430).

[0101] In one embodiment, the receiving interface (410) can recover a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (DE), and data (DATA) from a video stream. In this case, the vertical sync signal and the horizontal sync signal may be received separately from the video stream. The clock signal may be bypassed to the logic controller (430), but is not limited thereto. In this case, the data enable signal (DE) is an indicator signal indicating valid data, where the data is valid when the data enable signal (DE) is enabled and invalid when it is disabled.

[0102] The comparator (420) can determine whether the frame data is identical by comparing the attribute value of the current frame data with the attribute value of the previous frame data. Here, the attribute value can be set to one of the data integrity detection methods, such as a hash value, frame number, checksum, cyclic redundancy check (CRC), secure hash algorithm (SHA), or Hamming code.

[0103] When the comparator (420) receives frame data, it calculates an attribute value and can store the calculated attribute value in the attribute value memory (460).

[0104] If the attribute value is a hash value, the comparator (420) can calculate the hash value for the current frame data and determine whether it is the same by comparing it with the hash value of the previous frame data.

[0105] When the attribute value of the current frame data and the attribute value of the previous frame data are the same, the comparator (420) generates a control signal instructing the frame data transmission path to be disabled. At this time, the comparator (420) generates a control signal instructing the frame data transmission path to be disabled. After blocking the frame data transmission path, the comparator (420) can directly transmit the control signal to the logic controller (430). Additionally, the comparator (420) can transmit the control signal to the path control unit (421). In FIG. 4, the control signal is represented as 'CTL'. At this time, the screen update of the display panel is performed using the previous frame data stored in the existing pixel internal memory.

[0106] If the attribute value of the current frame data and the attribute value of the previous frame data are different, the comparator (420) may instruct the path control unit (421) to maintain the frame data transmission. At this time, the comparator (420) transmits the new frame data received through the receiving interface (410) to the logic controller (430), and the display panel can update the screen by writing the new frame data to the pixel built-in memory.

[0107] When the logic controller (430) receives a control signal, it controls the panel interface (440) and the display panel to update the screen using previous frame data stored in the existing pixel internal memory.

[0108] The attribute value memory (460) stores attribute values ​​for frame data. The attribute values ​​can be updated and stored for each frame. The attribute value memory (460) can be implemented as an SRAM, flip-flop, latch, or shift register, etc.

[0109] The path control unit (421) can prevent unnecessary data transmission and reduce power consumption by blocking the frame data transmission path when it receives a control signal.

[0110] If the frame data is changed, the path control unit (421) can control the path so that the currently received frame data is output to the logic controller (430). Alternatively, the frame data can be directly transmitted from the comparator (420) to the logic controller (430).

[0111] The panel interface (440) can transmit video data input during the enable interval of the timing signal to the display panel to write to the corresponding pixel location within the display panel.

[0112] Meanwhile, in one embodiment, the comparator (420) may be configured to be activated only when the system is operating in low-power mode. In this case, when not in low-power mode, the receiving interface (410) may be directly connected to the logic controller (430). In this embodiment, the receiving interface (410) may activate the comparator (420) when it receives a low-power mode command from the host. In this case, when the comparator (420) receives the low-power mode command, it is activated to perform a comparison operation and may perform an operation to compare the attribute value of the current frame data with the attribute value of the previous frame data.

[0114] FIG. 5 is a diagram illustrating the configuration of a logic controller according to one embodiment.

[0115] Referring to FIG. 5, the logic controller (500) may include a data controller (510) and a timing controller (520). The line buffer (530) shown in FIG. 5 may be the panel interface (333, 440) of FIG. 3 or FIG. 4.

[0116] First, we examine the operation of the logic controller (500) when the frame data changes, and the operation of the logic controller (500) when there is no change in the frame data.

[0117] <When frame data changes: Normal operation mode>

[0118] The data controller (510) can generate a data enable signal (DE') using an internal clock signal CLK and transmit the data enable signal (DE') and data (DATA) to the timing controller (520). The data enable signal (DE') can function as an indicator signal that indicates the valid interval of the data (DATA).

[0119] The oscillator (540) generates an internal clock (fosc). The timing controller (520) can generate signals (e.g., CLK, iVsync, and iHsync) based on the internal clock (fosc).

[0120] The timing controller (520) may include a control signal generator (523) and an image processing module (521).

[0121] As an example, the control signal generator (523) can generate a clock (CLK) based on an internal clock (fosc). The clock (CLK) can be generated using the internal clock (fosc), and the frequency of the clock (CLK) and the frequency of the internal clock (fosc) may be the same or different from each other.

[0122] As another example, the control signal generator (523) may further generate an internal vertical synchronization signal (iVsync) and an internal horizontal synchronization signal (iHsync) based on an internal clock (fosc). The internal vertical synchronization signal (iVsync) may be a vertical synchronization signal related to the display of display data (DDATA), and the internal horizontal synchronization signal (iHsync) may be a horizontal synchronization signal related to the display of display data (DDATA).

[0123] The image processing module (521) receives a clock (CLK), a data enable signal (DE'), and data (DATA), processes the read data (DATA) using the clock (CLK) and the data enable signal (DE'), and generates a data enable signal (DDE) and display data (DDATA) as a result of the processing. At this time, the display data DDATA is n-bit data corresponding to the pixel values ​​of each pixel of the display panel.

[0124] The data enable signal (DDE) can perform the function of an indicator signal that indicates the valid interval of the display data (DDATA).

[0125] For example, the image processing module (521) can perform image enhancement and / or image editing functions. For example, the image processing module (521) can adjust the brightness, contrast, saturation, or sharpness of the data (DATA) and generate display data (DDATA) corresponding to the result of the adjustment.

[0126] A line buffer (530) or a shift register can receive a data enable signal (DDE) and display data (DDATA) and transmit a corresponding signal to a display panel.

[0127] For example, the line buffer (530) can write analog signals corresponding to display data (DDATA) and scan the written signals to transmit them to data lines placed on the display panel.

[0128] Specifically, the line buffer (530) can write data (DDATA) in response to a clock (CLK) and a data enable signal (DDE) that is periodically activated. More specifically, the line buffer (530) can write data (DDATA) when the data enable signal (DDE) is activated or turned on.

[0129] As an example, the line buffer (530) can perform a scan operation in response to an internal vertical synchronization signal (iVsync) and an internal horizontal synchronization signal (iHsync). The scan operation means the line buffer (530) reads data (DATA) and transmits the read data (DATA) to a display panel.

[0130] The line buffer (530) can write data (DDATA). Specifically, the line buffer (530) can write data (DATA) whenever the data enable signal (DDE) is activated.

[0131] The line buffer (530) can scan stored data (DATA) in response to an internal horizontal synchronization signal (iHsync) and transmit it to a display panel. Specifically, whenever the internal horizontal synchronization signal (iHsync) is disabled, the line buffer (530) reads and scans the written data and transmits it to a display panel (400), and the display panel can write the data to memory within the pixel.

[0132] The display panel can read and display data (DATA) stored in pixel memory in response to the internal horizontal synchronization signal (iHsync). Specifically, the display panel can display the written data whenever the internal horizontal synchronization signal (iHsync) is activated.

[0133] <When frame data is not changed: Low-power operation mode>

[0134] If the previous frame data and the currently received frame data are the same, the data controller (510) and the image processing module (521) may stop operations or perform only some operations. Accordingly, the frame data transmission path within the display driving device may be blocked, and power consumption may be reduced. For example, the frame data transmission path may include paths represented as 'DATA' and 'DDATA' in FIG. 5.

[0135] When a control signal (e.g., CTL') that maintains the synchronization signal of an existing frame is received, the control signal generator (523) may not generate a new internal synchronization signal and may output the synchronization signal used in the previous frame to the line buffer (530).

[0136] Meanwhile, the logic controller (500) enters Low Power Mode after receiving a command indicating that there is no change in frame data, and can send an interrupt signal to the host to check whether to transmit frame data after a preset time has elapsed. For example, it can send an interrupt signal to the host after the number of times the screen refreshes itself or after a preset time has elapsed.

[0138] FIG. 6 is a drawing for explaining an example of a method of operating a display device according to one embodiment.

[0139] The method illustrated in Fig. 6 can be performed by the system illustrated in Fig. 3.

[0140] Referring to Fig. 6, in step 610, the host checks whether to update the frame data by performing an error check on the data of the current frame F(t+1) based on the data of the previous frame F(t).

[0141] As previously explained, the update check of the current frame compared to the previous frame can be performed by comparing the attribute value of the data in the current frame F(t) with the attribute value of the data in the previous frame F(t+1) to determine whether the frame data is identical. Here, the attribute value can be set to one of the data integrity detection methods, such as a hash value, frame number, checksum, Cyclic Redundancy Check (CRC), Secure Hash Algorithm (SHA), or Hamming code.

[0142] If F(t) and F(t+1) are the same, low-power mode is performed at step 620, otherwise, normal mode is operated at step 630.

[0143] In step 621, the DDIC can receive a signal from the host indicating a low-power mode. The signal indicating a low-power mode may be any one of a 'command indicating that the current frame data and the previous frame data are the same', a mutually agreed 'low-power mode entry command', or 'reception of a synchronization signal without frame data'.

[0144] In step 623, when the DDIC receives a signal indicating low-power mode, it performs low-power mode operation.

[0145] For example, when the DDIC receives a PSR command, it may disable the frame data transmission path and maintain an internal synchronization signal generated based on the previous frame data. At this time, disabling the frame data transmission path may include disabling the reception of frame data from the host and disabling internal data transmission, excluding the synchronization signal generation control signal of the display driver IC.

[0146] The display panel performs display operations based on an internal synchronization signal and previous frame data stored in the pixel internal memory. For example, the display panel may retain previous frame data stored in the pixel internal memory at step 625 and perform panel self-refresh at step 627.

[0147] Additionally, when the DDIC receives a synchronization signal from the host without frame data, it can disable the frame data transmission path and update the internal synchronization signal generated based on the previous frame data. For example, the DDIC can synchronize the existing internal synchronization signal with the synchronization signal received from the host. For example, the DDIC can generate the internal synchronization signal by synchronizing with the MIPI signal based on the clock generated by the internal oscillator.

[0148] At this time, the display panel can refresh the screen based on the updated internal synchronization signal and previous frame data stored in the pixel's built-in memory.

[0149] For example, 'synchronization of the internal synchronization signal' may involve adjusting the timing of the internal synchronization signal based on a synchronization signal received from the host. Additionally, it may involve detecting the phase of the host synchronization signal and adjusting the phase of the internal synchronization signal according to the detected phase. Furthermore, it may involve measuring the frequency of the host synchronization signal and correcting the frequency of the internal synchronization signal according to the measured frequency. It may also involve performing synchronization by initializing the internal synchronization signal whenever a specific synchronization signal event is received from the host.

[0150] Meanwhile, if the DDIC receives a synchronization signal from the host at the current frame data transmission time, it determines whether the frame data has been received, and if the frame data is not received within a preset time, it may determine that the synchronization signal has been received without the frame data. The synchronization signal received from the host may include a vertical synchronization signal (Vsync) and a horizontal synchronization signal (Hsync).

[0151] In the normal mode of step 630, the host may or may not send a command to the DDIC indicating that it is in normal mode. In step 633, the DDIC receives a data stream of the current frame F(t+1) from the host. In step 635, the display panel updates the data in the pixel memory, and in step 637, the screen may be refreshed.

[0153] FIGS. 7 and FIGS. 8 are drawings for illustrating an example of a frame data comparison method according to one embodiment.

[0154] The host processor can utilize a hash comparison method to verify whether new frame data is identical to the previous frame data. First, the host calculates the hash value of the corresponding image before processing the new frame data. The hash function converts the image into a unique string, and identical images generate the same hash value. Subsequently, when new frame data arrives, the hash value of the image is calculated and compared with the hash value of the previous frame data. If the hash values ​​match, it is determined that the image has not changed, so data transmission is omitted and the existing frame data is maintained. On the other hand, if the hash values ​​differ, the new frame data is transmitted to update the display.

[0155] Figure 7 shows an example of a pseudo-code for generating a hash value of a 2x2 pixel grayscale image. Referring to Figure 7, the process of generating a SHA-256 hash value using each pixel value of the 2x2 pixels, which are the first row [255, 0] and the second row [0, 255].

[0156] Figure 8 shows an example of calculating a hash value using an image processing library example.

[0157] Referring to Fig. 8, the process of generating a hash value is performed by first receiving image data, converting it into a one-dimensional byte array, and then applying it to a hash function to generate a hash value of a fixed size. In general, in addition to comparing the entire image data, partial image comparison is also possible. If one wishes to compare only a specific area, the data of that area can be extracted and a checksum calculated. Additionally, to improve the accuracy of image comparison, methods to normalize the image by performing preprocessing such as noise removal and resizing can also be applied.

[0158] Image processing libraries such as OpenCV (Open Source Computer Vision Library) or PIL (Python Imaging Library) can be utilized in the process of generating hash values ​​from image data. For example, using OpenCV, an image can be converted to grayscale to reduce color information, transformed into a one-dimensional array, and then a hash function applied. This method is more efficient than directly comparing the entire image data and is suitable for quickly identifying identical images.

[0159] As such, comparison methods utilizing hash values ​​are effective in minimizing computational load and reducing unnecessary data transmission while maintaining data comparison accuracy. In particular, they support fast and reliable identity verification in environments where large volumes of digital images are processed, and can be utilized in display systems to detect changes in frame data and prevent unnecessary data updates.

[0160] To generate a hash value, an appropriate hash function must be selected. Commonly used hash functions include MD5, SHA-1, SHA-256, and SHA-512, and a suitable function can be selected depending on the purpose.

[0161] If the host processor determines that the frame data has not changed, it may notify the display driver to prevent unnecessary data transmission. Methods for this include 'transmitting a special command signal (Control Signal)' or utilizing 'frame numbers' and 'timestamps'.

[0162] In the special command signal transmission method, the host processor can utilize the Panel Self Refresh (PSR) command (eDP v1.5, etc.) to convey to the display driver that the "image is identical." The host processor generates a special control signal indicating that the "current frame is identical to the previous frame" and transmits it to the display driver; upon receiving this, the display driver can refresh the screen while maintaining the existing frame data without receiving new frame data. For example, commands such as "Frame Hold," "No Data Update," and "Skip Frame Transmission" may be used. By utilizing the PSR command, the display driver can perform screen refreshes autonomously, thereby reducing unnecessary power consumption.

[0163] In PSR (Panel Self Refresh) mode, the display panel can maintain frame synchronization without Vsync and Hsync signals. This is because it refreshes the screen by utilizing frame data stored in the panel's own memory, further reducing power consumption by minimizing the transmission of unnecessary synchronization signals.

[0164] In PSR mode, frame synchronization can be maintained through various methods. The first is the method utilizing an internal timer. The panel uses a built-in timer to refresh the screen at a constant interval, enabling screen updates to be performed while maintaining a consistent cycle even in the absence of Vsync and Hsync signals.

[0165] Second is the method using a frame buffer. This approach refreshes the screen by utilizing frame buffer data stored in the panel's memory; when maintaining the same image without dynamic changes, it can provide consistent screen output without a separate synchronization signal.

[0166] Third, there is an integrity verification method using Cyclic Redundancy Check (CRC). The panel periodically performs CRC checks to verify the integrity of frame data and guarantees that the data has not been altered. This allows for maintaining screen consistency even in PSR mode and prevents unexpected data modifications.

[0167] Through these methods, stable frame synchronization can be maintained even in PSR mode, and power efficiency can be maximized compared to existing synchronization signal-based methods.

[0168] PSR commands are defined in the eDP (Embedded DisplayPort) standard and are transmitted to the panel through a specific packet structure. The packet structure of a PSR command consists of the following elements.

[0169] Packet header: The part that signals the start of the packet and contains information such as the packet type and length.

[0170] Command Code: A code that identifies a PSR command, enabling the display driver to interpret and execute the command.

[0171] Data Field: Contains specific data for controlling the PSR function. For example, it may include the PSR enable / disable status, PSR mode switching conditions, current PSR status information, etc.

[0172] Checksum: A value used to verify the integrity of packet data, serving the role of checking whether an error occurred during data transmission.

[0173] The host processor may recognize identical images using frame numbers or timestamps. The display driver can verify through the received frame number or timestamp that the frame data has not changed and retain the existing frame data. For example, if a new frame is identical to an existing frame, the host processor may transmit the timestamp of the previous frame as is to indicate that there is no data change. If the received frame number is identical to the previous frame, the display driver skips the transmission of new data and retains the existing data.

[0174] A method in which the host determines whether images are identical and controls the transmission of frame data if they are identical can reduce data traffic between the AP and DDIC by blocking unnecessary data transmission. Additionally, by reducing unnecessary computations within the display driver, it enables low-power operation and is expected to minimize overall power consumption. This approach can be particularly advantageous in environments where battery efficiency is critical, such as mobile and wearable devices.

[0176] FIG. 9 is a drawing for explaining another example of a display device operation method according to one embodiment.

[0177] The method illustrated in Fig. 9 can be performed by the system illustrated in Fig. 4.

[0178] Referring to Fig. 9, in step 910, the DDIC receives the current frame data F(t) from the host.

[0179] In step 920, the DDIC checks whether to update by comparing the previous frame data F(t-1) and F(t). If F(t-1) and F(t) are not the same, data and synchronization signals are transmitted to the display panel in step 930, and the pixel embedded memory data can be updated in step 935.

[0180] DDIC receives frame data F(t+1) at step 940 and checks for frame data updates at step 950. At this time, DDIC compares the attribute value of frame data F(t+1) with the attribute value of F(t). If the attribute value is a hash value, it can calculate the hash value of the current frame data F(t+1) and compare it with the hash value of the previous frame data F(t).

[0181] If the above attribute value is a frame number or metadata, the attribute value for the current frame data is received from the host, and whether they are the same can be determined by comparing the frame number or metadata of the current frame data with that of the previous frame data.

[0182] If the attribute value for F(t+1) and the attribute value of F(t) are different, data and synchronization signals are transmitted to the display panel at step 960, and the pixel embedded memory data can be updated at step 965.

[0183] If the attribute value for F(t+1) and the attribute value of F(t) are the same, the frame data transmission path is disabled, and at step 970 only the synchronization signal iSync(t+1) is transmitted to the display panel, and at step 975 the data in the pixel internal memory is maintained as the previously stored F(t). Then, at step 980, the screen can be refreshed based on the previous frame data F(t) stored in the pixel internal memory.

[0184] If the attribute value for F(t+1) is the same as the attribute value of F(t), the DDIC can enter Low Power Mode. For example, if they are consecutively the same from F(t+1) to F(t+s) (where s is an integer greater than 10), the DDIC can operate in Low Power Mode. In this case, in Low Power Mode, the DDIC can block the reception of frame data for a preset time. When the preset time has elapsed, the DDIC can send an interrupt signal to the host to check whether to transmit frame data. The host can detect the interrupt signal and resume the transmission of frame data.

[0185] Meanwhile, regardless of whether the attribute values ​​of the current frame data and the previous frame data are identical, the internal synchronization signal generated from the previous frame data can be updated based on the synchronization signal included in the current frame data. The update of the internal synchronization signal includes a process of adjusting the timing of the internal synchronization signal by referencing the synchronization signal received from the host. The display driver IC (DDIC) may also display the previous frame data on the screen while maintaining the internal synchronization signal.

[0186] The synchronization signal and the data signal operate independently of each other, and the synchronization signal can be continuously generated even if data is not transmitted. The display driving circuit can update the screen based on this synchronization signal.

[0187] For example, if the display driver circuit needs to continuously display the same image, the host processor signals 'no change' via a control signal, and the driver circuit recognizes that the data has not changed. Subsequently, the synchronization signal is continuously transmitted from the host to the DDIC, and the screen can be updated while maintaining the previous data. In this case, the synchronization signal can be continuously maintained by transmitting only Vsync (vertical synchronization signal) and Hsync (horizontal synchronization signal) to the DDIC. The DDIC internally generates i-Vsync (internal vertical synchronization signal), and the data can maintain the existing data bits stored in the pixel in-pixel memory.

[0189] FIG. 10 is a drawing for explaining another example of a display device operation method according to one embodiment.

[0190] Referring to Figure 10, the DDIC periodically checks for the reception of a low-power mode command in step 1010, and when it receives a low-power mode command from the host, it enters a low-power operation mode.

[0191] Subsequently, the DDIC determines whether it is in partial data change mode or frame comparison mode. Whether it is in partial data change mode or frame comparison mode can be determined from commands or instructions received from the host.

[0192] The DDIC receives information from the host indicating whether to change the entire frame data or change some data, and can update the screen according to the received information.

[0193] For example, if no change in the entire frame data is received from the host, the frame comparison mode may be activated at step 1030. The frame comparison mode may be applied in the manner described in FIG. 9.

[0194] For example, when information instructing a partial data change is received from the host, the partial update mode may be activated in step 1040. Specific examples of the partial update mode will be explained through FIGS. 11 to 14.

[0195] Information instructing a partial change in data may include image data of the changed area and location information for the changed area. The changed image data may be updated in the pixel embedded memory corresponding to the location information, and the screen may be updated based on the data stored in the pixel embedded memory.

[0196] The DDIC can determine whether to exit low-power mode (1050) through communication with the host.

[0198] FIGS. 11 and FIGS. 12 are drawings for explaining a timing signal and a display control according to one embodiment.

[0199] When the host transmits data to the DDIC, it can transmit only partial image data of the changed area instead of transmitting the entire frame data. For example, if only the text changes in an image frame consisting of a background and text, the host can transmit only the image corresponding to the text without transmitting the image corresponding to the background. This reduces unnecessary data transmission and can decrease the system's power consumption and data processing burden.

[0200] The host can determine partial image data through frame data comparison or region of interest identification.

[0201] Referring to Fig. 11, HSYNC and Data Enable can be described as timing signals that reflect display position information that needs to be updated in the entire frame data.

[0202] At this time, the display panel may include a first line (1110), a second line (1120), and a third line (1130). At this time, each line may include pixels 1, 2, 3… N-2, N-1, N.

[0203] The logic controller of the display control device can determine row information of the display position based on the horizontal synchronization signal included in the timing signal.

[0204] From the perspective of the display panel, the display locations requiring an update are the first line (1110) and the third line (1130). The logic controller of the display control device can determine column information based on the time counted from the end of the porch section to the enable section of the timing signal.

[0205] For example, the logic controller may determine pixels 1 and 2 of the first line (1110) as 'none-update' based on the time counted from the end of the porch section until the section where Data Enable is enabled. Additionally, it may determine to update pixels 3 to N-2 of the first line (1110) based on the time counted from the section where Data Enable is enabled.

[0206] The logic controller can generate update bits indicating whether to update display pixels corresponding to row and column information based on Data Enable. For the sake of convenience, it was expressed as "determining column information based on the time counted up to the enable interval of the timing signal," but in reality, the logic controller can determine the update status on a pixel-by-pixel basis.

[0207] For example, the logic controller can generate an update bit '0' for pixel 1 and send the update bit to the display panel. It can also generate and send an update bit '0' for pixel 2, and generate and send an update bit '1' for pixel 3 and pixel N-2 to the display panel. On the other hand, it can generate and send an update bit '0' for pixel N-1 and pixel N.

[0208] Referring to FIG. 11, the Data Enable corresponding to the third line (1130) indicates that it is enabled for all pixels. Accordingly, the update bit for each pixel of the third line (1130) can be set to '1', and video data (1140) to be input to the third line (1130) can be input to each pixel.

[0209] Meanwhile, the On period of Data Enable and the video data input period may not necessarily coincide. Referring to FIG. 12, it can be seen that an embodiment in which video data is input to only some pixels even in the period where Data Enable is enabled is possible.

[0210] Accordingly, the logic controller can determine whether to update each pixel by checking the input of video data along with the timing signal. The logic controller can determine the pixel location requiring an update based on at least one of the Data Enable On period or the video data input period according to a prior agreement with the host.

[0211] The example illustrated in FIG. 12 corresponds to a case where only some pixels are updated. For example, among pixels 1 through N, only pixels 3 and N-2 may be updated. The logic controller can generate an update bit '1' for pixel 3 corresponding to the interval where video data is input during the interval where Data Enable is enabled, and transmit it to the display panel. Additionally, an update bit '1' can be generated and transmitted for pixel N-2 in the same manner.

[0212] Referring to FIG. 12, screen recognition from the user's perspective is shown when viewing a landscape (1201) of a real environment through smart glasses (1200). At this time, text information (1210, 1220) may be provided in a portion of the entire display area of ​​the smart glasses (1200) to provide augmented reality information.

[0213] Accordingly, partial updates may be applied in the area where text information (1210, 1220) is displayed. For example, the first text information (1210) may be time information including a second hand. The area where the second hand is displayed requires data updates more frequently than other areas, and the data updates may be controlled in pixel units.

[0215] FIG. 13 is a diagram illustrating the pixel operation of a display panel according to one embodiment.

[0216] Referring to FIG. 13, each pixel may include a pixel built-in memory (1310) and a path control unit (1320).

[0217] The pixel embedded memory (1310) can store m bits of image data applied through a column line or panel interface during a data writing interval. The pixel embedded memory (1310) can store at least 1 bit of data. The pixel embedded memory (1310) can be implemented as a memory of less than m bits depending on the driving frequency.

[0218] The pixel embedded memory (1310) may include a shift register. The pixel embedded memory (1310) may be implemented with one or more transistors. The pixel embedded memory (1310) may be implemented as random access memory (RAM), for example, SRAM or DRAM.

[0219] The pixel built-in memory (1310) can reset the memory and update the video data when video data is applied through the path control unit (1320).

[0220] The path control unit (1320) can perform the function of a comparator, a switch, or a multiplexer. The path control unit (1320) receives an update bit, and if the update bit is '0', it may not transmit video data to the pixel built-in memory (1310). Here, if the update bit is '0', there may be no video data input from the host.

[0221] Accordingly, when the update bit is '0', the path control unit (1320) may not perform a path control operation and may simply perform the function of transmitting a signal to the pixel built-in memory (1310) to indicate whether to retain data.

[0222] The path control unit (1320) receives an update bit, and if the update bit is '1', it can transfer video data to the pixel built-in memory (1310).

[0224] FIG. 14 is a flowchart illustrating a display control method for low-power driving according to one embodiment.

[0225] Referring to FIG. 14, in step 1410, the display control device receives a timing signal from the host that reflects display position information that needs to be updated in the entire frame data.

[0226] In step 1420, the display control device can check the preset porch section and the enable section of the timing signal, and determine the display position corresponding to the enable section of the timing signal.

[0227] Determining the display position may include a process of determining row information of the display position based on a horizontal synchronization signal included in the timing signal, and determining column information based on the time counted from the end point of the porch section to the enable section of the timing signal.

[0228] Display location information requiring update may include any one of the following: information regarding a preset zone of the display panel, information set for each line of the display panel, and information set for a pixel of the display panel. For example, Data Enable may be a timing signal that reflects information for updating a preset zone.

[0229] Accordingly, Data Enable may be an On or activated signal corresponding to a preset area. Additionally, in step 1420, the display control device may determine an update bit for each pixel of the display panel at a separated time interval based on the logic low or high interval of the timing signal. The logic low or high interval of the timing signal may be, for example, the On or Off interval of the Data Enable shown in FIGS. 12 to 14.

[0230] The display control device can transmit the update bit determined in step 1430 to the display panel. For example, the panel interface can transmit the update bit line by line or pixel by pixel of the display panel.

[0231] The display panel can perform maintenance or updates of pixel embedded memory on a line or pixel basis based on update bits at 1440 steps.

[0232] In other words, at step 1440, the display panel can write video data input during the enable interval of the timing signal to the built-in memory of a pixel provided at a display location requiring an update. At this time, the writing step may include controlling the update of the pixel built-in memory on a line-by-line basis of the display panel based on the row information. Additionally, the writing step may include the step of generating an update bit indicating whether the display pixel corresponding to the row information and column information is updated, and the step of the display pixel updating the pixel built-in memory or maintaining data stored in the pixel built-in memory based on the update bit.

[0234] FIGS. 15 and 16 are drawings for illustrating an example of a pixel driving circuit according to one embodiment.

[0235] Referring to FIG. 15, a pixel (PX) may include a pixel circuit comprising a light-emitting element (ED) and a first pixel circuit (1540) and a second pixel circuit (1550) connected thereto. The first pixel circuit (1540) may be a high-voltage driving circuit, and the second pixel circuit (1550) may be a low-voltage driving circuit. The second pixel circuit (1550) may be implemented with a plurality of logic circuits.

[0236] The light-emitting element (ED) selectively emits light for each subframe based on the bit value (logic level) of the image data provided by the data driver (1500) during one frame, thereby allowing the light emission time to be controlled within one frame and thus enabling the display of gradations. The first pixel circuit (1540) can control the light emission and non-light emission of the light-emitting element (ED) in response to a control signal applied to each of a plurality of subframes during one frame. The control signal may be a Pulse Width Modulation (PWM) signal.

[0237] The first pixel circuit (1540) may include a first transistor (1541), a second transistor (1545), and a level shifter (1543) electrically connected to a current supply unit (1500). The first transistor (1541) may output a driving current, and its gate may be connected to the current supply unit (1500), its first terminal may be connected to a power supply voltage (VDD) source, and its second terminal may be connected to the first terminal of the second transistor (1545).

[0238] The gate of the first transistor (1541) can be connected to the gate of the first transistor (51) of the current supply unit (1500) to form a current mirror circuit. Accordingly, when the first transistor (51) of the current supply unit (1500) is turned on, the first transistor (1541) can output a driving current corresponding to the current (Iref) formed in the current supply unit (1500). At this time, the driving current may be the same as the current (Iref) flowing in the current supply unit (1500).

[0239] The second transistor (1545) can supply or cut off the driving current to the light-emitting element (ED) according to the PWM signal. The gate of the second transistor (1545) is connected to the output terminal of the level shifter (1543), the first terminal is connected to the second terminal of the first transistor (1541), and the second terminal can be connected to the light-emitting element (ED).

[0240] The second transistor (1545) can be turned on or turned off depending on the voltage output from the level shifter (1543). The light emission time of the light-emitting element (ED) can be controlled according to the turn-on or turn-off time of the second transistor (1545). The second transistor (1545) is turned on when a gate-on level signal (low level in the embodiment of FIG. 15) is applied to the gate, thereby transmitting the driving current (Iref) output by the first transistor (1541) to the light-emitting element (ED) so that the light-emitting element (ED) emits light.

[0241] Conversely, the second transistor (1545) is turned off when a gate-off level signal (high level in the embodiment of FIG. 15) is applied to the gate, thereby blocking the transmission of the driving current (Iref) output by the first transistor (1541) to the light-emitting element (ED), so that the light-emitting element (ED) does not emit light. The light-emitting time and non-light-emitting time of the light-emitting element (ED) are controlled by the turn-on and turn-off times of the second transistor (1545) during one frame, so that the color depth of the pixel portion (110) can be expressed.

[0242] The level shifter (1543) is connected to the output terminal of the PWM controller (1551) of the second pixel circuit (1550) and can generate a second PWM signal by converting the voltage level of the first PWM signal output by the PWM controller (1551). The level shifter (1543) can generate a second PWM signal by converting the first PWM signal into a gate-on voltage level signal capable of turning on the second transistor (1545) and a gate-off level signal capable of turning off the second transistor (1545).

[0243] The pulse voltage level of the second PWM signal output by the level shifter (1543) may be higher than the pulse voltage level of the first PWM signal, and the level shifter (1543) may include a boost circuit that boosts the input voltage. Additionally, the level shifter (1543) may be implemented with a plurality of transistors.

[0244] Depending on the pulse width of the first PWM signal, the turn-on time and turn-off time of the second transistor (1545) during one frame may be determined. The second pixel circuit (1550) may store image data provided from the data driver (1500) during the data writing period for each frame, and generate the first PWM signal based on the bit value and clock signal during the light emission period.

[0245] The second pixel circuit (1550) may include a PWM controller (1551) and a memory (1553). The PWM controller (1551) may generate a first PWM signal based on a clock signal (CK) input from a clock generator (120) during the light emission period and a bit value of image data read from the memory (1553).

[0246] When a clock signal in subframe units is input from the clock generation unit (120), the PWM controller (1551) can generate a first PWM signal by reading the corresponding image data bit value from the memory (1553).

[0247] The PWM controller (1551) can control the pulse width of the first PWM signal based on the image data bit value and the signal width of the clock signal in subframe units. For example, if the bit value of the image data is 1, the pulse output of the PWM signal is turned on by the signal width of the clock signal, and if the bit value is 0, the pulse output of the PWM signal is turned off by the signal width of the clock signal.

[0248] That is, the on and off times of the pulse output of the PWM signal can be determined by the signal width (signal length) of the clock signal. The PWM controller (1551) may include a logic circuit (e.g., OR gate circuit, etc.) implemented with one or more transistors.

[0249] The memory (1553) can store image data provided from the data driver (1500) during the data writing period, synchronized with the frame start signal. In the case of a still image, data previously stored in the memory (1553) before an update or refresh can be used for image display continuously for multiple frames.

[0250] The memory (1553) can store data of 1 bit or more, and in one embodiment, it can be implemented as an n-bit memory. Additionally, depending on the driving frequency, it may be implemented as a memory of fewer than n bits and may be composed of one or more transistors.

[0252] FIG. 17 is a drawing for explaining another example of a display system according to one embodiment.

[0253] Referring to FIG. 17, the display system includes a host (1710), a display driver IC (1720), and a pixel-embedded memory type display panel (1730). Each pixel included in the display panel (1730) may include an embedded memory (1731) capable of storing digital data internally.

[0254] The display driver IC (1720) and the pixel embedded memory type display panel (1730) can be collectively referred to as a display module (1740).

[0255] The display driver IC (1720) and the display panel (1730) may each have the same configuration as the display driver IC (220) and the display panel (230) of FIG. 2.

[0256] It may include a host (1710), an application processor (AP) (1711), an AP buffer (1713), and a display controller (1715).

[0257] AP (1711) can perform image processing such as generating image data and rendering, and can organize image data into frames and store them in the AP buffer (1713). At this time, the image data may also be referred to as 'display data'.

[0258] The display controller (1715) can read stored frame data from the AP buffer (1713) and generate synchronization signals such as Hsync and Vsync. In other words, the display controller (1715) can generate synchronization signals to output display data generated by the AP (1711) in frame units. Additionally, the display controller (1715) can transmit the frame data and synchronization signals to the display module (1740). At this time, the display module (1740) can receive the frame data and synchronization signals from the display controller (1711). The display module (1740) can output display data using the frame data and synchronization signals.

[0259] The display controller (1710) can determine whether to update the frame data and generate a control command based on the update status. The control command based on the update status can be transmitted to the display module (1740). For example, the control command based on the update status may be a PSR.

[0261] The device described above may be implemented as a hardware component, a software component, and / or a combination of a hardware component and a software component. For example, the device and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and one or more software applications executed on said operating system. Additionally, the processing unit may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing unit may be described as being used as a single unit, but those skilled in the art will understand that the processing unit may include multiple processing elements and / or multiple types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. In addition, other processing configurations, such as parallel processors, are also possible.

[0262] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or command the processing unit independently or collectively. Software and / or data may be permanently or temporarily embodied in any type of machine, component, physical device, virtual equipment, computer storage medium or device, or transmitted signal wave so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0263] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc., either alone or in combination. The program instructions recorded on the medium may be those specifically designed and configured for the embodiment, or they may be those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc. The hardware devices described above may be configured to operate as one or more software modules to perform the operation of the embodiment, and vice versa.

[0264] Although the embodiments have been described above with reference to the limited drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results can be achieved even if the described techniques are performed in a different order than described, and / or the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

[0265] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.

Claims

Claim 1 A method for displaying first frame data and consecutive second frame data in a display device comprising a display driver IC and a display panel, wherein a video stream transmission path (DPAC) and a clock signal transmission path (CLKm) are provided between the display driver IC and a host device, and the method comprises: (1) receiving the first frame data, a vertical sync signal (Vsync), and a horizontal sync signal (Hsync) through the video stream transmission path, and receiving a clock signal through the clock signal transmission path; (2) synchronizing the received vertical sync signal (Vsync) and horizontal sync signal (Hsync) with an internal clock (fosc) to generate an internal vertical sync signal (iVsync) and an internal horizontal sync signal (iHsync), writing the first frame data to the pixel embedded memory of an individual pixel, and outputting the first frame data based on the internal vertical sync signal (iVsync) and internal horizontal sync signal (iHsync) during a data scan interval; (3) When a command is received from the host indicating that the first frame data and the second frame data are identical, the transmission of the second frame data through the video stream transmission path is blocked, the clock signal transmission path is maintained, and the first frame data recorded in the pixel internal memory of the individual pixels is maintained; (4) The interface control unit generates a control signal (CTL') instructing the internal vertical synchronization signal (iVsync) and the internal horizontal synchronization signal (iHsync) generated based on the first frame data to be maintained; (5) The logic controller maintains the internal vertical synchronization signal (iVsync) and the internal horizontal synchronization signal (iHsync) according to the control signal (CTL');and (6) a method of operation of a display device comprising the step of the display panel performing a display operation based on the internal vertical synchronization signal (iVsync) and the internal horizontal synchronization signal (iHsync), and the first frame data stored in the pixel internal memory of the individual pixel.; Claim 2 A method of operation of a display device according to claim 1, characterized in that the command is a Panel Self Refresh (PSR) command. Claim 3 A method of operation of a display device according to claim 1, characterized in that the command is transmitted via the eDP (Embedded DisplayPort) protocol. Claim 4 delete Claim 5 A method of operation of a display device according to claim 1, characterized in that the pixel-embedded memory (in-pixel memory) is a Static Random Access Memory (SRAM) embedded in each pixel. Claim 6 A method of operation of a display device according to claim 1, wherein the host determines that there is no change in frame data by comparing the hash value of the previous frame data and the current frame data. Claim 7 A method of operation of a display device according to claim 1, wherein the display driver IC receives a command indicating no change in frame data, enters a Low Power Mode, and transmits an interrupt signal to the host to check whether frame data is transmitted after a preset time has elapsed. Claim 8 A method of operation for displaying first frame data and consecutive second frame data in a display device comprising a display driver IC and a display panel, wherein a video stream transmission path (DPAC) and a clock signal transmission path (CLKm) are provided between the display driver IC and a host device, and the method comprises: (1) receiving the first frame data, a vertical sync signal (Vsync), and a horizontal sync signal (Hsync) through the video stream transmission path, and receiving a clock signal through the clock signal transmission path; (2) synchronizing the received vertical sync signal (Vsync) and horizontal sync signal (Hsync) with an internal clock (fosc) to generate an internal vertical sync signal (iVsync) and an internal horizontal sync signal (iHsync), writing the first frame data to the pixel embedded memory of an individual pixel, and outputting the first frame data based on the internal vertical sync signal (iVsync) and internal horizontal sync signal (iHsync) during a data scan interval; (3) receiving a sync signal from the host without the second frame data, and if the second frame data is not received within a preset time, determining that the first frame data and the second frame data are identical, blocking the transmission of the second frame data through the video stream transmission path, maintaining the clock signal transmission path, and maintaining the first frame data recorded in the pixel internal memory of the individual pixel; (4) generating a control signal (CTL') that instructs the interface control unit to maintain the internal vertical sync signal (iVsync) and internal horizontal sync signal (iHsync) generated based on the first frame data;(5) A method of operation of a display device comprising the step of a logic controller maintaining the internal vertical synchronization signal (iVsync) and the internal horizontal synchronization signal (iHsync) according to the control signal (CTL'), and the display panel performing a display operation based on the internal vertical synchronization signal (iVsync) and the internal horizontal synchronization signal (iHsync) generated based on the first frame data and the first frame data stored in the pixel internal memory of the individual pixel.; Claim 9 delete Claim 10 delete Claim 11 A display driving device for driving a display panel having a pixel embedded memory in an individual pixel driving circuit, wherein a video stream transmission path (DPAC) and a clock signal transmission path (CLKm) are provided between the display driving device and a host device, and the display driving device receives a first frame data, a vertical sync signal (Vsync) and a horizontal sync signal (Hsync) through the video stream transmission path, receives a clock signal through the clock signal transmission path, synchronizes the received vertical sync signal (Vsync) and horizontal sync signal (Hsync) with an internal clock (fosc) to generate an internal vertical sync signal (iVsync) and an internal horizontal sync signal (iHsync), writes the first frame data to the pixel embedded memory of an individual pixel, and outputs the first frame data based on the internal vertical sync signal (iVsync) and internal horizontal sync signal (iHsync) during a data scan interval, and the display driving device (1) determines whether the first frame data and a consecutive second frame data are identical, and if identical A receiving interface that blocks the transmission of second frame data through the video stream transmission path and maintains the clock signal transmission path; (2) an interface control unit that generates a control signal (CTL') that instructs to maintain the internal vertical synchronization signal (iVsync) and internal horizontal synchronization signal (iHsync) generated based on the first frame data;and (3) a display driving device comprising a logic controller that controls the display panel to refresh the screen of the display panel based on the internal vertical synchronization signal (iVsync) and the internal horizontal synchronization signal (iHsync) according to the control signal (CTL'), and the first frame data stored in the pixel internal memory, wherein the second frame data is not transmitted from the host to the receiving interface, and the display panel maintains multibit digital data according to the first frame data stored in the pixel internal memory of the individual pixels, and performs a panel self-refresh (PSR) operation based on the internal vertical synchronization signal (iVsync) and the internal horizontal synchronization signal (iHsync) and the multibit digital data stored in the pixel internal memory. Claim 12 A display driving device according to claim 11, characterized in that determining whether the first frame data and the consecutive second frame data are the same at the receiving interface is determined through a command received from the host, or if a sync signal is received from the host device without the second frame data and the second frame data is not received within a preset time, the first frame data and the second frame data are determined to be the same. Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete Claim 21 delete Claim 22 A display driving device having a pixel embedded memory in an individual pixel driving circuit, wherein a video stream transmission path (DPAC) and a clock signal transmission path (CLKm) are provided between the display driving device and a host device, and the display driving device receives a first frame data, a vertical sync signal (Vsync) and a horizontal sync signal (Hsync) through the video stream transmission path, receives a clock signal through the clock signal transmission path, synchronizes the received vertical sync signal (Vsync) and horizontal sync signal (Hsync) with an internal clock (fosc) to generate an internal vertical sync signal (iVsync) and an internal horizontal sync signal (iHsync), records the first frame data in the pixel embedded memory of an individual pixel, and outputs the first frame data based on the internal vertical sync signal (iVsync) and internal horizontal sync signal (iHsync) during a data scan interval, and the display driving device comprises: (1) a receiving interface that receives a second frame data consecutive to the first frame data from the host device; (2) Attribute Value Memory for storing the attribute value of the first frame data; (3) Comparator for calculating the attribute value of the second frame data, comparing the attribute value of the second frame data with the attribute value of the first frame data stored in the Attribute Value Memory to determine whether they are the same, and generating a control signal to instruct to disable the frame data transmission path if the attribute value of the second frame data and the attribute value of the first frame data are the same;and (4) a logic controller that, upon receiving the control signal, generates a control signal (CTL') that maintains an internal vertical synchronization signal (iVsync) and an internal horizontal synchronization signal (iHsync) for the first frame, and controls the display panel to refresh the screen based on the first frame data stored in the pixel internal memory of an individual pixel according to the control signal (CTL'), wherein the comparator is activated to perform a comparison operation when it receives a low-power mode command from the host, and when the attribute value for the second frame data and the attribute value for the first frame data are the same, the video stream transmission path is blocked and the clock signal transmission path is maintained. Claim 23 delete Claim 24 delete

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