Semiconductor device

Abstract

A semiconductor device comprises: a lower electrode on a substrate; a support pattern provided between the lower electrode and an adjacent lower electrode; an upper electrode covering the lower electrode and the support pattern; and a dielectric film provided between the lower electrode and the upper electrode and between the support pattern and the upper electrode. The lower electrode comprises a first portion including a seam and a second portion on the first portion. The upper end of the second portion is located at a height lower than the upper surface of the support pattern. A portion of the lower end of the second portion is exposed by the seam.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor memory device including a capacitor. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that process logic data, and hybrid semiconductor devices that include both memory and logic elements.

[0003] Recently, with the increasing speed and low power consumption of electronic devices, semiconductor devices embedded therein are also required to have fast operating speeds and / or low operating voltages, and to meet these requirements, more highly integrated semiconductor devices are necessary. However, as the high integration of semiconductor devices increases, the electrical characteristics and reliability of the semiconductor devices may decrease. Accordingly, much research is being conducted to improve the electrical characteristics and reliability of semiconductor devices. The technology forming the background of the present invention includes a prior art document (KR10-2021-0061162). The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics and reliability.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A semiconductor device according to the present invention may include: a lower electrode on a substrate; a support pattern provided between the lower electrode and an adjacent lower electrode; an upper electrode covering the lower electrode and the support pattern; and a dielectric film provided between the lower electrode and the upper electrode and between the support pattern and the upper electrode. The lower electrode may include a first portion comprising a seam and a second portion on the first portion. The upper end of the second portion may be located at a height lower than the upper surface of the support pattern. A portion of the lower end of the second portion may be exposed by the seam.

[0007] A semiconductor device according to the present invention may include: a lower electrode on a substrate; a support pattern provided between the lower electrode and an adjacent lower electrode; an upper electrode covering the lower electrode and the support pattern; and a dielectric film provided between the lower electrode and the upper electrode and between the support pattern and the upper electrode. The lower electrode may include a seam inside. The upper end of the lower electrode may be lower than the upper surface of the support pattern. It may be located at a height higher than the bottom surface of the support pattern.

[0008] A semiconductor device according to the present invention may comprise: a substrate including an active pattern; an impurity region provided within the active pattern; a word line disposed within the substrate and extending across the active pattern; a bit line disposed on the substrate and extending in a direction intersecting the word line; a storage node contact disposed on the substrate and electrically connected to the impurity region; a landing pad electrically connected to the storage node contact; a lower electrode electrically connected to the landing pad; an upper support pattern and a lower support pattern provided between the lower electrode and an adjacent lower electrode; an upper electrode covering the lower electrode and the upper support pattern; and a dielectric film provided between the lower electrode and the upper electrode and between the upper support pattern and the upper electrode. The lower electrode may comprise a first portion including a seam and a second portion on the first portion. The upper end of the second portion may be located at a height lower than the upper surface of the support pattern. A portion of the lower end of the second portion may be exposed by the seam. Effects of the invention

[0009] According to the concept of the present invention, the lower electrode of a capacitor may include a first portion and a second portion, and the second portion may minimize damage to the lower electrode by the etching solution during a subsequent etching process. As a result, the electrical characteristics and reliability of the semiconductor device may be improved. Brief explanation of the drawing

[0010] FIG. 1 is a plan view showing a semiconductor device according to embodiments of the present invention. Figures 2 and 3 are cross-sectional views corresponding to A-A' of Figure 1, respectively. FIGS. 4 to 13 are drawings showing a method for manufacturing a semiconductor device of FIG. 2, FIGS. 4 and 11 are plan views showing a method for manufacturing a semiconductor device of FIG. 2, and FIGS. 5 to 10, FIGS. 12 and FIGS. 13 are cross-sectional views showing a method for manufacturing a semiconductor device of FIG. 2. FIG. 14 is a cross-sectional view corresponding to A-A' in FIG. 1. FIGS. 15 to 17 are cross-sectional views illustrating a method for manufacturing a semiconductor device of FIG. 14. FIG. 18 is a cross-sectional view corresponding to A-A' in FIG. 1. FIGS. 19 and FIGS. 20 are cross-sectional views illustrating a method for manufacturing a semiconductor device of FIG. 18. FIG. 21 is a cross-sectional view corresponding to A-A' in FIG. 1. FIGS. 22 to 26 are cross-sectional views illustrating a method for manufacturing a semiconductor device of FIG. 21. FIG. 27 is a block diagram showing a semiconductor device according to embodiments of the present invention. Fig. 28 is an enlarged view corresponding to part P1 of Fig. 27. FIG. 29 is a cross-sectional view corresponding to A-A' in FIG. 28. Specific details for implementing the invention

[0011] Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings.

[0013] FIG. 1 is a plan view showing a semiconductor device according to embodiments of the present invention. FIG. 2 is a cross-sectional view corresponding to A-A' of FIG. 1.

[0014] Referring to FIGS. 1 and FIGS. 2, a substrate (10) may be provided. The substrate (10) may be a semiconductor substrate. The substrate (10) may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0015] An interlayer insulating film (12) may be disposed on the substrate (10). The interlayer insulating film (12) may cover at least a portion of the upper surface of the substrate (10). For example, the interlayer insulating film (12) may include at least one of silicon nitride, silicon oxide, or silicon oxynitride. For another example, the interlayer insulating film (12) may include an empty region.

[0016] A conductive contact (14) may be disposed within the interlayer insulating film (12). The conductive contact (14) may be a plurality of, and the conductive contacts (14) may be spaced apart in a first direction (D1) and a second direction (D2) that are parallel to and intersect each other (e.g., orthogonal) on the upper surface of the substrate (10). The conductive contact (14) may include at least one of an impurity-doped semiconductor material (e.g., polycrystalline silicon), a metal-semiconductor compound (e.g., tungsten silicide), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride, etc.), or a metal (e.g., titanium, tungsten, or tantalum, etc.). The conductive contact (14) may be electrically connected to an impurity region (e.g., source / drain terminals) formed within the substrate (10).

[0017] An etch stop pattern (420) may be disposed on the interlayer insulating film (12). The etch stop pattern (420) may cover the interlayer insulating film (12) and expose the conductive contacts (14). The etch stop pattern (420) may include at least one of silicon oxide, SiCN, or SiBN.

[0018] A lower electrode (BE) may be placed on a conductive contact (14). The lower electrode (BE) may penetrate the etching stop pattern (420) and may be electrically connected to the conductive contact (14). The lower electrode (BE) may have a pillar shape. There may be multiple lower electrodes (BE), and the lower electrodes (BE) may be spaced apart from each other in the first direction (D1) and the second direction (D2). In a planar view, for example, the lower electrodes (BE) may be arranged to have a honeycomb shape. In detail, with one lower electrode (BE) at the center, six lower electrodes (BE) may be arranged to surround the one lower electrode (BE) in a hexagon.

[0019] The lower electrode (BE) may include a conductive material. For example, the lower electrode (BE) may include at least one of silicon (Si), a metallic material (e.g., cobalt, titanium, nickel, tungsten, and molybdenum), a metallic nitride (e.g., titanium nitride (TiN), titanium silicon (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN, TaAlN), and tungsten nitride (WN)), a precious metal (e.g., platinum (Pt), ruthenium (Ru), and iridium (Ir)), a conductive oxide (PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo), or a metallic silicide.

[0020] An upper support pattern (US) and a lower support pattern (LS) may be provided on the substrate (10). The upper support pattern (US) and the lower support pattern (LS) may be spaced apart from each other in a third direction (D3) perpendicular to the upper surface of the substrate (10). The upper support pattern (US) may be located at a higher height than the lower support pattern (LS). Although not illustrated, additional support patterns spaced apart from each other in the third direction (D3) may be provided, and the support pattern provided on the top layer may be referred to as the upper support pattern (US). For example, three layers of support patterns spaced apart from each other in the third direction (D3) may be provided, and the support pattern provided on the top layer among the three layers of support patterns may be referred to as the upper support pattern (US). The upper support pattern (US) and the lower support pattern (LS) may be provided between adjacent lower electrodes (BE). The upper support pattern (US) and the lower support pattern (LS) may be in contact with the side of the lower electrode (BE) and may wrap around the side of the lower electrode (BE). The upper support pattern (US) and the lower support pattern (LS) may physically support the lower electrode (BE). The thickness of the upper support pattern (US) along the third direction (D3) and the thickness of the lower support pattern (LS) along the third direction (D3) may be different from each other. Each of the upper support pattern (US) and the lower support pattern (LS) may include, for example, at least one of silicon nitride, SiBN, or SiCN.

[0021] The lower electrode (BE) may include a first part (BE1) and a second part (BE2). The lower electrode (BE) may include a seam (SM) inside, and the seam (SM) may be placed within the first part (BE1) of the lower electrode (BE). The first part (BE1) may be a portion of the lower electrode (BE) provided below the top of the seam (SM). The second part (BE2) may be another portion of the lower electrode (BE) provided above the top of the seam (SM) and may be provided on the first part (BE1). The first part (BE1) and the second part (BE2) may be in contact without an interface. For example, the first part (BE1) and the second part (BE2) may include the same material. The first part (BE1) may further include a substance not included in the second part (BE2), and the second part (BE2) may further include a substance not included in the first part (BE1).

[0022] A portion of the lower end (BEb) of the second part (BE2) may be exposed by the seam (SM). The lower end (BEb) of the second part (BE2) may be defined at a height where the upper end of the seam (SM) is provided. For example, the lower end (BEb) of the second part (BE2) may be located at a height higher than the bottom surface (USb) of the upper support pattern (US), but is not limited thereto.

[0023] The upper portion (BEa) of the second portion (BE2) may constitute the upper surface of the lower electrode (BE). The upper portion (BEa) of the second portion (BE2) may be located at a height lower than the upper surface (USa) of the support pattern (US) and at a height higher than the bottom surface (USb) of the support pattern (US). That is, the upper surface of the lower electrode (BE) may be located at a height lower than the upper surface (USa) of the support pattern (US) and at a height higher than the bottom surface (USb) of the support pattern (US). Accordingly, the upper support pattern (US) may physically support the lower electrode (BE). The second portion (BE2) may not include a core (SM).

[0024] A through hole (PH) may be positioned between adjacent lower electrodes (BE). For example, the through hole (PH) may be positioned in a circular shape between three adjacent lower electrodes (BE) and may expose a portion of the side of each of the three lower electrodes (BE). However, it is not limited thereto, and the through hole (PH) may be positioned between multiple lower electrodes (BE) in various forms. The through hole (PH) may penetrate the upper support pattern (US) and the lower support pattern (LS). The through hole (PH) may expose the etching stop pattern (420). There may be multiple through holes (PH), and the through holes (PH) may be spaced apart from each other in the first direction (D1) and the second direction (D2).

[0025] A dielectric film (DL) may be provided on the upper support pattern (US), the lower support pattern (LS), the lower electrode (BE), and the etching stop pattern (420). The dielectric film (DL) may conformally cover the upper support pattern (US), the lower support pattern (LS), the lower electrode (BE), and the etching stop pattern (420). The dielectric film (DL) may be in contact with the upper surface of the lower electrode (BE). That is, the dielectric film (DL) may be in contact with the upper end (BEa) of the second portion (BE2) of the lower electrode (BE). The dielectric film (DL) may fill a portion of the through holes (PH). The dielectric film (DL) in contact with the lower electrode (BE) may have the same crystal structure as the crystal structure of the lower electrode (BE). For example, the dielectric film (DL) may have a tetragonal structure. The dielectric film (DL) may be formed as a single film selected from a combination of, for example, metal oxides such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2, and dielectric materials with a perovskite structure such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT, or as a combination of these films.

[0026] An upper electrode (TE) may be provided on the dielectric film (DL). The upper electrode (TE) may cover the lower electrode (BE), the upper support pattern (US), and the lower support pattern (LS). The upper electrode (TE) may fill the remainder of the through holes (PH), the space between the upper support pattern (US) and the lower support pattern (LS), and the space between the lower support pattern (LS) and the etch stop pattern (420). The dielectric film (DL) may be interposed between the lower electrode (BE) and the upper electrode (TE), between the upper support pattern (US) and the upper electrode (TE), and between the lower support pattern (LS) and the upper electrode (TE). The dielectric film (DL) may be interposed between the upper end (BEa) of the second portion (BE2) of the lower electrode (BE) and the upper electrode (TE).

[0027] The upper electrode (TE) may comprise at least one of titanium nitride, impurity-doped polysilicon, and impurity-doped silicon germanium. The upper electrode (TE) may be a single film or a multi-film. The lower electrode (BE), the dielectric film (DL), and the upper electrode (TE) may form a capacitor (CA). For example, the capacitor (CA) may perform the function of an information storage element for the semiconductor device according to the present invention to operate as a memory device.

[0029] FIG. 3 is a cross-sectional view corresponding to A-A' in FIG. 1, showing a semiconductor device according to other embodiments of the present invention. For the sake of simplification, descriptions of content that overlap with the foregoing are omitted, and the description focuses on features that differentiate it from the foregoing.

[0030] Referring to FIG. 3, the lower electrode (BE) may include a first part (BE1) and a second part (BE2). The lower electrode (BE) may include a plurality of cores (SM) inside, and each of the cores (SM) may be located at a different height. The cores (SM) may be placed within the first part (BE1) of the lower electrode (BE). The first part (BE1) may be a part of the lower electrode (BE) provided below the top of the uppermost core (SM) among the cores (SM). The second part (BE2) may be another part of the lower electrode (BE) provided above the top of the uppermost core (SM) and may be provided on the first part (BE1). The first part (BE1) and the second part (BE2) may be in contact without a boundary surface.

[0031] A portion of the bottom (BEb) of the second part (BE2) may be exposed by the top layer core (SM). The bottom (BEb) of the second part (BE2) may be defined at a height where the top of the top layer core (SM) is provided.

[0033] FIGS. 4 to 13 are drawings illustrating a method for manufacturing a semiconductor device of FIG. 2, FIGS. 4 and 11 are plan views illustrating a method for manufacturing a semiconductor device of FIG. 2, and FIGS. 5 to 10, FIGS. 12, and FIGS. 13 are cross-sectional views illustrating a method for manufacturing a semiconductor device of FIG. 2. Hereinafter, a method for manufacturing a semiconductor device according to FIG. 2 will be described with reference to FIGS. 4 to 13. For the sake of simplification of the explanation, descriptions of content that overlap with the foregoing content will be omitted.

[0034] Referring to FIGS. 4 and 5, a substrate (10) may be provided. An interlayer insulating film (12) may be formed on the substrate (10). A conductive contact (14) may be formed within the interlayer insulating film (12). An etch stop film (420L) may be formed on the substrate (10). The etch stop film (420L) may be formed to cover the upper surface of the interlayer insulating film (12) and the upper surface of the conductive contact (14).

[0035] A mold structure (MS) may be formed on the etch stop layer (420L). The mold structure (MS) may be formed by alternately stacking mold films and support films. For example, the mold structure (MS) may be formed by stacking a first mold film (20), a lower support film (22), a second mold film (24), and an upper support film (26) in sequence. The lower support film (22) may include a material having etch selectivity with respect to the first mold film (20). The upper support film (26) may include a material having etch selectivity with respect to the second mold film (24). The first mold film (20) and the second mold film (24) may include the same material. For example, the first mold film (20) and the second mold film (24) may include silicon oxide. The lower support film (22) and the upper support film (26) may each contain the same material. For example, the lower support film (22) and the upper support film (26) may include at least one of silicon nitride, SiBN, or SiCN.

[0036] A first mask film (40) and a second mask pattern (42) may be formed sequentially on the mold structure (MS). The first mask film (40) may cover the upper support film (26). The first mask film (40) may include, for example, at least one of polysilicon, silicon nitride, or silicon oxynitride. The second mask pattern (42) may be formed on the first mask film (40) and may have a first opening (OP1). The first opening (OP1) may be multiple, and a portion of the upper surface of the first mask film (40) may be exposed through the first opening (OP1). The first opening (OP1) may overlap vertically with the conductive contact (14). The second mask pattern (42) may include, for example, at least one of a Spin On Hardmask (SOH) or an Amorphous Carbon Layer (ACL).

[0037] Referring to FIG. 6, the second mask pattern (42) can be used as an etching mask to anisotropically etch the first mask film (40), the mold structure (MS), and the etch stop layer (420L). Accordingly, a conductive hole (CH) having a shape similar to the first opening (OP1) can be formed planarly, and the conductive hole (CH) can be formed in multiple numbers along the first opening (OP1). The conductive hole (CH) can penetrate the mold structure (MS) and the etch stop layer (420L) in the third direction (D3) and expose the upper surface of the conductive contact (14). After the etching process, the remaining portion of the etch stop layer (420L) that is not etched can form an etch stop pattern (420). For example, the first mask film (40) and the second mask pattern (42) can be removed through the etching process. For another example, the first mask film (40) and the second mask pattern (42) can be removed through a separate removal process after the etching process.

[0038] Referring to FIG. 7, a first lower electrode film (50) can be formed on the mold structure (MS) and can fill the conductive hole (CH). The first lower electrode film (50) can cover the exposed upper surface of the conductive contact (14) and the upper support film (26). For example, the first lower electrode film (50) can be formed through a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process.

[0039] The first lower electrode film (50) may be formed to fill the conductive holes (CH). The first lower electrode film (50) may begin to be deposited on the inner wall of the conductive hole (CH) and, as the deposition proceeds, may fill the conductive hole (CH) from the inner wall of the conductive hole (CH). As a result, a core (SM) may be formed inside the first lower electrode film (50). The core (SM) may be formed at the boundary where the first lower electrode film (50) is deposited from the mutually facing inner walls of the conductive hole (CH) and meets. The core (SM) may, for example, be a boundary surface inside the first lower electrode film (50). The core (SM) may, for another example, be an empty space inside the first lower electrode film (50).

[0040] The first lower electrode film (50) may comprise at least one of silicon (Si), a metal material (e.g., cobalt, titanium, nickel, tungsten, and molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN, TaAlN), and tungsten nitride (WN)), a precious metal (e.g., platinum (Pt), ruthenium (Ru), and iridium (Ir)), a conductive oxide (PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo) or a metal silicide.

[0041] Referring to FIG. 8, the upper portion of the first lower electrode film (50) may be removed, and a first portion (BE1) of the lower electrode (BE) may be formed. The first lower electrode film (50) may be separated into a plurality of first portions (BE1) that fill each of the conductive holes (CH). Removing the upper portion of the first lower electrode film (50) may, for example, include performing an etch-back process. The first portion (BE1) may penetrate the mold structure (MS) in the third direction (D3) and may be electrically connected to the conductive contact (14). For example, the first portion (BE1) may be formed to have a pillar shape. The upper portion of the conductive hole (CH) may not be filled by the first portion (BE1).

[0042] By removing the upper portion of the first lower electrode membrane (50), the core (SM) can be exposed to the outside. The core (SM) can be exposed to the outside by the upper surface of the first portion (BE1). The upper surface of the first portion (BE1) can be located at a lower height than the upper surface of the upper support membrane (26). For example, the upper surface of the first portion (BE1) can be located at a height lower than the upper surface of the upper support membrane (26) and higher than the bottom surface of the upper support membrane (26). As a result, the top of the core (SM) can be located at a height lower than the upper surface of the upper support membrane (26) and higher than the bottom surface of the upper support membrane (26). At least a portion of the side of the upper support membrane (26) can be exposed by the first portion (BE1).

[0043] Referring to FIG. 9, a second lower electrode film (55) may be formed on the first portion (BE1). The second lower electrode film (55) may fill the upper portion of the conductive hole (CH) that is not filled by the first portion (BE1) and may cover the upper support film (26). The upper portion of the core (SM) may be closed by the second lower electrode film (55). A portion of the lower portion (55b) of the second lower electrode film (55) may be exposed by the core (SM). The lower portion (55b) of the lower electrode film (55) may be a surface that meets the upper surface of the first portion (BE1), and the upper portion of the core (SM) may be located at a provided height.

[0044] The second lower electrode film (55) may include at least one of silicon (Si), a metallic material (e.g., cobalt, titanium, nickel, tungsten, and molybdenum), a metallic nitride (e.g., titanium nitride (TiN), titanium silicon (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN, TaAlN), and tungsten nitride (WN)), a precious metal (e.g., platinum (Pt), ruthenium (Ru), and iridium (Ir)), a conductive oxide (PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo), or a metallic silicide. The second lower electrode film (55) may include the same material as the first part (BE1) and may further include a material not included in the first part (BE1).

[0045] Referring to FIG. 10, the upper portion of the second lower electrode film (55) may be removed, and a lower electrode (BE) may be formed. The lower electrode (BE) may include a first portion (BE1) and a second portion (BE2) on the first portion (BE1). The second portion (BE2) may be formed by removing the upper portion of the second lower electrode film (55). In detail, the second lower electrode film (55) may be separated into a plurality of second portions (BE2) that fill each of the conductive holes (CH). Removing the upper portion of the second lower electrode film (55) may, for example, include performing an etch-back process. By removing the upper portion of the second lower electrode film (55), the upper surface of the upper support film (26) and a portion of the side surface of the upper support film (26) may be exposed.

[0046] The upper portion (BEa) of the second portion (BE2) may be located at a height lower than the upper surface of the upper support membrane (26). A portion of the lower portion (BEb) of the second portion (BE2) may be exposed by the core (SM). The lower portion (BEb) of the second portion (BE2) may be located at a height where the upper portion of the core (SM) is provided. The first portion (BE1) and the second portion (BE2) may be in contact with each other without a boundary surface.

[0047] Referring to FIGS. 11 and 12, a third mask film (60) and a fourth mask pattern (62) may be formed sequentially on the mold structure (MS) and the lower electrode (BE). The third mask film (60) may cover the upper support film (26) and the lower electrode (BE). The fourth mask pattern (62) may be formed on the third mask film (60) and may have a second opening (OP2). The second opening (OP2) may be multiple. A portion of the upper surface of the third mask film (60) may be exposed through the second opening (OP2). The third mask film (60) may include, for example, polysilicon. The fourth mask pattern (62) may include, for example, photoresist.

[0048] Referring to FIG. 13, the third mask film (60) and the upper support film (26) can be anisotropically etched using the fourth mask pattern (62) as an etching mask. Accordingly, a portion of the third mask film (60) and a portion of the upper support film (26) that overlap vertically with the second opening (OP2) can be removed. The remainder of the upper support film (26) can form an upper support pattern (US). A through hole (PH) penetrating the upper support pattern (US) can be formed. There may be multiple through holes (PH) and they may overlap vertically with the second opening (OP2). A portion of the upper surface of the second mold film (24) can be exposed by the through hole (PH).

[0049] Subsequently, the second mold film (24) may be removed. Accordingly, the bottom surface of the upper support pattern (US), a portion of the side of the lower electrode (BE), and the upper surface of the lower support film (22) may be exposed. The removal process of the second mold film (24) may include an isotropic etching process. Phosphoric acid (H3PO4) may be used to perform the isotropic etching process. For example, the remainder of the third mask film (60) may be removed before the removal of the second mold film (24), but is not limited thereto. By removing the second mold film (24), the through hole (PH) may be extended to the upper surface of the lower support film (22).

[0050] A portion of the lower support film (22) that overlaps vertically with the through hole (PH) can be etched, and a portion of the upper surface of the first mold film (20) can be exposed. The remainder of the lower support film (22) can form a lower support pattern (LS). The through hole (PH) can extend into the lower support pattern (LS) and can further penetrate the lower support pattern (LS).

[0051] Subsequently, the first mold film (20) can be removed. Accordingly, the bottom surface of the lower support pattern (LS), the remaining portion of the side of the lower electrode (BE), and the top surface of the etching prevention pattern (420) may be exposed. The removal process of the first mold film (20) may include an isotropic etching process. Phosphoric acid (H3PO4) may be used to perform the isotropic etching process.

[0052] According to the concept of the present invention, damage to the lower electrode (BE) can be minimized during the removal process of the first mold film (20) and the second mold film (24). Due to the second part (BE2) of the lower electrode (BE), the seam (SM) of the lower electrode (BE) may not be exposed to the outside, thereby preventing the isotropic etching solution from penetrating into the lower electrode (BE) along the seam (SM). That is, by forming the first part (BE1) and the second part (BE2) separately when forming the lower electrode (BE), damage to the lower electrode (BE) can be minimized during the subsequent etching process. As a result, the electrical characteristics and reliability of the semiconductor device can be improved.

[0053] Referring again to FIG. 2, a dielectric film (DL) may be formed on the upper support pattern (US), the lower support pattern (LS), the lower electrode (BE), and the etching stop pattern (420). The dielectric film (DL) may conformally cover the upper support pattern (US), the lower support pattern (LS), the lower electrode (BE), and the etching stop pattern (420). The dielectric film (DL) may fill a portion of the through hole (PH).

[0054] The dielectric film (DL) in contact with the lower electrode (BE) may be formed to have the same crystal structure as the lower electrode (BE). For example, the dielectric film (DL) may be formed to have a tetragonal structure. The dielectric film (DL) may be formed using a deposition technique with excellent step coverage, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0055] An upper electrode (TE) may be formed on the dielectric film (DL). The upper electrode (TE) may fill the remainder of the through hole (PH) and cover the lower electrode (BE). The upper electrode (TE) may fill the space between the lower electrode (BE) and an adjacent lower electrode (BE), the space between the upper support pattern (US) and the lower support pattern (LS), and the space between the lower support pattern (LS) and the etching stop pattern (420). By forming the upper electrode (TE), the dielectric film (DL) may be interposed between the lower electrode (BE) and the upper electrode (TE). The lower electrode (BE), the dielectric film (DL), and the upper electrode (TE) may form a capacitor (CA).

[0057] FIG. 14 is a cross-sectional view corresponding to A-A' of FIG. 1, showing a semiconductor device according to another embodiment of the present invention. For the sake of simplicity, descriptions of content that overlap with the foregoing are omitted.

[0058] Referring to FIG. 14, the top of the shim (SM) may be positioned at a height lower than the bottom surface (USb) of the upper support pattern (US). Accordingly, the bottom (BEb) of the second part (BE2) of the lower electrode (BE) may be positioned at a height lower than the bottom surface (USb) of the upper support pattern (US). The upper surface of the lower electrode (BE) (for example, the top (BEa) of the second part (BE2)) may be lower than the upper surface (USa) of the upper support pattern (US) and higher than the bottom surface (USb) of the upper support pattern (US). Through this, the lower electrode (BE) may be supported by the upper support pattern (US).

[0059] FIGS. 15 to 17 are cross-sectional views illustrating a method for manufacturing a semiconductor device of FIG. 14. For the sake of simplicity, descriptions of content that overlap with the foregoing are omitted.

[0060] Referring to FIG. 15, the upper portion of the lower electrode membrane (50) of FIG. 7 can be removed, and a first portion (BE1) of the lower electrode (BE) can be formed. By removing the upper portion of the first lower electrode membrane (50), the core (SM) can be exposed to the outside. The core (SM) can be exposed to the outside by the upper surface of the first portion (BE1). The upper surface of the first portion (BE1) can be located at a height lower than the bottom surface of the upper support membrane (26). As a result, the upper portion of the core (SM) can be located at a height lower than the bottom surface of the upper support membrane (26). The side of the upper support membrane (26) can be exposed by the first portion (BE1).

[0061] Referring to FIG. 16, a second lower electrode membrane (55) may be formed on the first portion (BE1). The upper end of the core (SM) may be closed by the second lower electrode membrane (55). A portion of the lower end (55b) of the second lower electrode membrane (55) may be exposed by the core (SM). The lower end (55b) of the lower electrode membrane (55) may be a surface that meets the upper surface of the first portion (BE1), and the upper end of the core (SM) may be located at a provided height. That is, the lower end (55b) of the lower electrode membrane (55) may be located at a height lower than the bottom surface of the upper support membrane (26).

[0062] Referring to FIG. 17, the upper portion of the second lower electrode film (55) may be removed, and a lower electrode (BE) may be formed. The lower electrode (BE) may include the first portion (BE1) and the second portion (BE2) on the first portion (BE1). The upper surface of the lower electrode (BE) (for example, the upper portion (BEa) of the second portion (BE2)) may be located at a height lower than the upper surface of the upper support film (26). A portion of the lower portion (BEb) of the second portion (BE2) may be exposed by the core (SM). The lower portion (BEb) of the second portion (BE2) may be located at a height provided by the upper portion of the core (SM). That is, the lower portion (BEb) of the second portion (BE2) may be located at a height lower than the bottom surface of the upper support film (26). The first part (BE1) and the second part (BE2) can be in contact with each other without a boundary surface. Subsequently, the semiconductor device of FIG. 14 can be formed through the manufacturing method described with reference to FIG. 11 to 13 and FIG. 2.

[0064] FIG. 18 is a cross-sectional view corresponding to A-A' of FIG. 1, showing a semiconductor device according to another embodiment of the present invention. For the sake of simplicity, descriptions of content that overlap with the foregoing are omitted.

[0065] Referring to FIG. 18, the lower electrode (BE) may include a first part (BE1), a second part (BE2), and a third part (BE3) provided sequentially along the third direction (D3) from the substrate (10). A first core (SM1) may be placed inside the first part (BE1), and a second core (SM2) may be placed inside the third part (BE3). Although not illustrated, one or more cores (SM) may be placed inside the first part (BE1) at different heights from each other, and the first core (SM1) may be the core (SM) located at the highest height among the cores (SM) inside the first part (BE1). The second core (SM2) may penetrate the third part (BE3) along the third direction (D3).

[0066] The second part (BE2) may be positioned between the first part (BE1) and the third part (BE3). The second part (BE2) may be a part of the lower electrode (BE) provided above the top of the first core (SM1) and below the bottom of the second core (SM2). The bottom (BEb) of the second part (BE2) may be located at a height where the top of the first core (SM1) is provided, and the top (BEa) of the second part (BE2) may be located at a height where the bottom of the second core (SM2) is provided. A portion of the bottom (BEb) of the second part (BE2) may be exposed by the first core (SM1), and a portion of the top (BEa) of the second part (BE2) may be exposed by the second core (SM2).

[0067] The upper portion (BEc) of the third portion (BE3) may be lower than the upper surface (USa) of the upper support pattern (US) and higher than the bottom surface (USb) of the upper support pattern (US). Accordingly, the lower electrode (BE) may be supported by the upper support pattern (US).

[0068] For example, as illustrated in FIG. 18, the top (BEa) and bottom (BEb) of the second part (BE2) may be located at a height higher than the bottom surface (USb) of the upper support pattern (US). As another example, although not illustrated, the top (BEa) of the second part (BE2) may be located at a height higher than the bottom surface (USb) of the upper support pattern (US), and the bottom (BEb) of the second part (BE2) may be located at a height lower than the bottom surface (USb) of the upper support pattern (US). As yet another example, although not illustrated, the top (BEa) and bottom (BEb) of the second part (BE2) may be located at a height lower than the bottom surface (USb) of the upper support pattern (US). The third part (BE3) may contain the same material as the second part (BE2).

[0069] The dielectric film (DL) may come into contact with the upper surface (BEc) of the third part (BE3) (i.e., the upper surface of the lower electrode (BE)) and may cover the upper surface (BEc) of the third part (BE3). The dielectric film (DL) may be exposed by the second core (SM2). That is, the dielectric film (DL) may cover the second core (SM2).

[0070] FIGS. 19 and FIGS. 20 are cross-sectional views illustrating a method for manufacturing a semiconductor device of FIG. 18. For the sake of simplicity, descriptions of content that overlap with the foregoing are omitted.

[0071] Referring to FIG. 19, a second lower electrode film (55) is formed, and a second core (SM2) may be formed within the second lower electrode film (55). The second core (SM2) may be formed above the first core (SM1). For example, as shown in FIG. 19, the second core (SM2) may be an area closed by the lower electrode film (55). For another example, although not shown, the second core (SM2) may be exposed by the upper surface of the lower electrode film (55).

[0072] Referring to FIG. 20, the upper portion of the second lower electrode film (55) may be removed, and a lower electrode (BE) may be formed. The lower electrode (BE) may include the first portion (BE1), the second portion (BE2) on the first portion (BE1), and the third portion (BE3) on the second portion (BE2). The upper surface of the lower electrode (BE) (for example, the upper portion (BEc) of the third portion (BE3)) may be located at a height lower than the upper surface of the upper support film (26) and may be located at a height higher than the bottom surface of the upper support film (26).

[0073] A portion of the upper part (BEa) of the second part (BE2) may be exposed by the second core (SM2). The upper part (BEa) of the second part (BE2) may be located at a height provided by the lower part of the second core (SM2). A portion of the lower part (BEb) of the second part (BE2) may be exposed by the first core (SM1). The lower part (BEb) of the second part (BE2) may be located at a height provided by the upper part of the first core (SM). For example, as illustrated in FIG. 20, the lower part (BEb) of the second part (BE2) may be located at a height higher than the bottom surface of the upper support membrane (26). As another example, although not illustrated, the lower part (BEb) of the second part (BE2) may be located at a height higher than the bottom surface of the upper support membrane (26).

[0074] The second core (SM2) may be exposed to the outside by the upper surface of the lower electrode (BE) (for example, the upper end (BEc) of the third part (BE3). This allows the etching solution used in a subsequent etching process to penetrate into the interior of the lower electrode (BE) along the second core (SM2). However, the second core (SM2) cannot be extended to the lower part of the lower electrode (BE) by the second part (BE2), and accordingly, damage to the lower electrode (BE) by the etching solution can be minimized.

[0075] The first part (BE1) and the second part (BE2) can be in contact with each other without a boundary surface, and the second part (BE2) and the third part (BE3) can be in contact with each other without a boundary surface. Subsequently, the semiconductor device of FIG. 18 can be formed through the manufacturing method described with reference to FIG. 11 to 13 and FIG. 2.

[0077] FIG. 21 is a cross-sectional view corresponding to A-A' of FIG. 1, showing a semiconductor device according to another embodiment of the present invention. For the sake of simplicity, descriptions of content that overlap with the foregoing are omitted.

[0078] Referring to FIG. 21, the first width (W1) along the second direction (D2) of the upper surface (USa) of the upper support pattern (US) may be different from the second width (W2) along the second direction (D2) of the lower surface (USb) of the upper support pattern (US). For example, as shown in FIG. 21, the first width (W1) may be larger than the second width (W2). As another example, although not shown, the first width (W1) may be smaller than the second width (W2). The width of the upper surface of the lower support pattern (LS) may be different from the width of the lower surface of the lower support pattern (LS).

[0079] A portion of the side of the lower electrode (BE) may be in contact with the side of the upper support pattern (US) and the side of the lower support pattern (LS). The contacting side of the lower electrode (BE) may follow the profile of the side of the upper support pattern (US) and the side of the lower support pattern (LS). A shim (SM) may be provided inside the lower electrode (BE) along the profile of the side of the upper support pattern (US) and the side of the lower support pattern (LS). For example, an upper shim (SMt) may be provided adjacent to the upper support pattern (US).

[0080] Other parts of the sides of the lower electrode (BE), namely the remaining sides of the lower electrode (BE) that do not come into contact with the upper support pattern (US) and the lower support pattern (LS), may have various profiles. For example, as illustrated in FIG. 21, the remaining sides may extend in a straight line along a direction intersecting the second direction (D2) and the third direction (D3). As another example, although not illustrated, the remaining sides may extend in a rough shape along the third direction (D3). However, the concept of the present invention is not limited thereto.

[0081] FIGS. 22 to 26 are cross-sectional views illustrating a method for manufacturing a semiconductor device of FIG. 21. For the sake of simplicity, descriptions of content that overlap with the foregoing are omitted.

[0082] Referring to FIG. 22, a conductive hole (CH) can be formed that sequentially penetrates the upper support film (26), the second mold film (24), the lower support film (22), and the first mold film (20) of the mold structure (MS). The conductive hole (CH) can be formed by performing anisotropic etching using the second mask pattern (42) of FIG. 5 as an etching mask. The width of the upper support film (26), the second mold film (24), the lower support film (22), and the first mold film (20) along the second direction (D2) may vary depending on the height. For example, the width of the upper surface of the upper support film (26) may be greater than the width of the bottom surface of the upper support film (26). The side of the upper support membrane (26), the side of the second mold membrane (24), the side of the lower support membrane (26), and the side of the first mold membrane (20) may have various profiles.

[0083] Referring to FIG. 23, a first lower electrode film (50) may be formed on the mold structure (MS) and may fill the conductive hole (CH). A core (SM) may be provided inside the first lower electrode film (50), and the core (SM) may be formed along the profile of the side of the conductive hole (CH). An upper core (SMt) may be formed along the profile of the side of the upper support film (26) in an area adjacent to the upper support film (26).

[0084] Referring to FIG. 24, the upper portion of the first lower electrode film (50) may be removed, and a first portion (BE1) of the lower electrode (BE) may be formed. The first lower electrode film (50) may be separated into a plurality of first portions (BE1) that fill each of the conductive holes (CH). By removing the upper portion of the first lower electrode film (50), the upper core (SMt) may be exposed to the outside. The upper core (SMt) may be exposed to the outside by the upper surface of the first portion (BE1). The upper end of the upper core (SMt) may be located at a height lower than the upper surface of the upper support film (26).

[0085] Referring to FIG. 25, a second lower electrode film (55) may be formed on the first portion (BE1). The second lower electrode film (55) may fill the upper portion of the conductive hole (CH) that is not filled by the first portion (BE1) and may cover the upper support film (26). The upper portion of the upper core (SMt) may be closed by the second lower electrode film (55). A portion of the lower portion (55b) of the second lower electrode film (55) may be exposed by the upper core (SMt). The lower portion (55b) of the lower electrode film (55) may be a surface that meets the upper surface of the first portion (BE1), and the upper portion of the upper core (SMt) may be located at a provided height.

[0086] Referring to FIG. 26, the upper portion of the second lower electrode film (55) may be removed, and a lower electrode (BE) may be formed. The lower electrode (BE) may include the first portion (BE1) and the second portion (BE2) on the first portion (BE1). The second portion (BE2) may be formed by removing the upper portion of the second lower electrode film (55). The profile of the side of the lower electrode (BE) may be formed along the profiles of the side of the upper support film (26), the side of the second mold film (24), the side of the lower support film (26), and the side of the first mold film (20).

[0087] Referring again to FIG. 21, a dielectric film (DL) may be formed on the upper support pattern (US), the lower support pattern (LS), the lower electrode (BE), and the etching stop pattern (420). The dielectric film (DL) may conformally cover the upper support pattern (US), the lower support pattern (LS), the lower electrode (BE), and the etching stop pattern (420). An upper electrode (TE) may be formed on the dielectric film (DL). The upper electrode (TE) may fill the remainder of the through hole (PH) and cover the lower electrode (BE). By forming the upper electrode (TE), the dielectric film (DL) may be interposed between the lower electrode (BE) and the upper electrode (TE). The lower electrode (BE), the dielectric film (DL), and the upper electrode (TE) may form a capacitor (CA).

[0089] FIG. 27 is a block diagram showing a semiconductor device according to embodiments of the present invention. FIG. 28 is an enlarged view corresponding to part P1 of FIG. 27. FIG. 29 is a cross-sectional view corresponding to A-A' of FIG. 28. For the sake of simplicity, descriptions of content that overlap with the foregoing are omitted.

[0090] Referring to FIG. 27, the semiconductor device may include cell blocks (CB) and a surrounding block (PB) that surrounds each of the cell blocks (CB). The semiconductor device may be a memory device, and each of the cell blocks (CB) may include a cell circuit such as a memory integrated circuit. The cell blocks (CB) may be spaced apart from each other in a first direction (D1) and a second direction (D2) that intersects (e.g., orthogonal) the first direction (D1).

[0091] The peripheral block (PB) may include various peripheral circuits necessary for the operation of the cell circuit, and the peripheral circuits may be electrically connected to the cell circuit. The peripheral block (PB) may include sense amplifier circuits (SA) and sub-wordline driver circuits (SWD). For example, the sense amplifier circuits (SA) may face each other with the cell blocks (CB) in between, and the sub-wordline driver circuits (SWD) may face each other with the cell blocks (CB) in between. The peripheral block (PB) may further include power supply and ground driver circuits for driving the sense amplifier, but the concept of the present invention is not limited thereto.

[0092] Referring to FIGS. 28 and 29, a substrate (10) including a cell region may be provided. The cell region may be a region of the substrate (10) in which each cell block (CB) of FIG. 27 is provided. The substrate (10) may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0093] Active patterns (ACTs) may be disposed on the cell region of the substrate (10). In a planar view, the active patterns (ACTs) may be spaced apart from each other along the first direction (D1) and the second direction (D2). The active patterns (ACTs) may have a bar shape extending in a fourth direction (D4) that is parallel to the upper surface of the substrate (10) and intersects the first direction (D1) and the second direction (D2). Any end of the active patterns (ACTs) may be arranged to be adjacent to the center of another active pattern (ACT) immediately adjacent in the second direction (D2). Each of the active patterns (ACTs) may be a part of the substrate (10) protruding from the substrate (10) along the third direction (D3).

[0094] Device isolation films (120) may be disposed between the active patterns (ACT). The device isolation films (120) may be disposed within the substrate (10) to define the active patterns (ACT). The device isolation films (120) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0095] Word lines (WL) may be disposed within the substrate (10) and may cross the active patterns (ACT) and the device isolation films (120). The word lines (WL) may be disposed within grooves formed in the active patterns (ACT) and the device isolation films (120). The word lines (WL) may extend in the second direction (D2) and be spaced apart from each other along the first direction (D1). The word lines (WL) may be embedded within the substrate (10).

[0096] Impurity regions may be provided within the active patterns (ACT). The impurity regions may include first impurity regions (110a) and second impurity regions (110b). The second impurity regions (110b) may be provided adjacent to each of the two ends within each active pattern (ACT). Each of the first impurity regions (110a) may be provided between the second impurity regions (110b) within each active pattern (ACT). The first impurity regions (110a) may contain impurities of the same conductivity type (e.g., N-type) as the second impurity regions (110b).

[0097] A buffer pattern (305) may be disposed on the cell region of the substrate (10). The buffer pattern (305) may cover the active patterns (ACT), the device isolation films (120), and the word lines (WL). The buffer pattern (305) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0098] Bit lines (BL) may be disposed on the substrate (10). The bit lines (BL) may extend along the first direction (D1) and may be spaced apart from each other along the second direction (D2). Each of the bit lines (BL) may include a first ohmic pattern (331) and a metal-containing pattern (330) stacked in sequence. For example, the first ohmic pattern (331) may include a metal silicide. For example, the metal-containing pattern (330) may include a metal (tungsten, titanium, tantalum, etc.).

[0099] Polysilicon patterns (310) may be interposed between the bit lines (BL) and the buffer pattern (305).

[0100] Bitline contacts (DC) may be interposed between the bitlines (BL) and the first impurity regions (110a), respectively. The bitlines (BL) may be electrically connected to the first impurity regions (110a) by the bitline contacts (DC). The bitline contacts (DC) may comprise polysilicon that is doped with or undoped with impurities.

[0101] The bitline contacts (DC) may be placed within a recess region (RE). The recess region (RE) may be provided above the first impurity regions (110a) and above the adjacent device isolation films (120). The first buried insulation pattern (314) and the second buried insulation pattern (315) may fill the remainder within the recess region (RE).

[0102] A bitline capping pattern (350) may be provided on the upper surface of each of the bitlines (BL). The bitline capping pattern (350) may extend along the first direction (D1) on each of the bitlines (BL) and may be spaced apart from adjacent bitline capping patterns (350) along the second direction (D2). The bitline capping pattern (350) may include a first bitline capping pattern (351), a second bitline capping pattern (352), and a third bitline capping pattern (353). The bitline capping pattern (350) may include a silicon nitride film. For example, the first bitline capping pattern (351), the second bitline capping pattern (352), and the third bitline capping pattern (353) may include a silicon nitride film.

[0103] Each side of the polysilicon patterns (310), each upper side of the bitline contacts (DC), each side of the bitlines (BL), and the side of the bitline capping pattern (350) may be covered by a bitline spacer (SP). The bitline spacer (SP) may extend along the first direction (D1) on each of the bitlines (BL).

[0104] The bitline spacer (SP) may include a first sub-spacer (321) and a second sub-spacer (325) spaced apart from each other. For example, the first sub-spacer (321) and the second sub-spacer (325) may be spaced apart by an air gap (AG). The first sub-spacer (321) may be in contact with each side of the bitlines (BL) and may extend along the side of the bitline capping pattern (350). The second sub-spacer (325) may be provided along the side of the first sub-spacer (321). The first sub-spacer (321) and the second sub-spacer (325) may have a single-layer or multi-layer structure among at least one silicon nitride film, silicon oxide film, or silicon oxynitride film. The first sub-spacer (321) and the second sub-spacer (325) may contain the same material.

[0105] The fourth capping pattern (360) may cover the side of the first sub-spacer (321) and extend to the upper surface of the second sub-spacer (325). The fourth capping pattern (360) may further cover the air gap (AG).

[0106] Storage node contacts (BC) may be interposed between adjacent bit lines (BL) on the substrate (10). A bit line spacer (SP) may be interposed between the storage node contacts (BC) and the adjacent bit lines (BL). The storage node contacts (BC) may be spaced apart from each other in the first direction (D1) and the second direction (D2). Each of the storage node contacts (BC) may be electrically connected to a corresponding one of the second impurity regions (110b). The storage node contacts (BC) may comprise polysilicon that is impurity-doped or undoped.

[0107] A second ohmic pattern (341) may be placed on each of the storage node contacts (BC). The second ohmic pattern (341) may include a metal silicide.

[0108] The diffusion prevention pattern (342) may conformally cover the second ohmic pattern (341), the bitline spacer (SP), and the bitline capping pattern (350). The diffusion prevention pattern (342) may include a metal nitride such as a titanium nitride film or a tantalum nitride film. The second ohmic pattern (341) may be interposed between the diffusion prevention pattern (342) and each of the storage node contacts (BC).

[0109] Landing pads (LP) may be placed on the storage node contacts (BC) respectively. Each of the landing pads (LP) may be electrically connected to a corresponding one of the storage node contacts (BC). The landing pads (LP) may comprise a metal-containing material such as tungsten. The upper portion of the landing pads (LP) may be shifted from the storage node contacts (BC) in the second direction (D2). In a planar view, the landing pads (LP) may be spaced apart from each other in the first direction (D1) and the second direction (D2). For example, the landing pads (LP) may be spaced apart from each other in the first direction (D1) and the second direction (D2) in a zigzag pattern. Each of the landing pads (LP) may correspond to the conductive contact (14) of FIG. 2.

[0110] A filling pattern (400) may wrap around each of the landing pads (LP). The filling pattern (400) may be interposed between adjacent landing pads (LP). For example, the filling pattern (400) may include at least one of silicon nitride, silicon oxide, or silicon oxynitride. For another example, the filling pattern (400) may include an empty region. The filling pattern (400) may correspond to the interlayer insulating film (12) of FIG. 2.

[0111] An etching prevention pattern (420) may be disposed on the filling pattern (400). The etching prevention pattern (420) may expose the upper surfaces of the landing pads (LP). A lower electrode (BE) may be disposed on the landing pads (LP). There may be multiple lower electrodes (BE) and they may be disposed on one of the corresponding landing pads (LP). The lower electrode (BE) may be electrically connected to the corresponding landing pad (LP).

[0112] A support pattern may be provided on the substrate (10). The support pattern may include an upper support pattern (US) and a lower support pattern (LS) spaced apart from each other in the third direction (D3). The support pattern may be interposed between the lower electrode (BE) and an adjacent lower electrode (BE).

[0113] An upper electrode (TE) may cover the lower electrode (BE) and the support pattern. A dielectric film (DL) may be interposed between the lower electrode (BE) and the upper electrode (TE), and between the support pattern and the upper electrode (TE). The lower electrode (BE), the dielectric film (DL), and the upper electrode (TE) may form a capacitor (CA). The capacitor (CA) may correspond to the capacitor (CA) of the semiconductor device according to the embodiments of the present invention described above. That is, the characteristics of the lower electrode (BE), the dielectric film (DL), and the upper electrode (TE) may correspond to the characteristics of each embodiment described above.

[0115] The above description of the embodiments of the present invention provides examples for explaining the present invention. Accordingly, the present invention is not limited to the above embodiments, and it is evident that many modifications and changes are possible within the technical scope of the present invention, such as combining the above embodiments by those skilled in the art. Explanation of the symbols

[0116] BE: Lower electrode DL: Dielectric film TE: Upper electrode US, LS: Upper and lower support patterns SM: Heart

Claims

Claim 1 A semiconductor device comprising: a lower electrode on a substrate; a support pattern provided between the lower electrode and an adjacent lower electrode; an upper electrode covering the lower electrode and the support pattern; and a dielectric film provided between the lower electrode and the upper electrode and between the support pattern and the upper electrode, wherein the lower electrode comprises a first portion including a seam and a second portion on the first portion, the upper portion of the second portion is located at a height lower than the upper surface of the support pattern, and a portion of the lower portion of the second portion is exposed by the seam. Claim 2 In claim 1, the upper portion of the second part is a semiconductor device located at a height higher than the bottom surface of the support pattern. Claim 3 In claim 1, the lower portion of the second part is a semiconductor device located at a height higher or lower than the bottom surface of the support pattern. Claim 4 A semiconductor device according to claim 1, wherein the first part comprises a plurality of cores located at different heights, and the lower part of the second part is exposed by the uppermost core among the cores. Claim 5 A semiconductor device according to claim 1, wherein the lower electrode further comprises a third portion on the second portion, the third portion comprises a core, and a portion of the dielectric film is exposed by the core of the third portion. Claim 6 In claim 5, the upper portion of the third part is lower than the upper surface of the support pattern and is located at a height higher than the bottom surface of the support pattern. Claim 7 In claim 1, the first width of the upper surface of the support pattern is different from the second width of the bottom surface of the support pattern. Claim 8 A semiconductor device according to claim 1, wherein the support pattern comprises a plurality of support patterns located at different heights, and the upper portion of the second part is located at a height lower than the upper surface of the uppermost support pattern among the plurality of support patterns. Claim 9 A semiconductor device comprising: a substrate including an active pattern; an impurity region provided within the active pattern; a word line disposed within the substrate and extending across the active pattern; a bit line disposed on the substrate and extending in a direction intersecting the word line; a storage node contact disposed on the substrate and electrically connected to the impurity region; a landing pad electrically connected to the storage node contact; a lower electrode electrically connected to the landing pad; an upper support pattern and a lower support pattern provided between the lower electrode and an adjacent lower electrode; an upper electrode covering the lower electrode and the upper support pattern; and a dielectric film provided between the lower electrode and the upper electrode and between the upper support pattern and the upper electrode, wherein the lower electrode comprises a first portion including a seam and a second portion on the first portion, the upper portion of the second portion is located at a height lower than the upper surface of the support pattern, and a portion of the lower portion of the second portion is exposed by the seam. Claim 10 A semiconductor device according to claim 9, wherein the lower electrode further comprises a third portion on the second portion, the third portion comprises a core, and a portion of the dielectric film is exposed by the core of the third portion.

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