Display panel and display apparatus including the same

Abstract

The present invention provides a display panel having improved resolution in an area where a component is placed and a display device having the same, comprising: a substrate having a first surface and a second surface facing the first surface; a first pixel circuit disposed on the first surface of the substrate; a first through electrode that penetrates the substrate and is connected to the first pixel circuit; a first pad electrode disposed on the second surface of the substrate and connected to the first through electrode; a counter electrode disposed on the first surface of the substrate and disposed on the first pixel circuit; a second through electrode that penetrates the substrate and is connected to the counter electrode; and a second pad electrode disposed on the second surface of the substrate and connected to the second through electrode.

Description

Technology Field

[0001] The present invention relates to a display panel and a display device equipped with the same. Background Technology

[0002] A display device is a device that visually displays data. Display devices are used as displays for small products such as mobile phones, as well as for large products such as televisions.

[0003] Such a display device includes a substrate partitioned into a display area and a non-display area, wherein gate lines and data lines are formed in the display area with mutual insulation. A plurality of pixel regions are defined within the display area, and pixels disposed in each of the plurality of pixel regions emit light by receiving electrical signals from intersecting gate lines and data lines to display an image externally. Each pixel region (or each of pixel regions) is equipped with a thin-film transistor and a pixel electrode electrically connected to said thin-film transistor, and a counter electrode is provided in common to said pixel regions. The non-display area may be equipped with various wirings that transmit electrical signals to the pixels within the display area, a gate driver, and pads to which a data driver and a control unit can be connected.

[0004] Recently, the applications of display devices have become more diverse. Furthermore, as display devices become thinner and lighter, their range of use is expanding. As display devices are utilized in various ways, there are diverse methods for designing their forms, and the number of functions that can be integrated or linked with display devices is increasing. The problem to be solved

[0005] The present invention aims to solve various problems by providing a display panel with an expanded display area and a display device equipped with the same, so that an image can be displayed even in an area where an electronic component is placed. However, this problem is exemplary and the scope of the present invention is not limited thereby. means of solving the problem

[0006] According to one aspect of the present invention, a display panel is provided comprising: a substrate having a first surface and a second surface opposite to the first surface; a first pixel circuit disposed on the first surface of the substrate; a first through electrode that penetrates the substrate and is connected to the first pixel circuit; a first pad electrode disposed on the second surface of the substrate and connected to the first through electrode; a counter electrode disposed on the first surface of the substrate and disposed on the first pixel circuit; a second through electrode that penetrates the substrate and is connected to the counter electrode; and a second pad electrode disposed on the second surface of the substrate and connected to the second through electrode.

[0007] According to one example, the display panel may further include a first display element that is disposed on the first surface of the substrate and connected to the first pixel circuit.

[0008] According to one example, the display panel further comprises a second pixel circuit disposed on the first surface of the substrate; and a second display element disposed on the first surface of the substrate and connected to the second pixel circuit, wherein the substrate has a component area and a main area surrounding at least a portion of the component area, the first pixel circuit disposed in the component area or the main area, the first display element, the first pad electrode, and the second pad electrode disposed in the component area, and the second pixel circuit and the second display element disposed in the main area.

[0009] According to one example, when the first pixel circuit is placed in the component area, the first pixel circuit and the first display element and the second pixel circuit and the second display element each overlap at least partially with each other, and when the first pixel circuit is placed in the main area, the first pixel circuit and the second display element may overlap at least partially with each other.

[0010] According to one example, the display panel further comprises a second pixel circuit disposed on the first surface of the substrate; and a second display element disposed on the first surface of the substrate and connected to the second pixel circuit, wherein the first pixel circuit comprises a first driving transistor that controls a current flowing to the first pad electrode; a first scan transistor that transmits a first data voltage to the first driving transistor in response to a first scan signal; and a first storage capacitor having a first electrode and a second electrode connected to the gate of the first driving transistor, and the second pixel circuit may comprise a second driving transistor that controls a current flowing to the second display element; a second scan transistor that transmits a second data voltage to the second driving transistor in response to a second scan signal; and a second storage capacitor having a third electrode and a fourth electrode connected to the gate of the second driving transistor.

[0011] According to one example, the ratio of the width to the length of the channel of the first driving transistor may be smaller than the ratio of the width to the length of the channel of the second driving transistor.

[0012] According to one example, the display panel may further include a connection line extending in a first direction to connect the first through electrode to the first pixel circuit.

[0013] According to another aspect of the present invention, a display device is provided comprising: a substrate having a first surface and a second surface opposite to the first surface; a first pixel circuit disposed on the first surface of the substrate; a first through electrode that penetrates the substrate and is connected to the first pixel circuit; a first pad electrode disposed on the second surface of the substrate and connected to the first through electrode; and a first display element disposed on the second surface of the substrate and connected to the first pad electrode.

[0014] According to one example, the display device further includes a counter electrode disposed on the first surface of the substrate, and the first display element may be connected to the counter electrode.

[0015] According to one example, the display device further comprises a second through electrode that penetrates the substrate and is connected to the opposing electrode; and a second pad electrode disposed on the second surface of the substrate and connected to the second through electrode, and the first display element may include a first conductive pad electrode connected to the first pad electrode and a second conductive pad electrode connected to the second pad electrode.

[0016] According to one example, the display device may further include a second display element disposed on the first surface of the substrate and connected to the first pixel circuit.

[0017] According to one example, the light-emitting layer of the first display element may include an inorganic material, and the light-emitting layer of the second display element may include an organic material.

[0018] According to one example, the light-emitting area of ​​the first display element may be smaller than the light-emitting area of ​​the second display element.

[0019] According to one example, the first display element and the second display element are each composed of a plurality, and the plurality of first display elements and the plurality of second display elements can be arranged alternately along a first direction.

[0020] According to one example, the display device further comprises a second pixel circuit disposed on a first surface of the substrate; and a second display element disposed on the first surface of the substrate and connected to the second pixel circuit, wherein the first pixel circuit comprises a first driving transistor that controls a current flowing to the first display element; a first scan transistor that transmits a first data voltage to the first driving transistor in response to a first scan signal; and a first storage capacitor having a first electrode and a second electrode connected to the gate of the first driving transistor, and the second pixel circuit may comprise a second driving transistor that controls a current flowing to the second display element; a second scan transistor that transmits a second data voltage to the second driving transistor in response to a second scan signal; and a second storage capacitor having a third electrode and a fourth electrode connected to the gate of the second driving transistor.

[0021] According to one example, the ratio of the width to the length of the channel of the first driving transistor may be smaller than the ratio of the width to the length of the channel of the second driving transistor.

[0022] According to one example, the light-emitting layer of the first display element may include an inorganic material, and the light-emitting layer of the second display element may include an organic material.

[0023] According to one example, the light-emitting area of ​​the first display element may be smaller than the light-emitting area of ​​the second display element.

[0024] According to one example, on a plane, the first display element and the first pixel circuit may be spaced apart from each other.

[0025] According to one example, the display device further includes a component disposed on the second surface of the substrate, and the first display element may be disposed between the substrate and the component.

[0026] Other aspects, features, and advantages other than those described above will become clear from the following specific details, claims, and drawings for implementing the invention.

[0027] These general and specific aspects may be implemented using a system, method, computer program, or any combination of a system, method, or computer program. Effects of the invention

[0028] According to one embodiment of the present invention as described above, a display element is disposed on the lower part of a substrate corresponding to the area where a component is disposed, thereby enabling the implementation of a display panel with improved resolution in the area where the component is disposed and a display device equipped with the same. Of course, the scope of the present invention is not limited by such effects. Brief explanation of the drawing

[0029] FIG. 1 is a cross-sectional view schematically illustrating a display device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view schematically illustrating a display device according to another embodiment of the present invention. FIG. 3 is an equivalent circuit diagram schematically showing a pixel circuit that can be applied to a display panel according to one embodiment of the present invention. FIG. 4 is a perspective view schematically illustrating an application example of a display device according to one embodiment of the present invention. Figure 5 is an enlarged plan view schematically illustrating a part of Figure 4. FIG. 6 is an exemplary cross-sectional view of the first to third pixels of FIG. 5, cut along II-II' and III-III', respectively. FIG. 7 is an exemplary cross-sectional view of the second and third pixels of FIG. 5 taken along III-III'. FIG. 8 is an enlarged plan view schematically illustrating a part of FIG. 4. FIG. 9 is an enlarged plan view schematically illustrating a part of FIG. 4. FIG. 10 is an exemplary cross-sectional view of the first to third pixels of FIG. 9, cut along IV-IV' and V-V', respectively. FIG. 11 is an enlarged plan view schematically illustrating a part of FIG. 4. FIG. 12 is an exemplary cross-sectional view of the second and third pixels of FIG. 11 taken along VI-VI'. FIG. 13 is an enlarged plan view schematically illustrating a part of FIG. 4. FIG. 14 is an enlarged plan view schematically illustrating a part of FIG. 4. FIG. 15 is an enlarged plan view schematically illustrating a part of FIG. 4. Specific details for implementing the invention

[0030] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0032] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0033] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0034] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0035] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of the other part, but also cases where another film, region, or component is interposed therein.

[0036] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0037] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0038] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. And, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0039] In the following embodiments, when a membrane, region, component, etc. is described as being connected, it includes cases where the membrane, region, or component is directly connected, or / or cases where other membranes, regions, or components are interposed between the membranes, regions, or components to be indirectly connected. For example, when a membrane, region, component, etc. is described as being electrically connected in this specification, it indicates cases where the membrane, region, or component, etc. are directly electrically connected, and / or cases where other membranes, regions, or components are interposed between them to be indirectly electrically connected.

[0040] The x-axis, y-axis, and z-axis are not limited to the three axes of an orthogonal coordinate system but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0041] FIG. 1 is a cross-sectional view schematically illustrating a display device according to one embodiment of the present invention.

[0042] Referring to FIG. 1, the display device (1) may include a display panel (10) and a display element (DE).

[0043] The display panel (10) may include a substrate (100), a pixel circuit (PC), an insulating layer (IL), a through-electrode (TE), and a pad electrode (PE).

[0044] The substrate (100) may have a first surface (100a) and a second surface (100b) facing the first surface (100a). The substrate (100) may be made of an insulating material such as glass, quartz, or polymer resin. The substrate (100) may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc.

[0045] A pixel circuit (PC) may be disposed on the first surface (100a) of the substrate (100). The pixel circuit (PC) may include at least one transistor and a storage capacitor as shown in FIG. 3, which will be described later. For example, the pixel circuit (PC) may include a driving transistor that controls the current flowing to the display element (DE).

[0046] An insulating layer (IL) may be disposed on the pixel circuit (PC). The insulating layer (IL) is silicon oxide (SiO2) or silicon nitride (SiN XIt may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO), etc. As another example, the insulating layer (IL) may include organic materials. For example, it may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof.

[0047] In FIG. 1, the insulating layer (IL) is shown being placed on the pixel circuit (PC), but in another embodiment, the insulating layer (IL) may be placed inside the pixel circuit (PC).

[0048] The through electrode (TE) can penetrate the substrate (100) and be connected to the pixel circuit (PC). The through electrode (TE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the through electrode (TE) may be formed as a multilayer structure of Ti / Al / Ti.

[0049] A pad electrode (PE) may be disposed on the second surface (100b) of the substrate (100). The pad electrode (PE) may be connected to a through electrode (TE). The pad electrode (PE) may be connected to a pixel circuit (PC) through the through electrode (TE). The pad electrode (PE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the pad electrode (PE) may be formed as a multilayer structure of Ti / Al / Ti.

[0050] The through electrode (TE) and the pad electrode (PE) may be a single unit. At least a portion of the pad electrode (PE) may be embedded in a hole formed in the substrate (100), and at least a portion of the pad electrode (PE) embedded in the hole may be referred to as the through electrode (TE).

[0051] A display element (DE) may be placed on a second surface (100b) of a substrate (100). A substrate (100) may be placed between the display element (DE) and the pixel circuit (PC).

[0052] The display element (DE) may include a light-emitting layer, and the light-emitting layer may include an inorganic or an organic material. The display element (DE) may be an inorganic light-emitting diode (or micro LED, m-LED) or an organic light-emitting diode (OLED).

[0053] The display element (DE) can be connected to the pad electrode (PE). The anode of the display element (DE) can be connected to the pad electrode (PE). The display element (DE) can be connected to the pixel circuit (PC) through the pad electrode (PE) and the through-electrode (TE). The display element (DE) can be driven by the pixel circuit (PC).

[0054] Although not shown in FIG. 1, a specific voltage may be applied to the cathode of the display element (DE). For example, a second driving voltage (ELVSS) shown in FIG. 3, which will be described later, may be applied to the cathode of the display element (DE). The cathode of the display element (DE) may be a common electrode to which the second driving voltage (ELVSS) is applied.

[0055] FIG. 2 is a cross-sectional view schematically illustrating a display device according to another embodiment of the present invention.

[0056] Referring to FIG. 2, the display device (1') may include a display panel (10') and a display element (DE').

[0057] The display panel (10) may include a substrate (100), a pixel circuit (PC), an insulating layer (IL), a counter electrode (230), a first through electrode (TE1), a second through electrode (TE2), a first pad electrode (PE1), and a second pad electrode (PE2).

[0058] A substrate (100) may have a first surface (100a) and a second surface (100b) facing the first surface (100a). A pixel circuit (PC) may be disposed on the first surface (100a) of the substrate (100). An insulating layer (IL) may be disposed on the pixel circuit (PC).

[0059] A counter electrode (230) may be disposed on the insulating layer (IL). The counter electrode (230) may be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode (230) may be a transparent or translucent electrode and may be formed of a metal thin film with a low work function comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. Additionally, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 may be further disposed on the metal thin film.

[0060] The first through-hole electrode (TE1) can be connected to a pixel circuit (PC) by penetrating the substrate (100). The second through-hole electrode (TE2) can be connected to a counter electrode (230) by penetrating the substrate (100). The first through-hole electrode (TE1) and the second through-hole electrode (TE2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the first through-hole electrode (TE1) and the second through-hole electrode (TE2) may be formed as a multilayer structure of Ti / Al / Ti.

[0061] A first pad electrode (PE1) and a second pad electrode (PE2) may be disposed on the second surface (100b) of the substrate (100). The first pad electrode (PE1) may be connected to a first through electrode (TE1), and the second pad electrode (PE2) may be connected to a second through electrode (TE2). The first pad electrode (PE1) may be connected to a pixel circuit (PC) through the first through electrode (TE1), and the second pad electrode (PE2) may be connected to a counter electrode (230) through the second through electrode (TE2).

[0062] The first pad electrode (PE1) and the second pad electrode (PE2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the first pad electrode (PE1) and the second pad electrode (PE2) may be formed as a multilayer structure of Ti / Al / Ti.

[0063] The first through electrode (TE1) and the first pad electrode (PE1) may be integral. At least a portion of the first pad electrode (PE1) may be embedded in a hole formed in the substrate (100), and at least a portion of the first pad electrode (PE1) embedded in the hole may be referred to as the first through electrode (TE1).

[0064] The second through electrode (TE2) and the second pad electrode (PE2) may be integral. At least a portion of the second pad electrode (PE2) may be embedded in a hole formed in the substrate (100), and at least a portion of the second pad electrode (PE2) embedded in the hole may be referred to as the second through electrode (TE2).

[0065] A display element (DE') may be disposed on a second surface (100b) of a substrate (100). A substrate (100) may be disposed between the display element (DE') and the pixel circuit (PC). The display element (DE') may include a light-emitting layer, and the light-emitting layer may include an inorganic or organic material. The display element (DE') may be an inorganic light-emitting diode (or micro LED, m-LED) or an organic light-emitting diode.

[0066] One end of the display element (DE') may be connected to the first pad electrode (PE1), and the other end of the display element (DE') may be connected to the second pad electrode (PE2). The anode of the display element (DE') may be connected to the first pad electrode (PE1), and the cathode of the display element (DE') may be connected to the second pad electrode (PE2).

[0067] One end (or anode) of the display element (DE') is connected to the pixel circuit (PC) through the first pad electrode (PE1) and the first through electrode (TE1), and the other end (or cathode) of the display element (DE') can be connected to the opposing electrode (230) through the second pad electrode (PE2) and the second through electrode (TE2).

[0068] FIG. 3 is an equivalent circuit diagram schematically showing a pixel that can be applied to a display panel according to one embodiment of the present invention.

[0069] Referring to FIG. 3, a pixel (PX) may include a pixel circuit (PC) connected to a scan line (SL) and a data line (DL), and a display element (DE) connected to the pixel circuit (PC). The cathode of the display element (DE) may be a common electrode to which a second driving voltage (ELVSS) is applied. The pixel circuit (PC) of FIG. 3 corresponds to the pixel circuit (PC) of FIG. 1 and FIG. 2, and the display element (DE) of FIG. 3 may correspond to the display element (DE) of FIG. 1 and the display element (DE') of FIG. 2.

[0070] The pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst).

[0071] The first transistor (T1) is a driving transistor in which the magnitude of the drain current is determined according to the gate-source voltage, and the second transistor (T2) may be a switching transistor that is turned on / off according to the gate-source voltage, substantially the gate voltage. The first transistor (T1) and the second transistor (T2) may be formed as thin-film transistors.

[0072] The first transistor (T1) may be referred to as a driving transistor, and the second transistor (T2) may be referred to as a scan transistor.

[0073] A storage capacitor (Cst) is connected between the power line (PL) and the gate of the driving transistor (T1). The storage capacitor (Cst) may have a second electrode (CE2) connected to the power line (PL) and a first electrode (CE1) connected to the gate of the driving transistor (T1). The storage capacitor (Cst) can store a voltage corresponding to the difference between the voltage received from the scan transistor (T2) and the first driving voltage (ELVDD) supplied to the power line (PL).

[0074] The driving transistor (T1) can control the magnitude of the current (Id) flowing from the power line (PL) to the display element (DE) according to the gate-source voltage. The display element (DE) can emit light having a predetermined brightness by the driving current (Id). The driving transistor (T1) may have a gate connected to the first electrode (CE1) of the storage capacitor (Cst), a source connected to the power line (PL), and a drain connected to the display element (DE).

[0075] The scan transistor (T2) can transmit a data voltage (Dm) to the gate of the driving transistor (T1) in response to a scan signal (Sn). The scan transistor (T2) may have a gate connected to the scan line (SL), a source connected to the data line (DL), and a drain connected to the gate of the driving transistor (T1).

[0076] FIG. 3 describes a case where the pixel circuit (PC) includes two transistors and one storage capacitor, but the present invention is not limited thereto. For example, the pixel circuit (PC) may include three or more transistors and / or two or more storage capacitors. In one embodiment, the pixel circuit (PC) may include seven transistors and one storage capacitor.

[0077] FIG. 4 is a perspective view schematically illustrating an application example of a display device according to one embodiment of the present invention.

[0078] Referring to FIG. 4, a display device (1a) may include a display area (DA) and a peripheral area (PA) outside the display area (DA). The display area (DA) may include a component area (CA) and a main area (MA) that at least partially surrounds the component area (CA). Each of the component area (CA) and the main area (MA) may display an image individually or together. The peripheral area (PA) may be a type of non-display area where display elements are not placed. The display area (DA) may be entirely surrounded by the peripheral area (PA).

[0079] FIG. 4 illustrates a component area (CA) located within a main area (MA). In another embodiment, the display device (1a) may have two or more component areas (CA), and the shapes and sizes of the multiple component areas (CA) may differ from one another. When viewed from a direction approximately perpendicular to the upper surface of the display device (1a), the shape of the component area (CA) may have various shapes such as a circle, an ellipse, a polygon such as a square, a star shape, or a diamond shape. Although FIG. 4 illustrates the component area (CA) being positioned at the upper center (+y direction) of the main area (MA), which has a roughly rectangular shape when viewed from a direction approximately perpendicular to the upper surface of the display device (1a), the component area (CA) may be positioned on one side of the rectangular main area (MA), for example, the upper right or upper left side.

[0080] The display device (1a) can provide an image using a plurality of pixels (PX) placed in a display area (DA). The display device (1a) can provide an image using a plurality of first pixels (PX1) placed in a main area (MA), a plurality of second pixels (PX2) and a plurality of third pixels (PX3) placed in a component area (CA).

[0081] Each of the first pixels (PX1), the second pixels (PX2), and the third pixels (PX3) may be equipped with a display element. Each pixel (PX) may emit light, for example, red, green, blue, or white light through the display element. Each pixel (PX) refers to a sub-pixel that emits a different color, and each pixel (PX) may be, for example, one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0082] In one embodiment, the third pixel (PX3) may have the structure of the display device (1, 1') illustrated in FIG. 1 or FIG. 2 described above. That is, the display element of the third pixel (PX3) may be placed at the bottom of the display panel and connected to the pixel circuit through a through electrode that penetrates the substrate of the display panel. This will be explained in more detail in FIG. 6.

[0083] In one embodiment, each of the first pixels (PX1), the second pixels (PX2), and the third pixels (PX3) may have different types of display elements. For example, each of the first pixels (PX1) and the second pixels (PX2) may include an organic light-emitting diode as a display element, and each of the third pixels (PX3) may include an inorganic light-emitting diode as a display element. In other words, the light-emitting layer of the display element of each of the first pixels (PX1) and the second pixels (PX2) may include an organic material, and the light-emitting layer of the display element of each of the third pixels (PX3) may include an inorganic material.

[0084] In another embodiment, the first pixels (PX1), the second pixels (PX2), and the third pixels (PX3) may each have the same type of display element. For example, the first pixels (PX1), the second pixels (PX2), and the third pixels (PX3) may each include an organic light-emitting diode or an inorganic light-emitting diode as a display element.

[0085] In one embodiment, the number of second pixels (PX2) per unit area may be less than the number of first pixels (PX1) per unit area. The number of third pixels (PX3) per unit area may be less than the number of first pixels (PX1) per unit area.

[0086] The number of second pixels (PX2) and third pixels (PX3) per unit area may be less than the number of first pixels (PX1) per unit area. Light and / or sound may be transmitted in areas of the component area (CA) where the second pixels (PX2) and third pixels (PX3) are not placed.

[0087] In addition, the number of second pixels (PX2) and the number of third pixels (PX3) per unit area are each less than the number of first pixels (PX1) per unit area, but both the second pixels (PX2) and the third pixels (PX3) are placed in the component area (CA) so that the difference in resolution between the image displayed in the component area (CA) and the image displayed in the main area (MA) can be improved.

[0088] In one embodiment, the size of the third pixel (PX3) may be smaller than the size of the second pixel (PX2). The space occupied by the third pixel (PX3) per unit area may be smaller than the space occupied by the second pixel (PX2) per unit area. As such, since the space occupied by the third pixel (PX3) per unit area is small, the transmittance of light and / or sound in the component area (CA) can be secured.

[0089] The second pixel (PX2) may include an organic light-emitting diode, and the third pixel (PX3) may include an inorganic light-emitting diode. In this case, even if the third pixel (PX3) is smaller than the second pixel (PX2), the third pixel (PX3) may emit light of the same brightness as the second pixel (PX2).

[0090] In the case of a display device (1a) according to one embodiment of the present invention, when light is transmitted through a component area (CA), the light transmittance may be about 10% or more, more preferably 40% or more, 25% or more, 50% or more, 85% or more, or 90% or more.

[0091] As described below with reference to FIG. 6, a component (20), which is an electronic element, may be disposed in the lower part of the display panel corresponding to the component area (CA). The component (20) may be a camera that uses infrared or visible light, and may be equipped with an imaging element. Alternatively, the component (20) may be a solar cell, a flash, an illuminance sensor, a proximity sensor, or an iris sensor. Alternatively, the component (20) may have a function of receiving sound.

[0092] Figure 5 is an enlarged plan view schematically illustrating a part of Figure 4.

[0093] Referring to FIG. 5, the display device (1a, FIG. 4) may include first pixels (PX1) placed in a main area (MA), and second pixels (PX2) and third pixels (PX3) placed in a component area (CA).

[0094] Each of the first pixels (PX1) may include a first pixel circuit (PC1) and a first display element (DE1), each of the second pixels (PX2) may include a second pixel circuit (PC2) and a second display element (DE2), and each of the third pixels (PX3) may include a second pixel circuit (PC2) and a third display element (DE3). The second pixel (PX2) and the third pixel (PX3) may share the second pixel circuit (PC2).

[0095] The first display element (DE1) is driven by the first pixel circuit (PC1), and the second display element (DE2) and the third display element (DE3) can be driven simultaneously by the second pixel circuit (PC2).

[0096] In FIG. 5, the third display element (DE3) is shown as being connected to a second pixel circuit (PC2) that is placed in the same column as the third display element (DE3), but in another embodiment, the third display element (DE3) may be connected to a second pixel circuit (PC2) that is placed in the same row as the third display element (DE3).

[0097] Additionally, although FIG. 5 illustrates that the third display elements (DE3) are each connected to the second pixel circuits (PC2), in another embodiment, the third display elements (DE3) may each be connected to the first pixel circuits (PC1). In yet another embodiment, some of the third display elements (DE3) may be connected to the first pixel circuits (PC1), and others may be connected to the second pixel circuits (PC2).

[0098] The first pixel circuit (PC1) and the first display element (DE1) may overlap at least partially with each other, and the second pixel circuit (PC2) and the second display element (DE2) may overlap at least partially with each other. The second pixel circuit (PC2) and the third display element (DE3) may not overlap with each other. In other words, the second pixel circuit (PC2) and the third display element (DE3) may be spaced apart from each other on a plane.

[0099] In FIG. 5, the planar shape of each of the first pixel circuit (PC1), the first display element (DE1), the second pixel circuit (PC2), the second display element (DE2), and the third display element (DE3) is depicted as a rectangle, but the planar shape of each of the first pixel circuit (PC1), the first display element (DE1), the second pixel circuit (PC2), the second display element (DE2), and the third display element (DE3) can be varied in various ways, such as a diamond shape, a circle, an ellipse, or a polygon.

[0100] Additionally, although FIG. 5 illustrates the second pixel circuit (PC2) being placed in the component area (CA), in another embodiment, the second pixel circuit (PC2) may be placed in the main area (MA). This will be described later in FIG. 9.

[0101] In one embodiment, as shown in FIG. 5, the light-emitting area of ​​the third display element (DE3) may be smaller than the light-emitting area of ​​the second display element (DE2). The light-emitting area of ​​the first display element (DE1) may be smaller than the light-emitting area of ​​the second display element (DE2).

[0102] The first display elements (DE1) can be arranged along a first direction (e.g., ±x direction) and a second direction (e.g., ±y direction). The second display elements (DE2) and the third display elements (DE3) can be arranged alternately along the first direction (e.g., ±x direction). The second display elements (DE2) and the third display elements (DE3) can be arranged alternately along the second direction (e.g., ±y direction).

[0103] Meanwhile, the area where the second display element (DE2) is placed within the component area (CA) may be referred to as the first area (AR1), and the remaining area excluding the first area (AR1) may be referred to as the second area (AR2). In the first area (AR1), the second pixel circuit (PC2) and the second display element (DE2) are placed overlapping each other, and in the second area (AR2), third display elements (DE3) with a small light-emitting area (or size) are placed; thus, the average transmittance per unit area of ​​the second area (AR2) may be greater than the average transmittance per unit area of ​​the first area (AR1).

[0104] In this way, by placing third display elements (DE3) with small light-emitting areas (or sizes) in the component area (CA), the transmittance of the component area (CA) can be secured while improving the difference in resolution between the image displayed in the component area (CA) and the image displayed in the main area (MA).

[0105] FIG. 6 is an exemplary cross-sectional view of the first to third pixels of FIG. 5, cut along II-II' and III-III', respectively.

[0106] Referring to FIG. 6, the display device (1a) may include a display panel (10a), a third display element (DE3), and a component (20). The component (20) may be positioned below the display panel (10a), and the third display element (DE3) may be positioned between the display panel (10a) and the component (20).

[0107] The display panel (10a) may include a first display element (DE1) and a first pixel circuit (PC1) disposed in a main area (MA), and a second display element (DE2) and a second pixel circuit (PC2) disposed in a component area (CA). The display panel (10a) may include a first through-electrode (TE1), a second through-electrode (TE2), a first pad electrode (PE1), and a second pad electrode (PE2) disposed in a component area (CA).

[0108] A first pixel circuit (PC1) and a second pixel circuit (PC2) may be placed on a first surface (100a) of a substrate (100). A first display element (DE1) may be placed on the first pixel circuit (PC1) and connected to the first pixel circuit (PC1). A second display element (DE2) may be placed on the second pixel circuit (PC2) and connected to the second pixel circuit (PC2). A third display element (DE3) may be placed on a second surface (100b) of the substrate (100) and connected to the second pixel circuit (PC2).

[0109] For example, as shown in FIG. 6, the second display element (DE2) and the third display element (DE3) can be connected to a connection line (CL) connected to the second pixel circuit (PC2). The second pixel circuit (PC2) can drive the second display element (DE2) and the third display element (DE3) simultaneously.

[0110] The first pixel circuit (PC1) and the second pixel circuit (PC2) may include at least one transistor and a storage capacitor as illustrated in FIG. 3 above. For example, the first pixel circuit (PC1) may include a first driving transistor that controls the current flowing to the first display element (DE1), and the second pixel circuit (PC2) may include a second driving transistor that controls the current flowing to the second display element (DE2) and the third display element (DE3). The at least one transistor may be formed as a thin-film transistor.

[0111] The first pixel circuit (PC1) and the first display element (DE1) overlap at least partially with each other, and the second pixel circuit (PC2) and the second display element (DE2) may overlap at least partially with each other. The second pixel circuit (PC2) and the third display element (DE3) may not overlap with each other.

[0112] The light-emitting layers of each of the first display element (DE1), the second display element (DE2), and the third display element (DE3) may each contain different materials. For example, the light-emitting layers of the first display element (DE1) and the second display element (DE2) may each contain an organic material, and the light-emitting layer of the third display element (DE3) may contain an inorganic material.

[0113] The first through electrode (TE1) can be connected to the second pixel circuit (PC2) by penetrating the substrate (100). The first through electrode (TE1) can be connected to the second pixel circuit (PC2) through a connection line (CL) extended in a second direction (e.g., ±y direction). The second through electrode (TE2) can be connected to the opposing electrode (230) by penetrating the substrate (100).

[0114] A first pad electrode (PE1) and a second pad electrode (PE2) may be disposed on the second surface (100b) of the substrate (100). The first pad electrode (PE1) may be connected to a first through electrode (TE1), and the second pad electrode (PE2) may be connected to a second through electrode (TE2). The first pad electrode (PE1) may be connected to a second pixel circuit (PC2) through the first through electrode (TE1), and the second pad electrode (PE2) may be connected to a counter electrode (230) through the second through electrode (TE2).

[0115] The first through electrode (TE1) and the first pad electrode (PE1) may be integral. At least a portion of the first pad electrode (PE1) may be embedded in a hole formed in the substrate (100), and at least a portion of the first pad electrode (PE1) embedded in the hole may be referred to as the first through electrode (TE1). Although the description was made based on the first through electrode (TE1) and the first pad electrode (PE1), the same can be applied to the second through electrode (TE2) and the second pad electrode (PE2).

[0116] The third indicator element (DE3) may include a first conductive pad electrode (240), an intermediate layer (250), and a second conductive pad electrode (260). The first conductive pad electrode (240) may be connected to the first pad electrode (PE1), and the second conductive pad electrode (260) may be connected to the second pad electrode (PE2). Both ends of the intermediate layer (250) may be connected to the first conductive pad electrode (240) and the second conductive pad electrode (260), respectively.

[0117] The intermediate layer (250) may include a first semiconductor layer (251), a second semiconductor layer (253), and a light-emitting layer (252) between the first semiconductor layer (251) and the second semiconductor layer (253).

[0118] The first semiconductor layer (251) can be implemented, for example, as a p-type semiconductor layer. The p-type semiconductor layer can be selected from semiconductor materials having the composition formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and p-type dopants such as Mg, Zn, Ca, Sr, and Ba can be doped. The first semiconductor layer (251) can be connected to the second pixel circuit (PC2) through the first conductive pad electrode (240).

[0119] The second semiconductor layer (253) may be formed, for example, by including an n-type semiconductor layer. The n-type semiconductor layer may be selected from semiconductor materials having the compositional formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with n-type dopants such as Si, Ge, Sn, etc. The second semiconductor layer (253) may be connected to the opposing electrode (230) through the second conductive pad electrode (260). The present invention is not limited thereto, and as another embodiment, the first semiconductor layer (251) may include an n-type semiconductor layer and the second semiconductor layer (253) may include a p-type semiconductor layer.

[0120] The light-emitting layer (252) is a region where electrons and holes recombine, and as electrons and holes recombine, they transition to a lower energy level and can emit light (e.g., blue light) having a corresponding wavelength. The light-emitting layer (252) can be formed by including a semiconductor material having, for example, the composition formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and can be formed as a single quantum well structure or a multi-quantum well (MQW) structure. Additionally, it may include a quantum wire structure or a quantum dot structure.

[0121] In one embodiment, the first conductive pad electrode (240) and the second conductive pad electrode (260) may be arranged side by side along the second direction (±y direction). The first pad electrode (PE1) and the second pad electrode (PE2), which are respectively connected to the first conductive pad electrode (240) and the second conductive pad electrode (260), may also be arranged side by side along the second direction (±y direction). The first pad electrode (PE1) and the second pad electrode (PE2) may be arranged on the same layer. In other words, the third display element (DE3) may be a horizontal or flip-type light-emitting diode.

[0122] In FIG. 6, the first conductive pad electrode (240) and the second conductive pad electrode (260) are shown arranged side by side along the second direction (±y direction), but in another embodiment, the first conductive pad electrode (240) and the second conductive pad electrode (260) may be located on opposite sides of the intermediate layer (250). This will be described later in FIG. 7.

[0123] Hereinafter, with reference to FIG. 6, the configuration included in the display panel (10a) will be described in more detail according to the stacked structure.

[0124] The substrate (100) may include glass or a polymer resin. The polymer resin may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate (100) containing the polymer resin may have flexible, rollable, or bendable properties. The substrate (100) may have a multilayer structure including a layer containing the aforementioned polymer resin and an inorganic layer (not shown).

[0125] The buffer layer (111) can reduce or block the penetration of foreign matter, moisture, or outside air from the bottom of the substrate (100) and can provide a flat surface on the substrate (100). The buffer layer (111) may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0126] A barrier layer (not shown) may be further included between the substrate (100) and the buffer layer (111). The barrier layer may serve to prevent or minimize the penetration of impurities from the substrate (100), etc., into the active layer (Act). The barrier layer may include inorganic materials such as oxides or nitrides, organic materials, or organic-inorganic composites, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0127] An active layer (Act) may be disposed on the buffer layer (111). The active layer (Act) may include amorphous silicon or polysilicon. In another embodiment, the active layer (Act) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0128] The active layer (Act) may include a channel region and source and drain regions disposed on both sides of the channel region. The active layer (Act) may be composed of a single layer or multiple layers.

[0129] A first gate insulating layer (113) and a second gate insulating layer (115) may be laminated and disposed on a substrate (100) to cover an active layer (Act). The first gate insulating layer (113) and the second gate insulating layer (115) may be silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO), etc.

[0130] A gate electrode (G) may be disposed on the first gate insulating layer (113) so as to overlap at least partially with the active layer (Act). The gate electrode (G) may be composed of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be a single layer or a multilayer. As an example, the gate electrode (G) may be a single layer of Mo.

[0131] In FIG. 6, the gate electrode (G) is shown placed on the upper surface of the first gate insulating layer (113), but in another embodiment, the gate electrode (G) may be placed on the upper surface of the second gate insulating layer (115).

[0132] In one embodiment, the storage capacitor (Cst) is provided with a first electrode (CE1) and a second electrode (CE2) and can be superimposed on a thin-film transistor (TFT) as shown in FIG. 6. For example, the gate electrode (G) of the thin-film transistor (TFT) can function as the first electrode (CE1) of the storage capacitor (Cst). Alternatively, the storage capacitor (Cst) may not be superimposed on the thin-film transistor (TFT) and may exist separately.

[0133] The second electrode (CE2) of the storage capacitor (Cst) overlaps with the first electrode (CE1) with the second gate insulating layer (115) in between, forming a capacitance. In this case, the second gate insulating layer (115) can function as a dielectric layer of the storage capacitor (Cst).

[0134] A second electrode (CE2) of a storage capacitor (Cst) may be disposed on the second gate insulating layer (115). The second electrode (CE2) of the storage capacitor (Cst) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials.

[0135] An interlayer insulating layer (117) may be provided on the second gate insulating layer (115) to cover the second electrode (CE2) of the storage capacitor (Cst). The interlayer insulating layer (117) may be silicon oxide (SiO2) or silicon nitride (SiN x It may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO), etc.

[0136] A source electrode and / or drain electrode and a connection line (CL) may be disposed on the upper part of the interlayer insulating layer (117).

[0137] The source electrode, drain electrode, and connecting line (CL) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. As an example, the source electrode, drain electrode, and connecting line (CL) may be formed as a multilayer structure of Ti / Al / Ti. The source electrode, drain electrode, and connecting line (CL) may be connected to an active layer (Act) through a contact hole.

[0138] The source electrode, drain electrode, and connection line (CL) may be covered by an inorganic protective layer (not shown). The inorganic protective layer is silicon nitride (SiN x ) and silicon oxide (SiO x It may be a single film or a multilayer film. The inorganic protective layer may be introduced to cover and protect some wiring placed on the interlayer insulating layer (117).

[0139] In FIG. 6, the connection line (CL) is shown placed on the interlayer insulating layer (117), but in another embodiment, the connection line (CL) may be placed on the buffer layer (111) and formed of the same material as the active layer (Act). In yet another embodiment, the connection line (CL) may be placed on the first gate insulating layer (113) and formed of the same material as the gate electrode (G), or placed on the second gate insulating layer (115) and formed of the same material as the second electrode (CE2) of the storage capacitor (Cst).

[0140] In one embodiment, the connecting line (CL) may be provided with a transparent conductive material. For example, the connecting line (CL) may be provided with a transparent conducting oxide (TCO). The connecting line (CL) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO).

[0141] A flattening layer (119) is disposed to cover a source electrode, a drain electrode, and a connection line (CL), and the flattening layer (119) includes contact holes for connecting a first pixel circuit (PC1) and a first pixel electrode (210a), and a second pixel circuit (PC2) and a second pixel electrode (210b), respectively.

[0142] The flattening layer (119) may be formed as a single layer or a multilayer film made of organic material and provides a flat upper surface. Such flattening layer (119) may include general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, or blends thereof.

[0143] A first display element (DE1) and a second display element (DE2) may be disposed on the flattening layer (119). The first display element (DE1) may include a first pixel electrode (210a), a first intermediate layer (220a) including an organic light-emitting layer, and a counter electrode (230), and the second display element (DE2) may include a second pixel electrode (210b), a second intermediate layer (220b) including an organic light-emitting layer, and a counter electrode (230). The first display element (DE1) and the second display element (DE2) may each be connected to a first pixel circuit (PC1) and a second pixel circuit (PC2) through contact holes formed in the flattening layer (119).

[0144] The first pixel electrode (210a) may be a (semi)transparent electrode or a reflective electrode. In some embodiments, the first pixel electrode (210a) may have a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof, and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may have at least one selected from the group comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the first pixel electrode (210a) may be provided as ITO / Ag / ITO. Although the first pixel electrode (210a) was described as the basis, the second pixel electrode (210b) can be applied in the same way.

[0145] In the display area (DA, FIG. 4) of the substrate (100), a pixel defining film (121) may be disposed on the planarization layer (119). The pixel defining film (121) may cover the edge of the first pixel electrode (210a) and may have an opening that exposes the central part of the first pixel electrode (210a). The pixel defining film (121) may cover the edge of the second pixel electrode (210b) and may have an opening that exposes the central part of the second pixel electrode (210b).

[0146] The pixel defining film (121) can serve to prevent arcs from occurring at the edge of the first pixel electrode (210a) by increasing the distance between the edge of the first pixel electrode (210a) and the opposing electrode (230) above the first pixel electrode (210a). Although the description was made based on the first pixel electrode (210a), the same can be applied to the second pixel electrode (210b).

[0147] The pixel definition film (121) can be formed by a method such as spin coating, using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene and phenolic resin.

[0148] In one embodiment, as shown in FIG. 6, a portion of the insulating layers disposed on the first surface (100a) of the substrate (100) may be removed so that a portion of the substrate (100) corresponding to the component region (CA) is exposed. As a portion of the insulating layers corresponding to the component region (CA) is removed, the transmittance of the component region (CA) may be improved.

[0149] In FIG. 6, it is shown that a portion of the insulating layers corresponding to the component region (CA) is removed, but in another embodiment, a portion of at least one of the insulating layers may be removed. In yet another embodiment, as shown in FIG. 10 which will be described later, a portion of the insulating layers may not be removed.

[0150] The first intermediate layer (220a) is disposed within an opening formed by the pixel defining film (121) and may include an organic light-emitting layer. The organic light-emitting layer may include an organic material comprising a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic light-emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) may be optionally disposed below and above the organic light-emitting layer. Although the description is based on the first intermediate layer (220a), the same can be applied to the second intermediate layer (220b).

[0151] The counter electrode (230) may be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode (230) may be a transparent or translucent electrode and may be formed from a metal thin film with a low work function comprising Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. Additionally, a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, or In2O3 may be further disposed on the metal thin film. The counter electrode (230) is disposed across the display area (DA) and may be disposed on top of the first intermediate layer (220a) and the second intermediate layer (220b) and the pixel defining film (121). The counter electrode (230) may be formed integrally with a plurality of display elements and may correspond to a plurality of pixel electrodes.

[0152] Since the first display element (DE1) and the second display element (DE2), which include an organic light-emitting layer, can be easily damaged by moisture or oxygen from the outside, an encapsulation layer (not shown) may cover and protect the first display element (DE1) and the second display element (DE2). The encapsulation layer covers the display area (DA) and may extend to at least a portion of the surrounding area (PA, FIG. 4). This encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0153] FIG. 7 is an exemplary cross-sectional view of the second and third pixels of FIG. 5 taken along III-III'. FIG. 7 is a modified embodiment of FIG. 6, differing in the structure of the third display element. Hereinafter, overlapping content will be replaced by the description of FIG. 6, and the differences will be explained primarily.

[0154] Referring to FIG. 7, unlike FIG. 6 described above, the second through electrode (TE2) and the second pad electrode (PE2) may be omitted. Instead, a third pad electrode (PE3) may be placed on the component (20). The third pad electrode (PE3) may be connected to the opposing electrode (230). For example, the third pad electrode (PE3) may be connected to the opposing electrode (230) through the through electrode. Alternatively, the third pad electrode (PE3) may be connected to an outer wiring or outer circuit placed in the peripheral area (PA, FIG. 4) of the display device (1a, FIG. 4) and connected to the opposing electrode (230).

[0155] The third indicator element (DE3) may include a first conductive pad electrode (240), an intermediate layer (250), and a second conductive pad electrode (260) as described above in FIG. 6. The first conductive pad electrode (240) may be connected to the first pad electrode (PE1), and the second conductive pad electrode (260) may be connected to the second pad electrode (PE2). The intermediate layer (250) may be disposed between the first conductive pad electrode (240) and the second conductive pad electrode (260). The first conductive pad electrode (240) and the second conductive pad electrode (260) may be located on opposite sides of each other with respect to the intermediate layer (250).

[0156] The intermediate layer (250) may include a first semiconductor layer (251), a second semiconductor layer (253), and a light-emitting layer (252) between the first semiconductor layer (251) and the second semiconductor layer (253). The first semiconductor layer (251) may be connected to a second pixel circuit (PC2) through a first conductive pad electrode (240) and a first pad electrode (PE1), and the second semiconductor layer (253) may be connected to a counter electrode (230) through a second conductive pad electrode (260) and a third pad electrode (PE3).

[0157] FIG. 8 is an enlarged plan view schematically illustrating a part of FIG. 4.

[0158] Referring to FIG. 8, three second pixels (PX2) may be placed in the first region (AR1) of the component region (CA). Three second pixel circuits (PC2) and three second display elements (DE2) may be placed in the first region (AR1) of the component region (CA). Three third display elements (DE3) connected to each of the three second pixel circuits (PC2) may be placed in the second region (AR2) of the component region (CA).

[0159] Three second pixels (PX2) placed in the first region (AR1) can each emit red, green, and blue light and can be arranged in a stripe structure. Three third pixels (PX3) placed in the second region (AR2) can each emit red, green, and blue light and can be arranged in a stripe structure.

[0160] Although FIG. 8 illustrates three second pixels (PX2) arranged in the first region (AR1), in other embodiments, the number of second pixels (PX2) arranged in the first region (AR1) may vary. Although the description was made based on the second pixels (PX2), the same can be applied to the third pixel (PX3).

[0161] Additionally, although FIG. 8 illustrates that the second pixels (PX2) and the third pixels (PX3) are arranged in a stripe structure, in other embodiments, the second pixels (PX2) and / or the third pixels (PX3) may be arranged in various shapes such as a Pentile Matrix structure (or Pentile structure), a mosaic array structure, a delta array structure, etc.

[0162] Meanwhile, the first pixels (PX1) placed in the main area (MA) can also be arranged in various shapes, such as a stripe structure, a pentile matrix structure (or pentile structure), a mosaic array structure, or a delta array structure.

[0163] FIG. 9 is an enlarged plan view schematically illustrating a portion of FIG. 4, and FIG. 10 is an exemplary cross-sectional view of the first to third pixels of FIG. 9, taken along IV-IV' and V-V', respectively. FIG. 9 and FIG. 10 are modified embodiments of FIG. 5 and FIG. 6, respectively, and differ in the structure of the second pixel circuit. Hereinafter, overlapping content will be replaced by the description of FIG. 5 and FIG. 6, and the explanation will focus on the differences.

[0164] Referring to FIG. 9, unlike FIG. 5 described above, the second pixel circuit (PC2) may be placed in the main area (MA). For example, the second pixel circuit (PC2) may be placed in the main area (MA) adjacent to the boundary between the main area (MA) and the component area (CA). The second pixel circuit (PC2) and the second display element (DE2) may not overlap each other, and the second pixel circuit (PC2) and the third display element (DE3) may not overlap each other.

[0165] In one embodiment, the first pixel circuit (PC1) and the first display element (DE1) may overlap at least partially or not overlap each other depending on their position in the main area (MA). For example, as shown in FIG. 9, the first pixel circuit (PC1) adjacent to the second pixel circuit (PC2) may not overlap with the first display element (DE1) connected to the first pixel circuit (PC1), and the first display element (DE1) may overlap at least partially with the second pixel circuit (PC2). Although not shown in FIG. 9, the first pixel circuit (PC1) not adjacent to the second pixel circuit (PC2) may overlap at least partially with the first display element (DE1).

[0166] Although not shown in FIG. 9, the area overlapping between the first pixel circuit (PC1) and the first display element (DE1) may vary depending on the distance between the first pixel circuit (PC1) and the second pixel circuit (PC2). When the distance between the first pixel circuit (PC1) and the second pixel circuit (PC2) is relatively large, the area overlapping between the first pixel circuit (PC1) and the first display element (DE1) may also be relatively large. In other words, as the position of the first pixel circuit (PC1) moves further away from the component area (CA), the area overlapping between the first pixel circuit (PC1) and the first display element (DE1) may increase.

[0167] Meanwhile, referring to FIG. 10, the second display element (DE2) and the third display element (DE3) can be connected to the second pixel circuit (PC2) through a connection line (CL) extended in the first direction (±x direction).

[0168] In FIG. 10, the second display element (DE2) and the third display element (DE3) are shown as being connected to the second pixel circuit (PC2) through a single connection line (CL), but in another embodiment, the second display element (DE2) and the third display element (DE3) may each be connected to the second pixel circuit (PC2) through separate connection lines.

[0169] FIG. 11 is an enlarged plan view schematically illustrating a portion of FIG. 4, and FIG. 12 is an exemplary cross-sectional view of the second and third pixels of FIG. 11 taken along VI-VI'. FIG. 11 and FIG. 12 are modified embodiments of FIG. 5 and FIG. 6, respectively, and differ in the structure of the third pixel circuit. In the following, overlapping content will be replaced by the description of FIG. 5 and FIG. 6, and the differences will be explained primarily.

[0170] Referring to FIG. 11, unlike FIG. 5 described above, the third pixel (PX3') may include a third pixel circuit (PC3) and a third display element (DE3). Since the third display element (DE3) can be driven by the third pixel circuit (PC3), it can be driven independently of the second display element (DE2).

[0171] In FIG. 11, the third display element (DE3) is shown as being connected to a third pixel circuit (PC3) that is placed in the same column as the third display element (DE3), but in another embodiment, the third display element (DE3) may be connected to a third pixel circuit (PC3) that is placed in the same row as the third display element (DE3).

[0172] Additionally, although FIG. 11 illustrates that the second pixel circuit (PC2) and the third pixel circuit (PC3) are placed in the component area (CA), in another embodiment, the second pixel circuit (PC2) and / or the third pixel circuit (PC3) may be placed in the main area (MA). This will be described later in FIG. 13 to 15.

[0173] The first pixel circuit (PC1) and the first display element (DE1) overlap at least partially with each other, and the second pixel circuit (PC2) and the second display element (DE2) may overlap at least partially with each other. The third pixel circuit (PC3) and the third display element (DE3) may not overlap with each other.

[0174] Meanwhile, referring to FIG. 12, the third pixel circuit (PC3) may be placed on the first surface (100a) of the substrate (100), and the third display element (DE3) may be placed on the second surface (100b) of the substrate (100). The third display element (DE3) may be connected to the third pixel circuit (PC3). For example, as shown in FIG. 12, the third display element (DE3) may be connected to the third pixel circuit (PC3) through a first pad electrode (PE1), a first through electrode (TE1), and a connection line (CL).

[0175] The third pixel circuit (PC3) may include at least one transistor and a storage capacitor as illustrated in FIG. 3 above. For example, the third pixel circuit (PC3) may include a third driving transistor that controls the current flowing to the third display element (DE3). The at least one transistor may be formed as a thin-film transistor.

[0176] In one embodiment, the ratio of the width to the channel length of the third driving transistor of the third pixel circuit (PC3) may be smaller than the ratio of the width to the channel length of the second driving transistor of the second pixel circuit (PC2).

[0177] When the current flowing through an inorganic light-emitting diode and an organic light-emitting diode is controlled by the same driving transistor, the inorganic light-emitting diode can emit light of greater brightness than the organic light-emitting diode due to the kink effect.

[0178] According to one embodiment of the present invention, a third driving transistor controlling the current flowing to a third display element (DE3) which may be formed as an inorganic light-emitting diode and a second driving transistor controlling the current flowing to a second display element (DE2) which may be formed as an organic light-emitting diode may have different structures. The ratio of the width to the length of the channel of the third driving transistor may be smaller than the ratio of the width to the length of the channel of the second driving transistor. In this case, the brightness of the third display element (DE3), which is an inorganic light-emitting diode, and the brightness of the second display element (DE2), which is an organic light-emitting diode, may be substantially the same.

[0179] FIGS. 13 to 15 are enlarged plan views schematically illustrating a portion of FIG. 4. FIGS. 13 to 15 are modified embodiments of FIG. 11, differing in the structure of the second pixel circuit and the third pixel circuit. Hereinafter, overlapping content will be replaced by the description of FIG. 11, and the differences will be explained primarily.

[0180] First, referring to FIG. 13, unlike FIG. 11 described above, the second pixel circuit (PC2) and the third pixel circuit (PC3) may be placed in the main area (MA). The second pixel circuit (PC2) and the second display element (DE2) may not overlap each other, and the third pixel circuit (PC3) and the third display element (DE3) may not overlap each other.

[0181] In one embodiment, the first pixel circuit (PC1) and the first display element (DE1) may overlap at least partially with each other or not overlap at all depending on their position in the main area (MA). For example, as shown in FIG. 13, the first pixel circuit (PC1) adjacent to the second pixel circuit (PC2) and the third pixel circuit (PC3) may not overlap with the first display element (DE1) connected to the first pixel circuit (PC1). The first display element (DE1) may overlap at least partially with the second pixel circuit (PC2) and / or the third pixel circuit (PC3).

[0182] Although not illustrated in FIG. 13, the area overlapping between the first pixel circuit (PC1) and the first display element (DE1) may vary depending on the distance between the first pixel circuit (PC1) and the component area (CA). When the distance between the first pixel circuit (PC1) and the component area (CA) is relatively large, the area overlapping between the first pixel circuit (PC1) and the first display element (DE1) may also be relatively large. In other words, as the position of the first pixel circuit (PC1) moves further away from the component area (CA), the area overlapping between the first pixel circuit (PC1) and the first display element (DE1) may increase.

[0183] In one embodiment, as shown in FIG. 14, the second pixel circuit (PC2) may be placed in the main area (MA), and the third pixel circuit (PC3) may be placed in the component area (CA).

[0184] In FIG. 14, the third display element (DE3) is shown as being connected to a third pixel circuit (PC3) that is placed in the same column as the third display element (DE3), but in another embodiment, the third display element (DE3) may be connected to a third pixel circuit (PC3) that is placed in the same row as the third display element (DE3).

[0185] In another embodiment, as shown in FIG. 15, the second pixel circuit (PC2) may be placed in the component area (CA) and the third pixel circuit (PC3) may be placed in the main area (MA).

[0186] Although the present invention has primarily described display panels and display devices so far, it is not limited thereto. For example, a method for manufacturing such a display panel and a method for manufacturing a display device are also considered to fall within the scope of the present invention.

[0187] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0188] 1, 1', 1a, 1a', 1c, 1d: display device 10, 10', 10a, 10a', 10c, 10d: Display panel 20: Component 100: Substrate 100a: First surface of the substrate 100b: Second surface of the substrate 230: Counter electrode TE: Through-hole electrode TE1, TE2: First and second penetrating electrodes PE: Pad electrode PE1, PE2, PE3: 1st to 3rd pad electrodes PX: Pixel PX1, PX2, PX3: 1st to 3rd pixels PC: Pixel circuit PC1, PC2, PC3: 1st to 3rd pixel circuits DE: Display element DE1, DE2, DE3: First to third display elements

Claims

Claim 1 A display panel comprising: a substrate having a first surface and a second surface opposite to the first surface; a first pixel circuit disposed on the first surface of the substrate; a first through electrode disposed through the substrate and connected to the first pixel circuit; a first pad electrode disposed on the second surface of the substrate and connected to the first through electrode; a counter electrode disposed on the first surface of the substrate and disposed on the first pixel circuit; a second through electrode disposed through the substrate and connected to the counter electrode; a second pad electrode disposed on the second surface of the substrate and connected to the second through electrode; and a first display element disposed on the second surface of the substrate and connected to the first pad electrode and the second pad electrode. Claim 2 A display panel according to claim 1, further comprising a second display element disposed on the first surface of the substrate and connected to the first pixel circuit. Claim 3 A display panel according to claim 2, further comprising: a second pixel circuit disposed on the first surface of the substrate; and a third display element disposed on the first surface of the substrate and connected to the second pixel circuit, wherein the substrate has a component area and a main area surrounding at least a portion of the component area defined therein, the first pixel circuit disposed in the component area or the main area, the second display element, the first pad electrode, and the second pad electrode disposed in the component area, and the second pixel circuit and the third display element disposed in the main area. Claim 4 A display panel according to claim 3, wherein when the first pixel circuit is placed in the component area, the first pixel circuit and the second display element and the second pixel circuit and the third display element each overlap at least partially with each other, and when the first pixel circuit is placed in the main area, the first pixel circuit and the third display element overlap at least partially with each other. Claim 5 A display panel according to claim 1, further comprising: a second pixel circuit disposed on the first surface of the substrate; and a third display element disposed on the first surface of the substrate and connected to the second pixel circuit, wherein the first pixel circuit comprises: a first driving transistor that controls a current flowing to the first pad electrode; a first scan transistor that transmits a first data voltage to the first driving transistor in response to a first scan signal; and a first storage capacitor having a first electrode and a second electrode connected to the gate of the first driving transistor, and the second pixel circuit comprises: a second driving transistor that controls a current flowing to the third display element; a second scan transistor that transmits a second data voltage to the second driving transistor in response to a second scan signal; and a second storage capacitor having a third electrode and a fourth electrode connected to the gate of the second driving transistor. Claim 6 In claim 5, a display panel in which the ratio of the width to the channel length of the first driving transistor is smaller than the ratio of the width to the channel length of the second driving transistor. Claim 7 A display panel according to claim 1, further comprising a connection line extending in a first direction and connecting the first penetrating electrode to the first pixel circuit. Claim 8 A display device comprising: a substrate having a first surface and a second surface opposite to the first surface; a first pixel circuit disposed on the first surface of the substrate; a first through electrode that penetrates the substrate and is connected to the first pixel circuit; a first pad electrode disposed on the second surface of the substrate and connected to the first through electrode; and a first display element disposed on the second surface of the substrate and connected to the first pad electrode; wherein the light-emitting layer of the first display element comprises an inorganic material. Claim 9 In claim 8, the display device further comprises a counter electrode disposed on the first surface of the substrate, and the first display element is connected to the counter electrode. Claim 10 A display device according to claim 9, further comprising: a second through electrode that penetrates the substrate and is connected to the opposing electrode; and a second pad electrode disposed on the second surface of the substrate and connected to the second through electrode, wherein the first display element comprises a first conductive pad electrode connected to the first pad electrode and a second conductive pad electrode connected to the second pad electrode. Claim 11 A display device according to claim 8, further comprising a second display element disposed on the first surface of the substrate and connected to the first pixel circuit. Claim 12 In claim 11, the light-emitting layer of the second display element comprises an organic material in a display device. Claim 13 In claim 11, a display device in which the light-emitting area of ​​the first display element is smaller than the light-emitting area of ​​the second display element. Claim 14 A display device according to claim 11, wherein the first display element and the second display element are each composed of a plurality of such elements, and the plurality of first display elements and the plurality of second display elements are alternately arranged along a first direction. Claim 15 A display device according to claim 8, further comprising: a second pixel circuit disposed on the first surface of the substrate; and a second display element disposed on the first surface of the substrate and connected to the second pixel circuit, wherein the first pixel circuit comprises: a first driving transistor that controls a current flowing to the first display element; a first scan transistor that transmits a first data voltage to the first driving transistor in response to a first scan signal; and a first storage capacitor having a first electrode and a second electrode connected to the gate of the first driving transistor, and wherein the second pixel circuit comprises: a second driving transistor that controls a current flowing to the second display element; a second scan transistor that transmits a second data voltage to the second driving transistor in response to a second scan signal; and a second storage capacitor having a third electrode and a fourth electrode connected to the gate of the second driving transistor. Claim 16 In claim 15, a display device in which the ratio of the width to the length of the channel of the first driving transistor is smaller than the ratio of the width to the length of the channel of the second driving transistor. Claim 17 A display device according to claim 15, wherein the light-emitting layer of the first display element comprises an inorganic material, and the light-emitting layer of the second display element comprises an organic material. Claim 18 In claim 15, a display device in which the light-emitting area of ​​the first display element is smaller than the light-emitting area of ​​the second display element. Claim 19 In claim 8, a display device in which the first display element and the first pixel circuit are spaced apart from each other on a plane. Claim 20 In claim 8, the display device further comprises a component disposed on the second surface of the substrate, wherein the first display element is disposed between the substrate and the component.

Images