Method and apparatus for expanding the zvs region in an isolated dc-dc converter using overlap control of synchronous rectifier switches

Abstract

A ZVS region expansion device according to one embodiment can perform the following operations: acquiring circuit information of an isolated DC-DC converter including a primary circuit including an active clamp circuit, a secondary circuit including a center tap circuit, and a transformer disposed between the primary circuit and the secondary circuit; controlling a gate signal applied to each switch to include an overlap time interval in which the switches of two synchronous rectifiers included in the secondary circuit conduct simultaneously; inducing resonance between an inductance component and a capacitance component included in the primary circuit through a short-circuit current loop formed within the secondary circuit during the overlap time interval; and controlling the first switch to turn on when a ZVS condition is achieved as the voltage across the first switch included in the primary circuit decreases due to the induction of resonance.

Description

Technology Field

[0001] The present invention relates to a control technology for a power conversion device, and more specifically, to a control technology for a synchronous rectifier that improves the ZVS condition of a primary switch by inducing resonant energy in a primary circuit through overlap control of a secondary synchronous rectifier switch in an isolated DC-DC converter. Background Technology

[0002] A DC-DC converter is a device that converts one DC voltage into another, and it is essential in a wide range of electronic devices, from smartphone chargers to electric vehicles. In particular, isolated DC-DC converters utilizing transformers are used when electrical isolation between the input and output voltages is required; in such cases, a method of switching on and off at high speed is employed to efficiently transfer power.

[0003] Meanwhile, isolated DC-DC converters have a problem in that energy loss occurs and heat generation increases when voltage and current exist simultaneously across the switch during the switching process. To reduce this energy loss and heat generation, a technology called Zero Voltage Switching (ZVS) is used, which lowers the voltage across the switch to zero before turning it on. This allows for more efficient power conversion and extends the lifespan of the switch components.

[0004] One method for implementing ZVS is the active clamp circuit, and in the active clamp circuit structure, the voltage is naturally lowered to zero by utilizing the energy remaining inside the circuit while the switch is off. However, if there is insufficient remaining energy in the circuit design, ZVS is not properly performed, which can lead to problems such as heat generation and wasted power.

[0005] In addition, synchronous rectifier technology, which replaces diodes with controllable switches to reduce conduction losses, is widely used. However, since the switching timing of conventional synchronous rectifiers is synchronized with the driving signal of the primary side switch, the control method is fixed and no separate control freedom is provided. As a result, synchronous rectifiers have limitations in that while they contribute to reducing conduction losses, they do not provide substantial help in achieving primary side ZVS.

[0006] These limitations are particularly pronounced under high-voltage input conditions or in application environments requiring high-frequency switching. In power electronics applications where high efficiency and miniaturization are simultaneously required, there is an urgent need for control techniques that can expand the ZVS range while maintaining existing circuitry without the addition of separate hardware. Therefore, there is a growing need for a new approach that departs from the conventional method of simply controlling the driving timing of synchronous rectifiers using synchronized signals, and instead utilizes this as an independent control parameter to actively change resonance conditions. Prior art literature

[0007] Republic of Korea Registered Patent Publication No. 10-2260300 The problem to be solved

[0008] The problem that the present invention aims to solve is to improve the control technique so that the primary side switch of an isolated DC-DC converter can stably achieve ZVS under a wider operating range. In particular, the main challenge is to provide a method that can satisfy ZVS conditions by utilizing control signals within the converter without changing the existing circuit structure or adding separate sensors and hardware.

[0009] To this end, the present invention aims to provide a technique that can actively control resonant energy within the primary circuit by utilizing the switching timing of the secondary synchronous rectifier as a single control variable. The proposed method can be implemented with simple signal regulation alone and can operate effectively without precise timing control, thereby providing a technical basis that can be practically applied in various application environments.

[0010] Meanwhile, the technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0011] A method performed by a ZVS region expansion device operated by a processor according to one embodiment may include: an operation of acquiring circuit information of an isolated DC-DC converter comprising a primary side circuit including an active clamp circuit, a secondary side circuit including a center tap circuit, and a transformer disposed between the primary side circuit and the secondary side circuit; an operation of controlling a gate signal applied to each switch to include an overlap time interval in which the switches of two synchronous rectifiers included in the secondary side circuit conduct simultaneously; an operation of inducing resonance between an inductance component and a capacitance component included in the primary side circuit through a short-circuit current loop formed within the secondary side circuit during the overlap time interval; and an operation of controlling the first switch to turn on when a ZVS condition is achieved as the voltage across the first switch included in the primary side circuit decreases due to the induction of resonance.

[0012] Additionally, the primary side circuit may include a first switch that switches current from an input power source; a clamp capacitor that stores leakage inductance energy generated when the first switch is turned off; and a clamp switch that resupplies the energy stored in the clamp capacitor to the circuit, wherein the clamp switch is configured to conduct when the first switch is turned off to form a self-reset path of the transformer through the clamp capacitor, and the voltage reset of the transformer is performed by the clamp circuit during the on-off period of the first switch, and may be characterized as an active clamp circuit of an Active Clamp Forward-Flyback structure.

[0013] Additionally, the secondary circuit may be characterized as an Active Clamp Forward-Flyback type output circuit configured such that the output voltage is maintained even after the first switch is turned off, wherein the secondary circuit includes a center tap terminal branched from the center of the secondary winding of a transformer that performs voltage conversion between the primary circuit and the secondary circuit; and two rectifier switches each connected to both ends of the center tap terminal, wherein one of the two rectifier switches maintains a conductive state even after the first switch is turned off, and energy transmitted through the transformer via the clamp capacitor is rectified and charged to the output capacitor.

[0014] In addition, the two synchronous rectifier switches may be characterized by having their gate signals controlled to turn on simultaneously during the overlap time interval, thereby forming a short-circuit current loop within the secondary circuit.

[0015] In addition, the operation of controlling the gate signal may include controlling the turn-off time of one of the two synchronous rectifier switches to extend beyond the turn-on time of the other switch to form the overlap time interval, and increasing the resonance energy of the primary circuit through the short-circuit current loop formed during the overlap time interval.

[0016] In addition, the operation of controlling the gate signal may include controlling the turn-on time of one switch to be earlier than the turn-off time of another switch to form the overlap time interval, and increasing the resonance energy of the primary circuit through the short-circuit current loop formed during the overlap time interval.

[0017] In addition, the overlap time may be characterized as a time interval formed by maintaining the gate signal of one of the two synchronous rectifier switches of the secondary circuit for a predetermined time or applying the gate signal of the other switch early, based on the time when the first switch included in the primary circuit is turned off, and being limited to a time within the time when the body diode of the rectifier switch naturally conducts.

[0018] In addition, the above overlap time may be characterized as a parameter that can be set by the user.

[0019] In addition, the above overlap time can be pre-set as a parameter greater than 0ns and less than or equal to 100ns.

[0020] Additionally, the primary side circuit may include a first switch that switches current from an input power source; a clamp capacitor that stores leakage inductance energy generated when the first switch is turned off; and a clamp switch that resets a transformer by circulating the energy stored in the clamp capacitor to the primary side circuit, wherein the clamp switch conducts when the first switch is turned off, thereby providing a self-reset path of the transformer through the clamp capacitor, and thus may be characterized as an active clamp circuit of an Active Clamp Forward structure that reduces switching losses and supports ZVS operation of the first switch.

[0021] In addition, the secondary circuit may be characterized as an Active Clamp Forward type output circuit configured to provide stable output power by including: a center tap terminal branched from the center of the secondary winding of a transformer that performs voltage conversion between the primary circuit and the secondary circuit; two rectifier switches each connected to both ends of the center tap terminal; and an output filter inductor connected between the common contact of the two rectifier switches and the output voltage, wherein the two rectifier switches conduct alternately in synchronization with the ON period of the first switch, and the output filter inductor releases energy stored during the conduction period to the load.

[0022] In addition, the two synchronous rectifier switches may be characterized by having their gate signals controlled to turn on simultaneously during the overlap time interval, thereby forming a short-circuit current loop within the secondary circuit.

[0023] In addition, the operation of controlling the gate signal may include controlling the turn-off time of one of the two synchronous rectifier switches to extend beyond the turn-on time of the other switch to form the overlap time interval, and increasing the resonance energy of the primary circuit through the short-circuit current loop formed during the overlap time interval.

[0024] In addition, the operation of controlling the gate signal may include controlling the turn-on time of one switch to be earlier than the turn-off time of another switch to form the overlap time interval, and increasing the resonance energy of the primary circuit through the short-circuit current loop formed during the overlap time interval.

[0025] In addition, the overlap time may be characterized as a time interval formed by maintaining the gate signal of one of the two synchronous rectifier switches of the secondary circuit for a predetermined time or applying the gate signal of the other switch early, based on the time when the first switch included in the primary circuit is turned off, and being limited to a time within the time when the body diode of the rectifier switch naturally conducts.

[0026] In addition, the above overlap time may be characterized as a parameter that can be set by the user.

[0027] In addition, the above overlap time can be pre-set as a parameter greater than 0ns and less than or equal to 100ns.

[0028] In addition, the operation of inducing the resonance may be characterized by forming a short-circuit current loop within the secondary circuit during an overlap time interval in which the switches of the two synchronous rectifiers included in the secondary circuit conduct simultaneously, thereby actively discharging the output capacitance of the switches included in the primary circuit to induce the rapid achievement of the ZVS condition.

[0029] A ZVS region expansion device according to one embodiment includes a memory containing instructions; and a processor that performs a predetermined operation based on the instructions, wherein the operation of the processor includes: an operation of acquiring circuit information of an isolated DC-DC converter comprising a primary circuit including an active clamp circuit, a secondary circuit including a center tap circuit, and a transformer disposed between the primary circuit and the secondary circuit; an operation of controlling a gate signal applied to each switch to include an overlap time interval in which the switches of two synchronous rectifiers included in the secondary circuit conduct simultaneously; an operation of inducing resonance between an inductance component and a capacitance component included in the primary circuit through a short-circuit current loop formed within the secondary circuit during the overlap time interval; and an operation of controlling the first switch to turn on when a ZVS condition is achieved as the voltage across the first switch included in the primary circuit decreases due to the induction of resonance.

[0030] A computer program stored on a computer-readable recording medium according to one embodiment may include, when executed on at least one processor, an operation in which the processor obtains circuit information of an isolated DC-DC converter comprising a primary circuit including an active clamp circuit, a secondary circuit including a center tap circuit, and a transformer disposed between the primary circuit and the secondary circuit; an operation in which a gate signal applied to each switch is controlled to include an overlap time interval in which the switches of two synchronous rectifiers included in the secondary circuit conduct simultaneously; an operation in which resonance is induced between an inductance component and a capacitance component included in the primary circuit through a short-circuit current loop formed within the secondary circuit during the overlap time interval; and an operation in which the first switch is controlled to turn on when a ZVS condition is achieved as the voltage across the first switch included in the primary circuit decreases due to the induction of resonance. Effects of the invention

[0031] According to the present invention, according to the above-described embodiment, by actively utilizing the switching timing control of the secondary side synchronous rectifier of an isolated DC-DC converter, Zero Voltage Switching (ZVS) operation for the primary side switch of the isolated DC-DC converter can be stably achieved under a wider range of conditions. In particular, the present invention can reduce switching losses and improve overall conversion efficiency without changing existing circuit configurations or parameters by inducing additional resonant energy in the primary side circuit through an overlap signal.

[0032] These effects are equally exhibited in the Active Clamp Forward structure as well as in the Active Clamp Forward Flyback structure, which combines the reset characteristics and power transfer characteristics of the transformer. That is, since the overlap control method of the present invention is based on a common principle that induces resonance conditions on the primary side by utilizing the operation of the rectifier section, it can be applied to both structures and function effectively, and the achievement of ZVS has been clearly confirmed through actual simulation results.

[0033] Furthermore, since the control method of the present invention is implemented by adding simple timing adjustments to the gate driving signal of the secondary synchronous rectifier without separate sensors or additional hardware circuits, it enables excellent performance improvement without increasing system complexity. Because precise timing adjustment is not required, it can be applied solely through software updates, and since it can be easily extended to various converter topologies, it has very high commercialization potential and versatility.

[0034] Meanwhile, the effects of the present invention are not limited to those mentioned above, and other unmentioned technical effects will be clearly understood by a person skilled in the art from the description below. Brief explanation of the drawing

[0035] FIG. 1 is a configuration diagram of a ZVS area expansion device according to one embodiment. FIG. 2 is a flowchart showing the steps of an operation performed by a ZVS area expansion device according to one embodiment. FIG. 3 is a circuit example diagram of an isolated DC-DC converter with an Active Clamp Forward-Flyback structure according to one embodiment. FIG. 4 is a circuit example diagram of an isolated DC-DC converter with an Active Clamp Forward structure according to one embodiment. Figure 5 is a graph showing the waveform of a gate signal applied to two synchronous rectifier switches included in the secondary circuit according to a conventional control method. Figure 6 is a graph showing the operation waveform of each circuit element over time according to the synchronous rectifier gate signal control of Figure 5. FIG. 7 is a graph showing the gate control waveform of the overlap time interval for achieving ZVS conditions according to one embodiment of the present invention. Figure 8 is a graph showing the operation waveform of each circuit element over time according to the synchronous rectifier gate signal control of Figure 7. Figure 9 is a graph showing the simulation results when a conventional synchronous rectifier control method is applied to an isolated DC-DC converter with an Active Clamp Forward-Flyback structure according to one embodiment. FIG. 10 is a graph showing the simulation results when the ZVS region expansion method of the present invention is applied to an isolated DC-DC converter with an Active Clamp Forward-Flyback structure according to one embodiment. Figure 11 is a graph showing the simulation results when a conventional synchronous rectifier control method is applied to an isolated DC-DC converter with an Active Clamp Forward structure according to one embodiment. FIG. 12 is a graph showing the simulation results when the ZVS region expansion method of the present invention is applied to an isolated DC-DC converter with an Active Clamp Forward structure according to one embodiment. Specific details for implementing the invention

[0036] Detailed information regarding the purpose, technical configuration, and resulting effects of the present invention will be more clearly understood through the following detailed description based on the drawings attached to the specification of the present invention. An embodiment according to the present invention will be described in detail with reference to the attached drawings.

[0037] The embodiments disclosed herein should not be interpreted or used to limit the scope of the invention. It is obvious to those skilled in the art that the description including the embodiments herein has various applications. Accordingly, any embodiments described in the detailed description of the invention are illustrative for better explaining the invention and are not intended to limit the scope of the invention to the embodiments.

[0038] The functional blocks shown in the drawings and described below are merely examples of possible implementations. In other implementations, other functional blocks may be used without departing from the spirit and scope of the detailed description. Additionally, while one or more functional blocks of the present invention are shown as individual blocks, one or more of the functional blocks of the present invention may be a combination of various hardware and software configurations that perform the same function.

[0039] Furthermore, the expression that it includes certain components is an “open-ended” expression that merely refers to the existence of such components and should not be understood as excluding additional components.

[0040] Furthermore, when it is stated that one component is “connected” or “joined” to another component, it should be understood that while it may be directly connected or joined to that other component, there may also be other components present in between.

[0041] Hereinafter, various embodiments of the present invention are described with reference to the accompanying drawings. However, this is not intended to limit the present invention to specific embodiments and should be understood to include various modifications, equivalents, and / or alternatives of the embodiments of the present invention.

[0042] The present invention proposes a ZVS region expansion device (100) that improves the ZVS condition of a primary switch by inducing resonant energy in a primary circuit through overlap control of a secondary synchronous rectifier switch in an isolated DC-DC converter.

[0043] Hereinafter, we will examine the configuration of the ZVS area expansion device (100) of the present invention and the operation of each configuration.

[0044] FIG. 1 is a configuration diagram of a ZVS area expansion device (100) (hereinafter referred to as 'device (100)') according to one embodiment.

[0045] Referring to FIG. 1, a device (100) according to one embodiment may each include a memory (110), a processor (120), an input / output interface (130), and a communication interface (140).

[0046] The memory (110) can store data obtained from an external device or data generated by itself. The memory (110) can store instructions that can perform operations of the processor (120). For example, the memory (110) can store circuit information of an isolated DC-DC converter, which will be described later.

[0047] The processor (120) is a computational device that controls the overall operation. The processor (120) can execute instructions stored in memory (110). The operation of the device (100) according to the embodiment of the present document can be understood as an operation performed by the processor (120).

[0048] The input / output interface (130) may include a hardware interface or a software interface for inputting or outputting information.

[0049] The communication interface (140) enables the transmission and reception of information through a communication network. To this end, the communication interface (140) may include a wireless communication module or a wired communication module.

[0050] The device (100) can be implemented in various forms of devices capable of performing calculations through a processor (120) and transmitting and receiving information through a network. For example, it can be implemented in the form of a server, a computer device, a portable communication device, a smartphone, a portable multimedia device, a laptop, a tablet PC, etc., but is not limited to these examples.

[0051] FIG. 2 is a flowchart of an operation performed by a device (100) according to one embodiment. The operation of the device (100) according to the embodiment of FIG. 2 can be understood as an operation performed by a processor (120).

[0052] Each step disclosed in FIG. 2 is merely a preferred embodiment for achieving the purpose of the present invention, and some steps may be added or deleted as needed, and any one step may be included in another step. The order of each operation disclosed in FIG. 2 is arranged only for ease of understanding and is not limited to a chronological order, and the order may be changed and operated differently according to the designer's choice.

[0053] Referring to FIG. 2, in step S1010, the device (100) can obtain circuit information of an isolated DC-DC converter that is subject to control for implementing ZVS conditions.

[0054] Here, ZVS stands for Zero Voltage Switching. It is a switching method that reduces switching losses and electromagnetic noise by ensuring that the voltage across the switch converges to 0V at the time of switch turn-on, in order to prevent problems such as energy loss and heat generation caused by current flowing simultaneously when voltage exists across the switch terminals when the switching element is turned on.

[0055] For example, the device (100) can obtain circuit information for an isolated DC-DC converter with an active clamp forward-flyback structure or an isolated DC-DC converter with an active clamp forward structure.

[0056] This circuit information may include the configuration of the primary and secondary circuits of the isolated DC-DC converter, the transformer connection method, the arrangement of the synchronous rectifier, and identification information of the control target switch. The acquired circuit information is used as basic data for gate signal control and resonance induction operation to achieve ZVS conditions performed in subsequent steps.

[0057] For example, the circuit information obtained in step S1010 may include the information of the following Fig. 3 or Fig. 4.

[0058] FIG. 3 is a circuit example diagram of an isolated DC-DC converter with an Active Clamp Forward-Flyback structure according to one embodiment.

[0059] Referring to FIG. 3, the circuit information of the isolated DC-DC converter obtained in step S1010 may include information about a primary circuit including an active clamp circuit, a secondary circuit including a center tap circuit, and a transformer placed between the primary circuit and the secondary circuit.

[0060] For example, the primary side circuit may include a first switch S1 that switches current from input power supply Vin, a clamp capacitor C1 that stores leakage inductance energy generated when the first switch is turned off, and a clamp switch S2 that resupplies the energy stored in the clamp capacitor to the circuit.

[0061] At this time, the clamp switch S2 conducts when the first switch S1 is turned off, forming a self-reset path of the transformer T1 through the clamp capacitor C1, and this voltage reset of the transformer exhibits the characteristics of an Active Clamp Forward-Flyback structure performed by the clamp circuit during the on-off period of the first switch.

[0062] Additionally, the secondary circuit may include a center tap terminal branched from the center of the secondary winding of transformer T1, two rectifier switches S3 and S4 respectively connected to both ends of the center tap, a capacitor C3 connected in parallel with S3, and a capacitor C4 connected in parallel with S4. At this time, one of the two rectifier switches maintains a conductive state even after the turn-off point of the first switch S1, thereby allowing the energy transmitted through the transformer via the clamp capacitor to be rectified and charged to the output capacitor, and accordingly, an output structure of the Active Clamp Forward-Flyback type is formed in which the output voltage is maintained even after the turn-off of the first switch.

[0063] FIG. 4 is a circuit example diagram of an isolated DC-DC converter with an Active Clamp Forward structure according to one embodiment.

[0064] Referring to FIG. 4, the circuit information of the isolated DC-DC converter obtained in step S1010 may include information about a primary circuit including an active clamp circuit, a secondary circuit including a center tap circuit, and a transformer placed between the primary circuit and the secondary circuit.

[0065] For example, the primary side circuit may include a first switch S1 that switches current from input power supply Vin, a clamp capacitor C1 that stores leakage inductance energy generated when the first switch is turned off, and a clamp switch S2 that is used to reset the transformer by circulating the energy stored in the clamp capacitor C1 through the primary side winding of the transformer T1.

[0066] At this time, the clamp switch S2 conducts when the first switch S1 is turned off, and exhibits the characteristics of an Active Clamp Forward structure configured to enable additional energy transfer to the load side by providing a self-reset path of the transformer through the clamp capacitor C1.

[0067] Additionally, the secondary circuit may include a center tap terminal branched from the center of the secondary winding of transformer T1; two rectifier switches S3 and S4, each connected to both ends of the center tap; a capacitor C3 connected in parallel with S3; a capacitor C4 connected in parallel with S4; and an output filter inductor L0 connected between the common contact of these rectifier switches and the output terminal Vo.

[0068] At this time, rectifier switch S3 or S4 conducts in synchronization with the ON state of the first switch S1, and the output filter inductor L0 provides stable DC output power by storing the energy transferred through the transformer during this period and releasing it to the load.

[0069] Next, a conventional synchronous rectifier control method for the isolated DC-DC converter circuit of Fig. 3 is explained through Figs. 5 and 6.

[0070] Figure 5 is a graph showing the waveforms of gate signals Vgs3 and Vgs4 applied to two synchronous rectifier switches S3 and S4 included in the secondary circuit according to the conventional control method.

[0071] Referring to FIG. 5, the gate signal Vgs3 controls the conduction of switch S3, and Vgs4 controls the conduction of switch S4. As shown, S3 and S4 are controlled to conduct alternately, and there is no overlap time interval during which both switches conduct simultaneously. Since this conventional control method does not form a separate resonance interval to discharge the output capacitance (Coss) of the primary circuit, there is a limitation in achieving the ZVS condition as shown in FIG. 6.

[0072] Figure 6 is a graph showing the operation waveform of each circuit element over time according to the synchronous rectifier gate signal control of Figure 5.

[0073] The first waveform in Fig. 6 represents gate signals Vgs3 and Vgs4 applied to two synchronous rectifier switches, S3 and S4, and the two switches are controlled to conduct alternately so as not to overlap each other.

[0074] The second waveform in Fig. 6 shows the change pattern of the primary magnetization inductance current (iLm1) and the T2 magnetization inductance current (iLm2) of T1, and the current rises or falls depending on the respective switch control timing.

[0075] The third waveform in Fig. 6 represents the voltages across the primary switches (Vds1, Vds2), showing that Vds1 is not zero at the moment Vgs1 increases. This implies that the ZVS condition is not satisfied because resonance is not sufficiently induced.

[0076] The fourth waveform of Fig. 6 represents the current (iS3, iS4) flowing through the two synchronous rectifier switches (S3, S4), and as the two switches conduct alternately, the current is interrupted and then flows again in a repeated interval.

[0077] As such, Figure 6 shows a waveform illustrating the problem that the ZVS condition is not sufficiently achieved according to the existing control method, and in particular, the high Vds1 voltage at the S1 turn-on time causes switching losses and increased heat generation.

[0078] To solve the above problem, in step S1020, the device (100) can control the gate signal applied to each switch to include an overlap time interval in which the switches of two synchronous rectifiers included in the secondary circuit conduct simultaneously.

[0079] The overlap time interval refers to a time interval during which synchronous rectifier switches included in the secondary circuit conduct simultaneously (conduction: a state in which the switch turn-on state is maintained and electricity flows). The overlap time interval is intentionally generated through gate signal control of the device (100), and causes two synchronous rectifier switches to conduct overlappingly, thereby forming a short-circuit current loop within the secondary circuit. At this time, the short-circuit current loop induces resonance between the output capacitance present in the primary circuit and the leakage inductance of the transformer, causing the voltage across the switch terminals to approach 0V at the time of switch turn-on, and ultimately performs a key function of enabling the achievement of the ZVS condition. An example of the overlap interval is shown in the following Fig. 7.

[0080] FIG. 7 is a graph showing the gate control waveform of the overlap time interval for achieving ZVS conditions according to one embodiment of the present invention.

[0081] Referring to FIG. 7, gate signals Vgs3 and Vgs4 applied to the two synchronous rectifier switches S3 and S4, respectively, can be controlled so that a portion of the conduction interval overlaps. In this case, the interval where Vgs3 and Vgs4 overlap during tov corresponds to the overlap time interval.

[0082] To this end, the device (100) can form an overlap time interval by extending the turn-off time of one of the two synchronous rectifier switches beyond the turn-on time of the other switch, controlling the turn-on time of one switch earlier than the turn-off time of the other switch, or controlling both in parallel.

[0083] This overlap time interval forms a short-circuit current loop in the secondary circuit and induces an increase in resonant energy between the transformer's leakage inductance and the primary switch's output capacitance through the short-circuit current loop. As a result, the voltage across the switch naturally decreases before the primary switch is turned on, and the ZVS condition can be satisfied.

[0084] In step S1030, the device (100) can induce resonance between the inductance component and the capacitance component included in the primary circuit through a short-circuit current loop formed in the secondary circuit during the overlap time interval. The specific operation for S1030 is as shown in FIG. 8 below.

[0085] Figure 8 is a graph showing the operation waveform of each circuit element over time according to the synchronous rectifier gate signal control of Figure 7.

[0086] The first waveform of FIG. 8 represents gate signals Vgs3 and Vgs4 applied to two synchronous rectifier switches, S3 and S4. At this time, the device (100) can control the turn-off time of switch S4 to be extended beyond the turn-on time of switch S3, or control the turn-on time of switch S3 to be earlier than the turn-off time of switch S4, thereby forming an overlap time interval in which the two switches conduct simultaneously. In the first waveform, the time interval in which the two gate signals overlap corresponds to the overlap time interval (tov), ​​which means the period during which the two switches are in a conducting state simultaneously. In the present invention, by intentionally controlling and forming such an overlap time interval, the resonance energy of the primary side circuit is induced to increase through the short-circuit current loop formed during the overlap time interval.

[0087] As such, the overlap time interval tov is a time interval formed by maintaining the gate signal of S4, one of the two synchronous rectifier switches in the secondary circuit, for a predetermined time or by applying the gate signal of S3, the other one, early, based on the time when the first switch included in the primary circuit is turned off, and may be a parameter that can be set by the user to be limited to a time within the time when the body diode of the rectifier switch naturally conducts. Accordingly, the overlap time may be pre-set to be greater than 0ns and less than or equal to 100ns.

[0088] The second waveform in Fig. 8 represents the primary side magnetization inductance current iLm1 of T1 and the primary side magnetization inductance current iLm2 of T2. Additionally, the portion indicated by the dashed line visualizes the result of adding the leakage inductance current (ilk) component generated through the short-circuit formed during the overlap time interval. In other words, this dashed line indicates that, in addition to the energy stored in the magnetization inductance during switch conduction, a resonant current component flowing through the leakage inductance is included.

[0089] The third waveform in Fig. 8 represents the drain-source voltages Vds1 and Vds2 corresponding to the primary side switches S1 and S2. Due to resonance occurring during the overlap period, Vds1 decreases rapidly and drops to near 0V; at this point, the ZVS condition is satisfied when the switch is turned on. That is, the voltage across the terminals approaches 0V at the time of switching on, thereby minimizing switching losses.

[0090] The fourth waveform in Fig. 8 is the current waveform iS3 and iS4 of the synchronous rectifier switches S3 and S4. Since both switches are conducted simultaneously during the overlap time, the current through the short loop increases instantaneously, and as a result, a sudden change in current appears in the corresponding switch current waveform, which resembles a transient response. This indicates the flow of resonant current through the short loop.

[0091] That is, according to FIG. 8, the device (100) can induce the rapid achievement of ZVS conditions by forming a short-circuit current loop in the secondary circuit during an overlap time interval (tov) in which the switches of two synchronous rectifiers included in the secondary circuit conduct simultaneously, thereby actively discharging the output capacitance of the switches included in the primary circuit.

[0092] Next, in step S1040, the device (100) can control the first switch to turn on when the ZVS condition is achieved, as the voltage across the first switch included in the primary circuit is reduced by resonance induction as described in FIG. 8.

[0093] For example, the device (100) can perform a turn-on operation by monitoring the time change of the drain-source voltage Vds of the primary switch or determining whether ZVS is achieved based on the turn-on delay time setting of the first switch, and applying a gate signal to the first switch at the time when ZVS is satisfied.

[0094] Figure 9 is a graph showing the simulation results when a conventional synchronous rectifier control method is applied to an isolated DC-DC converter with an Active Clamp Forward-Flyback structure according to one embodiment. In Figure 9, an experiment was conducted by simulating an Active Clamp Forward-Flyback converter with Vin = 400 V, Vo = 12 V, switching frequency = 200 kHz, output = 1 kW, transformer leakage inductance = 2.5 uH, switch Coss = 120 pF, and transformer turns ratio n = 18.

[0095] The left side of Fig. 9 shows the entire waveform of an Active Clamp Forward-Flyback converter with a conventional synchronous rectifier control method, and the right side shows an enlarged portion of the waveform to allow for a more precise analysis of whether the first switch achieves ZVS.

[0096] Referring to Fig. 9, in the overall waveform on the left, Vgs1 and Vgs2 represent the gate signals of the primary side main switch S1 and clamp switch S2, respectively, and Vgs3 and Vgs4 represent the gate signals of the secondary side synchronous rectifier switches S3 and S4. Vds1 and Vds2 represent the drain-source voltage of the primary side switches, iLk represents the leakage inductance current, and iLm1 and iLm2 represent the magnetization inductance currents of T1 and T2, respectively.

[0097] Looking at the magnified waveform on the right, it can be seen that a dead-time occurs after S2 turns off, and during this dead-time, S1 turns on again without Vds1 dropping completely to 0V, resulting in a hard switching phenomenon where the ZVS condition is not satisfied. This can be visually confirmed in the area labeled "ZVS X".

[0098] This shows that in the existing synchronous rectifier control method, the control of the secondary rectifier switch is synchronized with the primary switch, so additional resonant energy cannot be induced on the secondary side, and consequently, there is a structural limitation in that it cannot provide enough energy to satisfy the ZVS condition.

[0099] Therefore, Figure 9 illustrates a situation where, when applying the conventional synchronous rectifier control method to an Active Clamp Forward-Flyback converter, the energy stored in the leakage inductance alone is insufficient to cause sufficient Coss discharge, and thus ZVS is not achieved.

[0100] FIG. 10 is a graph showing the simulation results when the ZVS region extension method of the present invention is applied to an isolated DC-DC converter with an Active Clamp Forward-Flyback structure according to one embodiment. In FIG. 10, an experiment was conducted by simulating an Active Clamp Forward-Flyback converter with Vin = 400 V, Vo = 12 V, switching frequency = 200 kHz, output = 1 kW, transformer leakage inductance = 2.5 uH, switch Coss = 120 pF, and transformer turns ratio n = 18.

[0101] The left side of FIG. 10 shows the entire waveform of an Active Clamp Forward-Flyback converter to which the control method of the present invention is applied, and the right side shows a magnified portion of the waveform to allow for precise verification of whether ZVS is achieved.

[0102] Referring to FIG. 10, the present invention controls the gate signals Vgs3 and Vgs4 of secondary synchronous rectifier switches S3 and S4 to form an overlap time interval (e.g., 10ns, 30ns, 50ns) designed to intentionally overlap the conduction times of each other.

[0103] This overlap control induces a short-circuit current loop in the secondary circuit through the period in which both switches are turned on simultaneously, and increases the primary leakage inductance current (iLk) through the loop, thereby effectively inducing a resonant discharge for the drain-source voltage Vds1 of the primary switch S1.

[0104] In addition, looking at the enlarged waveform on the right, it can be seen that the ZVS condition is achieved, in which Vds1 decreases rapidly even after the clamp switch S2 is turned off and reaches 0V just before the first switch S1 is turned on. Whether the actual ZVS is achieved can be visually confirmed in the area marked "ZVS O" at the bottom right of Fig. 10.

[0105] As such, FIG. 10 shows that, unlike conventional methods, switching losses can be reduced and hard switching problems of the first switch can be prevented by increasing the resonance energy through the overlap section.

[0106] FIG. 11 is a graph showing the simulation results when a conventional synchronous rectifier control method is applied to an isolated DC-DC converter with an Active Clamp Forward structure according to one embodiment. In FIG. 11, an experiment was conducted by simulating an Active Clamp Forward converter with Vin = 400 V, Vo = 48 V, switching frequency = 200 kHz, output = 1 kW, transformer leakage inductance = 2.5 uH, switch Coss = 120 pF, and transformer turns ratio n=8.

[0107] The left side of FIG. 11 shows the overall operation waveform of an Active Clamp Forward converter with a conventional synchronous rectifier control method, and the right side shows an enlarged waveform centered on the turn-on time of the first switch (S1).

[0108] Referring to FIG. 11, Vgs1 and Vgs2 are gate signals of the primary side switches, Vgs3 and Vgs4 are gate signals of the secondary side synchronous rectifier switches, and Vds1 represents the drain-source voltage of the first switch. Additionally, iLk represents the transformer leakage inductance current, and iLm1 and iLm2 represent the magnetization inductance currents of T1 and T2, respectively.

[0109] In the conventional method, the gate signals of the switches (S3, S4) of the synchronous regularizer are controlled without overlap, and as a result, as shown in the right waveform of FIG. 11, it is confirmed that Vds1 of the first switch (S1) is turned on at a high voltage without sufficient voltage attenuation through resonance.

[0110] This means that S1 is turned on under hard switching conditions, which causes problems such as increased switching losses and reduced power conversion efficiency. In fact, the Vds1 waveform does not reach 0V immediately before turning on, and this can be visually confirmed in the area labeled "ZVS X".

[0111] Therefore, Figure 11 illustrates a situation where, when applying the conventional synchronous rectifier control method to an Active Clamp Forward converter, the energy stored in the leakage inductance alone is insufficient to cause sufficient Coss discharge, and thus ZVS is not achieved.

[0112] FIG. 12 is a graph showing the simulation results when the ZVS region extension method of the present invention is applied to an isolated DC-DC converter with an Active Clamp Forward structure according to one embodiment. In FIG. 12, an experiment was conducted by simulating an Active Clamp Forward converter with Vin = 400 V, Vo = 48 V, switching frequency = 200 kHz, output = 1 kW, transformer leakage inductance = 2.5 uH, switch Coss = 120 pF, and transformer turns ratio n=8.

[0113] The left side of FIG. 12 shows the overall operation waveform of an Active Clamp Forward converter to which the synchronous rectifier overlap control method of the present invention is applied, and the right side shows an enlarged waveform centered on the turn-on time of the first switch (S1).

[0114] Referring to FIG. 12, the gate signals Vgs3 and Vgs4 of the secondary rectifier switches S3 and S4 are controlled to conduct simultaneously, including an overlap time interval (tov), ​​unlike the conventional method. That is, the turn-off time of one switch is delayed, or the turn-on time of the other switch is advanced, creating an overlap interval in which the two switches conduct simultaneously for a time. As a result, a short-circuit current loop is formed in the secondary circuit, and through this loop, the leakage inductance current (iLk) of the primary transformer induces resonance.

[0115] As a result of the resonance induction, as confirmed in the right waveform of FIG. 12, the drain-source voltage (Vds1) of the first switch (S1) decreases rapidly until just before turning on and converges to 0V. This satisfies the Zero Voltage Switching (ZVS) condition, and S1 can be turned on without switching loss. Whether ZVS is actually achieved can be visually confirmed in the area marked "ZVS O" at the bottom right of FIG. 12.

[0116] As such, FIG. 12 shows that, unlike the conventional method, switching losses can be reduced and hard switching problems of the first switch can be prevented by increasing the resonance energy through the overlap section.

[0117] According to the above-described embodiment, by actively utilizing the switching timing control of the secondary-side synchronous rectifier of the isolated DC-DC converter, ZVS operation for the primary-side switch of the isolated DC-DC converter can be stably achieved under a wider range of conditions. In particular, the present invention can reduce switching losses and improve overall conversion efficiency without changing existing circuit configurations or parameters by inducing additional resonant energy in the primary-side circuit through an overlap signal.

[0118] These effects are equally exhibited in the Active Clamp Forward structure as well as in the Active Clamp Forward Flyback structure, which combines the reset characteristics and power transfer characteristics of the transformer. That is, since the overlap control method of the present invention is based on a common principle that induces resonance conditions on the primary side by utilizing the operation of the rectifier section, it can be applied to both structures and function effectively, and the achievement of ZVS has been clearly confirmed through actual simulation results.

[0119] Furthermore, since the control method of the present invention is implemented by adding simple timing adjustments to the gate driving signal of the secondary synchronous rectifier without separate sensors or additional hardware circuits, it enables excellent performance improvement without increasing system complexity. Because precise timing adjustment is not required, it can be applied solely through software updates, and since it can be easily extended to various converter topologies, it has very high commercialization potential and versatility.

[0120] The various embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of said embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more items unless the relevant context clearly indicates otherwise.

[0121] In this document, each of the phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B or C,” “at least one of A, B and C,” and “at least one of A, B, or C” may include all possible combinations of items listed together in the corresponding phrase. Terms such as “first,” “second,” or “first” or “second” may be used simply to distinguish a component from another component and do not limit the components in any other aspect (e.g., importance or order). Where any (e.g., first) component is referred to as “coupled” or “connected” to another (e.g., second) component, with or without the terms “functionally” or “communicationly,” it means that the component may be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0122] As used in this document, the term "module" may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be a component formed integrally, or a minimum unit of a component or part thereof that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0123] Various embodiments of this document may be implemented as software (e.g., a program) comprising one or more instructions stored in a storage medium (e.g., memory) that can be read by a device (e.g., an electronic device). The storage medium may include random access memory (RAM), a memory buffer, a hard drive, a database, erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM), read-only memory (ROM), and / or the like.

[0124] Additionally, the processor of the embodiments of this document may call at least one instruction among one or more instructions stored from a storage medium and execute it. This enables the device to operate to perform at least one function according to at least one called instruction. Such one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The processor may be a general-purpose processor, a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), and / or the like.

[0125] A device-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and this term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily.

[0126] Methods according to the various embodiments disclosed in this document may be provided as part of a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or distributed online (e.g., download or upload) through an application store (e.g., Play Store) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a device-readable storage medium, such as a manufacturer's server, an application store's server, or the server's memory.

[0127] According to various embodiments, each component (e.g., module or program) of the described components may include a singular or multiple entities. According to various embodiments, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Generally or additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the components of the multiple components in the same or similar manner as they were performed by the corresponding component among the multiple components prior to integration. According to various embodiments, operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically; one or more of the operations may be executed in a different order; omitted; or one or more other operations may be added. Explanation of the symbols

[0128] 100: Device 110: Memory 120: Processor 130: Input / Output Interface 140: Communication interface

Claims

Claim 1 A method performed by a ZVS region expansion device operated by a processor, comprising: acquiring circuit information of an isolated DC-DC converter including a primary circuit including an active clamp circuit, a secondary circuit including a center tap circuit, and a transformer disposed between the primary circuit and the secondary circuit; controlling a gate signal applied to each switch to include an overlap time interval in which the switches of two synchronous rectifiers included in the secondary circuit conduct simultaneously; inducing resonance between an inductance component and a capacitance component included in the primary circuit through a short-circuit current loop formed within the secondary circuit during the overlap time interval; and controlling the first switch to turn on when a ZVS condition is achieved as the voltage across the first switch included in the primary circuit decreases due to the induction of resonance. Claim 2 The method according to claim 1, wherein the primary side circuit comprises: a first switch for switching current from an input power source; a clamp capacitor for storing leakage inductance energy generated when the first switch is turned off; and a clamp switch for resupplying energy stored in the clamp capacitor to the circuit, wherein the clamp switch is configured to conduct when the first switch is turned off to form a self-reset path of the transformer through the clamp capacitor, and the voltage reset of the transformer is performed by the clamp circuit during the on-off interval of the first switch, characterized in that it is an active clamp circuit of an Active Clamp Forward-Flyback structure. Claim 3 A method according to claim 2, wherein the secondary side circuit comprises: a center tap terminal branched from the center of the secondary winding of a transformer that performs voltage conversion between the primary side circuit and the secondary side circuit; and two rectifier switches each connected to both ends of the center tap terminal, wherein one of the two rectifier switches maintains a conductive state even after the first switch is turned off, and the energy transmitted through the transformer via the clamp capacitor is rectified and charged to the output capacitor, thereby maintaining the output voltage even after the first switch is turned off, characterized by being an Active Clamp Forward-Flyback type output circuit. Claim 4 A method according to claim 3, characterized in that the gate signals of the two synchronous rectifier switches are controlled to be simultaneously turned on during the overlap time interval, thereby forming a short-circuit current loop in the secondary circuit. Claim 5 A method according to claim 4, wherein the operation of controlling the gate signal comprises controlling the turn-off time of one of the two synchronous rectifier switches to extend beyond the turn-on time of the other switch to form the overlap time interval, and increasing the resonance energy of the primary circuit through a short-circuit current loop formed during the overlap time interval. Claim 6 A method according to claim 4, wherein the operation of controlling the gate signal comprises controlling the turn-on time of one switch to be earlier than the turn-off time of another switch to form the overlap time interval, and increasing the resonance energy of the primary circuit through a short-circuit current loop formed during the overlap time interval. Claim 7 A method according to claim 4, wherein the overlap time is a time interval formed by maintaining the gate signal of one of the two synchronous rectifier switches of the secondary circuit for a predetermined time or by applying the gate signal of the other switch early, based on the time when the first switch included in the primary circuit is turned off, and is set to be limited to a time within the time when the body diode of the rectifier switch naturally conducts. Claim 8 A method according to claim 7, characterized in that the overlap time is a parameter that can be set by the user. Claim 9 In claim 7, the method wherein the overlap time is pre-set as a parameter greater than 0ns and less than or equal to 100ns. Claim 10 The method according to claim 1, wherein the primary side circuit comprises: a first switch for switching current from an input power source; a clamp capacitor for storing leakage inductance energy generated when the first switch is turned off; and a clamp switch for resetting a transformer by circulating the energy stored in the clamp capacitor to the primary side circuit, wherein the clamp switch conducts when the first switch is turned off, thereby providing a self-reset path of the transformer through the clamp capacitor, and is characterized as an active clamp circuit of an Active Clamp Forward structure that reduces switching losses and supports ZVS operation of the first switch. Claim 11 In claim 10, the secondary side circuit comprises: a center-tap terminal branched from the center of the secondary winding of a transformer that performs voltage conversion between the primary side circuit and the secondary side circuit; two rectifier switches each connected to both ends of the center-tap terminal; and an output filter inductor connected between the common contact of the two rectifier switches and the output voltage, wherein the two rectifier switches conduct alternately in synchronization with the ON period of the first switch, and the output filter inductor is configured to provide stable output power by releasing energy stored during the conduction period to the load, characterized in that it is an Active Clamp Forward type output circuit. Claim 12 A method according to claim 11, characterized in that the gate signals of the two synchronous rectifier switches are controlled to be simultaneously turned on during the overlap time interval, thereby forming a short-circuit current loop within the secondary circuit. Claim 13 A method according to claim 12, wherein the operation of controlling the gate signal comprises controlling the turn-off time of one of the two synchronous rectifier switches to extend beyond the turn-on time of the other switch to form the overlap time interval, and increasing the resonance energy of the primary circuit through a short-circuit current loop formed during the overlap time interval. Claim 14 A method according to claim 12, wherein the operation of controlling the gate signal comprises controlling the turn-on time of one switch to be earlier than the turn-off time of another switch to form the overlap time interval, and increasing the resonance energy of the primary circuit through a short-circuit current loop formed during the overlap time interval. Claim 15 A method according to claim 12, wherein the overlap time is a time interval formed by maintaining the gate signal of one of the two synchronous rectifier switches of the secondary circuit for a predetermined time or by applying the gate signal of the other switch early, based on the time when the first switch included in the primary circuit is turned off, and is set to be limited to a time within the time when the body diode of the rectifier switch naturally conducts. Claim 16 A method according to claim 15, characterized in that the overlap time is a parameter that can be set by the user. Claim 17 In claim 15, the method wherein the overlap time is pre-set as a parameter greater than 0ns and less than or equal to 100ns. Claim 18 A method according to claim 1, wherein the operation inducing resonance performs the role of inducing the rapid achievement of the ZVS condition by forming a short-circuit current loop within the secondary circuit during an overlap time interval in which the switches of two synchronous rectifiers included in the secondary circuit conduct simultaneously, thereby actively discharging the output capacitance of the switches included in the primary circuit. Claim 19 A ZVS region expansion device comprising: a memory including instructions; and a processor performing a predetermined operation based on the instructions, wherein the operation of the processor includes: an operation of acquiring circuit information of an isolated DC-DC converter including a primary side circuit including an active clamp circuit, a secondary side circuit including a center tap circuit, and a transformer disposed between the primary side circuit and the secondary side circuit; an operation of controlling a gate signal applied to each switch to include an overlap time interval in which the switches of two synchronous rectifiers included in the secondary side circuit conduct simultaneously; an operation of inducing resonance between an inductance component and a capacitance component included in the primary side circuit through a short-circuit current loop formed within the secondary side circuit during the overlap time interval; and an operation of controlling the first switch to turn on when a ZVS condition is achieved as the voltage across the first switch included in the primary side circuit decreases due to the induction of resonance. Claim 20 A computer program stored on a computer-readable recording medium, comprising instructions that, when performed on at least one processor, the processor acquires circuit information of an isolated DC-DC converter including a primary circuit including an active clamp circuit, a secondary circuit including a center tap circuit, and a transformer disposed between the primary circuit and the secondary circuit; controls a gate signal applied to each switch to include an overlap time interval in which the switches of two synchronous rectifiers included in the secondary circuit conduct simultaneously; induces resonance between an inductance component and a capacitance component included in the primary circuit through a short-circuit current loop formed within the secondary circuit during the overlap time interval; and controls the first switch to turn on when a ZVS condition is achieved as the voltage across the first switch included in the primary circuit decreases due to the induction of resonance.

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