Display device

Abstract

The embodiments of the present specification relate to a display device, and more specifically, provide a display device having improved color viewing angle characteristics by providing a display device comprising a substrate, a transistor having a first source-drain electrode material pattern located on the substrate, an active layer and a gate electrode located overlapping with the active layer, a first planarization layer located on the first source-drain electrode material pattern of the transistor, a metal pattern located on the first planarization layer and electrically connected to the transistor, a second planarization layer covering the metal pattern, and a bank having two or more openings of different sizes located on the second planarization layer, wherein in the region below the two or more openings of different sizes, the metal pattern is spaced apart at equal intervals.

Description

Technology Field

[0001] The embodiments of this specification relate to display devices. Background Technology

[0002] As the information society develops, the demand for display devices that display images is increasing, and various types of display devices, such as liquid crystal displays and organic light-emitting diode displays, are being utilized.

[0003] Users of a display device may view the image displayed on the device from the front of the device, but they may also view the screen displaying the image from various angles.

[0004] Therefore, the display device is required to minimize the phenomenon of color coordinate distortion caused by the viewing angle so that the user can view the image from various angles. The problem to be solved

[0005] The embodiments of the present specification can provide a display device with improved luminance deviation (color viewing angle characteristics) according to the viewing angle. means of solving the problem

[0006] Embodiments of the present disclosure may provide a display device comprising a substrate, a transistor having a first source-drain electrode material pattern located on the substrate, an active layer, and a gate electrode located overlapping the active layer, a first planarization layer located on the first source-drain electrode material pattern of the transistor, a metal pattern located on the first planarization layer and electrically connected to the transistor, a second planarization layer covering the metal pattern, and a bank having two or more openings of different sizes located on the second planarization layer, wherein in the region below the two or more openings of different sizes, the metal pattern is spaced apart at equal intervals. Effects of the invention

[0007] According to the embodiments of the present disclosure, a display device with improved color viewing angle characteristics can be provided. Brief explanation of the drawing

[0008] FIG. 1 is a system configuration diagram of a display device according to embodiments of the present specification. FIG. 2 is an equivalent circuit of a subpixel in a display panel according to embodiments of the present specification. FIG. 3 is a cross-sectional view of the display area of ​​a display panel according to embodiments of the present specification. FIG. 4 is a diagram briefly illustrating the arrangement of multiple subpixels in a display area of ​​a display panel according to embodiments of the present specification. Figure 5 is a conceptual diagram showing the appearance of a step difference occurring in the light-emitting region by the second source-drain electrode material pattern in the subpixel. FIGS. 6a to 6c are cross-sectional views of the green subpixel and blue subpixel of FIG. 5 by region and drawings showing color viewing angle characteristics. FIG. 7 is a diagram illustrating that in a display device according to embodiments of the present specification, a second source-drain electrode material pattern is arranged on a substrate with symmetry in an area that overlaps with the light-emitting region of a subpixel. FIGS. 8 to 11 are drawings showing in more detail a second source-drain electrode material pattern located overlapping with the light-emitting region of a subpixel. FIG. 12 is a diagram showing that in a display device according to embodiments of the present specification, at least a portion of the second source-drain electrode material pattern is overlapped with respect to the central axis. FIGS. 13a to 13d are drawings illustrating various embodiments of an inner pattern. Specific details for implementing the invention

[0009] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions may obscure the essence of the present disclosure, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless there is a special explicit description otherwise.

[0010] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used to describe the components of the present disclosure. These terms are used merely to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by such terms.

[0011] In describing the positional relationship of components, where it is stated that two or more components are "connected," "combined," or "joined," it should be understood that while the two or more components may be directly "connected," "combined," or "joined," they may also be "connected," "combined," or "joined" with other components "intervened." Here, the other components may be included in one or more of the two or more components that are "connected," "combined," or "joined" with one another.

[0012] In describing the temporal flow relationship regarding components, methods of operation, or methods of production, for example, when the temporal or sequential relationship is described using "after," "following," "next," or "before," it may include cases where the relationship is not continuous unless "immediately" or "directly" is used.

[0013] Meanwhile, where numerical values ​​or corresponding information regarding a component (e.g., levels, etc.) are mentioned, even without separate explicit notation, the numerical values ​​or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0014] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0015] FIG. 1 is a system configuration diagram of a display device (100) according to embodiments of the present specification.

[0016] Referring to FIG. 1, the display device (100) may include a display panel (110) and a display driving circuit as components for displaying images.

[0017] The display driving circuit is a circuit for driving a display panel (110) and may include a data driving circuit (120), a gate driving circuit (130), and a display controller (140), etc.

[0018] The display panel (110) may include a display area (AA) where an image is displayed and a non-display area (NA) where an image is not displayed. The non-display area (NA) may be an outer area of ​​the display area (AA) and is also referred to as a bezel area. All or part of the non-display area (NA) may be an area visible from the front of the display device (100), or an area that is bent and not visible from the front of the display device (100).

[0019] The display panel (110) may include a substrate (SUB) and a plurality of subpixels (SP) disposed on the substrate (SUB). Additionally, the display panel (110) may further include various types of signal lines to drive the plurality of subpixels (SP).

[0020] The display device (100) according to the embodiments of the present specification may be a liquid crystal display device, etc., or the display panel (110) may be a self-emitting display device. If the display device (100) according to the embodiments of the present specification is a self-emitting display device, each of the plurality of subpixels (SP) may include a light-emitting element.

[0021] For example, the display device (100) according to the embodiments of the present specification may be an organic light-emitting display device in which the light-emitting element is implemented as an organic light-emitting diode (OLED). As another example, the display device (100) according to the embodiments of the present specification may be an inorganic light-emitting display device in which the light-emitting element is implemented as an inorganic-based light-emitting diode. As yet another example, the display device (100) according to the embodiments of the present specification may be a quantum dot display device in which the light-emitting element is implemented as a quantum dot, which is a semiconductor crystal that emits light on its own.

[0022] Depending on the type of display device (100), the structure of each of the multiple subpixels (SP) may vary. For example, if the display device (100) is a self-emissive display device in which the subpixels (SP) emit light themselves, each subpixel (SP) may include a light-emitting element that emits light itself, one or more transistors, and one or more capacitors.

[0023] For example, various types of signal lines may include a number of data lines (DL) that transmit data signals (also called data voltages or image signals) and a number of gate lines (GL) that transmit gate signals (also called scan signals).

[0024] A plurality of data lines (DL) and a plurality of gate lines (GL) may intersect each other. Each of the plurality of data lines (DL) may be arranged to extend in a first direction. Each of the plurality of gate lines (GL) may be arranged to extend in a second direction.

[0025] Here, the first direction may be the column direction and the second direction may be the row direction. The first direction may be the row direction and the second direction may be the column direction.

[0026] The data driving circuit (120) is a circuit configured to drive a plurality of data lines (DL) and can output data signals to a plurality of data lines (DL). The gate driving circuit (130) is a circuit configured to drive a plurality of gate lines (GL) and can output gate signals to a plurality of gate lines (GL).

[0027] The display controller (140) may be a device configured to control the data driving circuit (120) and the gate driving circuit (130). The display controller (140) can control the driving timing for a plurality of data lines (DL) and the driving timing for a plurality of gate lines (GL).

[0028] The display controller (140) can supply a data driving control signal (DCS) to the data driving circuit (120) to control the data driving circuit (120). The display controller (140) can supply a gate driving control signal (GCS) to the gate driving circuit (130) to control the gate driving circuit (130).

[0029] The display controller (140) receives input image data from the host system (150) and can supply image data (Data) to the data driving circuit (120) based on the input image data.

[0030] The data driving circuit (120) can supply data signals to a plurality of data lines (DL) according to the driving timing control of the display controller (140).

[0031] The data driving circuit (120) receives digital image data (Data) from the display controller (140) and converts the received image data (Data) into analog data signals and outputs them to multiple data lines (DL).

[0032] The gate driving circuit (130) can supply gate signals to a plurality of gate lines (GL) according to the timing control of the display controller (140). The gate driving circuit (130) receives a first gate voltage corresponding to a turn-on level voltage and a second gate voltage corresponding to a turn-off level voltage along with various gate control signals (GCS), generates gate signals, and can supply the generated gate signals to a plurality of gate lines (GL).

[0033] For example, the data driving circuit (120) may be connected to the display panel (110) by a Tape Automated Bonding (TAB) method, connected to the bonding pad of the display panel (110) by a Chip On Glass (COG) or Chip On Panel (COP) method, or implemented and connected to the display panel (110) by a Chip On Film (COF) method.

[0034] The gate driving circuit (130) may be connected to the display panel (110) by a tape automatic bonding (TAB) method, connected to the bonding pads of the display panel (110) by a chip-on-glass (COG) or chip-on-panel (COP) method, or connected to the display panel (110) by a chip-on-film (COF) method. Alternatively, the gate driving circuit (130) may be formed in the non-display area (NA) of the display panel (110) in a gate-in-panel (GIP) type. The gate driving circuit (130) may be placed on a substrate (SUB) or connected to the substrate (SUB). That is, if the gate driving circuit (130) is of the gate-in-panel (GIP) type, it may be placed in the non-display area (NA) of the substrate (SUB). The gate driving circuit (130) can be connected to a substrate (SUB) in the case of a chip-on-glass (COG) type, chip-on-film (COF) type, etc.

[0035] Meanwhile, at least one of the data driving circuit (120) and the gate driving circuit (130) may be placed in the display area (AA) of the display panel (110). For example, at least one of the data driving circuit (120) and the gate driving circuit (130) may be placed so as not to overlap with the subpixels (SP), or it may be placed so as to overlap at least part or all with the subpixels (SP).

[0036] The data driving circuit (120) may be connected to one side (e.g., the upper side or the lower side) of the display panel (110). Depending on the driving method, panel design method, etc., the data driving circuit (120) may be connected to both sides (e.g., the upper side and the lower side) of the display panel (110), or may be connected to two or more of the four sides of the display panel (110).

[0037] The gate driving circuit (130) may be connected to one side (e.g., left or right) of the display panel (110). Depending on the driving method, panel design method, etc., the gate driving circuit (130) may be connected to both sides (e.g., left and right) of the display panel (110), or to two or more sides of the four sides of the display panel (110).

[0038] The display controller (140) may be implemented as a separate component from the data driving circuit (120), or it may be implemented as an integrated circuit integrated with the data driving circuit (120).

[0039] The display controller (140) may be a timing controller used in conventional display technology, or a control device capable of performing other control functions including a timing controller, or a control device different from a timing controller, or a circuit within a control device. The display controller (140) may be implemented as various circuits or electronic components such as an IC (Integrated Circuit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or processor.

[0040] The display controller (140) can be electrically connected to the data driving circuit (120) and the gate driving circuit (130) through a printed circuit board (PCB), a flexible printed circuit board (FPCB), etc.

[0041] The display controller (140) can transmit and receive signals to and from the data driving circuit (120) according to one or more predetermined interfaces. Here, for example, the interfaces may include an LVDS (Low Voltage Differential Signaling) interface, an EPI interface, an SPI (Serial Peripheral Interface), etc.

[0042] A display device (100) according to the embodiments of the present specification may include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or a pen, or detects the touch location, in order to provide not only an image display function but also a touch sensing function.

[0043] The touch sensing circuit may include a touch driving circuit (160) that drives and senses a touch sensor to generate and output touch sensing data, and a touch controller (170) that can detect the occurrence of a touch or detect a touch location using the touch sensing data.

[0044] The touch sensor may include a plurality of touch electrodes. The touch sensor may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes and the touch driving circuit (160).

[0045] The touch sensor may exist in the form of a touch panel outside the display panel (110) or inside the display panel (110).

[0046] When a touch sensor exists outside the display panel (110) in the form of a panel, the touch sensor is referred to as an external type. When the touch sensor is external, the touch panel and the display panel (110) may be manufactured separately and combined during the assembly process. The external touch panel may include a substrate for the touch panel and a plurality of touch electrodes on the substrate for the touch panel.

[0047] When a touch sensor is present inside a display panel (110), the touch sensor may be formed on a substrate (SUB) along with signal lines and electrodes related to display driving during the manufacturing process of the display panel (110).

[0048] The touch driving circuit (160) can supply a touch driving signal to at least one of a plurality of touch electrodes and sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0049] The touch sensing circuit can perform touch sensing using a self-capacitance sensing method or a mutual-capacitance sensing method.

[0050] When a touch sensing circuit performs touch sensing using a sulf-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., finger, pen, etc.).

[0051] According to the self-capacitance sensing method, each of the plurality of touch electrodes can act as both a driving touch electrode and a sensing touch electrode. The touch driving circuit (160) can drive all or part of the plurality of touch electrodes and sense all or part of the plurality of touch electrodes.

[0052] When a touch sensing circuit performs touch sensing using a mutual-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between touch electrodes.

[0053] According to the mutual-capacitance sensing method, multiple touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit (160) can drive the driving touch electrodes and sense the sensing touch electrodes.

[0054] The touch driving circuit (160) and touch controller (170) included in the touch sensing circuit may be implemented as separate devices or as a single device. Additionally, the touch driving circuit (160) and the data driving circuit (120) may be implemented as separate devices or as a single device.

[0055] The display device (100) may further include a power supply circuit that supplies various power to a display driving circuit and / or a touch sensing circuit.

[0056] The display device (100) according to the embodiments of the present specification may be a mobile terminal such as a smartphone or tablet, or a monitor or television (TV) of various sizes, but is not limited thereto, and may be a display device of various types and sizes capable of displaying information or images.

[0057] FIG. 2 is an equivalent circuit of a subpixel (SP) in a display panel (110) according to embodiments of the present specification.

[0058] Referring to FIG. 2, each of the subpixels (SP) placed in the display area (AA) of the display panel (110) may include a light-emitting element (ED), a driving transistor (DRT) for driving the light-emitting element (ED), a scan transistor (SCT) for transmitting a data voltage (Vdata) to a first node (N1) of the driving transistor (DRT), and a storage capacitor (Cst) for maintaining a constant voltage for one frame.

[0059] The driving transistor (DRT) may include a first node (N1) to which a data voltage (Vdata) is applied, a second node (N2) electrically connected to a light-emitting element (ED), and a third node (N3) to which a high potential common voltage (ELVDD) is applied from a driving voltage line (DVL). In the driving transistor (DRT), the first node (N1) is a gate node, the second node (N2) may be either a source node or a drain node, and the third node (N3) may be the other of the source node or drain node.

[0060] The light-emitting element (ED) may include an anode electrode (AE), a light-emitting layer (EL), and a cathode electrode (CE). The anode electrode (AE) may be a pixel electrode placed in each subpixel (SP) and may be electrically connected to a second node (N2) of a driving transistor (DRT) of each subpixel (SP). The cathode electrode (CE) may be a common electrode placed in common across a plurality of subpixels (SP) and may have a low potential common voltage (ELVSS) applied to it.

[0061] For example, the anode electrode (AE) may be a pixel electrode and the cathode electrode (CE) may be a common electrode. Conversely, the anode electrode (AE) may be a common electrode and the cathode electrode (CE) may be a pixel electrode. For convenience of explanation, it is assumed below that the anode electrode (AE) is a pixel electrode and the cathode electrode (CE) is a common electrode.

[0062] For example, the light-emitting element (ED) may be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting element. In this case, if the light-emitting element (ED) is an organic light-emitting diode, the light-emitting layer (EL) in the light-emitting element (ED) may include an organic light-emitting layer containing organic material.

[0063] The scan transistor (SCT) is turned on and off by a scan signal (SCAN), which is a gate signal applied through the gate line (GL). The scan transistor (SCT) can switch the electrical connection between the first node (N1) of the driving transistor (DRT) and the data line (DL).

[0064] The storage capacitor (Cst) can be electrically connected between the first node (N1) and the second node (N2) of the driving transistor (DRT).

[0065] Each subpixel (SP) may have a 2T (Transistor) 1C (Capacitor) structure including two transistors (DRT, SCT) and one capacitor (Cst), as shown in FIG. 2, and may additionally include one or more transistors or one or more capacitors.

[0066] The storage capacitor (Cst) may be an external capacitor intentionally designed outside the driving transistor (DRT), rather than a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor that may exist between the first node (N1) and the second node (N2) of the driving transistor (DRT).

[0067] The driving transistor (DRT) and the scan transistor (SCT) can each be an n-type transistor or a p-type transistor.

[0068] Since the circuit elements (especially light-emitting elements (ED)) within each subpixel (SP) are vulnerable to external moisture or oxygen, an encapsulation layer (ENCAP) can be placed on the display panel (110) to prevent external moisture or oxygen from penetrating into the circuit elements (especially light-emitting elements (ED)).

[0069] FIG. 3 is a cross-sectional view of a display area (AA) of a display panel (110) according to embodiments of the present specification.

[0070] Referring to FIG. 3, the substrate (SUB) may include a first substrate (SUB1), an interlayer insulating film (IPD), and a second substrate (SUB2). The interlayer insulating film (IPD) may be located between the first substrate (SUB1) and the second substrate (SUB2). By configuring the substrate (SUB) with the first substrate (SUB1), the interlayer insulating film (IPD), and the second substrate (SUB2), moisture penetration can be prevented. For example, the first substrate (SUB1) and the second substrate (SUB2) may be polyimide (PI) substrates. The first substrate (SUB1) may be referred to as a primary PI substrate, and the second substrate (SUB2) may be referred to as a secondary PI substrate.

[0071] Referring to FIG. 3, on the substrate (SUB), various patterns for forming transistors such as a driving transistor (DRT), various patterns (ACT, SD1, GATE), various insulating films (MBUF, ABUF1, ABUF2, GI, ILD1, ILD2, PAS0), and various metal patterns (TM, GM, ML1, ML2) may be positioned.

[0072] Referring to FIG. 3, a multi-buffer layer (MBUF) may be disposed on a second substrate (SUB2), and a first active buffer layer (ABUF1) may be disposed on the multi-buffer layer (MBUF).

[0073] A first metal layer (ML1) and a second metal layer (ML2) may be disposed on a first active buffer layer (AUBF1). Here, the first metal layer (ML1) and the second metal layer (ML2) may be light shield layers (LS) that shield light.

[0074] A second active buffer layer (ABUF2) may be disposed on the first metal layer (ML1) and the second metal layer (ML2).

[0075] A gate insulating film (GI) can be placed over the active layer (ACT).

[0076] The gate electrode (GATE) of the driving transistor (DRT) can be placed on the gate insulating film (GI).

[0077] A first interlayer insulating film (ILD1) may be disposed covering a gate electrode (GATE) and a gate material layer (GM). A metal pattern (TM) may be disposed on the first interlayer insulating film (ILD1). The metal pattern (TM) may be located at a different location from the formation site of the driving transistor (DRT). A second interlayer insulating film (ILD2) may be disposed covering the metal pattern (TM) on the first interlayer insulating film (ILD1).

[0078] Two first source-drain electrode material patterns (SD1) may be disposed on the second interlayer insulating film (ILD2). One of the two first source-drain electrode material patterns (SD1) is the source node of the driving transistor (DRT), and the other is the drain node of the driving transistor (DRT).

[0079] Two first source-drain electrode material patterns (SD1) can be electrically connected to one side and the other side of the active layer (ACT) through contact holes of the second interlayer insulating film (ILD2), the first interlayer insulating film (ILD1), and the gate insulating film (GI).

[0080] The portion overlapping with the gate electrode (GATE) in the active layer (ACT) is the channel region. One of the two first source-drain electrode material patterns (SD1) can be connected to one side of the channel region in the active layer (ACT), and the other of the two first source-drain electrode material patterns (SD1) can be connected to the other side of the channel region in the active layer (ACT).

[0081] A passivation layer (PAS0) is disposed over two first source-drain electrode material patterns (SD1). A planarization layer (PLN) may be disposed on the passivation layer (PAS0). The planarization layer (PLN) may include a first planarization layer (PLN1) and a second planarization layer (PLN2). This planarization layer (PLN) may be an organic insulating film layer capable of performing a planarization function.

[0082] A first flattening layer (PLN1) can be disposed on a passivation layer (PAS0).

[0083] A second source-drain electrode material pattern (SD2) may be disposed on the first planarization layer (PLN1). The second source-drain electrode material pattern (SD2) may be connected to one of the two first source-drain electrode material patterns (SD1) (corresponding to the second node (N2) of the driving transistor (DRT) in the subpixel (SP) of FIG. 2) through a contact hole of the first planarization layer (PLN1).

[0084] The second planarization layer (PLN2) can be disposed over the second source-drain electrode material pattern (SD2). A light-emitting element (ED) can be disposed on the second planarization layer (PLN2).

[0085] Looking at the stacked structure of the light-emitting device (ED), an anode electrode (AE) can be disposed on a second planarization layer (PLN2). The anode electrode (AE) can be electrically connected to a second source-drain electrode material pattern (SD2) through a contact hole (CNT) of the second planarization layer (PLN2).

[0086] A bank can be positioned to cover a portion of the anode electrode (AE). A portion of the bank corresponding to the light-emitting region (EA) of the subpixel (SP) can be left open.

[0087] A portion of the anode electrode (AE) may be exposed to an opening (open portion) of the bank. The light-emitting layer (EL) may be located on the side of the bank and at an opening (open portion) of the bank. All or part of the light-emitting layer (EL) may be located between adjacent banks.

[0088] At the opening of the bank, the light-emitting layer (EL) can come into contact with the anode electrode (AE). A cathode electrode (CE) can be placed on the light-emitting layer (EL).

[0089] A light-emitting device (ED) can be formed by an anode electrode (AE), a light-emitting layer (EL), and a cathode electrode (CE). The light-emitting layer (EL) may include an organic film.

[0090] An encapsulation layer (ENCAP) can be disposed on the aforementioned light-emitting element (ED).

[0091] The encapsulation layer (ENCAP) may have a single-layer structure or a multi-layer structure. For example, as shown in FIG. 3, the encapsulation layer (ENCAP) may include a first encapsulation layer (PAS1), a second encapsulation layer (PCL), and a third encapsulation layer (PAS2).

[0092] For example, the first encapsulation layer (PAS1) and the third encapsulation layer (PAS2) may be inorganic membranes, and the second encapsulation layer (PCL) may be an organic membrane. Among the first encapsulation layer (PAS1), the second encapsulation layer (PCL), and the third encapsulation layer (PAS2), the second encapsulation layer (PCL), which is an organic membrane, is the thickest and can serve as a leveling layer.

[0093] The first encapsulation layer (PAS1) is placed on the cathode electrode (CE) and can be positioned closest to the light-emitting element (ED). The first encapsulation layer (PAS1) can be formed from an inorganic insulating material capable of low-temperature deposition. For example, the first encapsulation layer (PAS1) may be silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first encapsulation layer (PAS1) is deposited in a low-temperature atmosphere, during the deposition process, the first encapsulation layer (PAS1) can prevent damage to the light-emitting layer (EL), which contains organic materials susceptible to high-temperature atmospheres.

[0094] The second encapsulation layer (PCL) may be formed with an area smaller than that of the first encapsulation layer (PAS1). In this case, the second encapsulation layer (PCL) may be formed to expose both ends of the first encapsulation layer (PAS1). The second encapsulation layer (PCL) acts as a buffer to relieve stress between each layer due to bending of the display device (100) and may also serve to enhance flattening performance. For example, the second encapsulation layer (PCL) may be acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbon (SiOC), and may be formed from an organic insulating material. For example, the second encapsulation layer (PCL) may be formed using an inkjet method.

[0095] A third inorganic encapsulation layer (PAS2) may be formed on a substrate (SUB) on which a second encapsulation layer (PCL) is formed, so as to cover the upper surface and side surface of the second encapsulation layer (PCL) and the first encapsulation layer (PAS1), respectively. The third encapsulation layer (PAS2) can minimize or block external moisture or oxygen from penetrating into the first inorganic encapsulation layer (PAS1) and the second encapsulation layer (PCL). For example, the third encapsulation layer (PAS2) may be formed from an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiON), or aluminum oxide (Al2O3).

[0096] Referring to FIG. 3, a touch sensor (TS) can be placed on the encapsulation layer (ENCAP). The structure of the touch sensor (TS) is described in detail as follows.

[0097] A touch buffer film (T-BUF) can be disposed on the encapsulation layer (ENCAP). A touch sensor (TS) can be disposed on the touch buffer film (T-BUF).

[0098] The touch sensor (TS) may include a touch sensor metal (TSM) and a bridge metal (BRG) located on different layers.

[0099] A touch interlayer insulating film (T-ILD) may be placed between the touch sensor metal (TSM) and the bridge metal (BRG).

[0100] For example, touch sensor metals (TSMs) may include a first touch sensor metal (TSM), a second touch sensor metal (TSM), and a third touch sensor metal (TSM) that are arranged adjacent to each other. When a third touch sensor metal (TSM) is located between the first touch sensor metal (TSM) and the second touch sensor metal (TSM), and the first touch sensor metal (TSM) and the second touch sensor metal (TSM) need to be electrically connected to each other, the first touch sensor metal (TSM) and the second touch sensor metal (TSM) may be electrically connected to each other through a bridge metal (BRG) located in a different layer. The bridge metal (BRG) may be insulated from the third touch sensor metal (TSM) by a touch interlayer insulating film (T-ILD).

[0101] When a touch sensor (TS) is formed on a display panel (110), a chemical solution (such as a developer or etching solution) used in the process may flow into the interior, or moisture may flow in from the outside. By placing the touch sensor (TS) on a touch buffer film (T-BUF), it is possible to prevent the chemical solution or moisture from penetrating into the light-emitting layer (EL) containing organic material during the manufacturing process of the touch sensor (TS). Accordingly, the touch buffer film (T-BUF) can prevent damage to the light-emitting layer (EL), which is vulnerable to the chemical solution or moisture.

[0102] To prevent damage to the light-emitting layer (EL) containing organic material that is susceptible to high temperatures, the touch buffer film (T-BUF) can be formed at a low temperature (e.g., 100°C) or lower and can be formed from an organic insulating material having a low dielectric constant of 1 to 3. For example, the touch buffer film (T-BUF) can be formed from an acrylic-based or siloxane-based material. As the display device (100) bends, the encapsulation layer (ENCAP) may be damaged and the touch sensor metal located on the touch buffer film (T-BUF) may break. Even if the display device (100) bends, the touch buffer film (T-BUF), which has flattening performance as an organic insulating material, can prevent damage to the encapsulation layer (ENCAP) and / or breakage of the metal (TSM, BRG) constituting the touch sensor (TS).

[0103] Meanwhile, referring to FIG. 3, a protective layer (PAC) may be disposed to cover the touch sensor (TS). The protective layer (PAC) may be an organic insulating film. Such an organic insulating film may be, for example, a material such as the planarization layer (PLN) described above. Such an organic insulating film may be formed of a material different from the second encapsulation layer (PCL2). For example, such a protective layer (PAC) may include a thermosetting resin.

[0104] FIG. 4 is a diagram briefly illustrating the arrangement of a plurality of subpixels (SP) in a display area (AA) of a display panel (110) according to embodiments of the present specification.

[0105] In FIG. 4, among the various layers described in FIG. 3, a first source-drain electrode material (SD1), a second source-drain electrode material (SD2), an anode electrode (AE), and a light-emitting layer (EL) located in a light-emitting region (EA) are shown. The light-emitting region (EA) may correspond to the aforementioned opening (open portion).

[0106] As illustrated in FIG. 4, a single pixel (P) may include one blue light-emitting region (EA), one red light-emitting region (EA), and two green light-emitting regions (EA). Subpixels (SP) may be arranged within the pixel (P) so that the pixel (P) can be formed in a diamond shape.

[0107] According to this, a red light-emitting region (EA) and one green light-emitting region (EA) can be driven as one subpixel (also called an RG subpixel), and a blue light-emitting region (EA) and another green light-emitting region (EA) can be driven as one subpixel (also called a BG subpixel). Accordingly, a pixel (P) is composed of a combination of an RG subpixel and a BG subpixel, and such a structure of a pixel (P) is also called an RG-BG pixel structure.

[0108] However, in this specification, the description of the blue light-emitting region is referred to as the blue subpixel (B), the description of the red light-emitting region is referred to as the red subpixel (R), and the description of the green light-emitting region is referred to as the green subpixel (G).

[0109] That is, according to this, the RG subpixel consists of a red subpixel (R) and a green subpixel (G), and the BG subpixel consists of a blue subpixel (B) and a green subpixel (G).

[0110] Referring to FIG. 4, a plurality of data lines (DL) and a plurality of common voltage lines (DVL) are extended in a first direction and disposed on a substrate. The plurality of data lines (DL) and the plurality of common voltage lines (DVL) may be made of the aforementioned second source-drain electrode material (SD2).

[0111] The light-emitting regions (EA) of a plurality of subpixels (SP) can be arranged to overlap with at least one data line (DL) and / or at least one common voltage line (DVL).

[0112] Referring to FIG. 4, the light-emitting region (EA) of the first color subpixel (SP) may be positioned overlapping with at least one data line (DL). Although FIG. 4 illustrates the first color subpixel (SP) as being a red subpixel (R) or a blue subpixel (B), the first color subpixel (SP) may be a green subpixel (G1, G2) or a subpixel (SP) expressing other colors. For convenience of explanation, the first color subpixel (SP) is assumed to be a blue subpixel (B), but the present invention is not limited thereto.

[0113] From the perspective of data lines (DL), multiple data lines (DL) may be seen as being arranged to penetrate the area below the light-emitting region (EA) of at least one first color subpixel (SP).

[0114] Referring to FIG. 4, the light-emitting region (EA) of the second color subpixel (SP) may be positioned to overlap with at least one common voltage line (DVL). The light-emitting region (EA) of the second color subpixel (SP) may not be positioned to overlap with the data line (DL).

[0115] In FIG. 4, the second color subpixel (SP) is depicted as a green subpixel (G1, G2), but the second color subpixel (SP) may be a red subpixel (R) or a blue subpixel (B), or a subpixel expressing any other color. For convenience of explanation, the second color subpixel (SP) is assumed to be a green subpixel (G1, G2), but the present invention is not limited thereto.

[0116] The light-emitting region (EA) of the second color subpixel (SP) can be positioned in a direction tilted relative to the first direction.

[0117] Specifically, the light-emitting region (EA) of the second color subpixel (SP) may be positioned at a predetermined angle from the first direction in which a plurality of data lines (DL) and a plurality of common voltage lines (DVL) extend.

[0118] The second color subpixel (SP) and the first color subpixel (SP) can be placed in different rows. Additionally, the second color subpixel (SP) and the first color subpixel (SP) can be placed in different columns.

[0119] Referring to FIG. 4, green subpixels (G) may be placed in even rows (R2, R4, etc.), while blue subpixels (B) may be placed in odd rows (R1, R3, etc.). Additionally, green subpixels (G1, G2) may be placed in even columns (C2, C4), while blue subpixels (B) may be placed in odd columns (C1, C3, etc.).

[0120] Additionally, referring to FIG. 4, the red subpixel (R) may be placed in even rows (R2, R4, etc.) and odd columns (C1, C3).

[0121] According to this, blue subpixels (B) and red subpixels (R) are alternately arranged in even rows (R2, R4, etc.) and odd columns (C1, C3, etc.). In this case, the area of ​​the light-emitting region (EA) of the blue subpixel (B) and the area of ​​the light-emitting region (EA) of the red subpixel (R) may be different from each other. For example, the area of ​​the light-emitting region (EA) of the blue subpixel (B) may be larger than the area of ​​the light-emitting region (EA) of the red subpixel (R). Accordingly, the distance between blue subpixels (B) may be smaller than the distance between red subpixels (R).

[0122] Because the distance between the blue subpixels (B) and the distance between the red subpixels (R) may differ from each other, the shape of the opening (EA) of the green subpixels (G1, G2) placed between them may not be diamond-shaped.

[0123] For example, in order to make the area of ​​the light-emitting region (EA) of the green subpixels (G1, G2) as large as possible, the shape of the light-emitting region (EA) of the green subpixels (G1, G2) may be elongated in the direction of the red subpixel (R).

[0124] Accordingly, the green subpixels (G1, G2) may include a first green subpixel (G1) that is elongated in the upper-left and lower-right directions, and a second green subpixel (G2) that is elongated in the upper-right and lower-left directions.

[0125] Meanwhile, referring to FIG. 4, a plurality of data lines (DL) can be arranged such that two or more data lines (DL) form a pair.

[0126] For example, referring to FIG. 4, the first data line (DL1) and the second data line (DL2) can be arranged adjacent to each other as a pair. The first data line (DL1) and the second data line (DL2) form a pair and are arranged in the area between two different common voltage lines (DVL).

[0127] The first data line (DL1) can supply data voltage for image display to the first color subpixel (SP). The second data line (DL2) can supply data voltage for image display to the second color subpixel (SP).

[0128] For example, the first data line (DL1) can supply data voltage for image display to subpixels (SP) located in odd columns (C1, C3, etc.). Accordingly, the first data line (DL1) can supply data voltage for image display to red subpixels (R) and blue subpixels (B) located in odd columns (C1, C3, etc.).

[0129] Additionally, the second data line (DL2) can supply data voltage for image display to subpixels (SP) located in even columns (C2, C4, etc.). Accordingly, the second data line (DL2) can supply data voltage for image display to green subpixels (G1, G2) located in even columns (C2, C4, etc.).

[0130] Conversely, the first data line (DL1) can supply data voltage for image display to subpixels (SP) located in even columns (C2, C4, etc.), and the second data line (DL2) can supply data voltage for image display to subpixels (SP) located in odd columns (C1, C3, etc.).

[0131] For convenience of explanation, the following description assumes that the first data line (DL1) supplies data voltage for image display to subpixels (SP) located in odd columns (C1, C3, etc.) and the second data line (DL2) supplies data voltage for image display to subpixels (SP) located in even columns (C2, C4, etc.), but the present invention is not limited thereto.

[0132] According to this, the first data line (DL1) can supply data voltage to the red subpixel (R) and the blue subpixel (B), and the second data line (DL2) can supply data voltage to the green subpixels (G1, G2).

[0133] Referring to FIG. 4, the light-emitting region (EA) of the red subpixel (R) and the light-emitting region (EA) of the blue subpixel (B) are located on the first data line (DL1) and the second data line (DL2). Depending on the design method of the common voltage line (DVL), the light-emitting region (EA) of the red subpixel (R) and the light-emitting region (EA) of the blue subpixel (B) may be arranged to overlap with the common voltage line (DVL). The light-emitting region (EA) of the green subpixels (G1, G2) is located on the common voltage line (DVL).

[0134] Meanwhile, as previously observed in FIG. 3, in order to increase the resolution and increase the aperture ratio by arranging many subpixels (SP) in a narrow area, the display device according to the embodiments of the present specification may include both a first source-drain electrode material pattern (SD1) and a second source-drain electrode material pattern (SD2).

[0135] Referring to the aforementioned FIG. 3, the first source-drain electrode material pattern (SD1) is covered by the first flattening layer (PLN1), and the second source-drain electrode material pattern (SD2) is covered by the second flattening layer (PLN2).

[0136] Additionally, in the display device according to the embodiments of the present specification, a plurality of data lines (DL) may be formed using the second source-drain electrode material pattern (SD2). And, a plurality of common voltage lines (DVL) may be formed using the second source-drain electrode material pattern (SD2).

[0137] According to this, multiple data lines (DL) and multiple common voltage lines (DVL) affect the flatness of the opening formed by removing at least a portion of the bank.

[0138] Referring to FIG. 4, the red subpixel (R) and blue subpixel (B) are penetrated by data lines (DL) of a narrow area, while the green subpixels (G1, G2) are located overlapping with a common voltage line (DVL) of a wide area.

[0139] According to this, the red subpixel (R), blue subpixel (B), and green subpixels (G1, G2) can each have different step patterns. Consequently, the luminance varies by color depending on the viewing angle of the display area. Therefore, a problem arises where the color coordinates become distorted depending on the viewing angle.

[0140] In addition, the first source-drain electrode material pattern (SD1) is also positioned to overlap with the light-emitting region (EA), and the first source-drain electrode material pattern (SD1) also affects the flatness of the aperture. That is, the problem of the aforementioned color coordinates being distorted also occurs due to the first source-drain electrode material pattern (SD1).

[0141] Therefore, there is a need for a solution to the problem of color coordinates being distorted by the first source-drain electrode material pattern (SD1) and the second source-drain electrode material pattern (SD2).

[0142] FIG. 5 is a conceptual diagram showing how a step occurs in the light-emitting region (EA) by the second source-drain electrode material pattern (SD2) in the subpixel (SP).

[0143] Referring to FIG. 5, the step means that the light-emitting region (EA) is raised above the surrounding region by the second source-drain electrode material pattern (SD2).

[0144] Referring to FIG. 4 and FIG. 5 together, for the red subpixel (R) and blue subpixel (B), a step can be formed by the data line (DL). For the green subpixels (G1, G2), a step can be formed by the common voltage line (DVL).

[0145] The data line (DL) can be formed over a relatively thin area. Accordingly, a step pattern is formed across the light-emitting region (EA) in the blue subpixel (B) and red subpixel (R). In contrast, the common voltage line (DVL) can overlap with the green subpixels (G1, G2) over a relatively wide area. Accordingly, a step can be formed over the remaining wide area, excluding a portion of the light-emitting region (EA) of the green subpixels (G1, G2).

[0146] Meanwhile, in FIG. 5, a spherical coordinate system is briefly illustrated to analyze the cause of the luminance deviation according to the viewing angle due to the step.

[0147] A spherical coordinate system defines the position of a point using (r, π, θ).

[0148] r is the distance from the origin (0, 0, 0) to a point. π is the angle that a point makes with the positive x-axis along the z-axis. θ is the angle that a point makes with the positive z-axis.

[0149] Referring to FIG. 5, the II' cross of the green subpixel (G2) may be a cross cut along the line connecting π=180˚ and π=0. The II-II' cross of the blue subpixel (B) may be a cross cut along the line connecting π=245˚ and π=45˚. The III-III' cross of the blue subpixel (B) may be a cross cut along the line connecting π=135˚ and π=315˚. That is, I-I', II-II', and III-III' correspond to the line connecting π=α and π=α+180˚, respectively.

[0150] Meanwhile, as a method to verify the luminance deviation according to the viewing angle, a reference origin is set, and measurements are taken while maintaining a constant distance from the origin. According to this, r corresponds to a fixed constant value. In addition, since the change in luminance is measured across the front of the display area, color viewing angle characteristics are measured within the range of 0 < θ ≤ 90˚. According to this, θ corresponds to the viewing angle of the display area.

[0151] Color viewing angle characteristics can be defined as the difference between the luminance measured at π=α and the luminance measured at π=α+180˚, with θ set in advance. In other words, color viewing angle characteristics (luminance deviation according to viewing angle) can be said to be superior when the value is small and inferior when it is large.

[0152] Below, the deviation in luminance according to the difference in viewing angle (θ) is explained based on the green subpixel (G2) and blue subpixel (B) of FIG. 5.

[0153] FIGS. 6a to 6c are cross-sectional views of the green subpixel (G2) and blue subpixel (B) of FIG. 5, and drawings showing color viewing angle characteristics.

[0154] FIG. 6a is a cross-sectional view taken along I-I' of the green subpixel (G2) of FIG. 5 and a diagram explaining the color viewing angle characteristics along the II' line.

[0155] Referring to the top figure of FIG. 6a, the second source-drain electrode material pattern (SD2) is asymmetrically positioned in the region overlapping with the light-emitting region (EA). The second source-drain electrode material pattern (SD2) is located in the region below the light-emitting region (EA), specifically in the π=180˚ region, but not in the π=0˚ region.

[0156] Referring to the bottom figure of Fig. 6a, the color viewing angle characteristic (deviation in luminance) is defined as 0 when θ=0˚, and the color viewing angle characteristic according to the value of θ is displayed. As θ increases from 0, the color viewing angle characteristic increases rapidly, and it can be seen that the deviation in luminance is largest in the range of θ=20˚ to 50˚.

[0157] In particular, in the case of mobile terminals used in various lighting environments where the user views the screen from various angles, poor color viewing angle characteristics in the range of θ=20~50˚ cause a decrease in screen quality. According to this, the green subpixel (G2) can be seen as having poor color viewing angle characteristics.

[0158] This characteristic is also true for the green subpixel (G1).

[0159] FIG. 6b is a cross-sectional view taken along II-II' of the blue subpixel (B) of FIG. 5 and a diagram explaining the color viewing angle characteristics along the II-II' line.

[0160] Referring to the top figure of FIG. 6b, in the cross-sectional view taken by cutting the blue subpixel (B) along II-II', the second source-drain electrode material pattern (SD2) is not located.

[0161] That is, according to this, in the cross-sectional view in which the blue subpixel (B) is cut along the line II-II', no step difference is observed due to the second source-drain electrode material pattern (SD2).

[0162] Meanwhile, at the bottom of Fig. 6b, a graph is shown showing the color viewing angle characteristics according to the value of θ from θ=0 to θ=90˚, with the color viewing angle characteristic defined as 0 when θ=0˚.

[0163] Referring to this, the case where there is no second source-drain electrode material pattern (SD2) is superior in terms of color viewing angle characteristics compared to the case where the second source-drain electrode material pattern (SD2) is asymmetrically arranged. However, it can be confirmed that even in the case where there is no second source-drain electrode material pattern (SD2), the color viewing angle deviation gradually increases as the θ value increases from 0˚.

[0164] The reason the color viewing angle characteristics deteriorate somewhat even when the second source-drain electrode material pattern (SD2) is absent may be due to the fact that there are some limitations in the planarization of the planarization layer (PLN; collectively referred to as PLN1 and PLN2) located on the first source-drain electrode material pattern (SD1). According to this, the step difference caused by the first source-drain electrode material pattern (SD1) may cause a step difference on the bottom surface of the opening in the light-emitting region (EA).

[0165] That is, the color viewing angle characteristics can be affected by the first source-drain electrode material pattern (SD1).

[0166] In particular, as the pixel structure becomes more complex, the first source-drain electrode material pattern (SD1) can be placed on the substrate in various patterns. If the first source-drain electrode material pattern (SD1) and the light-emitting region (EA) are designed so as not to overlap, a problem may arise where the area of ​​the light-emitting region (EA) is reduced, resulting in a lower aperture ratio. Alternatively, there is a problem where the difficulty of designing the circuit portion of the subpixel increases significantly.

[0167] Therefore, even if the first source-drain electrode material pattern (SD1) and the light-emitting region (EA) overlap, it is required that the effect of the step difference caused by the arrangement of the first source-drain electrode material pattern (SD1) be minimized in the light-emitting region (EA).

[0168] FIG. 6c is a cross-sectional view taken along III-III' of the blue subpixel (B) of 5, and a diagram illustrating the color viewing angle characteristics along the III-III' line.

[0169] Referring to the top figure of Fig. 6c, the second source-drain electrode material pattern (SD2) is symmetrically arranged along the III-III' line.

[0170] The bottom graph of Fig. 6c is a graph showing the color viewing angle characteristics up to the case where θ=90˚, with the color viewing angle characteristics defined as 0 when θ=0˚ along the III-III' line of the blue subpixel (B).

[0171] According to the graph, as θ gradually increases from the case where θ=0˚, the color field of view characteristics have a negative value. In other words, as the value of θ increases from 0˚, the color field of view deviation can be seen to be further improved compared to the case where θ=0˚.

[0172] These results are also true for the red subpixel (R) placed overlapping with the data lines.

[0173] Comparing FIG. 6c and FIG. 6b, it means that even if the first source-drain electrode material pattern (SD1) is placed in overlap with the light-emitting region (EA), the step difference at the bottom of the opening caused by the placement of the first source-drain electrode material pattern (SD1) is compensated when the second source-drain electrode material pattern (SD2) is placed symmetrically.

[0174] In addition, when comparing FIG. 6c and FIG. 6a, even if the second source-drain electrode material pattern (SD2) is placed inside the opening (EA), the effect of improving the color viewing angle characteristics is greater when it is placed symmetrically inside the opening (EA).

[0175] In other words, the color viewing angle characteristics may be best when the second source-drain electrode material pattern (SD2) is positioned to penetrate and traverse the central region of the opening (EA), rather than being completely absent from the opening (EA) or only in the edge region. Additionally, the color viewing angle characteristics may be best when the second source-drain electrode material pattern (SD2) is positioned inside the opening (EA) such that at least a portion overlaps with respect to the axis of symmetry.

[0176] FIG. 7 is a diagram illustrating that in a display device according to embodiments of the present specification, a second source-drain electrode material pattern (SD2) is arranged on a substrate with symmetry in an area overlapping with a light-emitting region (EA) of a subpixel (SP).

[0177] Referring to FIG. 7, the light-emitting region (EA) of the blue subpixel (B) is positioned overlapping with a pair of data lines (DL) extending in a first direction. Specifically, the light-emitting region (EA) of the blue subpixel (B) is positioned overlapping with the first data line (DL1) and the second data line (DL2), and in the area below the light-emitting region (EA), the first data line (DL1) and the second data line (DL2) are positioned symmetrically with respect to a virtual axis of symmetry extending in the first direction.

[0178] These pairs of data lines (DL) are positioned to penetrate the lower region of the light-emitting area (EA) of the blue subpixel (B).

[0179] Additionally, referring to FIG. 7, the light-emitting region (EA) of a first color subpixel (e.g., blue subpixel (B)) located overlapping with a pair of data lines (DL1, DL2) may also overlap with a common voltage line (DVL). Here, the common voltage line (DVL) may be symmetrically positioned on both sides of the light-emitting region (EA) with respect to the virtual axis of symmetry.

[0180] For example, referring to FIG. 7, the light-emitting region (EA) of the blue subpixel (B) and the common voltage line (DVL) overlap in some areas. The areas that overlap with the common voltage line (DVL) in the light-emitting region (EA) of the blue subpixel (B) are arranged symmetrically with respect to the virtual axis of symmetry.

[0181] According to this, the second source-drain electrode material pattern (SD2) has the feature of being able to be placed overlapping with the light-emitting region (EA) over a wide area.

[0182] Since the second source-drain electrode material pattern (SD2) is located closer to the aperture (open portion) compared to the first source-drain electrode material pattern (SD1), it can have a greater impact on the color viewing angle characteristics compared to the first source-drain electrode material pattern (SD1). By positioning the second source-drain electrode material pattern (SD2) to overlap with the light-emitting region (EA) over a wide area using a common voltage line (DVL), it is possible to freely position the first source-drain electrode material pattern (SD1) in the area overlapping with the light-emitting region (EA). Accordingly, the size of each subpixel can be reduced while the aperture ratio can be increased.

[0183] Meanwhile, the light-emitting region (EA) of the green subpixels (G1, G2) is arranged to overlap with the driving voltage line (DVL) which is extended in the first direction.

[0184] In the lower region of the light-emitting area (EA) of the green subpixels (G1, G2), a pair of second source-drain electrode material patterns (SD2) that transmit a high potential driving voltage (ELVDD) are arranged extending in a first direction. Additionally, at least a portion of these pair of second source-drain electrode material patterns (SD2) may overlap each other with respect to a virtual axis of symmetry extending in the first direction. Furthermore, these pair of second source-drain electrode material patterns (SD2) may penetrate the lower region of the light-emitting area (EA) of the green subpixels (G1, G2) and be connected to each other in a region that does not overlap with the light-emitting area (EA).

[0185] These pairs of second source-drain electrode material patterns (SD2), located in the region below the light-emitting region (EA) of the green subpixels (G1, G2), may be spaced apart from each other. The spacing between the second source-drain electrode material patterns (SD2) below the light-emitting region (EA) of the green subpixels (G1, G2) may be equal to the spacing between the pair of data lines (DL) located below the light-emitting region (EA) of the blue subpixel (B).

[0186] Additionally, the thickness of each of these pairs of second source-drain electrode material patterns (SD2) located in the region below the light-emitting region (EA) of the green subpixels (G1, G2) may be equal to the thickness of each of the pair of data lines (DL) located below the light-emitting region (EA) of the blue subpixel (B).

[0187] According to this, in the blue subpixel (B), green subpixel (G), and red subpixel (R), a second source-drain electrode material pattern (SD2) located below the light-emitting region (EA) can be symmetrically arranged. Accordingly, the color viewing angle characteristics of the second color subpixel (e.g., green subpixel (G1, G2)) located in overlap with the driving voltage line (DVL) can be improved to a degree similar to the color viewing angle characteristics of the first color subpixel (e.g., blue subpixel (B)) located in overlap with the data lines.

[0188] Therefore, even if the viewing angle (corresponding to θ in Fig. 5) of the user looking at the display area changes, the luminance deviation between subpixels can be maintained at a constant level, so the problem of color coordinate distortion can be significantly improved.

[0189] Meanwhile, referring to FIG. 7, the contact hole (CNT) connecting the anode electrode (AE) of the light-emitting element and the second source-drain electrode material pattern (SD2) may preferably be located in an area that does not overlap with the light-emitting region (EA).

[0190] Referring to FIG. 3 and FIG. 7 together, at least a portion of the second planarization layer (PLN2) is removed in the area where the contact hole (CNT) is located. Consequently, a problem may arise where the bottom surface of the opening (open part) sinks due to the contact hole (CNT). This may result in poor color viewing angle characteristics. Therefore, it may be more desirable for the contact hole (CNT) to be located in an area that does not overlap with the light-emitting region (EA) in order to improve color viewing angle characteristics.

[0191] FIGS. 8 to 11 are drawings showing in more detail a second source-drain electrode material pattern (SD2) located overlapping with the light-emitting region of a subpixel.

[0192] Referring to FIGS. 8 to 11, the second source-drain electrode material pattern (SD2) includes an inner pattern (IP) located overlapping with the light-emitting region (EA).

[0193] Here, the inner pattern (IP) includes either a data line (DL) or a common voltage line (DVL) among the second source-drain electrode material pattern (SD2) that overlaps with the light-emitting region (EA).

[0194] Referring to FIGS. 8 and 9, when the light-emitting regions (EA) of the first subpixel (SP1) and the second subpixel (SP2) are positioned overlapping with a pair of data lines (DL), the inner pattern (IP) can form a data line. That is, a data voltage for image display can be applied to the inner pattern.

[0195] Referring to FIGS. 10 and 11, when the light-emitting regions (EA) of the third subpixel (SP3) and the fourth subpixel (SP4) overlap with the common voltage line (DVL) and do not overlap with the data line, the inner pattern (IP) can form the common voltage line. That is, a high-potential driving voltage for driving the subpixel can be applied to the inner pattern (IP).

[0196] According to this, the inner pattern (IP) may be a pattern in which both the inner boundary and the outer boundary overlap with the light-emitting region (EA). In the same sense, the inner pattern (IP) may be a second source-drain electrode material pattern (SD2) that penetrates the region below the light-emitting region (EA).

[0197] The inner patterns (IPs) are arranged symmetrically with respect to a virtual boundary line extending in the first direction.

[0198] Referring to FIGS. 8 to 11, the inner patterns (IPs) are arranged symmetrically with respect to the central axis (CA). The distances from the central axis (CA) to the inner boundaries of the inner patterns (IPs) are equal. Also, the distances from the central axis (CA) to the outer boundaries of the inner patterns (IPs) are equal.

[0199] The distance between the inner boundaries of the inner pattern (IP) can be defined as the first distance (ΔH1), and the distance between the outer boundaries of the inner pattern (IP) can be defined as the second distance (ΔH2). These first distance (ΔH1) and second distance (ΔH2) are the same for both the red subpixel (R) and the green subpixels (G1, G2). Accordingly, the color viewing angle characteristics are aligned to a similar level for the blue subpixel (B), the red subpixel (R), and the green subpixels (G1, G2).

[0200] Meanwhile, referring to FIGS. 8 to 11, the second source-drain electrode material pattern (SD2) may include an outer pattern (OP).

[0201] Here, the outer pattern (OP) refers to a pattern that is located outside the inner pattern (IP) among the second source-drain electrode material patterns (SD2) that overlap with the light-emitting region (EA).

[0202] For example, referring to FIGS. 8 and 9, the light-emitting region (EA) of the first subpixel (SP1) and the second subpixel (SP2) can overlap not only with the data line, which is the inner pattern (IP), but also with the common voltage line (DVL). Accordingly, for the first subpixel (SP1) and the second subpixel (SP2), the outer pattern (OP) constitutes the common voltage line (DVL).

[0203] Additionally, referring to FIGS. 10 and 11, the light-emitting regions (EA) of the third subpixel (SP3) and the fourth subpixel (SP4) may be positioned to overlap further with the common voltage line (DVL) outside the common voltage line (DVL), which is the inner pattern (IP). In this case, for the third subpixel (SP3) and the fourth subpixel (SP4), the common voltage line (DVL) located outside the inner pattern (IP) corresponds to the outer pattern (OP).

[0204] Referring to FIGS. 8 to 11, the outer pattern (OP) is arranged symmetrically with respect to the central axis (CA). The distance from the central axis (CA) to the inner boundary of the outer pattern (OP) is equal to that of the first to fourth subpixels (SP1 to SP4).

[0205] That is, the distance (ΔH3) between the inner boundaries of the outer pattern (OP) is equal to each other in the first to fourth subpixels (SP1~SP4).

[0206] However, the first to fourth subpixels (SP1 to SP4) may differ in size and shape. Accordingly, the distance (ΔH4) between the outer boundaries of the outer pattern (OP) may not be the same for the first to fourth subpixels (SP1 to SP4).

[0207] The first subpixel (SP1) may be a blue subpixel (B), the second subpixel (SP2) may be a red subpixel (R), the third subpixel (SP3) may be a first green subpixel (G1), and the fourth subpixel (SP4) may be a second green subpixel (G2), but is not limited thereto.

[0208] As described above, the distance between inner patterns (IPs) can be the same for each subpixel. Accordingly, the color viewing angle deviation caused by the second source-drain electrode material pattern (SD2) can be minimized.

[0209] In addition, the distance between the inner boundaries of the outer patterns (OP) for each subpixel can be the same. Accordingly, the color viewing angle deviation caused by the first source-drain electrode material pattern (SD1) can be minimized.

[0210] FIG. 12 is a diagram showing that in a display device according to embodiments of the present specification, at least a portion of the second source-drain electrode material pattern (SD2) is overlapped with respect to the central axis (CA).

[0211] FIG. 12 briefly illustrates only the second source-drain electrode material pattern (SD2) and the light-emitting region.

[0212] Referring to FIG. 12, the first subpixel (SP1) and the second subpixel (SP2) are separated by a first data line (DL1) and a second data line (DL2) by a first distance (ΔH1). These first data line (DL1) and the second data line (DL2) are arranged symmetrically with respect to the central axis (CA) so that at least a portion of them can overlap.

[0213] Additionally, the first subpixel (SP1) and the second subpixel (SP2) may be located at the same distance from each other with respect to the center axis (CA) with respect to the common voltage line (DVL), and accordingly, at least a portion of the common voltage line (DVL) may overlap with respect to the center axis (CA).

[0214] The center axis (CA) of the first subpixel (SP1) and the center axis of the second subpixel (SP2) can coincide.

[0215] Referring to FIG. 12, the third subpixel (SP3) and the fourth subpixel (SP4) are spaced apart by a first distance (ΔH1) in the region where the common voltage line (DVL) overlaps with the light-emitting region (EA). The common voltage line (DVL) spaced apart from each other may overlap at least a portion of each other with respect to the central axis (CA).

[0216] The center axis (CA) of the third subpixel (SP3) and the fourth subpixel (SP4) can coincide.

[0217] The third subpixel (SP3) and the fourth subpixel (SP4) may include a slit configured to position a common voltage line (DVL) spaced apart from each other in an area overlapping with the light-emitting region. The center axis (CA) of the third subpixel (SP3) and the fourth subpixel (SP4) may pass through the center of the slit in a first direction.

[0218] FIGS. 13a to 13d are drawings illustrating various embodiments of an inner pattern (IP) as examples.

[0219] Referring to FIG. 13a, the inner pattern (IP) may include branched branches. For example, when a data line and a common voltage line are extended and arranged in a first direction, the inner pattern (IP) may include branches that are branched and extended in a second direction different from the first direction in an area overlapping with the light-emitting region of a subpixel. The branches are arranged symmetrically with respect to the central axis (CA).

[0220] When the inner pattern (IP) includes a branch, the distance between the outer boundaries of the branch is defined as the fifth distance (ΔH5). The fifth distance (ΔH5) may vary depending on the subpixel, but it may be preferable for the branch to be formed extending to the boundary of the light-emitting region.

[0221] Accordingly, the inner pattern (IP) can overlap with the light-emitting region and a wider region. According to this, even when the outer pattern (OP) is not placed, the inner pattern (IP) alone can partially compensate for the step difference caused by the first source-drain electrode material pattern (SD1).

[0222] Referring to FIG. 13b, the inner pattern (IP) according to the embodiments of the present specification may include two or more branches. Accordingly, the inner pattern (IP) may overlap with the light-emitting region and a wider region. Accordingly, even when the outer pattern (OP) is not placed, the inner pattern (IP) alone can partially compensate for the step difference caused by the first source-drain electrode material pattern (SD1).

[0223] Referring to FIG. 13c and FIG. 13d, the inner pattern (IP) can be routed and positioned in an area overlapping with the light-emitting region so that it can be placed at the boundary of the light-emitting region.

[0224] When routing in an area where the inner pattern (IP) overlaps with the light-emitting area, the maximum distance of the inner boundary in the inner pattern is the “modified first distance (ΔH1')”, and the maximum distance of the outer area in the inner pattern is the “modified second distance (ΔH2')”. The minimum distance of the inner boundary in the inner pattern is the first distance (ΔH1), and the minimum distance of the outer boundary in the inner pattern is the second distance (ΔH2).

[0225] According to this, even when the outer pattern (OP) is not placed, the step difference of the second planarization layer (PLN2) caused by the first source-drain electrode material pattern (SD1) can be partially compensated by the inner pattern (IP) alone.

[0226] The embodiments of the present specification described above are briefly explained as follows.

[0227] Embodiments of the present specification may provide a display device (100) comprising a substrate (SUB), a transistor (e.g., DRT, etc.) located on the substrate (SUB) and including a first source-drain electrode material pattern (SD1), an active layer (ACT), and a gate electrode (GATE) located overlapping the active layer (ACT), a first planarization layer (PLN1) located on the first source-drain electrode material pattern (SD1) of the transistor, a metal pattern (e.g., SD2) located on the first planarization layer (PLN1) and electrically connected to the transistor, a second planarization layer (PLN2) covering the metal pattern (SD2), and a bank (BANK) located on the second planarization layer (PLN2) and including two or more openings of different sizes, wherein in the region below the two or more openings of different sizes, the metal pattern (SD2) is spaced apart at equal intervals.

[0228] Embodiments of the present specification may provide a display device (100) in which the metal pattern (SD2) includes an inner pattern (IP), the inner pattern (IP) includes an inner boundary close to the center of the opening and an outer boundary far from the center of the opening, and the inner boundary of the inner pattern (IP) and the outer boundary of the inner pattern (IP) are positioned overlapping with at least one opening.

[0229] The embodiments of the present specification can provide a display device (100) in which the spacing (ΔH1) between the inner boundaries of the inner pattern (IP) in the area below the openings is the same.

[0230] The embodiments of the present specification may provide a display device (100) in which the gap (ΔH2) between the outer boundaries of the inner pattern (IP) in the area below the openings is the same.

[0231] Embodiments of the present specification may provide a display device (100) in which the metal pattern (SD2) extends in a first direction in the area below the openings, and the inner pattern (IP) includes a branch formed by extending the outer boundary of the inner pattern (IP) in a second direction different from the first direction.

[0232] Embodiments of the present specification may provide a display device (100) in which one of two or more openings of different sizes is an opening of a first color subpixel (e.g., a blue subpixel (B)), and another of two or more openings of different sizes is an opening of a second color subpixel (e.g., a green subpixel (G1, G2)) different from the first color, and the opening of the first color subpixel is positioned overlapping with two different data lines (DL1, DL2), and the opening of the second color subpixel is positioned overlapping with the driving voltage line (DVL).

[0233] Embodiments of the present specification may provide a display device (100) in which the driving voltage line (DVL) includes a slit, and at least a portion of the slit is positioned overlapping with the opening of the second color subpixel.

[0234] The embodiments of the present specification may provide a display device (100) in which the slit is positioned overlapping with the center of the opening.

[0235] The embodiments of the present specification may provide a display device (100) in which the opening of the first color subpixel is positioned to overlap with at least a portion of the driving voltage line (DVL).

[0236] The embodiments of the present specification may provide a display device (100) comprising an inner pattern (IP) having the same thickness as the data lines (DL1, DL2) which are positioned overlapping the opening of the second color subpixel, wherein the metal pattern (SD2) positioned overlapping the opening of the second color subpixel.

[0237] Embodiments of the present specification may provide a display device (100) comprising a metal pattern (SD2) that includes an outer pattern (OP) positioned outside the inner pattern (IP) in overlap with the opening of the first color subpixel or the opening of the second color subpixel.

[0238] The embodiments of the present specification may provide a display device (100) in which the outer pattern (OP) constitutes the driving voltage line (DVL).

[0239] The embodiments of the present specification may provide a display device (100) in which the metal pattern (SD2) is a second source-drain electrode material pattern (SD2) of the same material as the first source-drain electrode material pattern.

[0240] The embodiments of the present specification may provide a display device (100) in which the second flattening layer (PLN2) includes a step corresponding to the metal pattern (SD2) in an area overlapping with the openings.

[0241] Embodiments of the present specification may further include a light-emitting element (ED) comprising a first electrode (e.g., anode electrode (AE)) connected to the metal pattern (SD2) and the contact hole (CNT), a light-emitting layer (EL), and a second electrode (e.g., cathode electrode (CE)) which is a common electrode, and the contact hole (CNT) is located outside the openings, thereby providing a display device (100).

[0242] The foregoing description is merely an illustrative explanation of the technical concept of the present disclosure, and those skilled in the art to which the present disclosure pertains may make various modifications and variations within the scope of the essential characteristics of the present disclosure. Furthermore, the embodiments disclosed in the present disclosure are intended to explain, not limit, the technical concept of the present disclosure, and thus the scope of the technical concept of the present disclosure is not limited by these embodiments. The scope of protection of the present disclosure shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present disclosure. Explanation of the symbols

[0243] 100: Display device 110: Display panel 120: Data driving circuit 130: Gate driving circuit 140: Display controller 150: Host system 160: Touch driving circuit 170: Touch controller

Claims

Claim 1 A display device comprising: a substrate; a transistor located on the substrate and including a first source-drain electrode material pattern, an active layer, and a gate electrode located in overlap with the active layer; a first planarization layer located on the first source-drain electrode material pattern of the transistor; a metal pattern located on the first planarization layer and electrically connected to the transistor; a second planarization layer covering the metal pattern; and a bank located on the second planarization layer and including two or more openings of different sizes, wherein in the region below the two or more openings of different sizes, the metal pattern is spaced apart at equal intervals, and the metal pattern located in overlap with one of the two or more openings of different sizes forms a data line to which a data voltage for image display is applied, and the metal pattern located in overlap with another of the two or more openings of different sizes forms a driving voltage line that transmits a high potential driving voltage supplied to the first source-drain electrode material pattern. Claim 2 A display device according to claim 1, wherein the metal pattern includes an inner pattern, the inner pattern includes an inner boundary close to the center of the opening and an outer boundary far from the center of the opening, and the inner boundary of the inner pattern and the outer boundary of the inner pattern are positioned overlapping with at least one opening. Claim 3 In paragraph 2, the spacing between the inner boundaries of the inner pattern in the area below the openings is the same as the display device. Claim 4 In paragraph 2, the spacing between the outer boundaries of the inner pattern in the area below the openings is the same as the display device. Claim 5 A display device according to paragraph 2, wherein the metal pattern extends in a first direction in the area below the openings, and the inner pattern includes a branch formed by the outer boundary of the inner pattern extending in a second direction different from the first direction. Claim 6 delete Claim 7 A display device according to claim 1, wherein one of the two or more openings of different sizes is an opening of a first color subpixel, and the other of the two or more openings of different sizes is an opening of a second color subpixel different from the first color, and the opening of the first color subpixel is positioned overlapping with two different data lines, and the opening of the second color subpixel is positioned overlapping with the driving voltage line. Claim 8 A display device according to claim 7, wherein the driving voltage line includes a slit, and at least a portion of the slit is positioned overlapping with the opening of the second color subpixel. Claim 9 In paragraph 8, the slit is a display device positioned overlapping the center of the opening. Claim 10 A display device according to claim 7, wherein the opening of the first color subpixel is positioned to overlap with at least a portion of the driving voltage line. Claim 11 In claim 7, the metal pattern positioned overlapping with the opening of the second color subpixel comprises an inner pattern having the same thickness as the data lines positioned overlapping with the opening of the first color subpixel. Claim 12 A display device according to claim 11, wherein the metal pattern comprises an outer pattern positioned outside the inner pattern, overlapping with the opening of the first color subpixel or the opening of the second color subpixel. Claim 13 In Clause 12, the outer pattern is a display device constituting the driving voltage line. Claim 14 A display device according to claim 1, wherein the metal pattern is a second source-drain electrode material pattern of the same material as the first source-drain electrode material pattern. Claim 15 A display device comprising: a substrate; a transistor located on the substrate and including a first source-drain electrode material pattern, an active layer, and a gate electrode located overlapping the active layer; a first planarization layer located on the first source-drain electrode material pattern of the transistor; a metal pattern located on the first planarization layer and electrically connected to the transistor; a second planarization layer covering the metal pattern; and a bank located on the second planarization layer and including two or more openings of different sizes, wherein in the region below the two or more openings of different sizes, the metal pattern is spaced apart at equal intervals, and in the region overlapping the openings, the second planarization layer includes a step corresponding to the metal pattern. Claim 16 A display device according to claim 15, further comprising a light-emitting element including a first electrode connected to the metal pattern and a contact hole, a light-emitting layer, and a second electrode which is a common electrode, wherein the contact hole is located outside the openings.

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