Semiconductor memory device

Abstract

A semiconductor memory device comprises a device isolation pattern that defines a first active portion and a second active portion spaced apart from each other and disposed on a substrate, wherein the center of the first active portion is adjacent to the end of the second active portion, a first bit line crossing the center of the first active portion, a second bit line crossing the center of the second active portion, a bit line contact interposed between the first bit line and the center of the first active portion, and a storage node pad disposed on the end of the second active portion. The level of the lower surface of the first bit line is lower than the level of the lower surface of the second bit line.

Description

Technology Field

[0001] The present invention relates to a semiconductor memory device. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are receiving significant attention as important elements in the electronics industry. However, as the electronics industry develops rapidly, the trend toward high integration of semiconductor devices is intensifying. To achieve high integration, the linewidths of semiconductor device patterns are gradually decreasing. However, the recent miniaturization of patterns requires new lithography technologies and / or high-cost lithography technologies, making the high integration of semiconductor devices increasingly difficult. Consequently, much research on new integration technologies is currently being conducted. (Patent Document 1) US 9953985 B2 (Patent Document 2) US 11056494 B2 The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor memory device with improved reliability. Another problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor memory device with improved reliability. means of solving the problem

[0004] A semiconductor memory device according to embodiments of the present invention comprises a device isolation pattern that defines a first active part and a second active part spaced apart from each other and disposed on a substrate, wherein the center of the first active part is adjacent to the end of the second active part, a first bit line crossing the center of the first active part, a second bit line crossing the center of the second active part, a bit line contact interposed between the first bit line and the center of the first active part, and a storage node pad disposed on the end of the second active part, wherein the level of the lower surface of the first bit line may be lower than the level of the lower surface of the second bit line.

[0005] A semiconductor memory device according to some embodiments comprises a device isolation pattern that defines a first active part and a second active part spaced apart from each other and disposed on a substrate, wherein the center of the first active part is adjacent to the end of the second active part, a first bit line crossing the center of the first active part, a second bit line crossing the center of the second active part, a bit line contact interposed between the first bit line and the center of the first active part, and a storage node pad disposed on the end of the second active part, wherein the first bit line and the second bit line may be located at different heights with respect to the upper surface of the substrate.

[0006] A semiconductor memory device according to some embodiments comprises a substrate including a cell array region and a boundary region, a device isolation pattern defining a first active region and a second active region and a third active region spaced apart from each other and disposed on the cell array region, wherein the center of the first active region is adjacent to the end of the second active region and the third active region is disposed adjacent to the boundary region, a first bit line crossing the center of the first active region, a second bit line crossing the center of the second active region, a third bit line crossing the center of the third active region, a bit line contact interposed between the first bit line and the center of the first active region, a first storage node pad disposed on the end of the second active region, and a second storage node pad disposed on the end of the third active region, wherein the thickness of the second storage node pad is greater than the thickness of the first storage node pad and the level of the lower surface of the first bit line may be lower than the level of the lower surface of the second bit line. Effects of the invention

[0007] According to the concept of the present invention, as adjacent first bitlines and second bitlines are positioned at different heights, the portion of the storage node contact interposed between the first bitline and the second bitline that overlaps simultaneously with the first bitline and the second bitline can be reduced. As a result, parasitic capacitance between the first bitline and the second bitline can be reduced.

[0008] The method for manufacturing a semiconductor memory device according to the present invention uses a silicon nitride mask pattern as an etching mask for forming contact holes that expose impurity regions. Even when a remainder of the silicon nitride mask pattern exists in the boundary region after the etching process, it is non-conductive, thereby increasing the reliability of the device. In addition, over-etching can be prevented, thereby protecting the interlayer insulating film. Brief explanation of the drawing

[0009] FIG. 1 is a schematic layout showing a semiconductor memory device according to embodiments of the present invention. FIG. 2 is a plan view showing a semiconductor memory device according to semiconductor embodiments of the present invention. FIG. 3a is a cross-sectional view taken along the line A-A' of FIG. 2 according to embodiments of the present invention. FIG. 3b is a cross-sectional view of FIG. 2 taken along the line B-B' according to embodiments of the present invention. Figure 4a is an enlarged view of aa in Figure 3a. Fig. 4b is an enlarged view of bb in Fig. 3a. Figure 5 is an enlarged view corresponding to aa in Figure 3. FIGS. 6a to 6k and FIGS. 6m to 6q are cross-sectional views sequentially illustrating the process of manufacturing a semiconductor memory device of FIG. 3a according to embodiments of the present invention. Fig. 6l is an enlarged view of cc of Fig. 6k. FIG. 7 is a cross-sectional view illustrating the process of manufacturing a semiconductor memory device according to some embodiments. FIGS. 8a to 8c are cross-sectional views illustrating the process of manufacturing a semiconductor memory device according to some embodiments. FIGS. 9a to 9c are cross-sectional views illustrating the process of manufacturing a semiconductor memory device according to some embodiments. Specific details for implementing the invention

[0010] Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings.

[0011] FIG. 1 is a layout schematically showing a semiconductor memory device according to embodiments of the present invention. FIG. 2 is a plan view showing a semiconductor memory device according to semiconductor embodiments of the present invention. FIG. 3a is a cross-sectional view taken along line A-A' of FIG. 2 according to embodiments of the present invention. FIG. 3b is a cross-sectional view taken along line B-B' of FIG. 2 according to embodiments of the present invention.

[0012] Referring to FIG. 1, in some embodiments, the semiconductor memory device may be a DRAM memory device. Memory cell circuits, such as a memory integrated circuit, may be provided in the cell array region (CR). Peripheral circuits, such as a transistor, may be provided in the peripheral circuit region (PR). For example, the peripheral circuits may include sense amplifier circuits and sub-wordline driver circuits. The peripheral circuits may further include power and ground driver circuits for driving the sense amplifier.

[0013] Referring to FIGS. 2, FIGS. 3a, and FIGS. 3b, a substrate (301) may be provided. The substrate (301) may include a cell array region (CR), a peripheral circuit region (PR), and a boundary region (IR) between them. A region separation pattern (303) may be disposed on the boundary region (IR) to separate the peripheral circuit region (PR) from the cell array region (CR). A first diffusion barrier (112) and a second diffusion barrier (114) may be disposed on the region separation pattern (303).

[0014] The substrate (301) may include a semiconductor material. For example, the substrate (301) may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Device isolation patterns (302) may be disposed on the substrate (301) in the cell array region (CR) to define active parts (ACTs). Each of the active parts (ACTs) may have an isolated shape. Each of the active parts (ACTs) may be in the shape of a bar elongated in a first direction (X1) in a planar view. In a planar view, each of the active parts (ACTs) may correspond to parts of the substrate (301) surrounded by the device isolation patterns (302). The active parts (ACTs) may be arranged parallel to each other in the first direction (X1), and the ends of the active parts (ACTs) may be arranged adjacent to the centers of other adjacent active parts (ACTs). Each of the device isolation patterns (302) may include a single film or multiple film structure of at least one material, for example, silicon oxide, silicon oxynitride, and silicon nitride.

[0015] Word lines (WL) may cross the active parts (ACT). The word lines (WL) may be placed within grooves formed in the device isolation patterns (302) and the active parts (ACT). The word lines (WL) may be parallel to a second direction (X2) that intersects the first direction (X1). The word lines (WL) may be formed of a conductive material. A gate dielectric film (307) may be placed between each word line (WL) and the inner surface of each groove. Although not illustrated, the bottom of the grooves may be relatively deep within the device isolation patterns (302) and relatively shallow within the active parts (ACT). The gate dielectric film (307) may comprise at least one of a thermal oxide, silicon oxide, silicon oxynitride, and a high dielectric material. The lower surface of the word lines (WL) may be curved.

[0016] A first impurity region (3d) may be disposed within each of the active parts (ACT) between a pair of word lines (WL), and a pair of second impurity regions (3b) may be disposed within each of the two edge regions of each of the active parts (ACT). The first impurity region (3d) may correspond to a common source region, and the second impurity region (312b) may correspond to a drain region. Each of the word lines (WL) and the first and second impurity regions (3b, 3d) adjacent thereto may form a transistor. By placing the word lines (WL) within the grooves, the channel length of the channel region below the word lines (WL) can be increased within a limited planar area.

[0017] The upper surface of the word lines (WL) may be lower than the upper surface of the active portions (ACT). A word line capping pattern (310) may be placed on each of the word lines (WL). The word line capping patterns (310) may have a line shape extending along the longitudinal direction of the word lines (WL) and may cover the entire upper surface of the word lines (WL). The word line capping patterns (310) may fill the grooves on the word lines (WL). The word line capping pattern (310) may be formed, for example, from a silicon nitride film. A gate dielectric film (307) may extend between the word line capping pattern (310) and the device isolation pattern (302), and between the word line capping pattern (310) and the substrate (301).

[0018] Bit lines (BL) may be disposed on the substrate (301). The bit lines (BL) may cross the word line capping patterns (310) and word lines (WL). As disclosed in FIG. 2a, the bit lines (BL) may be parallel to a third direction (X3) that intersects the first and second directions (X1, X2). The bit lines (BL) may include a bit line diffusion prevention pattern (331) and a bit line wiring pattern (333) stacked in turn. The bit line diffusion prevention pattern (331) may include at least one of titanium, titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum, tantalum nitride, and tungsten nitride. The bit line wiring pattern (333) may include a metal such as, for example, tungsten, aluminum, copper, ruthenium, and iridium. A bitline capping pattern (337) may be disposed on each of the bitlines (BL). The bitline capping patterns (337) may be formed of an insulating material such as a silicon nitride film.

[0019] A storage node pad (XP) may be placed on the active part (ACT) doped with the second impurity region (3b). The storage node pad (XP) may include, for example, polysilicon doped with impurities.

[0020] A pad separation pattern (38) is interposed between the storage node pads (XP). For example, the pad separation pattern (38) may include silicon nitride. A plurality of interlayer insulating films (420) may be provided on the storage node pads (XP) and the pad separation pattern (38). The interlayer insulating films (420) may include first and second interlayer insulating films (407, 409) stacked in sequence. The sidewalls of the second interlayer insulating films (409) may be aligned with the sidewalls of the bit line (BL). The first interlayer insulating film (407) may have a wider width than the second interlayer insulating film (409). The sidewalls of the first interlayer insulating film (407) may be aligned with the sidewalls of the first spacer (323). The first and second interlayer insulating films (407, 409) may each include an insulating material having etch selectivity with respect to each other. The first and second interlayer insulating films (407, 409) may each include different materials. For example, the first interlayer insulating film (407) may include silicon oxide. The second interlayer insulating film (409) may include silicon nitride.

[0021] Bitline contacts (DC) may be disposed within a recess region (R1) intersecting the bitlines (BL). The bitline contacts (DC) may comprise polysilicon. The bitline contacts (DC) may comprise polysilicon that is doped with impurities or not doped. The bitline contacts (DC) may electrically connect the first impurity region (3b) and the bitline (BL). A lower buried insulation pattern (341) may be disposed within the recess region where the bitline contacts (DC) are not disposed. The lower buried insulation pattern (341) may comprise a silicon nitride film or a silicon oxynitride film.

[0022] The sidewalls of the bitline (BL) and the bitline capping pattern (337) may be covered by a bitline spacer (SP). The bitline spacer (SP) may include a spacer liner (321), a first spacer (323), and a second spacer (325). The spacer liner (321), the first spacer (323), and the second spacer (325) may each independently include one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxide carbonate (SiOC). For example, the spacer liner (321) and the first spacer (323) may each include the same material, for example, silicon oxide. Alternatively, the spacer liner (321) may have a material having etch selectivity with respect to the first spacer (323), in which case the spacer liner (321) may include silicon nitride and the first spacer (323) may include silicon oxide. The second spacer (325) may include an insulating material having etch selectivity with respect to the first spacer (323), for example, silicon nitride. Preferably, the spacer liner (321) may include silicon oxide. The spacer liner (321) may extend to conformally cover the sidewalls of the bitline contact (DC) and the sidewalls of the storage node pad (XP), corresponding to the inner walls of the recess area and the bottom surface. A buried insulating pattern (341) may be positioned on the spacer liner (321) and may fill the recess area (R1). The bottom of the second spacer (325) may be lower than the bottom of the first spacer (323).

[0023] A storage node contact (BC) is interposed between adjacent bit lines (BL), for example, between the first bit line (BL(1)) and the second bit line (BL(2)) of FIG. 3a and FIG. 4a. The storage node contact (BC) can be placed within a storage node contact hole (BCH) between adjacent bit lines (BL).

[0024] Although not illustrated, multiple node separation patterns may be disposed between adjacent bitline spacers (SP). The node separation patterns may be arranged in a single column between the bitline spacers (SP) and spaced apart from each other. The node separation patterns may overlap with the wordlines (WL). Storage node contact holes (BCH) may be defined between the bitline spacers (SP) and between the node separation patterns. The node separation patterns may comprise an insulating material, preferably silicon oxide.

[0025] The storage node contact (BC) may include a contact metal pattern (313) and a contact diffusion prevention pattern (311) covering the sidewalls and bottom surface thereof. The contact diffusion prevention pattern (311) may conformally cover the sidewalls and bottom surface of the storage node contact hole (BCH) (with a constant thickness regardless of location). Both the contact metal pattern (313) and the contact diffusion prevention pattern (311) may include metal. The contact diffusion prevention pattern (311) may include, for example, at least one of titanium, titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum, tantalum nitride, and tungsten nitride. The contact metal pattern (313) may include, for example, a metal such as tungsten, aluminum, or copper. The bottom surface of the contact diffusion prevention pattern (311) may be rounded. The bottom surface of the contact metal pattern (313) may also be rounded.

[0026] A contact ohmic layer (309) may be interposed between the storage node contact (BC) and the storage node pad (XP). The contact ohmic layer (309) may include a metal silicide, such as cobalt silicide, for example. The contact ohmic layer (309) may have a rounded cross-section. Alternatively, the lower surface of the contact ohmic layer (309) may be rounded. The contact surface (or upper surface) of the storage node pad (XP) in contact with the contact ohmic layer (309) may also be rounded.

[0027] Landing pads (LP) may be located on each of the storage node contacts (BC). From a planar perspective, the landing pads (LP) may have a shape of islands spaced apart from each other. Six landing pads (LP) surrounding one landing pad (LP) may form a regular hexagon. The landing pads (LP) may be arranged to form a honeycomb shape.

[0028] Data storage patterns (DSPs) may be disposed on each of the above landing pads (LPs). The data storage patterns (DSPs) may be capacitors comprising a lower electrode, a dielectric film, and an upper electrode. In this case, the semiconductor memory device may be a Dynamic Random-Access Memory (DRAM). Alternatively, the data storage patterns (DSPs) may include a magnetic tunnel junction pattern. In this case, the semiconductor memory device may be a Magnetic Random Access Memory (MRAM). Alternatively, the data storage patterns (DSPs) may include a phase change material or a variable resistor material. In this case, the semiconductor memory device may be a Phase-Change Random Access Memory (PRAM) or a Resistive RAM (ReRAM).

[0029] In the cross-section B-B' of FIG. 3b, a contact insulation pattern (DCL) may be interposed between the bitline contact (DC) and the pad separation pattern (38) below the bitline (BL). The contact insulation pattern (DCL) may include a first contact insulation pattern (403) and a second contact insulation pattern (405). The first contact insulation pattern (403) is in contact with the sidewall of the pad separation pattern (38), which is the sidewall of the contact hole (DCH), and the sidewall of the interlayer insulation film (420). The second contact insulation pattern (405) is in contact with the sidewall of the bitline contact (DC). The first contact insulation pattern (403) may cover the lower surface of the second contact insulation pattern (405). The first contact insulation pattern (403) and the second contact insulation pattern (405) may contain different materials. For example, the first contact insulation pattern (403) may include silicon nitride, and the second contact insulation pattern (405) may include silicon oxide.

[0030] FIG. 4a is an enlarged view of aa in FIG. 3a. Referring to FIG. 3a and FIG. 4a, a first active part (ACT1), a second active part (ACT2), and a third active part (ACT3) are arranged in a row along a second direction (X2). A first impurity region (3d) is formed in the first active part. A bitline contact (DC) can cover the upper surface of the first active part (ACT1). A second impurity region (3b) is formed in the second active part (ACT2). A first impurity region (3d) is formed in the third active part (ACT3). A first storage node pad (XP1) can cover the upper surface of the second active part (ACT2) and the device isolation pattern (302). A second storage node pad (XP2) can cover the upper surface of the third active part (ACT3) and the device isolation pattern (302). A pad separation pattern (38) is interposed between adjacent storage node pads (XP1, XP2). The lower portion of the pad separation pattern (38) may be lower than the lower portion of the storage node pads (XP1, XP2). According to some embodiments, the upper portion of the pad separation pattern (38) may be coplanar with the upper portion of the storage node pads (XP1, XP2). In FIG. 4a, the first bit line (BL(1)) may be located on a bit line contact (DC) covering the first impurity region (3d) of the first active portion (ACT1). The second bit line (BL2) adjacent to the first bit line (BL1) is located on the pad separation pattern (38) and may be perpendicularly overlapped with the separation pattern (38). A storage node contact (BC) is interposed between adjacent bit lines (BL), for example, between the first bit line (BL(1)) and the second bit line (BL(2)) of FIG. 4a. The storage node contact (BC) can be placed within the storage node contact hole (BCH) between adjacent bit lines (BL).

[0031] The level (LV1) of the lower surface of the first bit line (BL1) may be lower than the level (LV2) of the lower surface of the second bit line (BL2).

[0032] The first bitline (BL1) may include a bitline first diffusion prevention pattern (331a) and a second bitline wiring pattern (333a) stacked in sequence. The second bitline may include a bitline second diffusion prevention pattern (331b) and a second bitline wiring pattern (333b) stacked in sequence.

[0033] The first diffusion prevention pattern (331a) and the second diffusion prevention pattern (331b) may comprise the same first metal material, and the first bitline wiring pattern (333a) and the second bitline wiring pattern (333b) may comprise the same second metal material. The second diffusion prevention pattern (331b) may come into contact with the uppermost portion of the interlayer insulating film (420). For example, the second diffusion prevention pattern (331b) may come into contact with the second interlayer insulating film (409).

[0034] The level of the lower surface of the first diffusion prevention pattern (331a) may be lower than the level of the lower surface of the second diffusion prevention pattern (331b). The thickness of the first diffusion prevention pattern (331a) and the second diffusion prevention pattern (331b) may be substantially the same. The thickness of the first bitline wiring pattern (333a) and the thickness of the second bitline wiring pattern (333b) may be substantially the same. The level of the upper surface of the first bitline (BL1) may also be lower than the level of the upper surface of the second bitline (BL2).

[0035] As the first bit line (BL1) and the second bit line (BL2) are positioned at different heights, the portion of the storage node contact (BC) that overlaps simultaneously with the first bit line (BL1) and the second bit line (BL2) along the second direction (X2) can be reduced. As a result, the parasitic capacitance between the first bit line (BL1) and the second bit line (BL2) can be reduced.

[0036] FIG. 4b is an enlarged view of bb in FIG. 3a. Referring to FIG. 3a and FIG. 4b, a storage node pad (XP) on the boundary region (IR) may have an inclined upper surface. A first and second diffusion barrier film (112, 114) may be located below the storage node pad (XP). The thickness of the storage node pad (XP) may be greater than the thickness of an adjacent storage node pad (XP). The diffusion barrier pattern (331) of the bit line on the boundary region (IR) may be in contact with the second interlayer insulating film (409). FIG. 5 is an enlarged view corresponding to aa in FIG. 3a.

[0037] Referring to FIG. 5, the first bit line (BL1) may further include a first bit line polysilicon pattern (335a) doped with impurities below the first diffusion prevention pattern (331a). The second bit line (BL2) may further include a second bit line polysilicon pattern (335b) doped with impurities below the second diffusion prevention pattern (331b). The first bit line polysilicon pattern (335a) may be observed integrally with the bit line contact (DC). The second bit line polysilicon pattern (335b) may be interposed between the second diffusion prevention pattern (331b) and the second interlayer insulating film (409). As previously described, the level of the lower surface of the first bit line (BL1) may be lower than the level of the lower surface of the second bit line (BL2). The level (LV1) of the lower surface of the first diffusion prevention pattern (331a) may be lower than the level (LV2) of the lower surface of the second diffusion prevention pattern (332a).

[0039] FIGS. 6a to 6k and FIGS. 6m to 6q are cross-sectional views sequentially illustrating the process of manufacturing the semiconductor memory device of FIG. 3A.

[0040] Referring to FIG. 6a, device isolation patterns (302) and region isolation patterns (303) are formed on a substrate (301) including a cell array region (CR), a peripheral circuit region (PR), and a boundary region (IR). This allows active regions (ACT) to be defined in the cell array region (CAR). Specifically, device isolation trenches and region isolation trenches can be formed on the substrate (301), and device isolation patterns (302) can fill the device isolation trenches, and region isolation patterns (303) can fill the region isolation trenches.

[0041] Grooves can be formed by patterning the active parts (ACT) and device isolation patterns (302). Word lines (WL) can be formed in each of the grooves (see FIG. 3b). A pair of the word lines (WL) can cross each of the active parts (ACT). Before forming the word lines (WL), a gate dielectric film (307) can be formed on the inner surface of the grooves. The upper surfaces of the word lines (WL) can be recessed so as to be lower than the upper surfaces of the active parts (ACT). An insulating film, such as silicon nitride, can be laminated on the substrate (301) to fill the grooves and etched to form a word line capping pattern (310) on each of the word lines (WL). The wordline capping patterns (310) and the device isolation pattern (302) can be used as masks to inject impurities into the active parts (ACT) to form first and second impurity regions (3d, 3b). Although not illustrated, when forming the first and second impurity regions (3d, 3b), at least the peripheral circuit region (PR) can be covered by a mask pattern (not illustrated). This prevents impurities from being doped into the peripheral circuit region (PR).

[0042] A first diffusion barrier layer (112) and a second diffusion barrier layer (114) are formed sequentially to cover the boundary region (IR). Subsequently, a conductive film can be formed on the cell array region (CR) and the peripheral circuit region (PR) of the substrate (301). The conductive film may be, for example, a polysilicon film doped with impurities. The conductive film may be etched to form conductive patterns (20p), and gap regions may be formed between them. The gap regions may partially expose the device isolation pattern (302), region isolation pattern (303), active parts (ACT), and gate dielectric film. A pad isolation layer may be stacked to fill the gap regions, and an isolation pattern (38) may be formed within the gap regions by etching back. The pad isolation pattern (38) may have a planar grid shape.

[0043] Referring to FIG. 6b, interlayer insulating films (420) are formed on the conduction patterns (20P) and the pad separation pattern (38). The interlayer insulating films (420) may include first to third interlayer insulating films (407, 409, 411) stacked in sequence. The first interlayer insulating film (407) may include, for example, silicon oxide, the second interlayer insulating film (409) may include, for example, silicon nitride, and the third interlayer insulating film (411) may include silicon oxide. Subsequently, a thick silicon nitride layer (430a) may be formed on the third interlayer insulating film (411). The thickness of the silicon nitride layer (430a) may be greater than the thickness of the interlayer insulating films (420).

[0045] Referring to FIG. 6c, an opening can be formed in the silicon nitride layer (430a) to form a silicon nitride mask pattern (430). Using the silicon nitride mask pattern (430) as an etching mask, the interlayer insulating films (420) and the pad separation pattern (38) on the first impurity region (3d) can be etched to form contact holes (DCH) that expose the first impurity region (3d). At this time, the conductive patterns (20p) adjacent to the pad separation pattern (38) can also be partially etched to form storage node pads (XP).

[0047] Referring to FIG. 6d, after a first contact insulating film and a sacrificial film are conformally and sequentially formed on the front surface of a substrate (301), an anisotropic etching process is performed on the first contact insulating film and the sacrificial film to form a first contact insulating pattern (405) and a sacrificial pattern (405) that sequentially cover the inner walls of the contact holes (DCH). The first contact insulating pattern (403) and the sacrificial pattern (405) may each be formed from a material having etch selectivity toward each other. For example, the first contact insulating pattern (403) may include silicon nitride, and the sacrificial pattern (404) may include silicon oxide. Subsequently, a polysilicon spacer (334a) may be formed on the sacrificial pattern (404). Specifically, after forming a polysilicon liner, the polysilicon spacer (334a) may be formed through an etching process or the like.

[0049] Referring to FIG. 6e, a polysilicon film (333L) can be formed on the front surface of the substrate (301). The polysilicon film (333L) may be doped with impurities. The polysilicon film (333L) can fill the contact hole (DCH).

[0051] Referring to FIG. 6f, at least a portion of the polysilicon film (333L) can be removed using an etch-back process. The etching process can be performed first until the silicon nitride mask pattern (430) on the peripheral region (PR) is exposed, and second until the silicon nitride mask pattern (430) on the cell array region (CR) is exposed. Checking whether the silicon nitride mask pattern (430) is exposed can be done by an End Point Detection (EPD) process. Even when the silicon nitride mask pattern (430) on the cell array region (CR) is exposed, the polysilicon film (333L) may remain on the boundary region (IR). Through the etching process, the polysilicon film (333L) may form a polysilicon pattern (333P) that fills the contact hole (DCH) but does not extend onto the silicon nitride mask pattern (430). The etching process may be a selective etching process that selectively etches polysilicon material.

[0053] Referring to FIG. 6g, additional etching may be performed on the polysilicon pattern (333P). In this process, any remaining polysilicon film (333L) on the boundary region (IR) may be completely removed. The etching process may be a selective etching process that selectively etches the polysilicon material. According to some embodiments, the silicon nitride mask pattern (430) may also be partially etched in the etching process, so that its thickness may be slightly reduced. By adjusting the etching time, the level of the upper surface of the polysilicon pattern (333P) may be controlled. The level of the upper surface of the polysilicon pattern (333P) may be lower than the level of the upper surface of the silicon nitride mask pattern (430).

[0054] Referring to FIG. 6h, an oxide film (412) can be formed by an oxidation process of the polysilicon pattern (333P). Referring to FIG. 6i, a selective etching process of the silicon nitride mask pattern (430) can be performed. The selective etching process can be performed using phosphoric acid (HF). The upper portion of the first contact insulation pattern (403) can also be partially removed during this process. According to some embodiments, the first contact insulation pattern (403) can be co-planed with the upper surface of the polysilicon pattern (333P).

[0055] Referring to FIG. 6j, the protruding portions of the third interlayer insulating film (411), oxide film (412), and sacrificial pattern (405) can be removed using a cleaning solution or wet etching, etc.

[0056] Referring to FIG. 6k, a bitline diffusion barrier film (331L), a bitline wiring film (332L), and a bitline capping film (337L) can be formed sequentially. Referring together to FIG. 6l, the level of the upper surface of the polysilicon pattern (333P) can be lower than the level of the upper surface of the interlayer insulating film (420) by a selective etching process as described in FIG. 6g. Accordingly, the level (LV3) of the lower surface of the bitline diffusion barrier film (331L) that overlaps vertically with the polysilicon pattern (333P) can be lower than the level (LV4) of the lower surface of the bitline diffusion barrier film (331L) that overlaps vertically with the interlayer insulating film (420).

[0057] Referring to FIG. 6m, the bitline capping film (337L), the bitline wiring film (332L), and the bitline diffusion barrier film (331L) are sequentially etched to expose the upper surface of the second interlayer insulating film (409) while simultaneously forming the bitline capping pattern (337) and the bitline (BL). A polysilicon pattern (333P) that fills the contact hole (DCH) may be located below the bitline (BL). In this specification, the polysilicon pattern (333P) may also be referred to as a preliminary bitline contact (333P). Additionally, a first protective spacer (413) and a second protective spacer (415) may be formed to sequentially cover the sidewalls of the bitline capping pattern (337) and the bitline (BL). The first protection spacer (413) and the second protection spacer (415) may include a material having etch selectivity with respect to each other. The second protection spacer (415) may include the same material as the sacrificial pattern (405). The first protection spacer (413) may include a material having etch selectivity with respect to the bitline capping pattern (337) and the second interlayer insulating film (409). The first protection spacer (413) may include, for example, SiOC.

[0058] Referring to FIG. 6n, the sacrifice pattern (405) can be removed to form a void region (VD) between the preliminary bitline contact (333p) and the first contact insulation pattern (403). At this time, the second protective spacer (415), which is made of the same material as the sacrifice pattern (404), can also be removed. Thus, the sidewall of the first protective spacer (413) can be exposed. The first protective spacer (413) can protect the bitline capping pattern (337) and the bitline (BL).

[0060] Referring to FIGS. 6n and 6o, the first protective spacer (413) can be removed. By using the bitline capping pattern (337) as an etching mask, the preliminary bitline contact (333P) can be etched to form a bitline contact (DC). At this time, the etchant etching the preliminary bitline contact (333P) can easily penetrate into the contact hole (DCH) due to the void region (VD), so that the bitline contact (DC) can be formed with a uniform width regardless of height. The first contact insulation pattern (403) can protect the storage node pad (XP) from being etched. In the etching process, the first contact insulation pattern (403) covering the side of the storage node pad (XP) can be removed. The second interlayer insulating film (409) can also be etched by the etching process so that the upper surface of the first interlayer insulating film (407) is exposed.

[0062] Referring to FIG. 6p, a spacer liner (321) can be conformally formed on the front surface of a substrate (301). At this time, a buried insulating film (not shown) can be laminated on the spacer liner (321) to fill the contact hole (DCH). An etch-back process can be performed on the buried insulating film to form a buried insulating pattern (341) inside the contact hole (DCH). A first spacer film is conformally laminated on the front surface of the substrate (301) and etch-backed to form a first spacer (323) that covers the side wall of the spacer liner (321). At this time, the first interlayer insulating film (407) can also be etched so that the upper surface of the storage node pads (XP) is exposed. Additionally, the buried insulating pattern (341) and the spacer liner (321) can also be partially exposed. Then, a second spacer film is conformally laminated on the front surface of the substrate (301) and etched back to form a second spacer (325) that covers the side wall of the first spacer (323). This allows for the formation of a bitline spacer (SP). A sacrificial filling film that fills the space between bitlines (BL) is laminated on the front surface of the substrate (301) to form sacrificial filling patterns (42) between bitlines (BL) and between bitlines (BL) and gate patterns (GLP). The sacrificial filling patterns (42) can preferably be formed from silicon oxide, TEOS, or TOSZ. The sacrificial filling patterns (42) on the cell region (CR) can overlap with storage node pads (XP). A node separation film can be laminated on the front surface of the substrate (301) to fill the node separation holes and etched back to form node separation patterns. Node separation patterns may include, for example, silicon oxide.

[0064] Referring to FIG. 6q, the sacrificial buried patterns (42) interposed between the bit lines (BL) are removed to expose the buried insulation pattern (341) and the storage node pads (XP). An etching process is performed to partially etch the buried insulation pattern (341) and the storage node pads (XP) exposed between the bit lines (BL) to form a storage node contact hole (BCH) that exposes the storage node pads (XP).

[0065] Referring again to FIG. 3a, a contact diffusion barrier film (not shown) is conformally laminated on the front surface of the substrate (301), and a contact metal film (not shown) is formed thereon to fill the storage node contact hole (BCH). Both the contact diffusion barrier film and the contact metal film contain metal, and the formation process (deposition process) of these is carried out at a lower temperature (e.g., several hundred degrees, more specifically at a temperature of 300 to 400 degrees) than the annealing process (which is carried out at a temperature of about 1000°C), thereby reducing process defects.

[0066] Subsequently, a CMP process is performed to expose the upper surface of the bitline capping pattern (337) while simultaneously forming a contact diffusion prevention pattern (311) and a contact metal pattern (313). The contact diffusion prevention pattern (311) is formed as part of a contact diffusion prevention film. The contact metal pattern (313) is formed as part of a contact metal film. The contact diffusion prevention pattern (311) and the contact metal pattern (313) can form a storage node contact (BC). Subsequently, a conductive film is deposited on the storage node contact (BC) and the bitline capping patterns (337), and then etched to form landing pads (LP), and trenches are formed between the landing pads (LP). After filling the trenches with an insulating film, etch-back or CMP can be performed to form landing pad separation patterns (LPS). Then, data storage patterns (DSP) can be formed on the landing pads (LP).

[0068] FIG. 7 is a cross-sectional view illustrating the process of manufacturing a semiconductor memory device according to some embodiments.

[0069] Referring to FIG. 6j and FIG. 7, an additional polysilicon film (333M) doped with impurities can be formed on the front surface of the substrate (301) before forming the bitline diffusion barrier film (331L). Subsequently, the process can be performed in the same manner as in FIG. 6k, FIG. 6m to FIG. 6q, and FIG. 3a. The additional polysilicon film (333M) doped with impurities can be placed under the diffusion barrier pattern (331) to form a bitline (BL) and can have a structure as in FIG. 5.

[0071] FIGS. 8a to 8c are cross-sectional views illustrating the process of manufacturing a semiconductor memory device according to some embodiments.

[0072] Referring to FIG. 8a, interlayer insulating films (420) including a first interlayer insulating film (407) and a second interlayer insulating film (409) may be formed on a conductive pattern (20p) and a pad separation pattern (38). A thick silicon nitride layer (430a) may be formed directly on the second interlayer insulating film (409).

[0073] Next, substantially the same process as in FIG. 6c and FIG. 6d can be performed. Referring to FIG. 8b, a polysilicon film (333L) can be formed on the front surface of the substrate (301).

[0074] Referring to FIG. 8c, a polysilicon film (333L) can be partially removed using a selective etching process (e.g., an etch-back process). The etching process can be performed first until the silicon nitride mask pattern (430) on the peripheral region (PR) is exposed, and second until the silicon nitride mask pattern (430) on the cell array region (CR) is exposed, and a polysilicon pattern (333P) can be formed. The etching process of the polysilicon pattern (333P) can be performed until no polysilicon material remains on the silicon nitride mask pattern (430), and during this process, the level of the upper surface of the polysilicon pattern (333P) may be lower than the level of the interlayer insulating film (420). Subsequently, the silicon nitride mask pattern (430) can be removed. At this time, a portion of the silicon nitride mask pattern (430) may remain on the boundary region (IR). Next, the process can be performed identically as in FIG. 6k, FIG. 6m to FIG. 6q, and FIG. 3a.

[0075] FIGS. 9a to 9c are cross-sectional views sequentially illustrating the process of manufacturing a semiconductor memory device according to a comparative example.

[0076] Referring to FIG. 9a, unlike the embodiments of the present invention, a polysilicon mask pattern (530) was used as the etching mask instead of a silicon nitride mask pattern (430).

[0077] Referring to FIG. 9b, in the etching process of the polysilicon film (333L), the polysilicon mask pattern (530) and the polysilicon film (333L) contain the same material. By using the polysilicon mask pattern (530) as an etching mask, the etching process of the polysilicon film (333L) can be carried out to form a polysilicon pattern (333P). The polysilicon mask pattern (530) may remain on the boundary region (IR) even after the polysilicon pattern (333P) is formed. If the etching process is further carried out to remove the remaining polysilicon mask pattern (530), there is a risk that the interlayer insulating film (420) will be damaged.

[0078] As shown in Fig. 9c, if a bit line (BL) is formed in a boundary region (IR) without removing the polysilicon mask pattern (530), there is a risk of a short circuit occurring due to electrical connection with the bit line (BL).

[0079] A method for manufacturing a semiconductor memory device according to the present invention uses a silicon nitride mask pattern (430) as an etching mask to form a contact hole (DCH) that exposes impurity regions (3d, 3b). Even if a remainder of the silicon nitride mask pattern (430) exists in the boundary region (IR) after the etching process, it is non-conductive, thereby increasing the reliability of the device. Additionally, over-etching can be prevented, which can protect the interlayer insulating film (420).

[0080] The above description of the embodiments of the present invention provides examples for explaining the present invention. Accordingly, the present invention is not limited to the above embodiments, and it is evident that many modifications and changes are possible within the technical scope of the present invention, such as combining the above embodiments by those skilled in the art.

Claims

Claim 1 A semiconductor memory device comprising: a device isolation pattern defining a first active part and a second active part spaced apart from each other and disposed on a substrate; the center of the first active part being adjacent to the end of the second active part; a first bit line crossing the center of the first active part; a second bit line crossing the center of the second active part; a bit line contact interposed between the first bit line and the center of the first active part; and a storage node pad disposed on the end of the second active part, wherein the level of the lower surface of the first bit line is lower than the level of the lower surface of the second bit line, the bit line contact is disposed on one side of the storage node pad, and further comprising a pad isolation pattern disposed on the other side of the storage node pad, wherein the lower end of the pad isolation pattern is located below the lower end of the storage node pad. Claim 2 A semiconductor memory device according to claim 1, wherein the first bit line includes a first diffusion prevention pattern and a first bit line wiring pattern stacked in sequence, and the second bit line includes a second diffusion prevention pattern and a second bit line wiring pattern stacked in sequence. Claim 3 A semiconductor memory device according to paragraph 2, wherein the level of the lower surface of the first diffusion prevention pattern is lower than the level of the lower surface of the second diffusion prevention pattern. Claim 4 A semiconductor memory device according to paragraph 2, wherein the thickness of the first diffusion prevention pattern is substantially the same as the thickness of the second diffusion prevention pattern. Claim 5 A semiconductor memory device according to claim 2, wherein the first diffusion prevention pattern and the second diffusion prevention pattern comprise the same first metal material, and the first bitline wiring pattern and the second bitline wiring pattern comprise the same second metal material. Claim 6 A semiconductor memory device according to claim 2, further comprising an interlayer insulating film between the substrate and the second bit line, wherein the first diffusion prevention pattern contacts the bit line contact and the second diffusion prevention pattern contacts the interlayer insulating film. Claim 7 A semiconductor memory device according to claim 6, further comprising: a first bitline polysilicon pattern between the first diffusion prevention pattern and the bitline contact; and a second bitline polysilicon pattern between the second diffusion prevention pattern and the interlayer insulating film. Claim 8 delete Claim 9 A semiconductor memory device comprising: a device isolation pattern defining a first active part and a second active part spaced apart from each other and disposed on a substrate; the center of the first active part being adjacent to the end of the second active part; a first bit line crossing the center of the first active part; a second bit line crossing the center of the second active part; a bit line contact interposed between the first bit line and the center of the first active part; and a storage node pad disposed on the end of the second active part, wherein the first bit line and the second bit line are located at different heights relative to the upper surface of the substrate, the bit line contact is disposed on one side of the storage node pad, and further comprising a pad isolation pattern disposed on the other side of the storage node pad, wherein the bottom of the pad isolation pattern is located below the bottom of the storage node pad. Claim 10 A semiconductor memory device comprising: a substrate including a cell array region and a boundary region; a device isolation pattern defining a first active region, a second active region, and a third active region spaced apart from each other and disposed on the cell array region, wherein the center of the first active region is adjacent to the end of the second active region and the third active region is disposed adjacent to the boundary region; a first bit line crossing the center of the first active region; a second bit line crossing the center of the second active region; a third bit line crossing the center of the third active region; a bit line contact interposed between the first bit line and the center of the first active region; a first storage node pad disposed on the end of the second active region; and a second storage node pad disposed on the end of the third active region, wherein the thickness of the second storage node pad is greater than the thickness of the first storage node pad and the level of the lower surface of the first bit line is lower than the level of the lower surface of the second bit line.

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