Semiconductor device and method of forming an embedded redistribution layer

Abstract

A semiconductor device has a semiconductor die. A first dielectric layer is formed on the semiconductor die. A second dielectric layer is formed on the first dielectric layer. A trench is formed within the second dielectric layer. A via opening is formed within the trench to expose the contact pads of the semiconductor die. A seed layer is formed on the second dielectric layer. The seed layer extends into the trench and the via opening. A conductive material is deposited into the via opening and the trench. The conductive material is overburdened from the trench. The seed layer around the conductive material is etched in a first etching step. The conductive material is etched in a second etching step.

Description

Technology Field

[0001] The present invention generally relates to semiconductor devices, and more specifically to a semiconductor device for forming an embedded redistribution layer and a method thereof. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmission and reception of electromagnetic signals, control of electronic devices, conversion of sunlight into electricity, and generation of visual images for television displays. Semiconductor devices are used in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. They can also be found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor packages are increasingly shifting toward fan-out technology. In many cases, semiconductor packages contain multiple semiconductor dies and multiple redistribution layer (RDL) layers. The non-planar top surface of a single RDL poses a challenge for forming the next RDL in a stack. Non-planar surfaces require greater depth of field and resolution for the photolithography exposure system, among other things. The problem to be solved

[0004] The dual damascene process is typically used in CMOS fabrication to leave individual RDLs with planar top surfaces. However, the dual damascene process requires a Chemical Mechanical Planarization (CMP) step to remove excess conductive material. The CMP step adds complexity and cost to the process flow and acts as a barrier to the adoption of advanced packaging. Therefore, there is a need for improved semiconductor devices and methods for forming embedded RDLs. Brief explanation of the drawing

[0005] FIGS. 1a-1n illustrates a semiconductor wafer having an RDL formed on a semiconductor die and a plurality of semiconductor dies. Figures 2a-2d illustrate a double exposure method for patterning RDL. Figure 3 illustrates a half-tone mask used to pattern the RDL. Figures 4a-4d illustrate alternative process flows for depositing a conductive material to form an RDL. Figure 5 illustrates a fan-out semiconductor package having a semiconductor die. And FIGS. 6A and FIGS. 6B illustrate the integration of a semiconductor package into an electronic device. Specific details for implementing the invention

[0006] The present invention is described in the following description by one or more embodiments with reference to drawings in which the same or similar elements are represented. Although the present invention is described in the best form for achieving the purpose of the invention, those skilled in the art will understand that it is intended to include alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and the equivalents supported by the following detailed description and drawings. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and thus may refer to both a single semiconductor device and multiple semiconductor devices.

[0007] Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, function to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, generate the relationship between voltage and current necessary to perform the electrical circuit function.

[0008] Back-end manufacturing refers to the process of cutting or singulating a finished wafer into individual semiconductor dies and packaging the dies for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor dies, the wafer is scored and cut along non-functional areas of the wafer known as saw streets or scribes. The wafer is individualized using laser cutting tools or saw blades. After singulation, the individual semiconductor dies are mounted on a package substrate containing pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor dies are connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, stud bumps, conductive paste, wire bonds, or other suitable interconnection structures. Encapsulant or other molding compounds are deposited on the package to provide physical support and electrical insulation. The finished package is then inserted into an electrical system, allowing the functions of the semiconductor device to be utilized by other system components.

[0009] FIG. 1a illustrates a semiconductor wafer (100) having a base substrate material (102) such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor materials. A plurality of semiconductor dies or components (104) are formed on the wafer (100) separated by a wafer area between inactive dies or a saw street (106) as described above. The saw street (106) provides a cutting area for singulating the semiconductor wafer (100) into individual semiconductor dies (104). In one embodiment, the semiconductor wafer (100) has a width or diameter of 100 to 450 millimeters (mm).

[0010] FIG. 3b illustrates a cross-sectional view of a portion of a semiconductor wafer (100). Each semiconductor die (104) has a back surface or an inactive surface (108) and an active surface (210) comprising an analog or digital circuit implemented as an active component, a passive component, a conductive layer, and a dielectric layer formed inside the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface (210) to implement an analog or digital circuit, such as a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a MEMS, a memory, or other signal processing circuit. The semiconductor die (104) may also include integrated passive components (IPDs), such as inductors, capacitors, and resistors, for RF signal processing. The back surface (108) of the semiconductor wafer (100) may undergo an optional back grinding operation by mechanical grinding or etching process to remove a portion of the substrate (102) and reduce the thickness of the semiconductor wafer (100) and the semiconductor die (104).

[0011] An electrically conductive layer (112) is formed on an active surface (110) using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer (112) comprises one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive materials. The conductive layer (112) acts as a contact pad electrically connected to a circuit on the active surface (110).

[0012] The conductive layer (112) may be formed as contact pads arranged side-by-side at a first distance from the edge of the semiconductor die (104) as illustrated in FIG. 1B. Alternatively, the conductive layer (112) may be formed as contact pads offset into multiple rows such that a first row of contact pads is arranged at a first distance from the edge of the die, and a second row of contact pads is arranged alternately with the first row at a second distance from the edge of the die. The conductive layer (112) represents a single conductive layer formed on the semiconductor die (104) having contact pads for subsequent electrical interconnection to a larger system. However, there may be one or more intermediate conductive and insulating layers formed between the actual semiconductor device on the active surface (110) and the contact pads (112) for signal routing.

[0014] A dielectric layer (116) is formed on a semiconductor wafer (100) as part of a wafer manufacturing process to protect an active surface (110). An opening is generally formed through the dielectric layer (116) to allow for electrical connection. The dielectric layer (116) is formed from polyimide (PI), polybenzoxazole (PBO), or other suitable dielectric, passivation, or insulating material.

[0015] A dielectric layer (118) is formed on top of a dielectric layer (116). The dielectric layer (118) is a repassivation layer formed by an outsourced semiconductor assembly and test (OSAT) company for additional protection. The dielectric layer (118) may be formed from the material for the dielectric layer (116) described above or any other suitable insulating material. The dielectric layers (116 and 118) may be formed from the same or different materials. In some embodiments, one thicker dielectric layer is used rather than two separate dielectric layers.

[0016] In FIG. 1c, the opening is formed in an RDL pattern within the dielectric layers (116 and 118) using a laser (124) to ablate the desired pattern into the dielectric layer. The trench (122) is formed in the second dielectric layer (118) in a desired redistribution pattern, e.g., a fan-in or fan-out pattern. The trench (122) will become a conductive trace after being filled with a conductive material. The trench (122) extends directly over the contact pad (112), where a via opening (110) is formed below the contact pad. The via opening (110) is formed through an opening within the dielectric layer (116), or if necessary, through the first dielectric layer, to expose the contact pad (112) to the trench (122).

[0017] In one embodiment, the trench (122) is formed using a first laser removal step, and then the via opening (120) is formed using a second laser removal step. The opening (120) can be formed simply by focusing the laser (124) on the contact pad (112) for a longer time than the rest of the RDL pattern.

[0018] In FIG. 1d, a seed layer (130) is formed on a semiconductor wafer (100). The seed layer (130) is formed using any suitable metal deposition technique, such as chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or plating. The sputtered material is typically titanium, titanium-tungsten, or titanium-copper, but may also be copper, steel, aluminum, gold, a combination thereof, or other suitable conductive material.

[0019] The seed layer (130) is a conformal lay, which means that a material of substantially uniform thickness is deposited on all exposed surfaces, including horizontal and vertical surfaces. The seed layer (130) extends into a trench (122) below the side of the second dielectric layer (118) and into a via opening (120) below the side of the first dielectric layer (116). The seed layer (130) is physically and electrically connected to the contact pads (112) at the via opening (120). The seed layer (130) extends across the upper surface of the second dielectric layer (118) to completely cover the semiconductor wafer (100) and interconnect all contact pads (112).

[0020] In FIG. 1e, a photoresist layer (134) is formed on a seed layer (130). The photoresist layer (134) completely covers the wafer (100). The photoresist layer (134) is exposed to light rays through a mask so that the light rays strike the photoresist layer in a pattern similar to the trench (122).

[0021] In FIG. 1f, a developer is used to wash away a portion of the photoresist layer (134) exposed to light to form a trench (136). A negative photoresist is used in another embodiment. The trench (136) formed through the photoresist layer (134) completely exposes the underlying via (120) and the seed layer (130) within the trench (122). The trench (136) within the photoresist layer (134) is wider than the trench (122) within the second dielectric layer (120) to leave an exposed lip (138) around each trench (122).

[0022] In FIG. 1g, a conductive material (140-144) is deposited in a trench (136) using a bottom-up fill deposition method. The conductive material fill forms a conductive via (140) in a via opening (120), a conductive trace (142) in a trench (122), and a flange (144) on a lip (138). The conductive material is generally copper, but gold, aluminum, titanium, tin, iron, nickel, combinations thereof, and other suitable conductive materials may be used in other embodiments.

[0023] The trench (122) of the second dielectric layer (118) is overfilled to form a sacrificial flange (144) on the lip (138). The flange (144) combines with the excess conductive material just above the trench (122) and forms an overload through the opening (120). The conductive material (140-144) is filled into the trench (136) until the conductive material exposes the upper surface of the second dielectric layer (118). The conductive material is deposited into the trench (136) until the flange (144) is approximately 1-2 μm thick in one embodiment.

[0024] The remainder of the photoresist layer (134) is removed in FIG. 1h, leaving the conductive material (140-144) in the pattern of the overloaded conductive trace (142) to form the flange (144). In FIG. 1j, the photoresist (150) is exposed to light and developed to remove the second portion of photoresist outside the conductive trace (142). The opening (152) through the photoresist (150) exposes the portion of the seed layer (130) not covered by the flange (144) and the conductive material (140-144). The remainder of the photoresist (150) has a footprint similar or identical to that of each lower conductive trace (142).

[0025] In FIG. 1k, a seed etching (160) step occurs, which is indicated by the arrow shown in the drawing. Seed etching (160) occurs chemically or by other mechanisms selective for the material of the seed layer (130). Seed etching (160) may be a wet or dry method. While the photoresist layer (150) protects the conductive trace (142) from the etching process, the seed layer (130) is removed between the regions of the conductive material (140-144). The flange (144) may be slightly etched by seed etching (160), but is not completely removed due to the selective nature of the etching. The portion of the seed layer (130) below the flange (144) is not removed because it is protected from etching by the flange.

[0026] The remaining portion of the photoresist layer (150) is removed in FIG. 1L. The conductive material (140-144) remains together with the portion of the seed layer (130) below the conductive material, while the seed layer is removed between the individual portions of the conductive material. The conductive material (140-144) remains in an overloaded state on the second dielectric layer (118).

[0027] At FIG. 1m, a second etching (166) step, indicated by an arrow in the drawing, occurs. Etching (166) uses other chemicals or processes effective in removing both the conductive material (140-144) and the seed layer (130). Etching (166) removes the top portion of the conductive material (140-144) over time, and

[0028] The process continues until the flange (144) is removed and the top surface of the conductive trace (142) is coplanar or approximately coplanar with the top surface of the second dielectric layer (118).

[0029] The second dielectric layer (118) can be used as an etch-stop layer by exposing it when the flange (144) is completely removed, as more of the second dielectric layer is visible when the etching is complete. The portion of the seed layer (130) under the flange (144) is also removed, but the portion of the seed layer under the conductive trace (142) and the conductive via (140) remains. The conductive trace (142) remains as a desired redistribution pattern having an upper surface that is nearly flat with the upper surface of the second dielectric layer (118). In some embodiments, the conductive trace (142) is formed to include a contact pad to which a subsequently formed RDL layer or other interconnect structure is connected to the conductive trace.

[0030] In FIG. 1n, the semiconductor wafer (100) is divided into individual semiconductor dies (104) via a saw street (106) using a saw blade or laser cutting tool (168). The individual semiconductor dies (104) can be inspected and electrically tested for identification of KGD after division. In another embodiment, an additional conductive layer is formed prior to division to allow for more complex routing. All layers of a multiple RDL stack on the semiconductor die (104) can be formed as described above.

[0031] The semiconductor die (104) can be stored in tape and reel or other storage for later packaging, or directly integrated into a fan-out semiconductor package. Forming a conductive trace (142) having an upper surface coplanar with the surrounding dielectric layer (118) facilitates the processing requirements for packaging the semiconductor die (104). Forming a coplanar surface without requiring chemical mechanical planarization (CMP) means that the semiconductor die (104) manufacturing process is cheaper and simpler.

[0032] FIGS. 2a-2d illustrate the formation of trenches (122) and via openings (120) using double exposure photolithography as an alternative to the laser removal shown in FIG. 1c. In FIG. 2a, a first mask (200) is placed over a wafer (100). The mask (200) includes openings (202) formed in a desired pattern for the trenches (122), except where the trenches overlap through the openings (120). When the dielectric layer (118) is first deposited over the wafer (100), the second dielectric layer is photosensitive. Radiation (204) is exposed to the wafer (100) through the mask (200) and strikes the dielectric layer (118) in the pattern of the openings (202). The radiation (202) is relatively weak, so the material in the region (208) below the openings (202) is only partially cross-linked. The region (208) of the dielectric layer (118) is partially hardened by radiation (204) and remains in a slightly soft state.

[0033] In FIG. 2b, a second mask (210) is placed over the wafer (100). The mask (210) covers the desired pattern for the trench (122) containing the via opening (120). The opening (212) is formed over another area of ​​the wafer (100). Radiation (214) is exposed on the dielectric layer (118) through the opening (212). Since the radiation (214) is relatively stronger than the radiation (204), the area (218) of the dielectric layer (118) is hardened with greater intensity than the area (208). The area (220) over the contact pad (112) remains unexposed to both radiation (204, 214).

[0034] In FIG. 2c, a developer is used to wash away the portion of the dielectric layer (118) that is not exposed to light. The area (220) on the contact pad (112) is completely removed, while the area (208) exposed to weak light (204) is only partially removed. After development, the dielectric layer (118) is cured in FIG. 2d.

[0035] FIG. 3 illustrates a half-tone mask (230) used to expose all desired areas of a dielectric layer (118) to light in a single step. The mask (230) has different discrete areas with varying light transmittances. Area (232) of the mask (230) over the contact pad (112) is completely opaque, area (234) over the desired location of the trench (122) is partially transparent, and area (236) around the trench is completely transparent. In one embodiment, area (232) has approximately 0% transmittance, area (234) has approximately 50% transmittance, and area (236) has approximately 100% transmittance.

[0036] Radiation (240) is exposed onto the wafer (100) through the mask (230). Radiation (240) passes through region (236) with greater intensity than radiation passes through region (234). Region (232) completely blocks the transmission of radiation (240). Region (220) is exposed to a stronger portion of the light radiation (240) than region (208), and region (220) is hardly exposed to radiation. As shown in FIGS. 2c and 2d. The dielectric layer (118) is developed and cured so that the formation of trenches (122) and via openings (120) in the dielectric layer (118) is completed.

[0037] FIGS. 4a through 4d illustrate an alternative process for filling trenches (122) and via openings (120) with a conductive material as an alternative to the process illustrated in FIGS. 1f-1m. In FIG. 4a, an opening (236) is formed in the photoresist layer (134). The opening (236) is similar to the previous opening (136) but slightly smaller. The opening (236) has the same or nearly the same footprint as the trench (122), whereas the opening (136) was slightly larger.

[0038] In FIG. 4b, a conductive material is deposited in the opening (236) to form a conductive via (240) within the via opening (120) and an RDL pattern (242) within the trench (122). The conductive material is charged upward to control the charge level and to form an RDL where the upper surface is coplanar with the upper surface of the dielectric. The conductive material can be deposited slightly on the dielectric layer (118) and then removed as before. However, because the size of the opening (236) is smaller than that of the opening (136), a flange (144) is not formed.

[0039] FIG. 4c illustrates the photoresist layer (134) removed as in FIG. 4h. In FIG. 4d, the seed layer etching step (160) is performed as before to remove the seed layer (130) between the RDL pattern (240) portions. Next, the semiconductor dies (104) are singulated from each other as shown in FIG. 1n.

[0040] FIG. 5 illustrates an exemplary fan-out package (300) formed with a semiconductor die (104) after forming an RDL pattern (142 or 242). The semiconductor die (104) is embedded within a molding compound or an encapsulant (304). The encapsulant (304) is deposited over the semiconductor die (104), while a plurality of semiconductor dies are placed on the carrier with the active surface (110) oriented toward the carrier. Face down results in a semiconductor die (104) having a surface in which the encapsulant (304) is coplanar with the upper surface of the second dielectric layer (118) because the second dielectric layer contacts the carrier during molding. The encapsulant (304) extends over the back surface (108) opposite the carrier but may optionally be back-grinded or film-assisted molded to leave the back surface exposed.

[0041] The encapsulant (304) may be a polymer composite material such as epoxy resin, epoxy acrylate, or a polymer with or without fillers. The encapsulant (304) is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. The encapsulant (304) also protects the semiconductor die (104) from degradation caused by light exposure.

[0042] A build-up interconnect structure (310) is formed on the active surface (110) of the semiconductor die (104) and the encapsulant (304). The build-up interconnect structure (310) is formed on a surface area larger than the surface area of ​​the semiconductor die (104) due to the presence of the encapsulant (304). The encapsulant (304) provides additional surface area to allow the build-up interconnect structure (304) to fan out. In some embodiments, a first dielectric layer (116) is formed on the semiconductor die (104) at the end of manufacturing of the semiconductor wafer (100), and a second dielectric layer (118) is formed on both the semiconductor die (104) and the encapsulant (304) by an OSAT company as part of the formation of the fan-out build-up interconnect structure (310). A conductive trace (142) is optionally extended over the encapsulant (304).

[0043] The build-up interconnect structure (310) includes a first dielectric layer (312), a second dielectric layer (314), and a solder mask layer (316). A first conductive layer (320) is formed between the dielectric layer (312) and the dielectric layer (314). The conductive layer (320) includes a conductive via passing through an insulating layer to contact a conductive trace (142). A second conductive layer (322) is formed on or within the dielectric layer (314). The conductive layer (322) includes a conductive via passing through the insulating layer (314) to contact the conductive layer (320). The conductive layers (320 and 322) may be formed by being embedded within the insulating layers (312, 314), respectively, as described above, without requiring chemical-mechanical planarization.

[0044] Each RDL layer, composed of a pair of conductive and insulating layers, has a flat top surface, which facilitates the requirements for layers formed thereafter. Any number of pairs of insulating and conductive layers interleaved on the semiconductor die (104) and encapsulant (304) may be formed as needed to implement the desired signal routing. In another embodiment, a build-up interconnect structure is formed on the semiconductor die (104) and encapsulant (304) using any suitable process.

[0045] An electrically conductive bump material is deposited on a conductive layer (316) within an opening of a solder mask layer (316) using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, combinations thereof, or other suitable conductive materials having an optional flux solution. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer (322) using a suitable attachment or bonding process. The bump material may be reflowed by heating the material above its melting point to form a conductive ball or bump (324). In one embodiment, the conductive bump (324) is formed on a lower bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. The conductive bump (324) may also be compression bonded or thermally bonded to the conductive layer (322). The conductive bump (214) represents one type of interconnection structure that can be formed on the conductive layer (322) for electrical connection to the substrate. The interconnection structure may also use bond wires, conductive paste, stud bumps, microbumps, conductive pillars, or other electrical interconnections. Multiple semiconductor packages (300) are generally formed within a panel or a reconfigured wafer and, after completion, are unified via an encapsulant (304).

[0046] FIGS. 6a and 6b illustrate the integration of the aforementioned semiconductor package, for example, the semiconductor package (300), into a larger electronic device (340). FIG. 6a illustrates a partial cross-section of the semiconductor package (300) mounted on a printed circuit board (PCB) or another substrate (342) as part of the electronic device (340). A bump (324) is reflowed onto a conductive layer (344) of the PCB (342) to physically attach the semiconductor package to the PCB (300) and electrically connect it. In other embodiments, thermal compression or other suitable attachment and connection methods are used. In some embodiments, an adhesive layer or an underfill layer is used between the semiconductor package (300) and the PCB (342). A semiconductor die (104) is electrically coupled to the conductive layer (344) through a build-up interconnect structure (310), a conductive trace (142), and a conductive via (140).

[0047] FIG. 6b illustrates an electronic device (340) comprising a PCB (342) having a plurality of semiconductor packages mounted on the surface of the PCB, including a semiconductor package (300). Depending on the application, the electronic device (340) may have one type of semiconductor package or multiple types of semiconductor packages. The electronic device (340) may be a standalone system that uses semiconductor packages to perform one or more electrical functions. Alternatively, the electronic device (340) may be a sub-component of a larger system. For example, the electronic device (340) may be part of a tablet computer, a mobile phone, a digital camera, a communication system, or other electronic device. The electronic device (340) may also be a graphics card, a network interface card, or other signal processing card inserted into a computer. The semiconductor packages may include a microprocessor, memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, an individual active or passive device, or other semiconductor dies or electrical components.

[0048] The PCB (342) provides a general substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces (344) are formed on the surface of or within a layer of the PCB (342) using deposition, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces (344) provide electrical communication between the semiconductor packages, mounted components, and other external systems or components. The traces (344) also provide power and ground connections to the semiconductor packages as needed.

[0049] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second level packaging includes mechanically and electrically attaching the intermediate substrate to a PCB (342). In other embodiments, the semiconductor device may have only the first level packaging in which the die is directly mechanically and electrically mounted to the PCB (342).

[0050] For example, various types of first-stage packaging, including bond wire packages (346) and flip chips (348), are shown on the PCB (342). Additionally, various types of second-stage packaging, including ball grid arrays (BGA) (350), bump chip carriers (BCC) (352), land grid arrays (LGA) (356), multichip modules (MCM) (358), quad flat lead-free packages (QFN) (360), quad flat packages (362), and embedded wafer-level ball grid arrays (eWLB) (366), are shown mounted on the PCB (342) together with semiconductor packages (300). Conductive traces (344) electrically connect various packages and components placed on the PCB (342) to the semiconductor packages (300), allowing the semiconductor dies (104) to be used for other components on the PCB.

[0051] Depending on system requirements, any combination of semiconductor packages composed of any combination of first and second stage packaging styles and other electronic components may be connected to the PCB (342). In some embodiments, the electronic device (340) comprises a single attached semiconductor package, whereas other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can integrate prefabricated components into electronic devices and systems. Because the semiconductor packages contain sophisticated functions, electronic devices can be manufactured using inexpensive components and simplified manufacturing processes. As a result, the devices are less likely to fail and have lower manufacturing costs, leading to reduced consumer costs.

[0052] Although one or more embodiments of the present invention have been illustrated in detail, those skilled in the art will understand that modifications and changes to these embodiments may be made without departing from the scope of the present invention as described in the following claims.

Claims

Claim 1 A step of providing a semiconductor die; a step of forming a first dielectric layer on the semiconductor die; a step of forming a second dielectric layer on the first dielectric layer; a step of forming a trench within the second dielectric layer; a step of forming a via opening to expose a contact pad of the semiconductor die within the trench; a step of forming a seed layer on the second dielectric layer - the seed layer extends into the trench and via opening -; a step of depositing a conductive material within the via opening and trench - the conductive material is overburdened from the trench and a portion of the seed layer is maintained exposed from the conductive material -; a step of forming a photoresist layer on the conductive material within the trench - a portion of the conductive material outside the footprint of the trench is maintained exposed from the photoresist layer -; A method for manufacturing a semiconductor device, comprising: a step of etching a seed layer around a conductive material, including a portion of the seed layer, using the photoresist layer as a mask in a first etching step; a step of removing the photoresist layer after the first etching step; and a step of etching the conductive material in a second etching step after removing the photoresist layer, wherein the portion of the conductive material is removed. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein the step of etching a conductive material in the second etching step comprises etching the conductive material until the surface of the conductive material becomes coplanar with the surface of the second dielectric layer. Claim 3 A method for manufacturing a semiconductor device according to claim 1, further comprising the step of depositing the conductive material using a bottom-up filling deposition technique until the thickness of the conductive material on the second dielectric layer becomes 1 to 2 micrometers (μm). Claim 4 A semiconductor device manufacturing method according to claim 1, wherein the step of etching the seed layer removes a portion of the seed layer surrounding the trench. Claim 5 A method for manufacturing a semiconductor device according to claim 1, further comprising the steps of: depositing an encapsulant around a semiconductor die; and forming a fan-out interconnect structure on the semiconductor die and the encapsulant. Claim 6 delete Claim 7 A method for manufacturing a semiconductor device comprising: a step of forming an insulating layer; a step of forming a trench within the insulating layer; a step of forming a seed layer within the trench; a step of depositing a conductive material within the trench, wherein the conductive material is overburdened from the trench and a portion of the seed layer is maintained exposed from the conductive material; a step of forming a photoresist layer on the conductive material within the trench, wherein a portion of the conductive material outside the footprint of the trench is maintained exposed from the photoresist layer; a step of etching the seed layer around the conductive material, including the portion of the seed layer, using the photoresist layer as a mask, wherein a portion of the conductive material remains after etching the seed layer; a step of removing the photoresist layer after etching the seed layer; and a step of etching the conductive material after removing the photoresist layer, wherein the portion of the conductive material is removed. Claim 8 A method for manufacturing a semiconductor device according to claim 7, wherein the step of depositing a conductive material within the trench comprises depositing the conductive material using a bottom-up filling technique until the surface of the conductive material becomes flush with the surface of the insulating layer. Claim 9 A method for manufacturing a semiconductor device according to claim 7, wherein the step of etching a conductive material after removing the photoresist layer comprises etching the conductive material in a second etching step separate from the step of etching a seed layer around the conductive material until the surface of the conductive material becomes coplanar with the surface of the insulating layer. Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 A method for manufacturing a semiconductor device according to claim 7, further comprising the step of forming a fan-out interconnect structure on the conductive material and insulating layer. Claim 17 A method for manufacturing a semiconductor device according to claim 7, wherein the conductive material comprises copper and the seed layer comprises titanium. Claim 18 A method for manufacturing a semiconductor device according to claim 7, further comprising the steps of providing a semiconductor die, depositing an encapsulant around the semiconductor die, and forming a dielectric layer on the semiconductor die and the encapsulant. Claim 19 A method for manufacturing a semiconductor device according to claim 7, wherein the step of etching the conductive material is performed by chemical etching to yield the upper surface of the conductive material and the insulating layer on the same plane. Claim 20 A method for manufacturing a semiconductor device, comprising the steps of: forming a dielectric layer; forming a trench within the dielectric layer; forming a seed layer within the trench; depositing a conductive material within the trench; forming a photoresist layer on the conductive material within the trench, wherein a portion of the conductive material is exposed from the photoresist layer; as a first etching step, etching a seed layer around the conductive material using the portion of the photoresist layer and the conductive material as a mask; removing the photoresist layer after the first etching step; and etching the conductive material in a second etching step after removing the photoresist layer. Claim 21 A method for manufacturing a semiconductor device according to claim 20, further comprising the step of continuing a second etching step until the surface of the conductive material becomes coplanar with the surface of the dielectric layer. Claim 22 A method for manufacturing a semiconductor device according to claim 20, wherein the step of depositing a conductive material within the trench comprises depositing the conductive material using a bottom-up filling deposition technique until the surface of the conductive material becomes coplanar with the surface of the dielectric layer. Claim 23 A method for manufacturing a semiconductor device according to claim 20, wherein the first etching step removes a portion of the seed layer around the trench. Claim 24 A method for manufacturing a semiconductor device according to claim 20, further comprising the step of forming a fan-out interconnect structure on the conductive material and dielectric layer. Claim 25 A method for manufacturing a semiconductor device according to claim 20, wherein the conductive material comprises copper and the seed layer comprises titanium. Claim 26 A method for manufacturing a semiconductor device according to claim 20, further comprising the steps of providing a semiconductor die, depositing an encapsulant around the semiconductor die, and forming a dielectric layer on the semiconductor die and the encapsulant. Claim 27 A method for manufacturing a semiconductor device, comprising the steps of: forming an insulating layer; forming a trench within the insulating layer; forming a seed layer within the trench; depositing a conductive material on the seed layer within the trench; forming a photoresist layer on the trench— wherein a portion of the conductive material is maintained exposed from the photoresist layer—; and etching the seed layer around the trench using the photoresist layer and the portion of the conductive material as a mask; and etching the conductive material in a second etching step after etching the seed layer. Claim 28 A method for manufacturing a semiconductor device according to claim 27, wherein etching the seed layer removes a portion of the seed layer around the trench. Claim 29 A method for manufacturing a semiconductor device according to claim 27, further comprising the step of forming a fan-out interconnect structure on the insulating layer. Claim 30 A method for manufacturing a semiconductor device according to claim 27, further comprising the steps of providing a semiconductor die, depositing an encapsulant around the semiconductor die, and forming a dielectric layer on the semiconductor die and the encapsulant. Claim 31 A method for manufacturing a semiconductor device according to claim 27, further comprising the step of forming a via in the trench after forming a trench in the insulating layer and before forming a seed layer in the trench.

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