Semiconductor device and method of double shielding

Abstract

A semiconductor device has a substrate. A first electric component and a second electric component are disposed on the substrate. A conductive pillar is formed on the substrate between the first electric component and the second electric component. A first shielding layer is formed on the first electric component and the conductive pillar by jet printing a conductive material. A second shielding layer is formed on the first electric component and the second electric component by sputtering, spraying, or plating a conductive material. An insulating layer is optionally formed between the first shielding layer and the second shielding layer by jet printing an insulating material onto the first shielding layer.

Description

Technology Field

[0001] The present invention generally relates to semiconductor devices, and more specifically to a double-shielded semiconductor device for a semiconductor package and a method for manufacturing the same. Background Technology

[0003] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmission and reception of electromagnetic signals, control of electronic devices, conversion of light into electricity, and generation of visual images for television displays. Semiconductor devices are used in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. They can also be found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0004] Semiconductor devices are often susceptible to interference between devices, such as electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, or crosstalk—also known as capacitive, inductive, or conductive coupling—which can disrupt operation. High-speed analog circuits, such as radio frequency (RF) filters or digital circuits, also generate interference.

[0005] A conductive layer is typically formed on a semiconductor package to protect electronic components within the package from EMI and other interference. The shielding layer absorbs EMI before signals reach the semiconductor dies and discrete components within the package; otherwise, it could cause device malfunction. The shielding layer is also formed on packages containing components expected to generate EMI to protect peripheral devices.

[0006] One problem with conventional semiconductor package shielding methods is that conformal shielding layers fail to prevent EMI loop currents from flowing through the shielding layer and inducing electric and magnetic fields in sensitive neighboring components of the same semiconductor package. Selective shielding of the most sensitive die or component effectively blocks noise sources and improves the electrical performance of only the selectively shielded component. The problem to be solved

[0008] However, forming both selective shielding for sensitive components and conformal shielding for the entire semiconductor package is a complex and costly process. Therefore, there is a need for improved dual-shielding semiconductor devices and methods. Brief explanation of the drawing

[0010] FIGS. 1a-1c illustrates a semiconductor wafer having a plurality of semiconductor dies separated by top street. Figures 2a-2g illustrate the formation of a double shielding layer with selective shielding. FIG. 3 illustrates an example of double shielding with no isolation between the shielding layers. FIGS. 4a-4e illustrate the formation of an optional EMI shield within a recess. And Figures 5a and 5b illustrate the integration of a double-shielded semiconductor package into an electronic device. Specific details for implementing the invention

[0011] The present invention is described in the following description by one or more embodiments with reference to drawings in which the same or similar elements are represented. Although the present invention is described in the best form for achieving the purpose of the invention, those skilled in the art will understand that it is intended to include alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and the equivalents supported by the following detailed description and drawings. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and thus may refer to both a single semiconductor device and multiple semiconductor devices. The terms "die" and "semiconductor" are used interchangeably.

[0012] Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, function to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, generate the relationship between voltage and current necessary to perform the electrical circuit function.

[0013] Back-end manufacturing refers to the process of cutting or singulating a finished wafer into individual semiconductor dies and packaging the dies for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor dies, the wafer is scored and cut along non-functional areas of the wafer known as saw streets or scribes. The wafer is individualized using laser cutting tools or saw blades. After singulation, the individual semiconductor dies are mounted on a package substrate containing pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor dies are connected to contact pads within the package. Electrical connections can be made using conductive layers, bumps, stud bumps, conductive paste, wire bonds, or other suitable interconnection structures. Encapsulant or other molding compounds are deposited on the package to provide physical support and electrical insulation. The finished package is then inserted into an electrical system, allowing the functions of the semiconductor device to be utilized by other system components.

[0014] FIG. 1a illustrates a semiconductor wafer (100) having a base substrate material (102), such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor materials, for structural support. A plurality of semiconductor dies or components (104) are formed on the wafer (100) separated by a wafer area between inactive dies or a saw street (106) as illustrated above. The saw street (106) provides a cutting area for singulating the semiconductor wafer (100) into individual semiconductor dies (104). In one embodiment, the semiconductor wafer (100) has a width or diameter of 100 to 450 millimeters (mm).

[0015] FIG. 1b illustrates a cross-sectional view of a portion of a semiconductor wafer (100). Each semiconductor die (104) has an inactive back surface (108) and an active surface (110) comprising an analog or digital circuit implemented as an active component, a passive component, a conductive layer, and a dielectric layer formed inside or on the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface (210) to implement an analog or digital circuit, such as a digital signal processor (DSP), an ASIC, a MEMS, a memory, or other signal processing circuit. The semiconductor die (104) may also include integrated passive circuits (IPDs), such as inductors, capacitors, and resistors, for RF signal processing. The back surface (108) of the semiconductor wafer (100) may undergo an optional back grinding operation by mechanical grinding or etching process to remove a portion of the substrate (102) and reduce the thickness of the semiconductor wafer (100) and the semiconductor die (104).

[0016] An electrically conductive layer (112) is formed on an active surface (110) using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer (112) comprises one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive materials. The conductive layer (112) acts as a contact pad electrically connected to a circuit on the active surface (110).

[0017] The conductive layer (112) may be formed as contact pads arranged side by side at a first distance from the edge of the semiconductor die (104) as shown in FIG. 1B. Alternatively, the conductive layer (112) may be formed as contact pads offset in a plurality of rows such that a first row of contact pads is arranged at a first distance from the edge of the die, and a second row of contact pads is arranged at a second distance from the edge of the die, alternating with the first row. The conductive layer (112) represents the final conductive layer formed on the semiconductor die (104), having contact pads for subsequent electrical interconnection to a larger system. However, there may be one or more intermediate conductive and insulating layers formed between the actual semiconductor device on the active surface (110) and the contact pads (112) for signal routing.

[0018] An electrically conductive bump material is deposited on a conductive layer (112) using an evaporation, electroplating, electroless plating, ball drop, or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, and combinations thereof, having an optional flux solution. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer (112) using a suitable attachment or bonding process. In one embodiment, the bump material may be reflowed by heating the material above its melting point to form a conductive ball or bump (114). The conductive bump (114) is formed on an underlying bump metallization (UBM) having optionally a wetting layer, a barrier layer, and an adhesive layer. The conductive bumps (114) may also be compression bonded or thermally bonded to the conductive layer (112). The conductive bumps (114) represent one type of interconnection structure that can be formed on the conductive layer (112) for electrical connection to a substrate. The interconnection structure may also use bond wires, conductive paste, stud bumps, microbumps, or other electrical interconnections.

[0019] In FIG. 1c, a semiconductor wafer (100) is singulated into individual semiconductor dies (104) through a saw street (106) using a saw blade or a laser cutting tool (118). The individual semiconductor dies (104) can be inspected and electrically tested to identify known good dies (KGD) after singulation.

[0020] FIGS. 2a-2g illustrate the formation of a semiconductor package having a semiconductor die (104). In one embodiment, the package (150) is a system-in-package (SiP) module. FIG. 2a illustrates a partial cross-sectional view of a substrate (152). Although only one substrate (152) is illustrated, hundreds or thousands of substrates are commonly performed in bulk on a common carrier using the same steps described herein for a single unit. The substrate (152) may also start as a single large substrate for multiple units and singulate with each other during or after the manufacturing process.

[0021] The substrate (152) comprises one or more insulating layers (154) into which one or more conductive layers (156) are inserted. In one embodiment, the insulating layer (154) is a core insulating substrate, and the conductive layer (156) is patterned on the upper and lower surfaces, such as, for example, a copper-clad laminate substrate. The conductive layer (156) also comprises conductive vias electrically coupled through the insulating layer (154). The substrate (152) may comprise any number of conductive and insulating layers interleaved with one another. A solder mask or passivation layer may be formed on both sides of the substrate (152). Any suitable type of substrate or lead frame is used for the substrate (152) in other embodiments.

[0022] The semiconductor package (150) of FIG. 2a has a semiconductor die (104), individual components (160) and a conductive pillar (162) mounted thereon, as well as any other individual active or passive components, or other components necessary for the intended function of the semiconductor die or package. Solder bumps (114) are reflowed between the conductive layer (156) and the semiconductor die (104) to mechanically and electrically connect the die to the substrate (152). Any type and number of components may be mounted on either the top surface or the bottom surface of the substrate (152), or both, as shown in FIG. 2a, and may also be embedded within the substrate in any appropriate order and configuration.

[0023] The individual components (160) depicted are merely representative. Any type, number, and component may be used. The conductive pillar (162) provides lateral blocking of electromagnetic interference (EMI) between the semiconductor die (104) and the discrete components (160). The conductive pillar (162) is typically connected to ground through the substrate (152) to help reduce EMI, although this is not mandatory. The conductive pillar (162) may be a plurality of individual pillars distributed around the semiconductor die (104) or a single piece of material extending continuously around the semiconductor die. The conductive pillar (162) is formed from aluminum, copper, steel, titanium, gold, other metals, or a combination or alloy thereof. The conductive pillar (162) is formed individually and then selected and placed on the substrate (152). In another embodiment, the conductive pillar (162) is formed directly on the substrate (152) using a photoresist layer as a mask to be removed.

[0024] After mounting a semiconductor die (104), individual components (160), conductive pillars (162), and any other desired electrical components onto a substrate (152), the components are encapsulated by an encapsulant or molding compound (170). The encapsulant (170) is deposited onto the substrate (152), semiconductor die (104), individual components (160), and conductive pillars (162) using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicators. The encapsulant (170) may be a polymer composite material such as an epoxy resin, epoxy acrylate, or a polymer with or without fillers. The encapsulant (170) is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. The encapsulant (170) completely covers the top and sides of the semiconductor die (104), individual components (160), and conductive pillars (162). The encapsulant (170) fills all gaps between the substrate (152) and the semiconductor die (104) or individual components (160) unless a separate underfill is used.

[0025] In FIG. 2c, a portion of the encapsulant (170) is removed by backgrinding using a mechanical grinder (172). In other embodiments, chemical etching, chemical-mechanical planarization (CMP), or other suitable planarization methods are used. The grinding process exposes the conductive pillar (162) and leaves the top surface (174) of the encapsulant (170) coplanar with the top surface (176) of the conductive pillar as shown in FIG. 2d. In other embodiments, the encapsulant (170) is deposited before the formation of the conductive pillar (162). In such cases, the conductive pillar (162) is formed by perforating through the encapsulant (170) to the substrate (152) and filling the resulting via or bruise with a conductive material. In one embodiment, jet printing is used to form the conductive pillar (162) within the encapsulant (170).

[0026] In FIG. 2e, an optional shielding layer (180) is formed on a semiconductor die (104) and a conductive filament (162) by jet printing of metal ink. The jet printing is represented by a nozzle (182) in FIG. 2e. The nozzle (182) can be used to form the optional shielding layer (180) in any pattern. The conductive ink printing may be electrohydrodynamic (EHD) jet printing, and an electric field between the nozzle and the conductive plate, which is used as a carrier for the package (150) during manufacturing, is used to guide the conductive ink being printed. In some embodiments, laser transfer printing is used to form the optional shielding layer (180). In laser transfer printing, a transparent film coated with metal is placed on a semiconductor package (150) oriented so that the metal faces the package. By focusing a laser onto the film where printing of the optional shielding layer (180) is required, the metal is transferred from the film to the semiconductor package (150). Aerosol jet printing or printing of other types of conductive materials is used in other embodiments. The printed material is copper, steel, aluminum, gold, titanium, a combination thereof, or other suitable material.

[0027] The optional shielding layer (180) is formed from a sheet of material that extends to each conductive pillar (162) and fills the area of ​​the upper surface (174) between the conductive pillars. The optional shielding layer (180) is formed directly on the upper surface (176) of the conductive pillar (162). The optional shielding layer (180) combined with the conductive pillar (162) forms an EMI shield specifically for the semiconductor die (104) or one or more other components that are particularly sensitive to EMI. The optional shielding layer (180) may completely fill the footprint area between the conductive pillars (162) or may be formed as holes, stripes, or other discontinuities.

[0028] The selective shielding layer (180) is formed only over the region between the conductive pillars (162) where the sensitive component is located and is not formed outside of said region. The purpose of having a specific shielding layer on the semiconductor die (104) is to reduce EMI loop currents that are induced into the selective shielding layer (180) from other parts of the package (150) and cause interference in the semiconductor die, or vice versa. The selective shielding layer (180) may extend outside the region between the conductive pillars (162) for various reasons, but extending the selective shielding layer (180) over other components may reduce the efficiency of the selective shielding layer by increasing the EMI loop current between components inside and outside the selective shielding.

[0029] In FIG. 2f, an insulating layer (190) is formed over an optional shielding layer (180). The insulating layer (190) is jet printed with a nozzle (182) or a second nozzle to separate the printing of conductive and insulating materials. The insulating layer (190) is printed by laser transfer printing or, in other embodiments, by printing of other types of insulating layers. The insulating layer (190) comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or other materials having similar insulating and structural properties. The insulating layer (190) completely covers the optional shielding layer (180) and extends downward to make physical contact with the encapsulant (170) around the optional shielding layer.

[0030] The selective shielding layer (180) and insulating layer (190) are typically formed at the strip level, which means that the package (150) remains as a strip of packages formed together on the substrate (152) as a large, non-individualized strip or as a unified package on a common strip carrier. Jet printing forms the selective shielding layer (180) and insulating layer (190) only over the area between the conductive pillars (162), thereby reducing complexity and cost compared to conventional methods of covering the entire panel of the unit with material and then patterning the layers using photolithography or other suitable mechanisms.

[0031] If the semiconductor package (150) is formed as a strip of units, the strip is individualized before forming a conformal shielding layer (200) over the entire package in FIG. 2g. The conformal shielding layer (200) is formed using any suitable metal deposition technique, e.g., chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or plating. The sputtered material may be copper, steel, aluminum, gold, a combination thereof, or other suitable material. The conformal shielding layer (200) completely covers the exposed surfaces of the encapsulant (170), the substrate (152), and the insulating layer (190). A conductive layer (156) is exposed on the side of the substrate (152) to allow the shielding layer (200) to be connected to ground through the substrate.

[0032] The insulating layer (190) physically and electrically isolates the optional shielding layer (180) from the conformal shielding layer (200). Physically isolating the optional shielding layer (180) from the conformal shielding layer (200) reduces the impact on the semiconductor die (104) caused by the extra optional shielding of the semiconductor die, which is generated by the discrete component (160) or other components outside the optional shielding. Conversely, the impact on the discrete component (160) is reduced by shunting the EMI loop current generated by the semiconductor die (104) in the optional shielding layer (180) directly to ground rather than the conformal shielding layer (200). The jet-printed optional shielding layer (180) and insulating layer (190) reduce the cost and complexity of manufacturing.

[0033] FIG. 3 illustrates another embodiment as a semiconductor package (210). The semiconductor package (210) is formed in substantially the same way as the semiconductor package (150), except that an insulating layer (190) is not formed between the optional shielding layer (180) and the conformal shielding layer (200). The shielding layer (200) is formed directly above the optional shielding layer (180). Without physical isolation between the shielding layers, EMI loop current flows between them. However, an additional path to ground of the conductive pillar (162) still helps to shunt the EMI loop current to ground to a greater extent than having only the conformal shielding layer (200). The additional thickness of the optional shielding layer (180) in combination with the conformal shielding layer (200) helps to shield the semiconductor die (104) in particular without physical isolation of the insulating layer (190).

[0034] FIGS. 4a-4e illustrate the formation of a concave selective shielding layer within a semiconductor package (220). In FIG. 4a, the encapsulant (170) is deposited over the conductive pillar (162) as in FIG. 2b. The recess (222) is formed within the encapsulant (170) in FIG. 4b by laser ablation, chemical etching, or other suitable process. The recess (222) is formed downward to the height of the conductive pillar (162), so that the upper surface (176) of each conductive pillar is exposed within the recess. The recess (222) follows the same footprint as discussed above for the selective shielding layer (180).

[0035] In FIG. 4c, the optional shielding layer (230) is formed within the recess (222). The optional shielding layer (230) is formed by jet printing by sputtering through a photoresist mask, or by other suitable processes. The optional shielding layer (230) may be formed using any of the methods and materials discussed above for the optional shielding layer (180). In one embodiment, the optional shielding layer (230) fills the footprint of the recess (222) and is in physical contact with the upper surface (176) of each conductive pillar (162). In an embodiment where the optional shielding layer (230) does not completely fill the footprint area between the conductive pillars (162), the recess (222) may still completely fill the footprint area with the optional shielding layer (230) formed as a stripe, a hole, or any other desired discontinuity. Optionally, the recess (222) can be formed into a desired final shape for the optional shielding layer (230) and then have a footprint completely filled by jet-printed conductive material. The optional shielding layer (230) is recessed below the upper surface (232) of the encapsulant (170).

[0036] In FIG. 4d, the remaining volume of the recess (222) is filled with an insulating layer (240). The insulating layer (240) is formed of a similar material in a manner similar to the insulating layer (190) above. The insulating layer (240) may be jet-printed to fill the recess (222) with a surface that is coplanar with the upper surface (232) of the encapsulant (170). In some embodiments, the recess (222) is overfilled by the insulating layer (240), and then the package (222) is back-grinded so that the encapsulant (170) and the insulating layer (240) are coplanar. In other embodiments, the recess (222) is not completely filled.

[0037] In FIG. 4e, a conformal shielding layer (250) is formed on the package (220) to completely cover the top and sides of the package.

[0038] In an embodiment where the package (220) is formed as a panel of the device, the panel is individualized to separate the packages from each other and expose the sides of the packages for shielding. The shielding layer (250) is formed of a similar material in a manner similar to the conformal shielding layer (200) above. The package (220) provides an optional shielding layer (230) directly over the semiconductor die (104) or other sensitive components, as well as a conformal shielding layer (250) over the entire package. The optional shielding layer (230) reduces the influence of EMI loop current between different regions of the package (220). The optional shielding layer (230) is recessed within the encapsulant (170) so that the upper surface of the package (220) is flat over the entire footprint of the package. In another embodiment, the insulating layer (240) is not used, and the conformal shielding layer (250) is formed directly over the optional shielding layer (230) similar to the embodiment of FIG. 3, but the optional shielding layer is recessed. The optional shielding layer (230) can be formed to have a surface that is coplanar with the encapsulant (170) if it is desired to keep the upper surface of the package (220) flat.

[0039] FIGS. 5a and 5b illustrate the integration of the aforementioned semiconductor package, for example, semiconductor package (150), into a larger electronic device (340). FIG. 5a illustrates a partial cross-section of the semiconductor package (150) mounted on a printed circuit board (PCB) or another substrate (342) as part of the electronic device (340). A bump (345) is formed similarly to the description of the bump (114) at any desired manufacturing stage and is reflowed onto the conductive layer (344) of the PCB (342) to physically attach and electrically connect the semiconductor package (150) to the PCB. In other embodiments, thermal compression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between the semiconductor package (150) and the PCB (342). A semiconductor die (104) is electrically connected to the conductive layer (344) through the substrate (152).

[0040] FIG. 5b illustrates an electronic device (340) comprising a PCB (342) having a plurality of semiconductor packages mounted on the surface of the PCB, including semiconductor packages (150). Depending on the application, the electronic device (340) may have one type of semiconductor package or multiple types of semiconductor packages. The electronic device (340) may be a standalone system that uses semiconductor packages to perform one or more electrical functions. Alternatively, the electronic device (340) may be a sub-component of a larger system. For example, the electronic device (340) may be part of a tablet computer, a mobile phone, a digital camera, a communication system, or other electronic device. The electronic device (340) may also be a graphics card, a network interface card, or other signal processing card inserted into a computer. The semiconductor packages may include a microprocessor, memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, individual active or passive devices, or other semiconductor dies or electrical components.

[0041] In FIG. 5b, the PCB (342) provides a general substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces (344) are formed on the surface of or within a layer of the PCB (342) using deposition, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. The signal traces (344) provide electrical communication between the semiconductor packages, mounted components, and other external systems or components. The traces (344) also provide power and ground connections to the semiconductor packages as needed.

[0042] In some embodiments, the semiconductor device has two packaging levels. The first stage packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second stage packaging involves mechanically and electrically attaching the intermediate substrate to a PCB (342). In other embodiments, the semiconductor device may have only the first stage packaging in which the die is directly mechanically and electrically mounted to the PCB (342).

[0043] For example, various types of first-stage packaging, including bond wire packages (346) and flip chips (348), are shown on the PCB (342). Additionally, a ball grid array (BGA) (350), a bump chip carrier (BCC) (352), a land grid array (LGA) (356), a multi-chip module (MCM) (358), a quad flat lead-free package (QFN) (360), a quad flat package (362), and an embedded wafer-level ball grid array (eWLB) (364) are shown mounted on the PCB (342) together with the (150). Conductive traces (344) electrically connect various packages and components placed on the PCB (342) to the (150), allowing other components on the PCB (342) to use the components within the (150).

[0044] Depending on system requirements, any combination of semiconductor packages composed of any combination of first and second stage packaging styles and other electronic components may be connected to the PCB (342). In some embodiments, the electronic device (340) comprises a single attached semiconductor package, whereas other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can integrate prefabricated components into electronic devices and systems. Because the semiconductor packages contain sophisticated functions, electronic devices can be manufactured using inexpensive components and simplified manufacturing processes. As a result, the devices are less likely to fail and have lower manufacturing costs, leading to reduced consumer costs.

[0045] Although one or more embodiments of the present invention have been illustrated in detail, those skilled in the art will understand that modifications and changes to these embodiments may be made without departing from the scope of the present invention as described in the following claims.

Claims

Claim 1 A step of providing a substrate; a step of placing a first electric component and a second electric component on the substrate; a step of placing a conductive pillar directly on the substrate between the first electric component and the second electric component; a step of depositing an encapsulant on the first electric component, the second electric component, and the conductive pillar after placing the conductive pillar on the substrate; a step of forming a recess within the encapsulant on the conductive pillar after depositing the encapsulant - wherein the upper surface of the conductive pillar is exposed within the recess and the lower surface of the recess is coplanar with the upper surface of the conductive pillar - a step of forming a first shielding layer on the encapsulant, the first electric component, and the conductive pillar by jet printing a conductive material - wherein the first shielding layer is completely contained within the recess - a step of forming an insulating layer on the first shielding layer - wherein the insulating layer is completely contained within the recess such that the upper surface of the insulating layer is coplanar with the upper surface of the encapsulant - , A method for manufacturing a semiconductor device, comprising the step of forming a second shielding layer on the insulating layer by sputtering, spraying, or plating a conductive material, wherein the insulating layer physically and electrically separates the second shielding layer from the first shielding layer, and the second shielding layer completely covers the upper surface and side surface of the encapsulant. Claim 2 A method for manufacturing a semiconductor device according to claim 1, further comprising the step of selectively forming a first shielding layer on the encapsulant. Claim 3 A method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming an insulating layer by jet printing. Claim 4 delete Claim 5 delete Claim 6 A method for manufacturing a semiconductor device according to claim 1, further comprising the step of singulating a substrate after forming a first shielding layer and before forming a second shielding layer. Claim 7 A method for manufacturing a semiconductor device, comprising the steps of: providing a substrate; placing an electrical component on the substrate; placing a conductive pillar directly on the substrate; depositing an encapsulant on the electrical component and the conductive pillar after placing the conductive pillar directly on the substrate; forming a recess within the encapsulant on the conductive pillar—wherein the upper surface of the conductive pillar is exposed within the recess while the side surface of the conductive pillar is kept completely covered by the encapsulant—; forming a first shielding layer on the electrical component and the conductive pillar—wherein the first shielding layer is completely contained within the recess—; forming an insulating layer on the first shielding layer—wherein the insulating layer is completely contained within a recess so that the upper surface of the insulating layer is coplanar with the upper surface of the encapsulant—; and forming a second shielding layer on the insulating layer. Claim 8 delete Claim 9 A method for manufacturing a semiconductor device according to claim 7, further comprising the step of forming a first shielding layer by jet printing. Claim 10 A method for manufacturing a semiconductor device according to claim 9, further comprising the step of forming the second shielding layer by sputtering, spraying, or plating. Claim 11 A semiconductor device comprising: a substrate; an electrical component disposed on the substrate; a conductive pillar disposed on the substrate; an encapsulant deposited on the electrical component and the conductive pillar; a recess formed within the encapsulant on the conductive pillar—wherein the upper surface of the conductive pillar is exposed within the recess—; a first shielding layer formed on the electrical component and the conductive pillar—wherein the first shielding layer is completely contained within the recess—; an insulating layer formed on the first shielding layer—wherein the insulating layer is completely contained within the recess such that the upper surface of the insulating layer is coplanar with the upper surface of the encapsulant—; and a second shielding layer formed on the insulating layer. Claim 12 delete Claim 13 A semiconductor device according to claim 11, wherein the first shielding layer is optionally formed on an electrical component and a conductive pillar. Claim 14 A semiconductor device according to claim 13, wherein the second shielding layer is a conformal shielding layer. Claim 15 A semiconductor device according to claim 11, wherein the second shielding layer extends over the side surface of the substrate. Claim 16 A method for manufacturing a semiconductor device according to claim 7, further comprising the step of singulating a substrate after forming a first shielding layer and before forming a second shielding layer. Claim 17 A method for manufacturing a semiconductor device comprising the steps of: providing a substrate; placing a first electric component and a second electric component on the substrate; placing a conductive pillar on the substrate between the first electric component and the second electric component; depositing an encapsulant on the first electric component, the second electric component, and the conductive pillar; forming a recess within the encapsulant on the conductive pillar—where the upper surface of the conductive pillar is exposed within the recess—; forming a first shielding layer on the encapsulant, the first electric component, and the conductive pillar—where the first shielding layer is completely contained within the recess—; forming an insulating layer on the first shielding layer and the conductive pillar—where the insulating layer is completely contained within the recess such that the upper surface of the insulating layer is coplanar with the upper surface of the encapsulant—; and forming a second shielding layer on the insulating layer, the first electric component, and the second electric component. Claim 18 A method for manufacturing a semiconductor device according to claim 17, further comprising the step of optionally forming a first shielding layer on an encapsulant. Claim 19 A method for manufacturing a semiconductor device according to claim 17, further comprising the step of forming a first shielding layer and an insulating layer by jet printing. Claim 20 A method for manufacturing a semiconductor device according to claim 19, further comprising the step of forming a second shielding layer by sputtering, spraying, or plating. Claim 21 A method for manufacturing a semiconductor device according to claim 20, further comprising the step of singulating a substrate after forming a first shielding layer and before forming a second shielding layer.

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