Semiconductor package

Abstract

The present invention provides a semiconductor package capable of improving the reliability of a product. The semiconductor package of the present invention comprises a package substrate including a first region and a second region excluding the first region, and a first surface and a second surface facing each other; a semiconductor chip mounted on the first surface of the package substrate; a pad including a first sub-pad disposed on the second surface of the first region of the package substrate and a second sub-pad disposed on the second surface of the second region of the package substrate and defining a solder ball recess; and a solder ball on the second surface including a first sub-solder ball connected to the first sub-pad and a second sub-solder ball connected to the second sub-pad, wherein the second sub-solder ball includes a first portion disposed within the solder ball recess and a second portion on the first portion.

Description

Technology Field

[0001] The present invention relates to a semiconductor package. More specifically, it relates to a semiconductor package in which reliability is improved by forming a hole in a pad disposed at the outermost edge of a package substrate. Background Technology

[0002] A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting semiconductor chips onto a printed circuit board and electrically connecting them using bonding wires or bumps. With the advancement of the electronics industry, various studies are underway to improve the reliability and miniaturize semiconductor packages.

[0003] Meanwhile, if the pad connecting the semiconductor package and the external board is formed flat without curvature, when a crack occurs in the pad, the crack is prone to propagation, which may degrade the performance and reliability of the semiconductor package. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a semiconductor package capable of improving product reliability.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0006] A semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises: a package substrate including a first region and a second region excluding the first region, and a first surface and a second surface facing each other; a semiconductor chip mounted on a first surface of the package substrate; a pad including a first sub-pad disposed on a second surface of the first region of the package substrate and a second sub-pad disposed on a second surface of the second region of the package substrate and defining a solder ball recess; and a solder ball on the second surface including a first sub-solder ball connected to the first sub-pad and a second sub-solder ball connected to the second sub-pad, wherein the second sub-solder ball comprises a first portion disposed within the solder ball recess and a second portion on the first portion.

[0007] A semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises: a package substrate including a corner region and a central region excluding the corner region, and a first surface and a second surface facing each other; a semiconductor chip mounted on the first surface of the central region of the package substrate; a first sub-redistribution pattern disposed in the central region of the package substrate; a second sub-redistribution pattern disposed in the corner region of the package substrate and including a trench; a first sub-pad disposed on the second surface and connected to the first sub-redistribution pattern; a second sub-pad disposed on the second surface and connected to the second sub-redistribution pattern; a first sub-solder ball connected to the first sub-pad; and a second sub-solder ball connected to the second sub-pad. The second sub-pad extends along the sidewall and bottom surface of the trench, at least a portion of the second sub-solder ball fills the trench remaining after the second sub-pad is formed, at least a portion of the second sub-solder ball overlaps the second sub-redistribution pattern in a direction perpendicular to the thickness direction of the package substrate, and the upper surface of the first sub-pad is flat.

[0008] A semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises a package substrate having four corner regions and a central region excluding the corner regions, and having a first surface and a second surface facing each other, wherein, from a planar perspective, each corner region has a stepped shape; at least one semiconductor chip mounted on a first surface of a central region of the package substrate; a solder resist layer disposed on a second surface and including a first trench; a first sub-redistribution pattern disposed in a central region of the package substrate; a redistribution pattern comprising a second sub-redistribution pattern disposed in a corner region of the package substrate and including a plurality of second trenches; a first sub-pad extending along the bottom surface of the first trench and connected to the first sub-redistribution pattern; a second sub-pad extending along the bottom surface of the first trench and the sidewall and bottom surface of the second trench and connected to the second sub-redistribution pattern; a first sub-solder ball connected to the first sub-pad; and a second sub-solder ball connected to the second sub-pad, with at least a portion filling the second trench. A trench exposes a redistribution pattern, and a plurality of second trenches do not expose a package substrate, and a second sub-solder ball includes a first portion filling the second trench and a second portion on the first portion, and the first portion of the second sub-solder ball does not overlap in a direction perpendicular to the thickness direction of the first sub-solder ball and the package substrate, and the first sub-pad and the second sub-pad each include NiAu.

[0009] Specific details of other embodiments are included in the description of the invention and the drawings. Brief explanation of the drawing

[0010] FIG. 1 is an exemplary plan view for illustrating a semiconductor package according to some embodiments. FIG. 2 is an exemplary cross-sectional view taken along line AA of FIG. 1. Figure 3 is an enlarged view of the P2 region of Figure 2. Figure 4 is an enlarged view of the P1 region of Figure 1. FIGS. 5 to 7 are plan views for illustrating semiconductor packages according to some embodiments. FIGS. 8 to 10 are enlarged views for illustrating semiconductor packages according to some embodiments. FIGS. 11 to 14 are enlarged views for illustrating semiconductor packages according to some embodiments. FIGS. 15 to 17 are cross-sectional views illustrating semiconductor packages according to some embodiments. FIG. 18 is a plan view illustrating a semiconductor package according to some embodiments. Figure 19 is a cross-sectional view taken along the BB line of Figure 18. FIGS. 20 to 24 are intermediate drawings for explaining a semiconductor package manufacturing method according to some embodiments. Specific details for implementing the invention

[0011] Hereinafter, a semiconductor package according to exemplary embodiments is described with reference to FIGS. 1 to 19.

[0012] FIG. 1 is an exemplary plan view for illustrating a semiconductor package according to some embodiments. FIG. 2 is an exemplary cross-sectional view cut along line AA of FIG. 1. FIG. 3 is an enlarged view of region P2 of FIG. 2. FIG. 4 is an enlarged view of region P1 of FIG. 1.

[0013] First, referring to FIGS. 1 and FIGS. 2, a semiconductor package (1000) according to some embodiments may include a first semiconductor package (1000a) and a second semiconductor package (1000b) provided on the first semiconductor package (1000a).

[0014] The first semiconductor package (1000a) may include a package substrate (300), a first semiconductor chip (100), a solder resist layer (385), a solder ball (390), and a pad (380).

[0015] The package substrate (300) may include a lower package substrate (300L) and an upper package substrate (300U). The lower package substrate (300L) may be placed below the first semiconductor chip (100). The upper package substrate (300U) may be placed above the first semiconductor chip (100). For example, the lower package substrate (300L) may include a first surface (300a) and a second surface (300b) facing each other. The upper package substrate (300U) and the first semiconductor chip (100) may be placed on the first surface (300a) of the lower package substrate (300L). A solder ball (390) may be placed on the second surface (300b) of the lower package substrate (300L).

[0016] In FIG. 1, the package substrate (300) may include a first region (R1) and a second region (R2) excluding the first region (R1). The first region (R1) may be a central region, and the second region (R2) may be a corner region. For example, if the package substrate (300) has a rectangular shape in a planar view, the second region (R2) may be a corner portion of the rectangular shape. The first region (R1) may be the remaining portion excluding the second region (R2). For example, the second region (R2) may be four, but is not limited thereto.

[0017] In some embodiments, the second region (R2) may have a stepped shape in a planar view. In this specification, the meaning of "having a stepped shape in a planar view" may mean that the boundary line between the second region (R2) and the first region (R1) is stepped. Additionally, the meaning of "having a stepped shape in a planar view" may mean that the solder ball (390) placed in the second region (R2) in a planar view is arranged in a stepped shape. For example, the second sub-solder ball (392) to be described later, placed in the second region (R2), may be arranged in a stepped shape, but is not limited thereto.

[0018] The first semiconductor chip (100) may be provided on the first region (R1). The first semiconductor chip (100) may be mounted on the first surface (300a). The first semiconductor chip (100) may completely overlap the first region (R1) and the package substrate (300) in the thickness direction or in a direction perpendicular to the first surface (300a). The first semiconductor chip (100) may not completely overlap the second region (R2) and the package substrate (300) in the thickness direction. However, the technical concept of the present invention is not limited thereto.

[0019] The lower package substrate (300L) may include a first surface (300a) and a second surface (300b). The first surface (300a) and the second surface (300b) may face each other. The first surface (300a) may face the first semiconductor chip (100). The second surface (300b) may face the solder ball (390).

[0020] In some embodiments, the lower package substrate (300L) may include first to fifth lower insulating layers (310L, 320L, 330L, 340L, 350L). First to fourth redistribution patterns (RDL1, RDL2, RDL3, RDL4) may be disposed within the first to fifth lower insulating layers (310L, 320L, 330L, 340L, 350L).

[0021] For example, the first lower insulating layer (310L) can cover the first redistribution pattern (RDL1). The second lower insulating layer (320L) can cover the via portion of the second redistribution pattern (RDL2). The third lower insulating layer (330L) can cover the wiring portion of the second redistribution pattern (RDL2) and the via portion of the third redistribution pattern (RDL3). The fourth lower insulating layer (340L) can cover the wiring portion of the third redistribution pattern (RDL3). The fifth lower insulating layer (350L) can cover the via portion of the fourth redistribution pattern (RDL4). However, the technical concept of the present invention is not limited thereto.

[0022] The first to fifth lower insulating layers (310L, 320L, 330L, 340L, 350L) may each be made of a photoimageable dielectric. For example, the first to fifth lower insulating layers (310L, 320L, 330L, 340L, 350L) may include a photosensitive polymer. The photosensitive polymer may be formed from at least one of, for example, a photosensitive polyimide, a polybenzoxazole, a phenolic polymer, and a benzocyclobutene-based polymer. As another example, the first to fifth lower insulating layers (310L, 320L, 330L, 340L, 350L) may be formed from a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

[0023] The first to fourth redistribution patterns (RDL1, RDL2, RDL3, RDL4) may include a conductive material. For example, the first to fourth redistribution patterns (RDL1, RDL2, RDL3, RDL4) may include copper (Cu), but are not limited thereto.

[0024] In some embodiments, the lower package substrate (300L) may include an organic material. For example, the lower package substrate (300L) may include a prepreg. A prepreg is a composite fiber in which a reinforcing fiber, such as a carbon fiber, glass fiber, or aramid fiber, is impregnated with a thermosetting polymer binder (e.g., epoxy resin) or a thermoplastic resin. In some embodiments, the lower package substrate (300L) may include a copper clad laminate (CCL). For example, the lower package substrate (300L) may have a structure in which a copper laminate is laminated on one or both sides of a thermosetting prepreg (e.g., a prepreg of C-Stage).

[0025] In some embodiments, the first redistribution pattern (RDL1) may include a first sub-redistribution pattern (RDLa) and a second sub-redistribution pattern (RDLb). The first sub-redistribution pattern (RDLa) may be placed in a first region (R1) of the package substrate (300). The second sub-redistribution pattern (RDLb) may be placed in a second region (R2) of the package substrate (300). That is, the first sub-redistribution pattern (RDLa) may be placed in a central region, and the second sub-redistribution pattern (RDLb) may be placed in a corner region.

[0026] A pad (380) may be placed on a first rewiring pattern (RDL1). A pad (380) may be placed on a second surface (300b). A pad (380) may be connected to the first rewiring pattern (RDL1). In some embodiments, a pad (380) may include a first sub-pad (381) and a second sub-pad (382). A first sub-pad (381) may be placed in a first region (R1). A second sub-pad (382) may be placed in a second region (R2). A first sub-pad (381) may be placed in a central region of the package substrate. A second sub-pad (382) may be placed in a corner region of the package substrate. A first sub-pad (381) may be connected to a first sub-rewiring pattern (RDLa). A second sub-pad (382) may be connected to a second sub-rewiring pattern (RDLb). The pad (380) may include, for example, NiAu, but is not limited thereto.

[0027] A solder ball (390) may be provided on a pad (380). The solder ball (390) may be connected to the pad (380). In some embodiments, the solder ball (390) may include a first sub-solder ball (391) and a second sub-solder ball (392). The first sub-solder ball (391) may be provided on a first region (R1). The second sub-solder ball (392) may be provided on a second region (R2). The first sub-solder ball (391) may be provided on a central region of the package substrate. The second sub-solder ball (392) may be provided on a corner region of the package substrate.

[0028] The first sub-solder ball (391) can be connected to the first sub-pad (381). The second sub-solder ball (392) can be connected to the second sub-pad (382). Although the solder ball (390) is illustrated as having a ball shape, the technical concept of the present invention is not limited thereto. The solder ball (390) can have various shapes such as a land, ball, pin, or pillar. The number, spacing, and arrangement of the solder balls (390) are not limited to what is illustrated and can vary depending on the design. The solder ball (390) may be a solder bump comprising a low-melting-point metal, such as tin (Sn) and a tin (Sn) alloy, but is not limited thereto.

[0029] A solder resist layer (385) may be disposed on the second surface (300b). A solder resist layer (385) may be disposed on the first redistribution pattern (RDL1) and the first lower insulating layer (310L). The solder resist layer (385) may include a solder resist material.

[0030] Hereinafter, with reference to FIG. 3, the solder ball (390), pad (380), first redistribution pattern (RDL1), and solder resist layer (385) will be described in more detail. FIG. 3 is an enlarged view of the P2 region of FIG. 2.

[0031] Referring to FIG. 3, the first redistribution pattern (RDL1) includes a first sub-redistribution pattern (RDLa) and a second sub-redistribution pattern (RDLb). The pad (380) includes a first sub-pad (381) and a second sub-pad (382). The solder ball (390) includes a first sub-solder ball (391) and a second sub-solder ball (392).

[0032] In some embodiments, the second sub-rewiring pattern (RDLb) may include a second trench (t2). The second trench (t2) may not expose the lower package substrate (300L). The second trench (t2) may expose the second sub-rewiring pattern (RDLb). The first sub-rewiring pattern (RDLa) does not include the second trench (t2). That is, the top surface of the first sub-rewiring pattern (RDLa) is flat. On the other hand, the top surface of the second sub-rewiring pattern (RDLb) is not flat. The top surface of the first sub-rewiring pattern (RDLa) may lie in a co-plane with the second surface (300b).

[0033] The first sub-pad (381) may be positioned along the upper surface of the first sub-rewiring pattern (RDLa). Accordingly, the upper surface of the first sub-pad (381) may be flat. The second sub-pad (382) may be positioned along the upper surface of the second sub-rewiring pattern (RDLb). The second sub-pad (382) may be positioned along the sidewall and bottom surface of the second trench (t2). The bottom surface of the first trench (t1) may face the first surface (300a). The bottom surface of the second trench (t2) may face the first surface (300a). The bottom surface of the second trench (t2) may face the second sub-solder ball (392). The second sub-pad (382) may define the solder ball recess (RC). The solder ball recess (RC) may include the remaining portion of the second trench (t2) after the second sub-pad (382) is formed.

[0034] In some embodiments, the thickness of the pad (380) may be constant. The thickness of the first sub-pad (381) may be constant. The thickness of the second sub-pad (382) may be constant. The pad (380) may be formed conformally on the first redistribution pattern (RDL1). However, the technical concept of the present invention is not limited thereto.

[0035] The solder resist layer (385) may include a first trench (t1). The first trench (t1) may expose a first redistribution pattern (RDL1). A pad (380) and a solder ball (390) may be disposed within the first trench (t1). A first sub-pad (381) may extend along the bottom surface of the first trench (t1). A second sub-pad (382) may extend along the bottom surface of the first trench (t1), the side wall of the second trench (t2), and the bottom surface of the second trench (t2).

[0036] A solder ball (390) may be provided on a pad (380). A first sub-solder ball (391) is placed on a first sub-pad (381). The first sub-solder ball (391) is connected to the first sub-pad (381). A second sub-solder ball (392) is placed on a second sub-pad (382). The second sub-solder ball (392) is connected to the second sub-pad (382). In some embodiments, at least a portion of the second sub-solder ball (392) may be placed within a solder ball recess (RC). At least a portion of the second sub-solder ball (392) may be placed within a second trench (t2).

[0037] In some embodiments, the second sub-solder ball (392) may include a first portion (392a) and a second portion (392b). The first portion (392a) of the second sub-solder ball (392) may be placed within a solder ball recess (RC). The first portion (392a) of the second sub-solder ball (392) may be placed within a second trench (t2). The second portion (392b) of the second sub-solder ball (392) may be placed on the first portion (391b).

[0038] As a portion of the second sub-solder ball (392) is disposed within the solder ball recess (RC), the contact area between the second sub-solder ball (392) and the second sub-pad (382) can be increased. Accordingly, if a crack occurs, the progression of the crack can be prevented. Accordingly, a semiconductor package with improved reliability can be provided.

[0039] A portion of the first part (392a) of the second sub-solder ball (392) may overlap with the second sub-rewiring pattern (RDLb) in the first direction. The first direction may be a direction perpendicular to the thickness direction of the package substrate (300). A portion of the first part (392a) of the second sub-solder ball (392) may overlap with the first sub-rewiring pattern (RDLa) in the first direction. The first part (392a) of the second sub-solder ball (392) does not completely overlap with the first sub-solder ball (391) in the first direction. The first sub-solder ball (391) does not overlap with the first sub-rewiring pattern (RDLa) in the first direction. The first sub-solder ball (391) does not overlap with the second sub-rewiring pattern (RDLb) in the first direction. However, the technical concept of the present invention is not limited thereto.

[0040] Hereinafter, the first trench (t1) and the second trench (t2) according to some embodiments will be described in more detail with reference to FIG. 4. FIG. 4 is an enlarged view of the P1 area of ​​FIG. 1. For convenience of explanation, the second sub-solder ball (392) and the second sub-pad (382) are omitted in FIG. 4.

[0041] Referring to FIG. 4, a second trench (t2) may be formed within a first trench (t1). From a planar perspective, the shape of the second trench (t2) may be part of a sector shape. For example, from a planar perspective, the shape of the second trench (t2) may be the shape obtained by subtracting a second sector having a second radius (r2) from a first sector having a first radius (r1). In this case, the central angle (θ) of the first sector and the central angle (θ) of the second sector may be the same. The first radius (r1) may be larger than the second radius (r2). However, the technical concept of the present invention is not limited thereto.

[0042] In some embodiments, the second trench (t2) may not be formed in the center region of the first trench (t1). That is, the second trench (t2) may not be formed at the center (C) of the first trench (t1), but is not limited thereto.

[0043] Although FIG. 4 shows six second trenches (t2), the technical concept of the present invention is not limited thereto. The number, shape, and arrangement of the second trenches (t2) can be varied in many ways depending on the design.

[0044] Referring again to FIG. 2, a semiconductor package (1000) according to some embodiments may further include a plurality of metal pillars (360), a molding film (370), a plurality of first chip pads (111), and a plurality of first connection terminals (150).

[0045] The first chip pads (111) may be provided on the lower surface of the first semiconductor chip (100). The lower surface of the first semiconductor chip (100) may be positioned to face the first surface (300a). The first chip pads (111) of the first semiconductor chip (100) may be connected to the fourth rewiring pattern (RDL4).

[0046] The first connection terminals (150) may be attached between the first chip pads (111) of the first semiconductor chip (100) and the lower fourth redistribution pattern (RDL4). The first semiconductor chip (100) and the solder ball (390) may be electrically connected through the first connection terminals (150). The first connection terminals (150) may be solder bumps comprising a low melting point metal, such as tin (Sn) and tin (Sn) alloy, but are not limited thereto. The first connection terminals (150) may have various shapes such as land, ball, pin, and pillar. The first connection terminals (150) may be formed as a single layer or multiple layers. When the first connection terminals (150) are formed as a single layer, the first connection terminals (150) may, for example, include tin-silver (Sn-Ag) solder or copper (Cu). When the first connection terminals (150) are formed in multiple layers, the first connection terminals (150) may, for example, include copper (Cu) filler and solder. The number, spacing, arrangement, etc. of the first connection terminals (150) are not limited to those illustrated and may vary depending on the design.

[0047] Metal pillars (360) may be provided around the first semiconductor chip (100). The metal pillars (360) may electrically connect the lower package substrate (300L) and the upper package substrate (300U). The metal pillars (360) may penetrate the molding film (370). The upper surface of the metal pillars (360) may be in a co-plane with the upper surface of the molding film (370). The lower surface of the metal pillars (360) may be in contact with the fourth redistribution patterns (RDL4) of the lower package substrate (300L).

[0048] A molding film (370) may be provided between a lower package substrate (300L) and an upper package substrate (300U). The molding film (370) may cover the first semiconductor chip (100). The molding film (370) may be provided on a first surface (300a). The molding film (370) may cover the sidewalls and the top surface of the first semiconductor chip (100). The molding film (370) may fill the spaces between the metal pillars (360). The thickness of the molding film (370) may be substantially the same as the thickness of the metal pillars (360). The molding film (370) may comprise an insulating polymer, such as an epoxy-based molding compound.

[0049] The upper package substrate (300U) may include first to third upper insulating layers (310U, 320U, 330U) and upper redistribution patterns (RDL_U) within the first to third upper insulating layers (310U, 320U, 330U). The first to third upper insulating layers (310U, 320U, 330U) may include the same material as the material included in the first to fifth lower insulating layers (310L, 320L, 330L, 340L, 350L). The upper redistribution patterns (RDL_U) may include the same material as the first to fourth redistribution patterns (RDL1, RDL2, RDL3, RDL4).

[0050] A second semiconductor package (1000b) may be disposed on an upper package substrate (300U). The second semiconductor package (1000b) may include a circuit board (410), a second semiconductor chip (200), and an upper molding film (430). The circuit board (410) may be a printed circuit board, but is not limited thereto. A lower conductive pad (405) may be disposed on the lower surface of the circuit board (410).

[0051] A second semiconductor chip (200) may be placed on a circuit board (410). The second semiconductor chip (200) may include integrated circuits. The integrated circuits may include memory circuits, logic circuits, or a combination thereof. The second chip pads (221) of the second semiconductor chip (200) may be electrically connected to an upper conductive pad (403) on the upper surface of the circuit board (410) by wire bonding. The upper conductive pad (403) on the upper surface of the circuit board (410) may be electrically connected to a lower conductive pad (405) through internal wiring within the circuit board (410).

[0052] The upper molding film (430) may be provided on the circuit board (410). The upper molding film (430) may cover the second semiconductor chip (200). The upper molding film (430) may include an insulating polymer such as an epoxy-based polymer.

[0053] A semiconductor package (1000) according to some embodiments may further include a plurality of second connection terminals (450). The second connection terminals (450) may be provided between the lower conductive pad (405) of the circuit board (410) and the upper redistribution patterns (RLD_U). The second connection terminals (450) may be solder bumps comprising a low melting point metal, e.g., tin (Sn) and tin (Sn) alloy, but are not limited thereto. The second connection terminals (450) may have various shapes such as land, ball, pin, pillar, etc. The second connection terminals (450) may be formed as a single layer or a multilayer. When the second connection terminals (450) are formed as a single layer, the second connection terminals (450) may, for example, include tin-silver (Sn-Ag) solder or copper (Cu). When the second connection terminals (450) are formed in multiple layers, the second connection terminals (450) may, for example, include copper (Cu) filler and solder. The number, spacing, arrangement, etc. of the second connection terminals (450) are not limited to those illustrated and may vary depending on the design.

[0054] FIGS. 5 to 7 are plan views illustrating semiconductor packages according to some embodiments. Hereinafter, various embodiments of the semiconductor package will be described with reference to FIGS. 5 to 7.

[0055] Referring to FIG. 5, the second region (R2) may have a three-story staircase shape from a planar perspective. That is, the area of ​​the second region (R2) may be increased. Six second sub-solder balls (392) may be placed in the second region (R2). As the area of ​​the second region (R2) increases, the progression of the crack can be prevented more effectively if a crack occurs. Alternatively, as the number of second sub-solder balls (392) placed in the second region (R2) increases, the progression of the crack can be prevented more effectively if a crack occurs.

[0056] Referring to FIG. 6, the second region (R2) may have a five-layer stepped shape in a planar view. That is, the area of ​​the second region (R2) may be further increased. Additionally, the second region (R2) may include an area that overlaps in the thickness direction of the first semiconductor chip (100) and the package substrate (300). Some of the second sub-solder balls (392) may overlap in the thickness direction of the first semiconductor chip (100) and the package substrate (300).

[0057] In some embodiments, a portion of the boundary line of the second region (R2) may be in contact with the boundary line of an adjacent second region (R2). However, the technical concept of the present invention is not limited thereto.

[0058] Referring to FIG. 7, the shape of the second region (R2) in a planar view may not be a stepped shape. For example, the shape of the second region (R2) in a planar view may be a square. Although not shown in the drawing, the shape of the second region (R2) in a planar view may be a rectangle. The second region (R2) does not overlap the thickness direction of the first semiconductor chip (100) and the package substrate (300).

[0059] FIGS. 8 to 10 are enlarged views illustrating semiconductor packages according to some embodiments. Hereinafter, various embodiments of the semiconductor package will be described with reference to FIGS. 8 to 10.

[0060] Referring to FIG. 8, the second sub-rewiring pattern (RDLb) does not include the second trench (t2).

[0061] A solder ball recess (RC) may be formed within the second sub-pad (382). The solder ball recess (RC) does not expose the second sub-rewiring pattern (RDLb). A first portion (392a) of the second sub-solder ball (392) is placed within the solder ball recess (RC). The first portion (392a) of the second sub-solder ball (392) does not overlap with the first sub-pad (381) in the first direction. The first direction may be a direction perpendicular to the thickness direction of the package substrate. The first portion (392a) of the second sub-solder ball (392) does not overlap with the second sub-pad (382) in the first direction.

[0062] In some embodiments, the thickness of the second sub-pad (382) may not be constant. The thickness of the second sub-pad (382) in the portion where the solder ball recess (RC) is formed may be smaller than the thickness of the second sub-pad (382) in the portion where the solder ball recess (RC) is not formed.

[0063] Referring to FIG. 9, the second trench (t2) can expose the package substrate. The second trench (t2) can expose the lower package substrate (300L in FIG. 2). The second trench (t2) can expose the second lower insulating layer (320L).

[0064] The upper surface of the second sub-pad (382) and the second lower insulating layer (320L) defines a solder ball recess (RC). The solder ball recess (RC) may expose the package substrate. The solder ball recess (RC) may expose the lower package substrate (300L in FIG. 2). The solder ball recess (RC) may expose the second lower insulating layer (320L).

[0065] The second sub-pad (382) may not extend along the bottom surface of the second trench (t2). The second sub-pad (382) may extend along the bottom surface of the first trench (t1) and the side wall of the second trench (t2).

[0066] A first portion (392a) of the second sub-solder ball (392) is placed within the solder ball recess (RC). At least a portion of the first portion (392a) of the second sub-solder ball (392) may be in contact with the second lower insulating layer (320L).

[0067] Referring to FIG. 10, the second trench (t2) may expose the package substrate. The second trench (t2) may expose the lower package substrate (300L in FIG. 2). The second trench (t2) may expose the second lower insulating layer (320L). However, the solder ball recess (RC) does not expose the package substrate. The solder ball recess (RC) does not expose the lower package substrate (300L in FIG. 2). The solder ball recess (RC) does not expose the second lower insulating layer (320L).

[0068] The second sub-pad (382) may extend along the bottom surface of the first trench (t1), the side wall of the second trench (t2), and the bottom surface of the second trench (t2). At least a portion of the second sub-pad (382) may be in contact with the second lower insulating layer (320L).

[0069] FIGS. 11 to 14 are enlarged views for illustrating semiconductor packages according to some embodiments. Using FIGS. 11 to 14, various shapes of the second trench (t2) are described from a planar perspective.

[0070] Referring to FIG. 11, the shape of the second trench (t2) may be circular from a planar perspective. The second trenches (t2) may be formed at positions spaced apart by the same distance from the center (C) of the first trench (t1). Although the spacing between each second trench (t2) and the area of ​​each second trench (t2) are depicted as being equal, the technical concept of the present invention is not limited thereto. The arrangement, spacing, size, etc. of the second trenches (t2) may vary depending on the design.

[0071] Referring to FIG. 12, the second trench (t2) may be formed in the center area of ​​the first trench (t1). The second trench (t2) may be formed six times in the outer area of ​​the first trench (t1) and one time in the center area of ​​the first trench (t1).

[0072] Referring to FIG. 13, the shape of the second trench (t2) may be square from a planar perspective. The second trenches (t2) may be formed at positions spaced apart from the center (C) of the first trench (t1) by the same distance. Although the spacing between each second trench (t2) and the area of ​​each second trench (t2) are depicted as being equal, the technical concept of the present invention is not limited thereto. The arrangement, spacing, size, etc. of the second trenches (t2) may vary depending on the design.

[0073] Referring to FIG. 14, the shape of the second trench (t2) may be rectangular from a planar perspective. Each second trench (t2) may include a long side and a cross-section. In some embodiments, the direction in which the long side of each second trench (t2) extends may differ. For example, two of the second trenches (t2) may extend in a horizontal direction, and four of the second trenches (t2) may extend in a direction that forms a certain angle with the horizontal direction. However, the technical concept of the present invention is not limited thereto.

[0074] FIGS. 15 to 17 are cross-sectional views illustrating semiconductor packages according to some embodiments. Hereinafter, various embodiments of the semiconductor package will be described. For convenience of explanation, the description will focus on the differences from the description using FIGS. 1 to 4. For reference, FIGS. 15 to 17 may be cross-sectional views cut along line AA of FIG. 1.

[0075] Referring to FIG. 15, unlike the embodiment shown in FIG. 2, a package substrate (300) may be formed on the active surface of the first semiconductor chip (100).

[0076] A lower package substrate (300L) can be placed directly on the first chip pads (111) of the first semiconductor chip (100). The lower package substrate (300L) can be in contact with the first chip pads (111) of the first semiconductor chip (100). First to fifth lower insulating layers (310L, 320L, 330L, 340L, 350L) can be laminated on the first chip pads (111) of the first semiconductor chip (100). First to fourth redistribution patterns (RDL1, RDL2, RDL3, RDL4) can be placed within the first to fifth lower insulating layers (310L, 320L, 330L, 340L, 350L).

[0077] For example, the via portion of the first redistribution pattern (RDL1) may be provided within the second lower insulating layer (320L). The wiring portion of the second redistribution pattern (RDL2) may be provided within the second lower insulating layer (320L). The via portion of the second redistribution pattern (RDL2) may be provided within the third lower insulating layer (330L). The wiring portion of the third redistribution pattern (RDL3) may be provided within the third lower insulating layer (330L). The via portion of the third redistribution pattern (RDL3) may be provided within the third lower insulating layer (330L). The fourth redistribution pattern (RDL4) may be provided within the fourth lower insulating layer (340L).

[0078] In some embodiments, via portions of the fourth rewiring pattern (RDL4) may be connected to the first chip pads (111) of the first semiconductor chip (100). The via portions of the fourth rewiring pattern (RDL4) may be connected to metal pillars (360). In some embodiments, via portions of the first to fourth rewiring patterns (RDL1, RDL2, RDL3, RDL4) may be disposed on the upper surface of the wiring portions of each of the first to fourth rewiring patterns (RDL1, RDL2, RDL3, RDL4). For example, via portions of the first to fourth rewiring patterns (RDL1, RDL2, RDL3, RDL4) may extend toward the first surface (300a) from the upper surface of each of the wiring portions.

[0079] Referring to FIG. 16, the second semiconductor package (1000b) may include two second semiconductor chips (200a, 200b). That is, the second semiconductor chip may include a first sub-semiconductor chip (200a) and a second sub-semiconductor chip (200b).

[0080] The first sub-semiconductor chip (200a) and the second sub-semiconductor chip (200b) may be spaced apart from each other. The first sub-semiconductor chip (200a) and the second sub-semiconductor chip (200b) may be separated from each other by an upper molding film (430). Each of the first sub-semiconductor chip (200a) and the second sub-semiconductor chip (200b) may include second chip pads (221) on its lower surface. The second semiconductor package (1000b) does not include an upper conductive pad (403). For example, the second chip pads (221) may be electrically connected to the lower conductive pad (405) through internal wiring (415) within the circuit board (410).

[0081] Although the first and second sub-semiconductor chips (200a, 200b) are shown as being provided at the same level on the upper surface of the circuit board (410) in FIG. 16, the first sub-semiconductor chip (200a) and the second sub-semiconductor chip (200b) may be sequentially stacked on the upper surface of the circuit board (410).

[0082] Referring to FIG. 17, unlike the embodiment shown in FIG. 2, the upper package substrate may be omitted in the first semiconductor package (1000a).

[0083] More specifically, an upper insulating layer (375) may be provided on the molding film (370). The upper insulating layer (375) may include an insulating material. For example, the upper insulating layer (375) may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric (low-k) material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0084] The second connection terminals (450) may be provided between the lower conductive pad (405) of the circuit board (410) and the metal pillars (360) of the first semiconductor package (1000a). A portion of the second connection terminals (450) may be disposed within the upper insulating layer (375). One side of the second connection terminals (450) may be connected to the lower conductive pad (405), and the other side of the second connection terminals (450) may be connected to the metal pillars (360). Accordingly, the first semiconductor package (1000a) and the second semiconductor package (1000b) may be electrically connected.

[0085] The second semiconductor chip (200) may be placed on a circuit board (410). The second chip pads (221) of the second semiconductor chip (200) may be in contact with the upper surface of the circuit board (410). The second chip pads (221) of the second semiconductor chip (200) may be electrically connected to a lower conductive pad (405) through internal wiring (415) within the circuit board (410).

[0086] FIG. 18 is a plan view illustrating a semiconductor package according to some embodiments. FIG. 19 is a cross-sectional view taken along the BB line of FIG. 18. Below, various embodiments of the semiconductor package are described.

[0087] Referring to FIGS. 18 and 19, a semiconductor package (2000) according to some embodiments may include a package substrate (500), a first redistribution pattern (RDL1), a pad (380), a solder ball (390), a solder resist layer (385), an interposer substrate (610), a third semiconductor chip (700a), and a fourth semiconductor chip (700b). Since the first redistribution pattern (RDL1), the pad (380), the solder ball (390), and the solder resist layer (385) may be the same as those described using FIGS. 1 to 4, a detailed description is omitted.

[0088] In FIG. 18, the package substrate (500) may include a first region (R1) and a second region (R2). The first region (R1) may be a central region, and the second region (R2) may be a corner region. From a planar perspective, the second region (R2) may have a stepped shape.

[0089] The third semiconductor chip (700a) and the fourth semiconductor chip (700b) may be provided on the second region (R2). The third semiconductor chip (700a) and the fourth semiconductor chip (700b) may not be provided on the first region (R1).

[0090] In some embodiments, the third semiconductor chip (700a) may be a logic semiconductor chip. For example, the first semiconductor chip (310) may be an application processor (AP) such as a CPU (Central Processing Unit), GPU (Graphic Processing Unit), FPGA (Field-Programmable Gate Array), digital signal processor, encryption processor, microprocessor, microcontroller, or ASIC (Application-Specific IC), but is not limited thereto.

[0091] In some embodiments, the fourth semiconductor chip (700b) may be a memory semiconductor chip. For example, the fourth semiconductor chip (700b) may be a volatile memory such as DRAM (dynamic random access memory) or SRAM (static random access memory), or a non-volatile memory such as Flash Memory, PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory).

[0092] For example, the first semiconductor chip (700a) may be an ASIC such as a GPU, and the second semiconductor chip (700b) may be a stacked memory such as High Bandwidth Memory (HBM). This stacked memory may be in the form of multiple integrated circuits stacked together. The stacked integrated circuits may be electrically connected to each other through TSVs (Through Silicon Via), etc.

[0093] The package substrate (500) may be a substrate for packaging. The package substrate (500) may be a printed circuit board (PCB). The package substrate (500) may include a lower surface and an upper surface opposite each other. The upper surface of the package substrate (500) may face the interposer substrate (610).

[0094] The package substrate (500) may include a substrate pad (504). The substrate pad (504) may be used to electrically connect the package substrate (500) to other components. For example, the substrate pad (504) may be exposed from the upper surface of the package substrate (500). The substrate pad (504) may electrically connect the first redistribution pattern (RDL1) and the third connection terminal (650) through internal wiring (505). The substrate pad (504) may include a metallic material such as copper (Cu) or aluminum (Al), for example, but is not limited thereto.

[0095] In some embodiments, the package substrate (500) may include a copper clad laminate (CCL). For example, the package substrate (500) may have a structure in which a copper laminate is laminated on one or both sides of a heat-cured prepreg (e.g., prepreg of a C-Stage).

[0096] An interposer substrate (610) may be disposed on the upper surface of a package substrate (500). The interposer substrate (610) may include a lower surface and an upper surface that are opposite to each other. The upper surface of the interposer substrate (610) may face the third and fourth semiconductor chips (700a, 700b). The lower surface of the interposer substrate (610) may face the package substrate (500). The interposer substrate (610) can facilitate the connection between the package substrate (500) and the third and fourth semiconductor chips (700a, 700b) and prevent warpage of the semiconductor package (2000). The interposer substrate (610) may be, for example, a silicon (Si) interposer, but is not limited thereto.

[0097] A semiconductor package (2000) according to some embodiments may include an interlayer insulating layer (620), a first passivation film (630), a second passivation film (635), wiring patterns (640), through-vias (645), a first interposer pad (602), and a second interposer pad (604).

[0098] An interlayer insulating layer (620) may be disposed on an interposer substrate (610). The interlayer insulating layer (620) may include an insulating material. For example, the interlayer insulating layer (620) may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-dielectric (low-k) material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0099] The first interposer pad (602) and the second interposer pad (604) can each be used to electrically connect with other components. For example, the first interposer pad (602) may be exposed from the lower surface of the interposer substrate (610), and the second interposer pad (604) may be exposed from the upper surface of the interlayer insulating layer (620). The first interposer pad (602) and the second interposer pad (604) may include a metallic material such as copper (Cu) or aluminum (Al), for example, but are not limited thereto. Wiring patterns for electrically connecting the first interposer pad (602) and the second interposer pad (604) may be formed within the interposer substrate (610) and the interlayer insulating layer (620).

[0100] For example, through-vias (645) may be formed within the interposer substrate (610). Wiring patterns (640) may be formed within the interlayer insulating layer (620). The through-vias (645) may penetrate the interposer substrate (610). As a result, the wiring patterns (640) and the through-vias (645) may be connected to each other. The wiring patterns (640) may be electrically connected to the second interposer pad (604). The through-vias (645) may be electrically connected to the first interposer pad (602). Through this, the package substrate (500), the third semiconductor chip (700a), and the fourth semiconductor chip (700b) may be electrically connected. The redistribution layers (240) and the through-vias (245) may each include a metallic material such as copper (Cu) or aluminum (Al), but are not limited thereto.

[0101] A third connection terminal (650) may be formed between the package substrate (500) and the interposer substrate (610). The third connection terminal (650) may connect the substrate pad (504) and the first interposer pad (602). Accordingly, the package substrate (500) and the interposer substrate (610) may be electrically connected.

[0102] The third connection terminal (650) may be a solder bump comprising a low-melting-point metal, such as tin (Sn) and tin (Sn) alloy, but is not limited thereto. The third connection terminal (650) may have various shapes such as a land, ball, pin, or pillar. The third connection terminal (650) may be formed as a single layer or a multilayer. When the third connection terminal (650) is formed as a single layer, the third connection terminal (650) may, for example, include tin-silver (Sn-Ag) solder or copper (Cu). When the third connection terminal (650) is formed as a multilayer, the third connection terminal (650) may, for example, include copper (Cu) filler and solder. The number, spacing, and arrangement of the third connection terminals (650) are not limited to those illustrated and may vary depending on the design.

[0103] The first passivation film (630) may be disposed on the interlayer insulating layer (620). The first passivation film (630) may extend along the upper surface of the interlayer insulating layer (620). The second interposer pad (604) may penetrate the first passivation film (630) and be connected to the wiring patterns (640). The second passivation film (635) may be disposed on the interposer substrate (610). The second passivation film (635) may extend along the lower surface of the interposer substrate (610). The first interposer pad (602) may penetrate the second passivation film (635) and be connected to the through-via (645).

[0104] The first passivation film (630) and the second passivation film (635) may each comprise silicon nitride. Alternatively, the first passivation film (630) and the second passivation film (635) may each be composed of a passivation material, BCB (benzocyclobutene), polybenzene oxazole, polyimide, epoxy, silicon oxide, silicon nitride, or a combination thereof.

[0105] In some embodiments, a first underfill (660) may be formed between the package substrate (500) and the interposer substrate (610). The first underfill (660) may fill the space between the package substrate (500) and the interposer substrate (610). Additionally, the first underfill (660) may cover the third connection terminal (650). The first underfill (660) may prevent breakage of the interposer substrate (610) by fixing the interposer substrate (610) on the package substrate (500). The first underfill (660) may include, for example, an insulating polymer material such as an EMC (epoxy molding compound), but is not limited thereto.

[0106] The third semiconductor chip (700a) and the fourth semiconductor chip (700b) may be spaced apart from each other and placed on the upper surface of the interposer substrate (610). The third semiconductor chip (700a) and the fourth semiconductor chip (700b) may each be an integrated circuit (IC) in which hundreds to millions or more semiconductor elements are integrated into a single chip.

[0107] The third semiconductor chip (700a) may include third chip pads (712). The third chip pads (712) may be used to electrically connect the third semiconductor chip (700a) to other components. For example, the third chip pads (712) may be exposed from the bottom surface of the third semiconductor chip (700a).

[0108] The fourth semiconductor chip (700b) may include fourth chip pads (714). The fourth chip pads (714) may be used to electrically connect the fourth semiconductor chip (700b) to other components. For example, the fourth chip pads (714) may be exposed from the bottom surface of the fourth semiconductor chip (700b).

[0109] The third chip pads (712) and the fourth chip pads (714) may each include a metallic material such as copper (Cu) or aluminum (Al), for example, but are not limited thereto.

[0110] The third semiconductor chip (700a) and the fourth semiconductor chip (700b) can be mounted on the upper surface of the interlayer insulating layer (620). For example, a fourth connection terminal (752) can be formed between the interlayer insulating layer (620) and the third semiconductor chip (700a). The fourth connection terminal (752) can connect some of the plurality of second interposer pads (604) with the third chip pads (712). Accordingly, the interposer substrate (610) and the third semiconductor chip (700a) can be electrically connected.

[0111] Additionally, for example, a fifth connection terminal (754) may be formed between the interlayer insulating layer (620) and the fourth semiconductor chip (700b). The fifth connection terminal (754) may connect the fourth chip pads (714) with some of the other parts of the plurality of second interposer pads (604). Accordingly, the interposer substrate (610) and the fourth semiconductor chip (700b) may be electrically connected.

[0112] The fourth connection terminal (752) and the fifth connection terminal (754) may each be solder bumps comprising a low-melting-point metal, such as tin (Sn) and tin (Sn) alloy, but are not limited thereto. The fourth connection terminal (752) and the fifth connection terminal (754) may each have various shapes such as land, ball, pin, and pillar. Additionally, the fourth connection terminal (752) and the fifth connection terminal (754) may each include UBM (Under Bump Metallurgy).

[0113] The fourth connection terminal (752) and the fifth connection terminal (754) may each be formed as a single layer or a multilayer. When the fourth connection terminal (752) and the fifth connection terminal (754) are each formed as a single layer, the fourth connection terminal (752) and the fifth connection terminal (754) may each, for example, include tin-silver (Sn-Ag) solder or copper (Cu). When the fourth connection terminal (752) and the fifth connection terminal (754) are each formed as a multilayer, the fourth connection terminal (752) and the fifth connection terminal (754) may each, for example, include copper (Cu) filler and solder. However, the technical concept of the present invention is not limited thereto, and the number, spacing, arrangement shape, etc., of the fourth connection terminal (752) and the fifth connection terminal (754) are not limited to those illustrated and may vary depending on the design.

[0114] In some embodiments, a portion of the wiring patterns (640) may electrically connect the fourth connection terminal (752) and the fifth connection terminal (754). For example, a portion of the wiring patterns (640) may be connected to a second interposer pad (604) connected to the fourth connection terminal (752), and may also be connected to a second interposer pad (604) connected to the fifth connection terminal (754). Accordingly, the third semiconductor chip (700a) and the second semiconductor chip (700b) may be electrically connected.

[0115] In some embodiments, a second underfill (762) may be formed between the interlayer insulating layer (620) and the third semiconductor chip (700a). A third underfill (764) may be formed between the interlayer insulating layer (620) and the fourth semiconductor chip (700b). The second underfill (762) may fill the space between the interlayer insulating layer (620) and the third semiconductor chip (700a). The third underfill (764) may fill the space between the interlayer insulating layer (620) and the fourth semiconductor chip (700b). Additionally, the second underfill (762) may cover the fourth connection terminal (752). The third underfill (764) may cover the fifth connection terminal (754).

[0116] The second underfill (762) and the third underfill (764) can prevent breakage, etc. of the third and fourth semiconductor chips (700a, 700b) by fixing the third and fourth semiconductor chips (700a, 700b) on the interposer substrate (610). The second underfill (762) and the third underfill (764) may each include an insulating polymer material such as, for example, EMC, but are not limited thereto.

[0117] The mold layer (800) may be disposed on the interposer substrate (610). The mold layer (800) may be provided between the third semiconductor chip (700a) and the fourth semiconductor chip (700b). The mold layer (800) may separate the third semiconductor chip (700a) and the fourth semiconductor chip (700b) from each other.

[0118] The mold layer (800) may include, for example, an insulating polymer material such as EMC, but is not limited thereto. The mold layer (800) may include a material different from the first underfill (660), the second underfill (762), and the third underfill (764). For example, the first underfill (660), the second underfill (762), and the third underfill (764) may each include an insulating material having better fluidity than the mold layer (800). Accordingly, the first underfill (660), the second underfill (762), and the third underfill (764) can efficiently fill the narrow space between the package substrate (500) and the interposer substrate (610) or between the interlayer insulating layer (620) and the third and fourth semiconductor chips (700a, 700b).

[0119] A semiconductor package (2000) according to some embodiments may further include an adhesive layer (850) and a heat slug (900).

[0120] An adhesive layer (850) may be provided on a mold layer (800). An adhesive layer (850) may be provided on a third semiconductor chip (700a) and a fourth semiconductor chip (700b). The adhesive layer (850) may be in contact with the upper surface of the mold layer (800). The adhesive layer (850) may be in contact with the upper surface of the third semiconductor chip (700a) and the upper surface of the fourth semiconductor chip (700b). The adhesive layer (850) may bond and fix the mold layer (800), the third semiconductor chip (700a), and the fourth semiconductor chip (700b) and the heat slug (900) to each other. The adhesive layer (850) may include an adhesive material. For example, the adhesive layer (850) may include a curable polymer. The adhesive layer (850) may include, for example, an epoxy-based polymer.

[0121] The heat slug (900) may be placed on the package substrate (500). The heat slug (900) may cover the third semiconductor chip (700a) and the fourth semiconductor chip (700b). The heat slug (900) may include a metallic material, but is not limited thereto.

[0122] Hereinafter, a method for manufacturing a semiconductor package according to several embodiments will be described with reference to FIGS. 20 to 24.

[0123] FIGS. 20 to 24 are intermediate drawings for explaining a method for manufacturing a semiconductor package according to some embodiments. For reference, FIGS. 20 to 24 are drawings illustrating a method for forming a pad (380), a first redistribution pattern (RDL1), a solder resist layer (385), and a solder ball (390) of a semiconductor package.

[0124] Referring to FIG. 20, a first lower insulating layer (310L), a first sub-rewiring pattern (RDLa), and a free second sub-rewiring pattern (RDLb_p) may be formed on a second lower insulating layer (320L). The free second sub-rewiring pattern (RDLb_p) may include, for example, copper (Cu), but is not limited thereto.

[0125] The first lower insulating layer (310L) and the second lower insulating layer (320L) may be components of the package substrate. The first lower insulating layer (310L) may be provided between the first sub-rewiring pattern (RDLa) and the free second sub-rewiring pattern (RDLb_p).

[0126] A pre-solder resist layer (385P) may be formed on the first lower insulating layer (310L), the first sub-rewiring pattern (RDLa), and the pre-second sub-rewiring pattern (RDLb_p). The pre-solder resist layer (385P) may cover the first lower insulating layer (310L), the first sub-rewiring pattern (RDLa), and the pre-second sub-rewiring pattern (RDLb_p). The pre-solder resist layer (385P) may include, for example, a silver solder resist material.

[0127] Referring to FIG. 21, a first trench (t1) can be formed. The first trench (t1) can be formed by etching the pre-solder resist layer (385P). A solder resist layer (385) can be formed by etching the pre-solder resist layer (385P). The solder resist layer (385) may include the first trench (t1).

[0128] The first trench (t1) can expose the first sub-rewiring pattern (RDLa). The first trench (t1) can expose the free second sub-rewiring pattern (RDLb_p). The first trench (t1) does not expose the first lower insulation layer (310L).

[0129] Referring to FIG. 22, a second trench (t2) can be formed. The second trench (t2) can be formed by etching the free second sub-rewiring pattern (RDLb_p). The second sub-rewiring pattern (RDLb) can be formed by etching the free second sub-rewiring pattern (RDLb_p). The first sub-rewiring pattern (RDLa) and the second sub-rewiring pattern (RDLb) can form the first rewiring pattern (RDL1).

[0130] The second sub-rewiring pattern (RDLb) may include a second trench (t2). The second trench (t2) does not expose the package substrate. The second trench (t2) does not expose the second lower insulating layer (320L). However, the technical concept of the present invention is not limited thereto. Depending on the embodiment, the second trench (t2) may expose the package substrate.

[0131] Referring to FIG. 23, a pad (380) may be formed. The pad (380) may include a first sub-pad (381) and a second sub-pad (382).

[0132] A first sub-pad (381) may be formed along the bottom surface of the first trench (t1). The first sub-pad (381) may be formed on the first sub-rewiring pattern (RDLa). A second sub-pad (382) may be formed along the bottom surface of the first trench (t1), the sidewall of the second trench (t2), and the bottom surface of the second trench (t2). The second sub-pad (382) may be formed on the second sub-rewiring pattern (RDLb). The second sub-pad (382) may define a solder ball recess (RC). The first sub-pad (381) and the second sub-pad (382) may each include NiAu.

[0133] Referring to FIG. 24, a solder ball (390) may be formed. The solder ball (390) may include a first sub-solder ball (391) and a second sub-solder ball (392). The first sub-solder ball (391) may be formed on a first sub-pad (381). The second sub-solder ball (392) may be formed on a second sub-pad (382).

[0134] In some embodiments, the second sub-solder ball (392) comprises a first portion (392a) and a second portion (392b). The first portion (392a) may be interposed within a solder ball recess (RC). The second portion (392b) may be disposed on the first portion (392a).

[0135] According to some embodiments, a semiconductor package may be provided with improved reliability as it includes a solder ball recess (RC) and has a structure in which a portion of a second sub-solder ball (392) is disposed within the solder ball recess (RC). Specifically, the contact area between the second sub-solder ball (392) and the second sub-pad (382) may be increased. Accordingly, if a crack occurs, the progression of the crack may be prevented.

[0136] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0137] 100: 1st semiconductor chip 200: 2nd semiconductor chip 300: Package substrate 360: Metal pillar 370: Molding film 380: Pad 381: 1st sub-pad 382: 2nd sub-pad RDL1: 1st rewiring pattern RDLa: 1st sub-rewiring pattern RDLb: 2nd sub-rewiring pattern 390: Solder ball 391: 1st sub-solder ball 392: 2nd sub-solder ball 385: Solder resist layer RC: Solder ball recess t1: 1st trench t2: 2nd trench

Claims

Claim 1 A semiconductor package comprising: a package substrate including a central region and a corner region excluding the central region, and a first surface and a second surface facing each other; a semiconductor chip mounted on the first surface of the package substrate; a pad comprising a first sub-pad disposed on the second surface of the central region of the package substrate and a second sub-pad disposed on the second surface of the corner region of the package substrate and defining a solder ball recess; and a solder ball comprising a first sub-solder ball connected to the first sub-pad and a second sub-solder ball connected to the second sub-pad on the second surface, wherein the second sub-solder ball comprises a first portion disposed within the solder ball recess and a second portion on the first portion, and the first portion of the second sub-solder ball does not overlap the first sub-solder ball in a direction perpendicular to the thickness direction of the package substrate. Claim 2 A semiconductor package according to claim 1, wherein the corner region has a stepped shape in a planar view. Claim 3 A semiconductor package according to claim 1, wherein at least a portion of the corner region overlaps the semiconductor chip and the package substrate in the thickness direction. Claim 4 In claim 1, the solder ball recess exposes the package substrate, forming a semiconductor package. Claim 5 A semiconductor package according to claim 1, wherein the thickness of the second sub-pad is constant. Claim 6 In claim 1, the pad comprises a semiconductor package including NiAu. Claim 7 A package substrate comprising a corner region and a central region excluding the corner region, and including a first surface and a second surface facing each other; a semiconductor chip mounted on a first surface of the central region of the package substrate; a first sub-rewiring pattern disposed in the central region of the package substrate; a second sub-rewiring pattern disposed in the corner region of the package substrate and including a trench; a first sub-pad disposed on the second surface and connected to the first sub-rewiring pattern; a second sub-pad disposed on the second surface and connected to the second sub-rewiring pattern; and a first sub-solder ball connected to the first sub-pad. A semiconductor package comprising a second sub-solder ball connected to the second sub-pad, wherein the second sub-pad extends along the sidewall and bottom surface of the trench, at least a portion of the second sub-solder ball fills the trench remaining after the second sub-pad is formed, at least a portion of the second sub-solder ball overlaps the second sub-rewiring pattern in a direction perpendicular to the thickness direction of the package substrate, and at least a portion of the second sub-solder ball does not overlap the first sub-solder ball in a direction perpendicular to the thickness direction of the package substrate, and the upper surface of the first sub-pad is flat. Claim 8 In claim 7, the semiconductor package wherein the first sub-pad and the second sub-pad each comprise NiAu. Claim 9 In claim 7, the semiconductor package, wherein, from a planar perspective, the corner region has a stepped shape. Claim 10 A package substrate comprising four corner regions and a central region excluding said corner regions, and comprising a first surface and a second surface facing each other, wherein, in a planar view, each of said corner regions has a stepped shape; at least one semiconductor chip mounted on a first surface of a central region of said package substrate; a solder resist layer disposed on the second surface and comprising a first trench; a redistribution pattern comprising a first sub-redistribution pattern disposed in the central region of said package substrate and a second sub-redistribution pattern disposed in a corner region of said package substrate and comprising a plurality of second trenches; a first sub-pad extending along the bottom surface of said first trench and connected to said first sub-redistribution pattern; a second sub-pad extending along the bottom surface of said first trench and the sidewall and bottom surface of said second trench and connected to said second sub-redistribution pattern; and a first sub-solder ball connected to said first sub-pad. A semiconductor package comprising a second sub-solder ball connected to the second sub-pad and having at least a portion filling the second trench, wherein the first trench exposes the redistribution pattern and the plurality of second trenches do not expose the package substrate, wherein the second sub-solder ball includes a first portion filling the second trench and a second portion on the first portion, wherein the first portion of the second sub-solder ball does not overlap the first sub-solder ball in a direction perpendicular to the thickness direction of the package substrate, and wherein the first sub-pad and the second sub-pad each comprise NiAu.

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