Planar Complementary MOSFET Structure to Reduce Leakages and Planar Areas

Abstract

The present invention discloses a planar CMOSFET structure used in a peripheral circuit of a DRAM chip and a sensing amplifier of an array core circuit of a DRAM chip, wherein the planar CMOSFET structure comprises a planar P-type MOSFET having a first conduction region, a planar N-type MOSFET having a second conduction region, and a cross-shaped local isolation region between the planar P-type MOSFET and the planar N-type MOSFET; the cross-shaped local isolation region comprises a horizontally extended isolation region in contact with the bottom side of the first conduction region and the bottom side of the second conduction region. The present invention may similarly be applied to transistors for CMOS logic circuits.

Description

Technology Field

[0001] The present invention relates to a novel planar transistor and planar complementary MOSFET (CMOS) structure, and in particular to a planar transistor and / or planar complementary MOSFET (CMOS) used in peripheral circuits or sense amplifiers of a DRAM capable of reducing current leakage, reducing short channel effects, and preventing latch-up. Background Technology

[0002] Advanced technology nodes (such as 3 to 7 nm) are frequently used in high-performance computing applications (such as artificial intelligence AI, CPUs, GPUs, etc.), but mature technology nodes (such as 20 to 30 nm) are still popular in many IC applications, such as power management ICs, MCUs, or DRAM chips. As an example, using DRAM, most custom DRAMs today are still manufactured by mature technology nodes (such as 12 to 30 nm), and all transistors of the DRAM chip (17), including those of the peripheral circuitry (171) (at least including data / address I / O circuitry, address decoder, command logic, and refresh circuitry, etc.) and those of the array core circuitry (172) (storage memory array, sense amplifier, etc.), are still planar transistors.

[0003] FIG. 1b illustrates a cross-sectional view of a modern planar complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) (10), which is most widely used in the peripheral circuits of a DRAM chip and in the sensing amplifiers of the array core circuits of a DRAM chip. The CMOSFET (10) includes a planar NMOS transistor (11) and a planar PMOS transistor (12), and a shallow trench isolation (STI) region (13) is located between the NMOS transistor (11) and the PMOS transistor (12). The gate structure (14) of an NMOS transistor (11) or PMOS transistor (12) using a small amount of conductive material (like metal, polysilicon, or polyside, etc.) over an insulator (such as an oxide, oxide / nitride, or some high dielectric constant, etc.) is formed on top of a CMOS where the sidewalls are separated from the sidewalls of the other transistor by using an insulating material (e.g., an oxide or oxide / nitride, or other dielectric). In the case of a planar NMOS transistor (11), there are source and drain regions formed by ion-implantation and thermal annealing techniques that create two separate n+ / p junction regions by injecting an n-type dopant into a p-type substrate (or p-well). In the case of a planar PMOS transistor (12), both source and drain regions are formed by ion-implanting a p-type dopant into an n-well, thereby creating two p+ / n junction regions. In addition, to reduce impact ionization and hot carrier injection prior to a strongly doped n+ / p or p+ / n junction, it is common to form a weakly doped drain (LDD) region (15) under the gate structure.

[0004] Meanwhile, during the aforementioned thermal annealing process, the n-type or p-type dopant injected into the CMOSFET (10) will inevitably diffuse in different directions and expand the area of ​​the source and drain regions. Additionally, another thermal annealing process will occur to reduce the connection resistance between the capacitor and the access transistor while forming a capacitor over the access transistor in the array core circuit of the DRAM chip. This secondary thermal annealing process again causes the diffusion of the n-type or p-type dopant and increases the area of ​​the source and drain regions. As the area of ​​the source and drain regions increases due to the thermal annealing process, the effective channel length (Leff in FIG. 1b) between the source and drain regions becomes shorter, and this reduced effective channel length Leff will cause a short channel effect (SCE). Therefore, to reduce the impact of SCE, it is common to ensure a longer gate length to accommodate the diffusion of the n-type or p-type dopant caused by thermal annealing. For example, if a technology node (λ) of 25 nm is used, the reserved gate length will be about 100 nm, which is nearly four times the technology node (λ).

[0005] Meanwhile, since the NMOS transistor (11) and the PMOS transistor (12) are each located within parts of adjacent regions of the p-substrate and n-well formed next to each other in close proximity, a parasitic junction structure called an n+ / p / n / p+ (the path indicated by the dotted line in FIG. 1b is called the n+ / p / n / p+ latch-up path) parasitic bipolar device is formed in its outline starting from the n+ region of the NMOS transistor (11), through the p-well to the neighboring n-well, and further to the p+ region of the PMOS transistor (12).

[0006] If significant noise occurs in either the n+ / p junction or the p+ / n junction, an abnormally large current may flow through this n+ / p / n / p+ junction, which may cause the operation of some parts of the CMOS circuit to stop and the entire chip to malfunction. This abnormal phenomenon, known as latch-up, must be avoided as it has an adverse effect on CMOS operation. One way to increase resistance to latch-up, which is certainly a weakness of CMOS, is to increase the distance from the n+ region to the p+ region (indicated as the latch-up distance in FIG. 1b), and both the n+ and p+ regions should be designed to be separated by some vertically oriented oxide as a separation region, which is typically a Shallow Trench Separation (STI) region (13). As an example, using a technology node (λ) of 25 nm, the reserved latch-up distance is about 500 nm, which is nearly 20 times the technology node (λ). More serious efforts to prevent latch-up involve designing a guard-band structure that increases the distance between the n+ and p+ regions and / or adding an extra n+ or p+ region to collect abnormal charges from noise sources. Such isolation methods always increase the extra planar region, sacrificing the die size of the CMOS circuit.

[0007] Other problems are occurring or worsening in current DRAM designs with planar transistors or CMOSFETs:

[0008] (1) As leakage current occurs through the surrounding and bottom regions, where additional damage such as holes and electrons are trapped due to lattice defects generated by ion implantation, the control of all junction leakage caused by junction formation processes, such as forming an LDD (Lightly Doped Drain) structure as a substrate / well region, an n+ source / drain structure as a p-substrate, and a p+ source / drain structure as an n-well, is worsened.

[0009] (2) In addition, since ion implantation to form an LDD structure (or n+ / p junction or p+ / n junction) acts like a bombardment to insert ions straight down from the top of the silicon surface to the substrate, the dopant concentration is vertically non-uniformly distributed from the top surface, which has a higher doping concentration, to the junction region below, which has a lower doping concentration, making it difficult to create a uniform material interface with lower defects from the source and drain regions to the channel and substrate-body regions.

[0010] (3) With conventional self-alignment methods using gate, spacer, and ion-implantation formation alone, it is becoming increasingly difficult to align the LDD junction edge to the edge of the transistor's gate structure in a perfect position. Additionally, the thermal annealing process to remove ion-implantation damage must rely on high-temperature process technologies, such as rapid thermal annealing methods using various energy sources or other thermal processes. Thus, one problem that arises is the gate-induced drain leakage (GIDL) current. As illustrated in Fig. 1c (Citation: A. Sen and J. Das, "MOSFET GIDL Current Variation with Impurity Doping Concentration - A Novel Theoretical Approach" IEEE ELECTRON DEVICE LETTERS, VOL.38, NO.5, May 2017), in MOSFET structures with thin oxides close to the gate and drain / source regions, parasitic metal-gate-diodes exist, and the GIDL induced by the parasitic metal-gate-diodes formed in the gate-to-source / drain region is difficult to control, even though it must be minimized to reduce leakage current; another problem that arises is that the effective channel length is difficult to control and therefore it is difficult to minimize SCE.

[0011] (4) Since it is difficult to make the vertical length of the STI structure deeper, and the planar width of the device separation must be reduced (a worse depth-aperture aspect ratio is created for the integrated process of etching, filling, and planarization), the proportional ratio of the planar separation distance between the n+ and p+ regions of adjacent transistors reserved to prevent latch-up for the reduced λ cannot be reduced but increased, which impairs the reduction of the die area when shrinking the CMOS device. The problem to be solved

[0012] The present invention discloses several new concepts for realizing a new planar transistor and planar CMOSFET structure, which is used particularly in the peripheral circuits of a DRAM chip and the sensing amplifiers of the array core circuits of a DRAM chip, and significantly improves or even solves most of the aforementioned problems, such as minimizing current leakage, improving channel-conduction performance and control, optimizing the functions of source and drain regions such as creating the closest physical integrity to the conductance and channel regions for metal interconnects with a seamlessly ordered crystal lattice matchup, increasing the tolerance of the CMOS circuit to latch-up, and minimizing the planar area used for layout isolation between NMOS and PMOS to prevent latch-up. means of solving the problem

[0013] According to one object of the present invention, a DRAM chip or circuit comprises a semiconductor substrate having a semiconductor surface, an array core circuit having a plurality of DRAM cells electrically coupled to the sensing amplifier circuit, and a peripheral circuit electrically coupled to the array core circuit. One of the sensing amplifier circuit or the peripheral circuit has a complementary MOSFET structure, and the complementary MOSFET structure comprises a planar P-type MOSFET having a first conduction region, a planar N-type MOSFET having a second conduction region, and a cross-shaped local isolation region between the planar P-type MOSFET and the planar N-type MOSFET. The cross-shaped local isolation region includes an isolation region extending horizontally below the semiconductor surface, and the horizontally extended isolation region contacts the bottom side of the first conduction region and the bottom side of the second conduction region.

[0014] According to one aspect of the present invention, a complementary MOSFET structure further comprises a first concave portion formed below a semiconductor surface, and the first concave portion accommodates a first conductive region.

[0015] According to one aspect of the present invention, 1 a conductive region comprises an undoped semiconductor region and / or a weakly doped semiconductor region, which is independent of the semiconductor substrate.

[0016] According to one aspect of the present invention, an undoped semiconductor region or a weakly doped semiconductor region is adjacent to the channel region of a planar P-type MOSFET.

[0017] According to one aspect of the present invention, the first conductive region further includes a strongly doped semiconductor region, the strongly doped semiconductor region is located in a first trench, and the weakly doped semiconductor region and the strongly doped semiconductor region are formed with the same lattice structure.

[0018] According to one aspect of the present invention, the first conductive region further comprises a metal region, and the metal region is located in a first concave portion and is adjacent to a strongly doped semiconductor region.

[0019] According to one aspect of the present invention, a complementary MOSFET structure further comprises a first recess formed below a semiconductor surface, and the first recess accommodates a first portion of a horizontally extended separation region.

[0020] According to one aspect of the present invention, a planar P-type MOSFET further comprises a gate region on a semiconductor surface, and the edge of the gate region is aligned with or substantially aligned with the edge of a first conductive region.

[0021] According to one aspect of the present invention, a planar P-type MOSFET further comprises a gate region, and all first portions of the horizontally extended separation region are not located immediately below the gate structure.

[0022] According to one aspect of the present invention, a planar P-type MOSFET further comprises a gate region, and less than 5% of a first portion of a horizontally extended separation region is located immediately below the gate structure.

[0023] According to one aspect of the present invention, the horizontally extended separation region is a composite separation region.

[0024] According to one aspect of the present invention, the composite separation region comprises an oxide layer and a nitride layer on top of the oxide layer.

[0025] According to one aspect of the present invention, the vertical depth of the oxide layer is smaller than the vertical depth of the nitride layer.

[0026] According to one aspect of the present invention, a horizontally extended separation region comprises a first horizontally extended separation region and a second horizontally extended separation region, wherein the bottom side of the first conductive region is shielded from the semiconductor substrate by the first horizontally extended separation region and the bottom side of the second conductive region is shielded from the semiconductor substrate by the second horizontally extended separation region.

[0027] According to one aspect of the present invention, a cross-shaped local separation region includes a vertically extended separation region between a first horizontally extended separation region and a second horizontally extended separation region, and the vertical depth of the vertically extended separation region is greater than the sum of the vertical depths of the first and second horizontally extended separation regions and the vertical depth of the first separation region.

[0028] According to another object of the present invention, a DRAM circuit formed by a technology node (λ) according to the present invention comprises a semiconductor substrate having a semiconductor surface, an array core circuit having a plurality of DRAM cells coupled to the sensing amplifier circuit, and a peripheral circuit electrically coupled to the array core circuit. One of the sensing amplifier circuit or the peripheral circuit has a complementary MOSFET structure, and the complementary MOSFET structure comprises a planar P-type MOSFET having a first source region, a first drain region, and a first gate region on the semiconductor surface, and a planar N-type MOSFET having a second source region, a second drain region, and a second gate region on the semiconductor surface. The first source region or the first drain region includes a weakly doped semiconductor region and a strongly doped semiconductor region laterally adjacent to the weakly doped semiconductor region; A single DRAM cell includes an access transistor and a storage capacitor, and the access transistor includes a third source region, a third drain region, and a third gate region, and the third source region or the third drain region includes a weakly doped semiconductor region and a strongly doped semiconductor region vertically adjacent to the weakly doped semiconductor region.

[0029] According to one aspect of the present invention, one edge of the gate region is aligned or substantially aligned with the edge of the first source region, and another edge of the gate region is aligned or substantially aligned with the edge of the first drain region.

[0030] According to one aspect of the present invention, a complementary MOSFET structure further comprises a local separation region between a planar P-type MOSFET and a planar N-type MOSFET, and a strongly doped P+ region of a first source region or a first drain region is shielded from the semiconductor substrate by the local separation region.

[0031] According to one aspect of the present invention, a local separation region comprises a vertically extended separation region and a horizontally extended separation region, and the latch-up path between a planar P-type MOSFET and a planar N-type MOSFET depends at least on the bottom length of the horizontally extended separation region.

[0032] According to another object of the present invention, a DRAM circuit according to the present invention comprises a semiconductor substrate having a semiconductor surface, a sensing amplifier circuit and an array core circuit having a plurality of DRAM cells electrically coupled to the sensing amplifier circuit, and a peripheral circuit electrically coupled to the array core circuit. Each DRAM cell comprises an access transistor and a storage capacitor. One of the sensing amplifier circuit or the peripheral circuit has a complementary MOSFET structure, and the complementary MOSFET structure includes a planar P-type MOSFET having a first source region, a first drain region, and a first gate region on the semiconductor surface, and a planar N-type MOSFET having a second source region, a second drain region, and a second gate region on the semiconductor surface. The access transistor includes a third source region, a third drain region, and a third gate region, at least a portion of the third gate region is below the semiconductor surface; the first source region or the first drain region has a first grid structure, and the third source region or the third drain region has a second grid structure, and the first grid structure is different from the second grid structure. Additionally, the first source region or the first drain region includes a bottom surface lower than the bottom surface of the first gate region, and the third source region or the third drain region includes a bottom surface higher than the bottom surface of the third gate region.

[0033] According to one aspect of the present invention, the third source region or the third drain region includes a bottom surface that is aligned with or substantially aligned with the upper surface of the third gate region.

[0034] According to one aspect of the present invention, the first source region and the first drain region are independent of the semiconductor substrate, and the third source region and the third drain region are independent of the semiconductor substrate.

[0035] According to one aspect of the present invention, the semiconductor substrate is a silicon substrate, and a first source region and a first drain region are selectively grown from the (110) orientation surface of the silicon substrate and extend laterally, and a third source region and a third drain region are selectively grown from the (100) orientation surface of the silicon substrate and extend vertically.

[0036] These and other objects of the present invention will undoubtedly become apparent to a person skilled in the art after reading the following detailed description of preferred embodiments illustrated in the various drawings and figures. Brief explanation of the drawing

[0038] Figure 1a is a diagram showing the circuit of a DRAM chip. FIG. 1b is a cross-sectional view of a conventional CMOS structure. Figure 1c is a diagram showing the parasitic metal-gate-diode formed in the gate-to-source / drain region of a MOSFET and the GIDL problem of the MOSFET. FIGS. 2a and 2b are drawings showing a plan view and a cross-sectional view along the cutting line (X-axis) after the pad-nitride layer is deposited and the STI is formed. FIGS. 3a and FIGS. 3b are drawings showing a plan view and a cross-sectional view along the cutting line (X-axis) after the gate length has been defined. FIGS. 3aa and FIGS. 3ab are drawings of another embodiment showing a plan view and a cross-sectional view along the cutting line (X-axis) after a shallow trench for the channel area has been formed. FIGS. 3ba and FIGS. 3bb are drawings of another embodiment showing a plan view and a cross-sectional view along the cutting line (X-axis) after the channel region is optionally formed. FIGS. 3ca and FIGS. 3cb are drawings of another embodiment showing a plan view and a cross-sectional view along the cutting line (X-axis) after a rounded shallow trench is formed for the channel area. FIGS. 3da and FIGS. 3db are drawings of another embodiment showing a plan view and a cross-sectional view along the cutting line (X-axis) after the channel area is optionally formed in a rounded shallow trench. FIGS. 4a and 4b are drawings showing a plan view and a cross-sectional view along the cutting line (X-axis) after the gate conduction region is formed. FIGS. 5A and 5B are drawings showing a plan view and a cross-sectional view along the cutting line (X-axis) after the gate cap region is formed. FIGS. 6a and 6b are drawings showing a plan view and a cross-sectional view along the cutting line (X-axis) after the pad nitride and pad oxide outside the gate region have been removed. FIGS. 7A and 7B are drawings showing a plan view and a cross-sectional view along the cutting line (X-axis) after a spacer is formed on the side wall of the gate area. FIGS. 8A and 8B are drawings showing a plan view and a cross-sectional view along the cutting line (X-axis) after a concave portion is formed outside the gate area. FIGS. 9a and 9b are drawings showing a plan view and a cross-sectional view along the cutting line (X-axis) after a local separation layer is formed in the concave portion. FIGS. 10a and FIGS. 10b are drawings showing a plan view and a cross-sectional view along the cutting line (X-axis) after a semiconductor region has grown laterally from a silicon sidewall exposed in a concave portion. FIG. 10c is a plan view and a cross-sectional view along the cutting line (X-axis) after a semiconductor region has grown laterally from a silicon sidewall exposed in a concave portion. FIGS. 10aa and FIGS. 10ab are drawings showing a plan view and a cross-sectional view along a cutting line (X-axis) after a semiconductor region is grown laterally from a silicon sidewall exposed in a concave portion according to another embodiment. FIGS. 11a and FIGS. 11b are drawings illustrating a plan view and a cross-sectional view along a vertical dotted line in one embodiment of a planar CMOS structure of a peripheral circuit / sensing amplifier of a DARM chip according to the present invention. FIG. 12 is a diagram illustrating a conventional CMOS structure having n+ and p+ regions that are not completely insulated by an insulator. FIGS. 13a and 13b are drawings illustrating a plan view and a cross-sectional view along a horizontal dotted line in another embodiment of a planar CMOS structure of a peripheral circuit / sensing amplifier of a DARM chip according to the present invention. FIG. 14 is a diagram illustrating a possible latch-up path from an n+ / p junction of a transition CMOS structure to an n / p+ junction structure through a p-well / n-well junction. FIG. 15a is a cross-sectional view of an access transistor proposed in an array core circuit of a DARM chip according to the present invention. FIG. 15b is a cross-sectional view of an access transistor proposed in an array core circuit of a DARM chip after a recess is formed to accommodate a source / drain region. FIGS. 16 to 18 are cross-sectional views of the formation steps for the semiconductor gate of the proposed NMOS transistor. FIGS. 19 to 21 are cross-sectional views of the formation steps for the semiconductor gate of the proposed PMOS transistor. FIG. 22a is a cross-sectional view of a conventional polygate transistor, and FIG. 22b is a cross-sectional view of a proposed semiconductor gate transistor according to the present invention. Figure 23a shows the electron backscatter diffraction (EBSD) results of the annealed α-Si layer in the actual sample structure, Figure 23b shows the transmission electron microscope (TEM) results of the annealed α-Si layer, and Figure 23c shows the X-ray diffraction (XRD) results of two regions identified in the annealed α-Si layer. Specific details for implementing the invention

[0039] The present invention discloses planar transistor and planar CMOSFET structures used particularly in peripheral circuits of a DRAM chip and in sensing amplifiers of array core circuits of a DRAM chip. Methods for manufacturing the proposed NMOS and PMOS transistors are exemplified as follows:

[0040] Step 10: Start.

[0041] Step 20: Based on the semiconductor substrate, define the active regions of the NMOS and PMOS transistors and form a shallow trench isolation (STI) structure.

[0042] Step 30: Form a gate structure on the original semiconductor surface of the semiconductor substrate.

[0043] Step 40: Form a spacer covering the gate structure and form a recess in the semiconductor substrate.

[0044] Step 50: Form a local separation layer in the depression.

[0045] Step 60: Silicon sidewalls are exposed in the concave area, and semiconductor regions are grown laterally from the silicon sidewalls exposed in the concave area to form source and drain regions of planar NMOS and PMOS transistors.

[0046] Referring to FIGS. 2a and 2b, step 20 may include the following:

[0047] Step 202: A pad-oxide layer (22) is formed and a pad-nitride layer (23) is deposited.

[0048] Step 204: Define the active regions of the planar NMOS and planar PMOS transistors using patterned photoresistance (PR), and remove a portion of the silicon material from the semiconductor substrate outside the pattern of these active regions to create temporary trenches.

[0049] Step 206: An oxide layer is deposited in the created temporary trench, then the oxide layer is etched back and flattened to form a shallow trench separation (STI) (21), and the upper surface of the STI (21) is aligned with the upper surface of the pad-nitride layer (23), as shown in FIG. 2b, which is a cross-sectional view along the x-axis cutting line of FIG. 2a.

[0050] Referring to FIGS. 3 through 5, step 30 of forming a gate structure may include the following:

[0051] Step 302: Another patterned photoresistance (PR) is used to define the gate length (Lgate) of the gate region for planar NMOS and PMOS transistors, and then a portion of the pad-oxide layer (302) and pad-nitride layer (304) not covered by the PR is removed to form a gate receiving trench (32) as shown in FIG. 3a and FIG. 3b, where FIG. 3b is a cross-sectional view along the x-axis cutting line of FIG. 3a.

[0052] Step 304: Next, as shown in FIGS. 4a and 4b, a gate dielectric layer (331) (such as a thermal oxide or Hi-K material), a heavily doped polysilicon (332) (N+ polysilicon for MOS and P+ polysilicon for MOS), a Ti / TiN layer (333), and a tungsten layer (334) are formed in the gate receiving trench (32), and FIG. 4b is a cross-sectional view along the x-axis cutting line of FIG. 4a.

[0053] Step 306: As shown in FIGS. 5a and 5b, a nitride cap layer (335) and an oxide cap (336) are formed on a tungsten layer (334) to complete the gate region or gate structure of the NMOS and PMOS transistors, and FIG. 5b is a cross-sectional view along the x-axis cutting line of FIG. 5a.

[0054] Then, referring to FIGS. 6 through 8, step 40 may include the following:

[0055] Step 402: As shown in FIGS. 6a and 6b, the pad-oxide layer (22) and pad-nitride layer (23) between the STI layer (21) and the aforementioned gate region are removed to reveal the OSS of the substrate, and FIG. 6b is a cross-sectional view along the x-axis cutting line of FIG. 6a.

[0056] Step 404: As illustrated in FIG. 7a and FIG. 7b, a spacer layer is formed on the side of the gate region described above, and the spacer layer may comprise a thin oxide sublayer (343) thermally grown on the OSS of the substrate, a thin nitride sublayer (341) and a thin oxide sublayer (342) on the thin oxide sublayer (343), and FIG. 7b is a cross-sectional view along the x-axis cutting line of FIG. 7a.

[0057] Step 406: As illustrated in FIG. 8a and FIG. 8b, a portion of the semiconductor substrate is etched to form a recess in the semiconductor substrate, FIG. 8b is a cross-sectional view along the x-axis cutting line of FIG. 8a. Each recess includes an exposed vertical side-surface having an orientation (100) just below the spacer layer in step 404, where the semiconductor substrate is a silicon substrate.

[0058] Referring to FIGS. 9a and 9b, step 50 may include: thermally growing an oxide-3 layer (41) comprising a vertical oxide-3V layer (411) covering the sidewalls of the aforementioned concave and a horizontal oxide-3B layer (412) covering the bottom of the aforementioned concave. Then, as shown in FIGS. 9a and 9b, a nitride-3 material is deposited to a sufficient thickness to completely fill the aforementioned concave, and then an etch-back process is used to remove unnecessary portions of the nitride-3 material so as to leave only a suitable nitride-3 layer inside the aforementioned concave, FIG. 9b is a cross-sectional view along the x-axis cutting line of FIG. 9a. It is noted that the nitride-3 layer (42) may be replaced with any suitable insulating material.

[0059] For reference, the thicknesses of the oxide 3-V layer (411) and oxide 3-B layer (412) shown in FIG. 9b and subsequent drawings are shown for illustrative purposes only, but it is very important to design this thermally grown oxide-3 layer (41) so that the thickness of the oxide-3V layer (411) is very precisely controlled in terms of the precisely controlled thermal oxidation temperature, timing, and growth rate. Thermal oxidation on a well-formed silicon surface results in 40% of the oxide-3V layer (411) thickness removing a portion of the silicon substrate from the aforementioned exposed (110) vertical side-surface (36), and the remaining 60% of the oxide-3V layer (411) thickness being calculated additionally outside the aforementioned exposed (110) vertical side-surface (36) (the distribution of these 40% and 60% on the oxide-3V layer (411) is clearly shown particularly in FIG. 9b). Since the thickness of the oxide-3V layer (411) is controlled very precisely based on the thermal oxidation process, the edge of the oxide-3V layer (411) can be aligned with the edge of the gate region. Of course, depending on the etching conditions and thermal oxidation growth conditions, in other embodiments, a portion of the oxide-3V layer (411) (such as less than 5 to 10%) may be below the gate structure.

[0060] Referring to FIGS. 10a and FIGS. 10b, step 60 may include the following:

[0061] Step 602: A portion of the oxide-3V layer (411) on the nitride-3 layer (42) is removed to expose another vertical semiconductor sidewall (501, 502), and these vertical semiconductor sidewalls (501, 502) have a crystal orientation (110) when the semiconductor substrate is a silicon substrate. The remaining oxide-3 layer (41) and nitride-3 layer (42) may be referred to as Localized Isolation into Silicon Substrate ("LISS").

[0062] Step 604: A first semiconductor region (430) is grown laterally from the exposed vertical semiconductor sidewalls (501, 502). Each first semiconductor region (430) may include a lightly doped region (or a lightly doped drain (LDD)) or may include a lightly doped region in addition to an undoped region. The first semiconductor region (430) may be formed by a selective growth method such as Selective Epitaxial Growth (SEG) technology or Atomic Layer Deposition (ALD) technology.

[0063] Step 606: A second semiconductor region is grown laterally from these first semiconductor regions (430); each second semiconductor region also includes a strongly doped region that can be formed by an optionally grown method. Thus, the drain region of the planar NMOS transistor includes an N-LDD region and an N+ doped region (431), and the source region of the planar NMOS transistor includes another N-LDD region and an N+ doped region (432). Similarly, the drain region of the planar PMOS transistor includes a P-LDD region and a P+ doped region (441), and the source region of the PMOS transistor includes another P-LDD region and a P+ doped region (442).

[0064] Note that each of the exposed vertical semiconductor sidewalls (501, 502) has its vertical boundary aligned (or substantially aligned) with the edge of the gate region as illustrated in FIG. 10b. That is, in a planar transistor, the edge of the source or drain region is aligned (or substantially aligned) with the edge of the gate region, and the present invention provides a profound SAPC (precisely generated crystal structure for gate-to-source / drain alignment and source / drain formation) technique. Thus, the alignment of the edge of the gate region from the edge of the source / drain can be precisely defined or controlled using thermal oxidation and crystal structure, and the GIDL effect should be reduced in contrast to the conventional method using LDD injection to serve as the gate-edge alignment for the LDD.

[0065] Additionally, the new source / drain regions are all formed by (110) crystalline silicon; improving the existing method of growing source / drain regions from two different seeding regions as described results in a lattice mixing of (100) orientation and (110) orientation on the silicon substrate. Thus, the present invention can produce a better source / drain-to-channel conduction mechanism and can also reduce sub-threshold leakage. Furthermore, the effective channel length (Leff) between the source and drain regions can be nearly equal to the gate length ("Lgate") shown in FIG. 10b during the formation of the planar transistor, since ion implantation and thermal annealing are not required. Since there is no need to use ion implantation to form the LDD region or source / drain regions, there is no need to use a thermal annealing process to reduce defects. Therefore, additional defects once induced are not created, and unexpected leakage current sources, which are difficult to completely remove even with an annealing process, must be significantly minimized.

[0066] Additionally, even if there is another thermal annealing process to reduce the connection resistance between the capacitor and the access transistor, since the first semiconductor region (430) of the present invention may include a weakly doped region in addition to an undoped region, the dopant redistribution due to the other thermal annealing process does not significantly reduce the effective channel length (Leff), and therefore, the design rule for the reserved gate length ("Lgate") of the gate region according to the present invention will be reduced compared to the design rule of the conventional CMOS structure. As an example, if a technology node (lambda or λ) of 20 to 30 nm is used for a planar transistor, the reserved gate length in the present invention will be between 1.5λ and 3λ, such as 2λ or 2.5λ.

[0067] Meanwhile, the source and drain regions of the planar transistor according to the present invention are each separated by an insulating material (nitride-3 layer (42) and the remaining oxide-3 layer (41)) on the bottom structure and separated by an STI layer (21) along three sidewalls, and the possibility of junction leakage can occur only in a very small area (immediately below the gate region of the planar transistor) from the first semiconductor region (430) to the channel region, and thus is significantly reduced.

[0068] In the previous embodiment, the channel region can be formed below and close to the original silicon surface (OSS) via ion implantation (not shown) prior to the formation of the gate structure. However, in addition to the channel region formed by ion implantation, the channel region according to the present invention can be formed by selective growth. For example, before forming the gate dielectric layer (331) in FIG. 4b, the exposed silicon surface can be etched to form a shallow trench having a depth of 1.5 nm to 3 nm, as shown in FIG. 3aa and FIG. 3ab. Then, the channel region (24) is selectively grown in the shallow trench, as shown in FIG. 3ba and FIG. 3bb. After that, another planar transistor structure shown in FIG. 10c can be formed by similarly applying the process of forming the gate region, source region, and drain region mentioned in FIG. 4a / 4b to FIG. 10a / 10b.

[0069] In another embodiment, before forming the gate dielectric layer (331) of FIG. 4b, the exposed silicon surface may be etched to form a shallow trench having a rounded or curved shape as shown in FIG. 3ca and FIG. 3cb. Then, as shown in FIG. 3da and FIG. 3db, the semiconductor channel region (24) is selectively grown along the sidewalls of the shallow trench. Because the semiconductor channel region (24) is selectively grown along the sidewalls of the curved or rounded shallow trench, the channel length of this embodiment may be longer. Afterward, the process of forming the gate region, source region, and drain region mentioned in FIG. 4a / 4b through FIG. 10a / 10b may be similarly applied to form another planar transistor.

[0070] FIGS. 10aa and FIGS. 10ab illustrate a plan view and a cross-sectional view along the cutting line (X-axis) after the semiconductor region has grown laterally from the silicon sidewall exposed in the concave region according to another embodiment. The difference between FIGS. 10aa / FIGS. 10ab and FIGS. 10c is that, before growing the LDD region (4302) for the NMOS, a vertical P-type layer (4301) is first formed by selective growth, and then the LDD region (4302) and the heavily doped region (431 / 432) are sequentially formed by selective growth. This vertical P-type layer (4301) can reduce leakage current during the OFF state of the NMOS transistor.

[0071] In another embodiment, the source (or drain) region may additionally include some tungsten or other suitable metallic material (not shown) in a recess that contacts the heavily doped region of the optionally grown source (or drain) region. Thus, the source (or drain) region is a composite source (or drain) region. Thus, an external metal contact is connected to the metal region of the composite source (or drain) region, and this metal-to-metal contact has a much lower resistance than a conventional silicon-to-metal contact.

[0072] Additionally, as illustrated in FIGS. 11a and 11b, FIG. 11a is a plan view of a new planar CMOS structure according to the present invention, and FIG. 11b is a cross-sectional view of the new planar CMOS structure along the cutting line (Y-axis) of FIG. 11a. The planar PMOS and planar NMOS transistors of FIG. 11a and FIG. 11b are positioned vertically side by side. In FIG. 11a, the four sides of the new planar CMOS structure are surrounded by STI (21). Furthermore, as illustrated in FIG. 11b, a composite local separation (including an oxide-3 layer (412) and a nitride-3 layer (42)) exists between the P+ source region (442) (or P+ drain region (441)) of the PMOS and the n-type N-well, and thus another composite local separation (including an oxide-3B layer (412) and a nitride-3 layer (42)) exists between the N+ source region (432) (or N+ drain region) of the NMOS and the p-type P-well or substrate. That is, the drain region and source region of the new planar CMOS structure are each surrounded by STI (21) on three sidewalls and surrounded by a composite local separation on the bottom wall. Thus, a possible latch-up path from the bottom of the P+ region of the PMOS to the bottom of the N+ region of the NMOS is completely blocked by the local separation. Therefore, the latch-up distance Xp+Xn (measured in a plane) can be reduced as small as possible without causing serious latch-up problems. Meanwhile, in traditional CMOS structures, the n+ and p+ regions are not completely insulated by an insulator as shown in FIG. 1b or FIG. 12, and possible latch-up paths existing from the n+ / p junction through the p-well / n-well junction to the n / p+ junction include lengths a, b, and c.

[0073] Also, refer to FIG. 13a and FIG. 13b according to another embodiment of the present invention. FIG. 13a is a plan view of a new planar CMOS structure having planar NMOS transistors and planar PMOS transistors, and FIG. 13b is a cross-sectional view of the new CMOS structure along the horizontal cutting line of FIG. 13a. The planar PMOS and planar NMOS transistors of FIG. 13a and FIG. 13b are positioned side by side laterally. As shown in FIG. 13b, it can be simplified to have a cross-shaped LISS (70) between the PMOS transistor and the NMOS transistor. A cross-shaped LISS (70) includes a vertically extended separation region (71) (e.g., STI (21), the vertical depth below the OSS as shown in FIG. 13b will be about 150 to 300 nm, such as 200 nm), a first horizontally extended separation region (72) on the right side of the vertically extended separation region (71) (the vertical depth will be about 50 nm to 120 nm, such as 100 nm), and a second horizontally extended separation region (73) on the left side of the vertically extended separation region (71) (the vertical depth will be about 50 nm to 120 nm, such as 100 nm). Each horizontally extended separation region may include an oxide-3 layer (41) and a nitride-3 layer (42). The vertical depth of the source / drain region of the PMOS / NMOS transistor is about 30 to 50 nm, such as 40 nm. The vertical depth of the gate region of the PMOS / NMOS transistor is about 40 to 60 nm, as shown in Fig. 13b, which is 50 nm.

[0074] In this embodiment, the first and second horizontally extended separation regions (72 / 73) are not located directly below the gate structure or the channel of the transistor. The first horizontally extended separation region (72) (to the right of the vertically extended separation region (71)) contacts the bottom side of the source / drain region of the PMOS transistor, and the second horizontally extended separation region (73) (to the left of the vertically extended separation region (71)) contacts the bottom side of the source / drain region of the MMOS transistor. Thus, the bottom side of the source / drain region of the PMOS and NMOS transistors is shielded from the semiconductor substrate. Furthermore, the first or second horizontally extended separation region (72 / 73) may be a composite separation, which may include two or more different separation materials (e.g., oxide-3 (41) and nitride-3 (42)), or each separation material may include two or more identical separation materials formed by a separation process.

[0075] As previously explained by the text and Fig. 1b, in contrast to pure NMOS technology, a disadvantage of conventional CMOS configurations / technologies is that parasitic bipolar structures, such as n+ / p-sub / n-well / p+ junctions, exist, and unfortunately, some poor designs cannot withstand large current surges caused by noise that trigger latch-up, leading to the shutdown of the entire chip or permanent damage to chip functionality. Layout and process rules for conventional CMOS always require a very large space to separate the n+ source / drain region of the NMOS from the p+ source / drain region of the PMOS, which is referred to as the latch-up distance (Fig. 1b), consuming a large planar surface to suppress the possibility of latch-up. Furthermore, if the source / drain n+ / p and p+ / n semiconductor junction areas are too large, once a forward bias fault occurs, a large surging current can be triggered, leading to latch-up.

[0076] The new planar CMOS structure of FIG. 13b results in a much longer path from the n+ / p junction to the n / p+ junction through the p-well (or p-substrate) / n-well junction. As illustrated in FIG. 7c, according to the present invention, a possible latch-up path from the LDD-n / p junction to the n / LDD-p junction through the p-well / n-well junction comprises length ①, length ② (length of the bottom wall of one horizontally extended separation region), length ③, length ④, length ⑤, length ⑥, length ⑦ (length of the bottom wall of another horizontally extended separation region), and length ⑧, as shown in FIG. 13b.

[0077] On the other hand, in a traditional CMOS structure, the possible latch-up path from the n+ / p junction through the p-well / n-well junction to the n / p+ junction includes only lengths d, e, f, and g (as shown in FIG. 14). This possible latch-up path in FIG. 13b is longer than the path in FIG. 14. Therefore, from the perspective of device layout, the reserved edge distance (Xn+Xp) between the NMOS and PMOS in FIG. 13b according to the present invention may be smaller than that of FIG. 14. Furthermore, the potential latch-up path in FIG. 13b starts from the LDD-n / p junction to the n / LDD-p junction, rather than from the n+ / p junction to the n / p+ junction in FIG. 14. Since the doping concentration of the LDD-n or LDD-p region in Fig. 13b is lower than that of the n+ or p+ region in Fig. 14, the amount of electrons or holes emitted from the LDD-n or LDD-p region in Fig. 13b will be much less than that emitted from the n+ or p+ region in Fig. 14. This low carrier emission not only effectively reduces the likelihood of induced latch-up phenomena but also drastically reduces the current even if latch-up phenomena are induced. Because both the n+ / p and p+ / n junction regions are significantly reduced, even a sharp forward bias of these junctions can reduce the abnormal current magnitude, thereby reducing the opportunity for latch-up to form in Fig. 13b.

[0078] Referring again to FIG. 13b, according to the present invention, the source or drain region of a planar PMOS is surrounded by a first horizontally extended separation region (72) and a vertically extended separation region (71), and only the LDD region of the source or drain region of the planar PMOS (vertical length of about 10 to 50 nm) contacts the semiconductor substrate to form an LDD-p / n junction, rather than a p+ / n junction. Similarly, the source or drain region of a planar NMOS is surrounded by a second horizontally extended separation region (73) and a vertically extended separation region (71), and only the LDD region of the source or drain region of the planar NMOS (vertical length of about 40 nm) contacts the substrate to form an LDD-n / p junction, rather than a p+ / n junction. Thus, the n+ region of the planar NMOS and the p+ region of the planar PMOS are shielded from the substrate or well region. Furthermore, since the first or second horizontally extended separation region (72 / 73) is a composite separation and sufficiently thick, parasitic metal gate diodes induced between the source (or drain) region and the silicon substrate can be minimized. Additionally, gate-induced drain leakage (GIDL) effects can be improved. It is expected that the planar latch-up distance reserved for neighboring NMOS and PMOS transistors can be significantly shortened, thereby greatly reducing the planar area of ​​the new planar CMOS.

[0079] Additionally, these source / drain regions grown directly from a specific crystal plane of a semiconductor substrate can be applied to the access transistors of DRAM cells in the array core circuit of a DRAM chip, each DRAM cell comprising an access transistor and a storage capacitor. As illustrated in FIG. 15a, the access transistor (Q1) comprises a source region (213A) connected to a storage capacitor (C1), a drain region (213B) connected to a bitline of the DRAM chip, a gate dielectric layer (209) (e.g., oxide), a gate conduction region (210A) (including metal or polysilicon), a dielectric gate cap (214A) (e.g., oxide / nitride), and a U-shaped channel region (208A) surrounding the gate conduction region (210A). Another access transistor (Q2) includes a source region (213C) connected to a storage capacitor (C2), a drain region (213B) connected to a bit line of a DRAM chip, a gate dielectric layer (209) (e.g., oxide), a gate conduction region (210B) (including metal or polysilicon), a dielectric gate cap (214B) (e.g., oxide / nitride), and a U-shaped channel region (208B) surrounding the gate conduction region (210B). The access transistors (Q1) and (Q2) are U-groove transistors or buried gate transistors and may be formed in a well region (204) of the substrate (201) and surrounded by an STI region (202).

[0080] As illustrated in FIG. 15b, it is mentioned that the source region (213A), drain region (213B) and source region (213C) can be selectively grown and vertically grown from the silicon surface exposed in the (100) orientation in the first recess (216A), second recess (216B) and third recess (216C). As illustrated in FIG. 15b, the source region (213A) may include an LDD region (217A) and a strongly doped region (218A), the drain region (213B) may include an LDD region (217B) and a strongly doped region (218B), and the source region (213C) may include an LDD region (217C) and a strongly doped region (218C). In the DRAM cell of the present invention, the source / drain region of the access transistor is grown vertically (e.g. by selective epitaxial growth or atomic layer deposition technology) and is formed directly from the (100) crystal plane, and the interface is formed seamlessly with the channel region. In addition, there is no ion implantation process while forming the source / drain region, and there is no thermal annealing process which can make it difficult to define and control the junction boundary.

[0081] In summary, since the source / drain regions of the planar transistors of the CMOS structure in the peripheral circuit / sensing amplifier of the DRAM chip are grown laterally and directly from the (110) crystal plane, their interface is formed seamlessly with the channel region so that the gate length (Lgate) is precisely controlled. Additionally, the plane of the LDD (weakly doped drain) is grown horizontally in both the transistor channel and the substrate body using an in-situ doping technique during selective growth, and there is no ion implantation process that can be formed only downward from the top silicon, nor is there a thermal annealing process that can make it difficult to define and control the source / drain regions and the junction boundary. Unlike conventional doped regions formed by an ion implantation process, these selectively grown semiconductor regions (e.g., undoped region, LDD region, and heavily doped region) are independent of the semiconductor substrate.

[0082] The present invention can more accurately define the source / drain boundary edge with respect to the edge of the gate region, and the effective channel length (Leff) can be well controlled to minimize SCE, GIDL, and junction leakage current.

[0083] In addition, the n+ and p+ regions are completely separated by an insulator in the newly invented planar CMOS structure, and the proposed LISS can reduce the surface distance between junctions by increasing the separation distance to the silicon substrate to separate the junctions of the NMOS and PMOS transistors.

[0084] In addition, the present invention improves channel mobility by increasing stress through the formation of SEG of LDD in a heavily doped region containing various non-silicon dopants, such as germanium or carbon atoms. The doping concentration profile is controllable or adjustable in the formation of SEG / ALD in the source / drain region according to the present invention.

[0085] In addition, in well-known CMOS processes, the conductive material of the transistor gate can be polysilicon or metal; polysilicon is used because its operational function is compatible with Si substrates and is generally used in the first gate process. Polysilicon is a material composed of small silicon crystals. However, polysilicon has very low conductivity, and due to this low conductivity, charge accumulation is reduced, which delays channel formation and causes unwanted delays in the circuit. Therefore, polysilicon is primarily doped with impurities to function like a perfect conductor and reduce delays.

[0086] However, in polysilicon gate CMOS processes, polysilicon gates are doped by ion implantation, and problems arise when the polysilicon gates are not sufficiently or uniformly doped. Therefore, there are limitations on the dopant activation concentration; for example, in PMOS transistors, this dopant activation concentration is typically 1 x 10⁻⁶. 20 / cm 3 Less than (e.g., 7x10 19 / cm 3 ) and in NMOS transistors, the activation concentration of these dopants is generally 4x10 20 / cm 3 Less than (e.g., 2.5 x 10⁻⁶ 20 / cm 3 ...and so on. In addition, polysilicon depletion effects, a phenomenon in which the threshold voltage of MOSFET devices using polysilicon as a gate material changes undesirably, often occur, leading to unpredictable operation of electronic circuits. Therefore, a critical issue in advanced semiconductor processes involving polysilicon gates is to ensure that appropriate dopant activation is achieved in the polycrystalline silicon (polysilicon) gate to minimize these polysilicon depletion effects.

[0087] Meanwhile, the introduction of metals as gate conductive materials coincides with the point in mainstream CMOS technology where the SiO2 dielectric gate oxide is replaced by a high-k dielectric such as hafnium oxide, with metals being introduced specifically in the final gate process. Since polysilicon is not used in the gate structure, these high-k dielectric metal gates (HKMGs) have been introduced to address the polysilicon depletion effect. However, these HKMG processes are more complex and costly compared to polysilicon gate CMOS processes.

[0088] The present invention further solves the dopant activation problem of conventional polysilicon gate transistors and sets the dopant activation concentration in the semiconductor / silicon gate of an NMOS transistor to 3x10 20 / cm 3 (N+) or more, e.g., 4x10 20 / cm 3 It can be increased to (N+) or higher. In addition, the dopant activation concentration in the semiconductor / silicon gate of the PMOS transistor of the present invention is 8x10 19 / cm 3 (P+) or more, e.g., 1 x 10 20 / cm 3 It can be enhanced to (P+) or higher. Such high dopant activation concentrations can reduce polysilicon depletion effects, reduce the thickness of the gate dielectric layer, and improve ion (on-current) and gate control capabilities.

[0089] In conventional transistors with a polysilicon gate structure, the dopant activation concentration of this polysilicon gate is approximately 2.5 x 10 for conventional NMOS transistors. 20 / cm 3 and in the case of conventional PMOS transistors, approximately 7x10 19 / cm 3It is nothing more than that. During the fabrication of a conventional polysilicon gate, an undoped polysilicon layer is typically deposited on top of a gate oxide layer. Then, taking an NMOS transistor as an example, arsenic (As) or phosphorus (P) ions are injected into the undoped polysilicon, and the dopant concentration is activated through rapid thermal annealing.

[0090] Meanwhile, in the proposed transistor having a highly doped silicon gate structure, the dopant activation concentration of this highly doped silicon gate is 4x10 for the NMOS transistor. 20 / cm 3 It can be larger, and in the case of PMOS transistors, 1x10 20 / cm 3 According to the present invention illustrated in FIGS. 16 to 18, which illustrates an exemplary manufacturing process of an NMOS transistor, in order to increase the dopant activation concentration in the gate structure, a gate dielectric layer (331) (e.g., a thermal oxide or Hi-K material) is formed, and then, as shown in FIG. 16, a thin layer (e.g., 6 to 10 nm) of undoped or doped amorphous silicon (or polysilicon) (3321) is first deposited on the gate dielectric layer (331) at a temperature of 500 to 650°C. Next, this amorphous silicon layer is annealed at a temperature of approximately 1000°C or higher for recrystallization (e.g., laser annealing at ~1200°C + thermal annealing at ~600°C) to convert it into a large-grain silicon layer, where the particle size can be 1–2 µm or larger (TI KANINS, TR CASS, "Structure of Chemically Deposited Polycrystalline Silicon Films") Thin Solid FilmsSee , 16 (1973) 147-165; see Yasuo Wada and Shigeru Nishimatsu, "Grain Growth Mechanism of Heavily Phosphorus-implanted Polycrystalline Silicon", J. Electrochem. Soc.: SOLID-STATE SCIENCE AND TECHNOLOGY, Vol. 125, No. 9, 1499-1504, September 1978).

[0091] Subsequently, as illustrated in FIG. 17, an in-situ N+ doped silicon layer (3323) is optionally grown (e.g., selective epitaxial growth “SEG”) using a silicon layer (3322) of larger particles as a seed layer, and then annealed by a rapid thermal annealing (RTA) process at a temperature of about 1000°C or higher so that the dopant activation concentration of the optionally grown Si layer is about 4 x 10 20 / cm 3 This is done so (see ZN Weinrich et al., “Dopant-defect interactions in highly doped epitaxial Si:P thin films”, Thin Solid Films 685 (2019) 1-7). In addition, because the thickness of the original undoped amorphous silicon layer is very thin, the dopant from the in-situ N+ doped silicon layer diffuses into the recrystallized larger-grain silicon layer through the aforementioned RTA, so that the dopant concentration in the recrystallized larger-grain silicon layer becomes nearly the same as that of the in-situ N+ doped silicon layer. Therefore, after rapid thermal annealing (RTA), it becomes almost difficult to distinguish between the in-situ N+ doped silicon layer (3323) and the larger-grain silicon layer (3322).

[0092] Subsequently, to complete the NMOS transistor structure as shown in FIG. 18, a standard gate patterning process is applied to form the gate shape, and a TiN layer (333) and a tungsten layer (334) are deposited on the in-situ doped N+ silicon (3322), and an LDD region and a nitride spacer are formed. Then, as shown in FIG. 18, an N+ source / drain region can be formed by an ion implantation and annealing process. Since the particle size of the recrystallized large-grain silicon layer can be 1 to 2 µm or larger, it can be seen that the in-situ N+ doped silicon layer formed by SEG is also likewise. After the standard gate patterning process is formed based on a technology node of 28 nm or less, the gate length generally does not exceed 150 nm. Therefore, within the gate length of the in-situ N+ doped silicon layer, it is almost a single crystal layer or contains three or fewer silicon particles along the cut line of the gate length.

[0093] Similarly, in the process of forming the polysilicon gate of a conventional PMOS transistor, an undoped polysilicon layer is first deposited on top of a gate oxide layer. Then, boron (B) ions are implanted into the undoped polysilicon, and the dopant concentration is activated through rapid thermal annealing. The dopant activation concentration of this polysilicon gate of a conventional PMOS transistor is 1 x 10⁻⁶. 20 / cm 3 It is not larger than. Meanwhile, FIGS. 19 to 21 illustrate an exemplary manufacturing process of a PMOS transistor according to the present invention; although the detailed description thereof is omitted as it is similar to FIGS. 16 to 18, the type of dopant in the epitaxial silicon gate of the PMOS transistor is different from the type of dopant in the epitaxial silicon gate of the NMOS transistor. The dopant activation concentration in such an epitaxial silicon gate of the PMOS transistor according to the present invention is 1x10 20 / cm 3It will be bigger.

[0094] FIGS. 22a and 22b illustrate a comparison between a polysilicon gate transistor according to a conventional process (Fig. 22a) and a polysilicon gate transistor according to the process of the present invention (Fig. 22b). A high dopant activation concentration of in-situ doped N+ / P+ silicon (3322) can reduce polysilicon depletion effects, reduce the thickness of the gate dielectric layer (331), and improve ion and gate control capabilities. In summary, the present invention solves the dopant activation problem of conventional polysilicon gate transistors and reduces the dopant activation concentration in the silicon gate of NMOS transistors and PMOS transistors to 4 x 10 20 / cm 3 (N +) and 1 x 10 20 / cm 3 The concentration is increased above (P+). Such a high dopant activation concentration can reduce the polysilicon depletion effect, reduce the thickness of the gate dielectric layer, and improve ion and gate control capabilities. The present invention can be applied to all transistors having silicon gates, such as planar transistors, fin structure transistors, GAA transistors, etc. Furthermore, these epitaxial silicon gate transistors can be applied not only to logic circuits but also to peripheral circuits of semiconductor memory such as DRAM. Additionally, the present invention can be applied to other semiconductor materials used in the gate structure of MOS transistors, such as SiGe, SiC, or GaN.

[0095] Figure 23a shows the electron backscatter diffraction (EBSD) results of an annealed α-Si layer in an actual sample structure. In the sample structure, the α-Si layer was formed on an oxide layer originally deposited on a Si substrate, and then the α-Si layer was annealed as shown in the top-left figure of Figure 23a. The EBSD results show that many particles are present in the annealed α-Si layer and that the particle size can be about 1.35 μm. In addition, from the transmission electron microscope (TEM) results shown in Figure 23b, polycrystalline planes of the annealed α-Si layer can be observed, and from the X-ray diffraction (XRD) results, two identified regions of the annealed α-Si layer in Figure 23b represent two (110) particles as shown in the right and left figures of Figure 23c. Thus, the process proposed in the present invention can form larger Si particles in the annealed α-Si layer.

[0096] A person skilled in the art will readily observe that numerous modifications and changes to the apparatus and method may be made while maintaining the teachings of the present invention. Accordingly, the foregoing disclosure should be interpreted as being limited only by the scope and limitations of the appended claims.

Claims

Claim 1 A semiconductor substrate; a first dielectric layer formed directly on a first portion of the semiconductor substrate - the length of the first dielectric layer is equal to the length of the first portion of the semiconductor substrate -; an undoped semiconductor layer on the first dielectric layer; and a semiconductor structure comprising a source or drain region disposed within the semiconductor substrate and adjacent to the first dielectric layer. Claim 2 A semiconductor structure according to claim 1, wherein the first sidewall of the undoped semiconductor layer is covered by a second dielectric layer, and the second sidewall of the undoped semiconductor layer located opposite the first sidewall is covered by a third dielectric layer. Claim 3 In claim 2, the non-doped semiconductor layer is a semiconductor structure comprising a Si-containing material. Claim 4 In claim 3, a semiconductor structure in which the particle size within the Si-containing material is greater than 1 μm. Claim 5 In claim 2, the first dielectric layer is a semiconductor structure comprising an oxide film. Claim 6 In claim 3, the semiconductor structure comprising both the second dielectric layer and the third dielectric layer, wherein the second dielectric layer and the third dielectric layer both comprise an oxide film. Claim 7 A semiconductor structure according to claim 2, further comprising a dielectric cap layer on top of the non-doped semiconductor layer. Claim 8 A semiconductor structure according to claim 7, further comprising a doped semiconductor layer between the dielectric cap layer and the undoped semiconductor layer, wherein the doped semiconductor layer comprises a Si-containing material and the particle size within the Si-containing material is greater than 1 μm. Claim 9 A semiconductor substrate; a first dielectric layer formed directly on a first portion of the semiconductor substrate, wherein the length of the first dielectric layer is equal to the length of the first portion of the semiconductor substrate; a first undoped semiconductor layer on the first dielectric layer, wherein the first undoped semiconductor layer comprises a first Si-containing material, and the particle size within the first Si-containing material is greater than 1 μm; a dielectric cap layer on top of the first undoped semiconductor layer; and a semiconductor structure comprising a source or drain region disposed within the semiconductor substrate and adjacent to the first dielectric layer. Claim 10 A semiconductor structure according to claim 9, wherein the first sidewall of the first undoped semiconductor layer is covered by a second dielectric layer, and the second sidewall of the first undoped semiconductor layer located opposite the first sidewall is covered by a third dielectric layer. Claim 11 In claim 10, the first dielectric layer comprises an oxide film, and the second dielectric layer and the third dielectric layer both comprise an oxide film. Claim 12 In claim 9, the semiconductor structure further comprises a second semiconductor layer between the dielectric cap layer and the first undoped semiconductor layer, wherein the second semiconductor layer comprises a second Si-containing material, and the particle size within the second Si-containing material is greater than 1 μm. Claim 13 A method for manufacturing a semiconductor structure comprising: a step of preparing a semiconductor substrate; a step of defining a first portion of the semiconductor substrate; a step of forming a first dielectric layer directly on the first portion of the semiconductor substrate, wherein the length of the first dielectric layer is equal to the length of the first portion of the semiconductor substrate; a step of forming an undoped semiconductor layer on the first dielectric layer; a step of annealing the undoped semiconductor layer; and a step of forming a source or drain region disposed within the semiconductor substrate and adjacent to the first dielectric layer. Claim 14 A method for manufacturing a semiconductor structure according to claim 13, wherein the annealing step is performed at a temperature of 1000°C or higher. Claim 15 A method for manufacturing a semiconductor structure according to claim 13, wherein the non-doped semiconductor layer comprises a first Si-containing material, and after the annealing step, the particle size within the first Si-containing material is greater than 1 μm. Claim 16 A method for manufacturing a semiconductor structure according to claim 13, further comprising the step of forming a dielectric cap layer on top of the undoped semiconductor layer after the annealing step. Claim 17 A method for manufacturing a semiconductor structure according to claim 16, further comprising the step of forming a doped semiconductor layer on the undoped semiconductor layer after the annealing step and before the step of forming the dielectric cap layer, wherein the doped semiconductor layer comprises a second Si-containing material and the particle size within the second Si-containing material is greater than 1 μm. Claim 18 A method for manufacturing a semiconductor structure comprising: a step of preparing a semiconductor substrate; a step of defining a first portion of the semiconductor substrate; a step of forming a first dielectric layer directly on the first portion of the semiconductor substrate, wherein the length of the first dielectric layer is equal to the length of the first portion of the semiconductor substrate; a step of forming a first undoped semiconductor layer on the first dielectric layer, wherein the first undoped semiconductor layer comprises a first Si-containing material; a step of annealing the first undoped semiconductor layer, wherein the particle size within the first Si-containing material after annealing is greater than 1 μm; a step of forming a dielectric cap layer on the first undoped semiconductor layer; and a step of forming a source or drain region disposed within the semiconductor substrate and adjacent to the first dielectric layer. Claim 19 A method for manufacturing a semiconductor structure according to claim 18, wherein the annealing step is performed at a temperature of 1000°C or higher. Claim 20 A method for manufacturing a semiconductor structure according to claim 18, further comprising the step of forming a second semiconductor layer on the first undoped semiconductor layer prior to the step of forming the dielectric cap layer, wherein the second semiconductor layer comprises a second Si-containing material and the particle size within the second Si-containing material is greater than 1 μm.

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