Light emitting display apparatus and multi screen display apparatus using the same

Abstract

A light-emitting display device according to an embodiment of the present specification comprises: a substrate; a display unit comprising a plurality of pixel driving lines disposed on the substrate and a plurality of pixels selectively connected to the plurality of pixel driving lines; a light-emitting element layer comprising a self-luminous element disposed on the display unit; a dam unit comprising at least one dam disposed along an edge portion of the substrate and having a metal line; an encapsulation layer comprising an organic encapsulation layer disposed to cover the light-emitting element layer and surrounded by the dam unit, a plurality of switching circuit units disposed to overlap with at least one dam and selectively connected to the plurality of pixel driving lines; and a front pad unit comprising a plurality of front pads disposed on one edge portion of the substrate and electrically coupled to the plurality of pixel driving lines and the metal line of at least one dam, wherein each of the plurality of switching circuit units comprises a first and second switching circuit having a gate electrode electrically coupled to the metal line of at least one dam.

Description

Technology Field

[0001] This specification relates to a light-emitting display device and a multi-screen display device using the same. Background Technology

[0002] Emissive displays are self-emissive display devices that, unlike liquid crystal displays, do not require a separate light source, allowing them to be manufactured in lightweight and thin forms. Furthermore, emissive displays are gaining attention as next-generation display devices because they offer advantages in terms of power consumption due to low-voltage driving, as well as superior color reproduction, response speed, viewing angle, and contrast ratio.

[0003] A light-emitting display device displays an image through the light emission of a light-emitting element layer comprising a light-emitting element interposed between two electrodes. At this time, light generated by the light emission of the light-emitting element is emitted to the outside through the electrodes and the substrate.

[0004] The light-emitting display device includes a display panel implemented to display an image. The display panel may include a display area having a plurality of pixels for displaying an image, and a bezel area surrounding the display area.

[0005] Conventional light-emitting display devices require a bezel (or structure) to cover a bezel area placed at the border (or edge portion) of a display panel, and the bezel width may increase due to the width of the bezel.

[0006] Recently, multi-screen display devices that realize a large screen by arranging light-emitting display devices in a grid shape are being commercialized.

[0007] However, conventional multi-screen display devices have boundary areas called seams between adjacent displays due to the bezel areas of each display device or the bezels. These boundary areas reduce immersion by creating a sense of discontinuity (or abruptness) when displaying a single image across the entire screen of the multi-screen device. The problem to be solved

[0008] The present specification has the technical objective of providing a light-emitting display device having zero bezel width and a multi-screen display device including the same.

[0009] The present specification has the technical objective of providing a light-emitting display device having a zero bezel width and minimizing the degradation of reliability of a self-luminous element due to moisture penetration, and a multi-screen display device including the same.

[0010] The present specification may provide a light-emitting display device capable of detecting an electrical short circuit between routing lines connecting front pads and rear pads, and a multi-screen display device including the same.

[0011] The present specification can provide a light-emitting display device capable of minimizing image degradation due to resistance deviation of routing lines connecting front pads and rear pads, and a multi-screen display device including the same.

[0012] The present specification has the technical objective of providing a light-emitting display device having zero bezel width and a pixel circuit that can be protected from electrostatic discharge, and a multi-screen display device including the same.

[0013] The problems to be solved according to this specification are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art to which the technical concept of this specification belongs from the description below. means of solving the problem

[0014] A light-emitting display device according to an embodiment of the present specification comprises: a substrate; a display unit comprising a plurality of pixel driving lines disposed on the substrate and a plurality of pixels selectively connected to the plurality of pixel driving lines; a light-emitting element layer comprising a self-luminous element disposed on the display unit; a dam unit comprising at least one dam disposed along an edge portion of the substrate and having a metal line; an encapsulation layer comprising an organic encapsulation layer disposed to cover the light-emitting element layer and surrounded by the dam unit, a plurality of switching circuit units disposed to overlap with at least one dam and selectively connected to the plurality of pixel driving lines; and a front pad unit comprising a plurality of front pads disposed on one edge portion of the substrate and electrically coupled to the plurality of pixel driving lines and the metal line of at least one dam, wherein each of the plurality of switching circuit units comprises a first and second switching circuit having a gate electrode electrically coupled to the metal line of at least one dam.

[0015] A multi-screen display device according to an embodiment of the present specification comprises a plurality of display devices arranged along at least one of a first direction and a second direction crossing the first direction, wherein each of the plurality of display devices comprises a light-emitting display device, and the light-emitting display device comprises: a substrate; a display portion comprising a plurality of pixel driving lines arranged on the substrate and a plurality of pixels selectively connected to the plurality of pixel driving lines; a light-emitting element layer comprising a self-luminous element arranged on the display portion; a dam portion comprising at least one dam arranged along an edge portion of the substrate and having a metal line; an encapsulation layer having an organic encapsulation layer arranged to cover the light-emitting element layer and surrounded by the dam portion; a plurality of switching circuit portions arranged to overlap with at least one dam and selectively connected to the plurality of pixel driving lines; and a front pad portion comprising a plurality of front pads arranged on one edge portion of the substrate and electrically coupled to the plurality of pixel driving lines and the metal line of at least one dam, wherein each of the plurality of switching circuit portions comprises a first and second switching circuit having a gate electrode electrically coupled to the metal line of at least one dam.

[0016] Specific details according to various examples of this specification, other than the means for solving the problem mentioned above, are included in the description and drawings below. Effects of the invention

[0017] According to the means of the solution of the present specification, a light-emitting display device having zero bezel width and a multi-screen display device including the same can be provided.

[0018] According to the solution of the present specification, a light-emitting display device having a zero bezel width and a multi-screen display device including the same can be provided, wherein the degradation of reliability of a self-luminous element due to moisture penetration can be minimized.

[0019] According to the solution of the present specification, a light-emitting display device capable of detecting an electrical short circuit between routing lines connecting front pads and rear pads and a multi-screen display device including the same can be provided.

[0020] According to the solution of the present specification, a light-emitting display device capable of minimizing image degradation due to resistance deviation of routing lines connecting front pads and rear pads, and a multi-screen display device including the same can be provided.

[0021] According to the solution of the present specification, a light-emitting display device having zero bezel width and a pixel circuit that can be protected from electrostatic discharge, and a multi-screen display device including the same can be provided.

[0022] According to the solution of the present specification, a multi-screen display device capable of displaying images without interruption can be provided.

[0023] Since the problem to be solved, the means of solving the problem, and the effects mentioned above do not specify the essential features of the claim scope, the scope of rights of the claim is not limited by the matters described in the content of the invention. Brief explanation of the drawing

[0024] FIG. 1 is a plan view showing a light-emitting display device according to one embodiment of the present specification. FIG. 2 is a rear perspective view showing a light-emitting display device according to one embodiment of the present specification. FIG. 3a is a drawing showing a single pixel according to an embodiment illustrated in FIG. 1. FIG. 3b is a drawing showing a single pixel according to another embodiment illustrated in FIG. 1. FIG. 3c is a drawing showing a single pixel according to another embodiment shown in FIG. 1. Figure 4 is a schematic enlarged view of the 'B1' portion shown in Figure 1. Figure 5 is an equivalent circuit diagram for a single pixel shown in Figures 1 and 3. Figure 6 is a diagram showing the gate driving circuit illustrated in Figures 1 and 4. FIG. 7 is a drawing for explaining a plurality of switching circuits in a light-emitting display device according to one embodiment of the present specification. FIG. 8 is a drawing showing the first pad section, one switching circuit section, and a damper section illustrated in FIG. 7. Figure 9 is a cross-sectional view of line I-I' shown in Figures 2 and 8. Figure 10 is an enlarged view of 'B2' shown in Figure 9. Figure 11 is an enlarged view of 'B3' shown in Figure 9. FIG. 12 is a cross-sectional view of line II-II' shown in FIG. 8. FIG. 13 is a drawing for explaining the first and second pad portions and routing portions according to another embodiment of the present specification. FIG. 14 is a plan view showing a light-emitting display device according to another embodiment of the present specification. FIG. 15 is a rear view showing a light-emitting display device according to another embodiment of the present specification. FIG. 16 is a schematic diagram showing a switching circuit, a driving integrated circuit, and a timing controller according to one embodiment of the present specification. FIG. 17 is a drawing for explaining a plurality of switching circuit sections according to another embodiment of the present specification. FIG. 18 is a cross-sectional view of line III-III' shown in FIG. 17. FIG. 19 is a schematic diagram showing a switching circuit, a driving integrated circuit, and a timing controller according to another embodiment of the present specification. FIG. 20 is a drawing for explaining a plurality of switching circuits according to another embodiment of the present specification. FIG. 21 is a cross-sectional view of line IV-IV' shown in FIG. 20. FIG. 22 is a cross-sectional view of line V-V' shown in FIG. 20. FIG. 23 is a schematic diagram showing a switching circuit, a driving integrated circuit, and a timing controller according to another embodiment of the present specification. FIG. 24 is a drawing showing a multi-screen display device according to one embodiment of the present specification. FIG. 25 is a schematic cross-sectional view of line VI-VI' shown in FIG. 24. Specific details for implementing the invention

[0025] The advantages and features of this specification and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below but may be implemented in various different forms; these embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and this specification is defined only by the scope of the claims.

[0026] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of this specification are exemplary and are not limited to the depicted items. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of this specification, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" mentioned above are used, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0027] In interpreting the components, even if there is no separate explicit description of the error range, it is interpreted as including the error range.

[0028] In the case of a description of a positional relationship, for example, when the positional relationship between two parts is described using terms such as "above," "upper," "lower," or "next to," for example, unless "immediately" or "directly" is used, one or more other parts may be located between the two parts.

[0029] In the case of an explanation of temporal relationships, when the temporal order is explained using "after," "followed," "next," "before," etc., cases that are not continuous may also be included unless "immediately" or "directly" is used.

[0030] The terms first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0031] In describing the components of this specification, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are intended only to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by the terms. Where it is stated that a component is "connected," "coupled," or "joined" to another component, it should be understood that the component may be directly connected or joined to the other component, but that other components may be "interposed" between each component that may be indirectly connected or joined unless specifically stated otherwise.

[0032] "At least one" should be understood to include all combinations of one or more associated components. For example, the meaning of "at least one of the first, second, and third components" may be said to include not only the first, second, or third components, but also all combinations of two or more of the first, second, and third components.

[0033] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0034] The embodiments of this specification are described below through the attached drawings and examples. For the convenience of explanation, the scale of the components shown in the drawings may differ from the actual scale and is therefore not limited to the scale shown in the drawings.

[0035] FIG. 1 is a plan view showing a light-emitting display device according to one embodiment of the present specification, and FIG. 2 is a rear perspective view of a light-emitting display device according to one embodiment of the present specification.

[0036] Referring to FIG. 1 and FIG. 2, a light-emitting display device (or light-emitting display panel) (10) according to one embodiment of the present specification may include a substrate (100), a wiring substrate (200), a coupling member (300), and a routing portion (400).

[0037] The substrate (100) may be represented as a first substrate, a front substrate, a base substrate, or a pixel array substrate. For example, the substrate (100) may be a glass substrate, a thin glass substrate that can be bent or curved, or a plastic substrate.

[0038] The substrate (100) may include a display unit (AA), a plurality of pixels (P), a damper unit (104), and a plurality of switching circuit units.

[0039] The display portion (AA) is an area where an image is displayed, and may be expressed as an active portion, an active area, or a display area. The size of the display portion (AA) may be the same as the size of the substrate (or light-emitting display device) (10). For example, the size of the display portion (AA) may be the same as the entire size of the first surface of the substrate (100). Accordingly, the display portion (AA) is implemented (or placed) over the entire front surface of the substrate (100), so that the entire front surface of the light-emitting display device can implement the display portion (AA).

[0040] The end (or outermost) of the display portion (AA) may overlap with the outer surface (OS) of the substrate (100) or be aligned with the outer surface (OS) of the substrate (100). For example, with respect to the thickness direction (Z) of the light-emitting display device (or light-emitting display panel), the side of the display portion (AA) may be aligned with a vertical extension line extending vertically from the outer surface (OS) of the substrate (100). The side of the display portion (AA) may be surrounded only by air without being surrounded by a separate structure. That is, all sides (or outer surfaces) of the display portion (AA) or the substrate (100) may be configured to be in direct contact with air without being surrounded by a separate structure. Accordingly, by having the outer surface (OS) of the substrate (100) corresponding to the end of the display portion (AA) surrounded only by air, the light-emitting display device (or light-emitting display panel) (10) according to the embodiment of the present specification may have an air-bezel structure or a bezel-less (or zeroed-bezel) structure in which the end (or side) of the display portion (AA) is surrounded by air.

[0041] A plurality of pixels (P) may be arranged (or positioned) on a display portion (AA) of a substrate (100) to have a first spacing (D1) along each of a first direction (X) and a second direction (Y). The first direction (X) may be a horizontal direction or a horizontal direction, or a first length direction (or horizontal length direction) of the substrate (100) or the light-emitting display device. The second direction (Y) may be a vertical direction or a vertical direction, or a second length direction (or vertical length direction) of the substrate (100) or the light-emitting display device.

[0042] Each of the plurality of pixels (P) can be implemented in a plurality of pixel regions arranged in a display portion (AA) of the substrate (100). Each of the plurality of pixel regions may have a first length (L1) parallel to a first direction (X) and a second length (L2) parallel to a second direction (Y). The first length (L1) may be the same as the second length (L2) or the same as a first interval (D1). The first length (L1) and the second length (L2) may be the same as the first interval (D1). Accordingly, the plurality of pixels (or pixel regions) (P) may all have the same size.

[0043] Two adjacent pixels (P) along each of the first direction (X) and the second direction (Y) may have the same first interval (D1) within the error range of the manufacturing process. The first interval (D1) may be the pitch (or pixel pitch) between two adjacent pixels (P). For example, the first interval (or pixel pitch) (D1) may be the distance (or length) between the centers of each of two adjacent pixels (P). For example, the first interval (or pixel pitch) (D1) may be the shortest distance (or shortest length) between the centers of each of two adjacent pixels (P).

[0044] Each of the plurality of pixels (P) may include a circuit layer comprising a pixel circuit implemented in a pixel area of ​​a substrate (100), and a light-emitting element layer disposed on the circuit layer and connected to the pixel circuit. The pixel circuit is connected to a pixel driving line comprising a data line, a gate line, and a reference line disposed in the pixel area, and outputs a data current corresponding to the difference voltage between a data signal supplied to the data line and a reference voltage supplied to the reference line according to a scan signal supplied to the gate line. The light-emitting element layer may include a self-emissive element (or self-emissive layer) commonly disposed in the remaining portion excluding the edge portion of the display portion (AA). The self-emissive element may be configured to emit light by a data current supplied from the pixel circuit.

[0045] Multiple pixels (P) can be divided into outermost pixels (Po) and inner pixels (Pi).

[0046] The outermost pixels (Po) may be pixels among a plurality of pixels (P) that are positioned closest to the outer surface (OS) of the substrate (100). For example, the outermost pixels (Po) may be pixels positioned in each of the first horizontal line (or first pixel row), the last horizontal line (or last pixel row), the first vertical line (or first pixel column), and the last vertical line (or last pixel column).

[0047] The second gap (D2) between the center of the outermost pixels (Po) and the outer surface (OS) of the substrate (100) may be half or less than half of the first gap (D1). For example, the second gap (D2) may be the shortest distance (or shortest length) between the center of the outermost pixels (Po) and the outer surface (OS) of the substrate (100).

[0048] When the second gap (D2) exceeds half of the first gap (D1), the substrate (100) must have a size larger than the display portion (AA) by the difference between half of the first gap (D1) and the second gap (D2), and thus the area between the end of the outermost pixel (Po) and the outer surface (OS) of the substrate (100) can be configured as a non-display area surrounding the entire display portion (AA). For example, when the second gap (D2) exceeds half of the first gap (D1), the substrate (100) inevitably includes a bezel area corresponding to the non-display area surrounding the entire display portion (AA). In contrast, when the second interval (D2) is half or less than half of the first interval (D1), the end of the outermost pixel (Po) may be aligned with the outer surface (OS) of the substrate (100) or the end of the display portion (AA) may be aligned with the outer surface (OS) of the substrate (100), and as a result, the display portion (AA) may be implemented (or placed) over the entire front surface of the substrate (100).

[0049] The inner pixels (Pi) may be the pixels among the plurality of pixels (P) excluding the outermost pixels (Po), or pixels among the plurality of pixels (P) that are surrounded by the outermost pixels (Po). These inner pixels (Pi) may be implemented with a different configuration or structure from the outermost pixels (Po).

[0050] The dam portion (104) may be implemented on the edge portion of the substrate (100) or on the edge portion of the outermost pixels (Po) placed in the display portion (AA). For example, the dam portion (104) may be placed within the display portion (AA) to have a planar closed-loop line shape (or continuous line shape or closed-loop shape) along the area between the center of the outermost pixels (Po) and the outer surface (OS) of the substrate (100). For example, the closed-loop line shape may be a continuously connected ring shape.

[0051] The dam (104) can be configured to block the spreading or overflow of the organic encapsulation layer among the encapsulation layers placed on the light-emitting element layer at the edge portions of the outermost pixels (Po). Additionally, the dam (104) can block the lateral moisture penetration path by separating (or disconnecting) at least some layer of the light-emitting element layer at the edge portions of the outermost pixels (Po), thereby preventing or minimizing the degradation of the reliability of the light-emitting element layer due to lateral moisture penetration.

[0052] The dam (104) may include an undercut structure or an eaves structure for separating (or severing) at least some layers of the light-emitting element layer. For example, the dam (104) may include an undercut region implemented by the undercut structure or the eaves structure. Accordingly, at least some layers of the light-emitting element layer may be physically separated (or severed) by the undercut region of the dam (104). For example, the self-luminous element (or self-luminous layer) of the light-emitting element layer formed (or deposited) on the dam (104) may be separated (or severed) at least once in the undercut region of the dam (104).

[0053] Each of the plurality of switching circuits may be configured to overlap with the damper (104). For example, each of the plurality of switching circuits may be placed below the damper (104). For example, the damper (104) may be placed above the plurality of switching circuits. Each of the plurality of switching circuits may be placed (or included) within the outermost pixels (Po) located in the first edge portion of the substrate (100). For example, one switching circuit may be placed within one outermost pixel (Po). These plurality of switching circuits will be described later.

[0054] A light-emitting display device (or light-emitting display panel) (10) or substrate (100) according to one embodiment of the present specification may further include a first pad portion (110).

[0055] The first pad portion (110) may be a front pad portion or a first routing pad. The first pad portion (110) may be placed (or included) within the outermost pixels (Po) located on the first edge portion (or one edge portion) of the first surface of the substrate (100) parallel to the first direction (X), thereby the substrate (100) does not include a non-display area (or bezel area) according to the first pad portion (110).

[0056] The first pad portion (110) may include a plurality of first pads (or front pads) connected (or coupled) to pixel driving lines. For example, the first pad portion (110) may include a plurality of first pads (or front pads) for receiving data signals, gate control signals, pixel driving power, reference voltage, and pixel common voltage, etc. from a driving circuit portion. Each of the outermost pixels (Po) disposed on a first edge portion of the substrate (100) to include the first pad portion (110) may include at least one of the plurality of first pads. Accordingly, the outermost pixel (Po) may be implemented with a configuration or structure different from an internal pixel (Pi) that does not include a first pad by including at least one first pad.

[0057] For example, when the first pad portion (110) is not placed (or included) inside the outermost pixels (Po) but is placed between the end of the outermost pixels (Po) and the outer surface (OS) of the substrate (100), the substrate (100) has a non-display area in which the first pad portion (110) is placed between the end of the outermost pixels (Po) and the outer surface (OS) of the substrate (100). Due to this non-display area, the second gap (D2) exceeds half of the first gap (D1), and the entire substrate (100) cannot be implemented as a display portion (AA), and a separate bezel is required to cover the non-display area. In contrast, the first pad portion (110) according to the embodiment of the present specification is positioned (or included) inside the outermost pixels (Po), so that a non-display area (or bezel area) according to the first pad portion (110) is not formed or does not exist between the end of the outermost pixels (Po) and the outer surface (OS) of the substrate (100), and thus the second gap (D2) may be half or less than half of the first gap (D1), so that the entire substrate (100) can be implemented as a display portion (AA).

[0058] A light-emitting display device (or light-emitting display panel) (10) or substrate (100) according to one embodiment of the present specification may further include a gate driving circuit (150).

[0059] A gate driving circuit (150) is placed or embedded within a display unit (AA) so as to be able to supply a scan signal (or gate signal) to pixels (P) placed on a substrate (100). The gate driving circuit (150) can simultaneously supply a scan signal to pixels (P) placed in a horizontal line parallel to the first direction (X). For example, the gate driving circuit (150) can supply at least one scan signal to pixels (P) placed in a single horizontal line.

[0060] The gate driving circuit (150) may be implemented as a shift register comprising a plurality of stage circuits. That is, the light-emitting display device (or light-emitting display panel) according to the embodiment of the present specification may include a gate shift register or a scan shift register that is embedded in the display portion (AA) of the substrate (100) and supplies a scan signal to pixels (P).

[0061] Each of the plurality of stage circuits may include a plurality of branch circuits (151) spaced apart along each horizontal line of the substrate (100) along the first direction (X). Each of the plurality of branch circuits (151) may be scattered between a plurality of pixels (P) within each horizontal line of the display unit (AA). Each of the plurality of branch circuits (151) may include at least one thin-film transistor (or branch thin-film transistor). For example, each of the plurality of branch circuits (151) may be placed one between each of at least one pixel (P) (or pixel area) within a single horizontal line. Each of these plurality of stage circuits may generate a scan signal according to the driving of the plurality of branch circuits in response to a gate control signal supplied through gate control lines, and supply the scan signal to the pixels (P) placed on the corresponding horizontal line.

[0062] A light-emitting display device (or light-emitting display panel) (10) or substrate (100) according to one embodiment of the present specification may further include at least one separation part (105).

[0063] At least one separation portion (105) may be implemented on the edge portion of the substrate (100) or on the edge portion of the outermost pixels (Po) placed in the display portion (AA). For example, at least one separation portion (105) may be placed within the display portion (AA) to have a planar closed-loop line shape (or continuous line shape or closed-loop shape) along the peripheral area of ​​the dam portion (104). By doing so, the outermost pixel (Po) may be implemented with a different configuration or structure from the inner pixel (Pi) that does not include the separation portion (105) by including at least one separation portion (105).

[0064] At least one separation part (105) blocks a lateral moisture penetration path by separating (or severing) at least a portion of the light-emitting element layer within the outermost pixels (Po), thereby preventing or minimizing the degradation of the reliability of the light-emitting element layer due to lateral moisture penetration. The separation part (105) may include an undercut structure or an eaves structure for separating (or severing) at least a portion of the light-emitting element layer. For example, the separation part (105) may include an undercut region implemented by the undercut structure or the eaves structure. Accordingly, at least a portion of the light-emitting element layer may be physically separated (or severed) by the undercut region of the separation part (105). For example, the self-emissive element (or self-emissive layer) of the light-emitting element layer formed (or deposited) on the separation part (105) may be separated (or severed) at least once in the undercut region of the separation part (105).

[0065] The wiring board (200) may be represented as a second board, a link board, a lower board, a rear board, or a link glass. The wiring board (200) may be a glass board, a thin glass board that can be bent or curved, or a plastic board. For example, the wiring board (200) may be made of the same material as the substrate (100). The wiring board (200) may have the same size as the substrate (100), but is not limited thereto, and may have a smaller size than the substrate (100). For example, it may be preferable for the wiring board (200) to have the same size as the substrate (100) in order to maintain or secure the rigidity of the substrate (100).

[0066] The wiring board (200) may include a second pad portion (210), at least one third pad portion (230), and a link line portion (250).

[0067] The second pad portion (210) may be a rear pad portion or a second routing pad. The second pad portion (210) may be placed on one edge portion (or the first rear edge portion) of the rear portion (200b) of the wiring board (200) that overlaps with the first pad portion (110) placed on the front portion of the substrate (100).

[0068] The second pad portion (210) may include a plurality of second pads (or rear pads) arranged parallel to each other along the first edge portion of the wiring board (200) along the first direction (X). For example, the second pad portion (210) may include a plurality of second pads (or rear pads) for receiving data signals, gate control signals, pixel driving power, reference voltage, and pixel common voltage, etc. from the driving circuit portion. Each of the plurality of second pads may overlap one-to-one with each of the plurality of first pads arranged on the first pad portion (110).

[0069] At least one third pad portion (230) may be an input pad portion, a driving circuit connection pad portion, a driving circuit bonding portion, or a driving circuit bonding pad portion. At least one third pad portion (230) may be placed on the rear surface (200b) of the wiring board (200). For example, at least one third pad portion (230) may be placed in the middle portion adjacent to the first edge portion of the rear surface (200b) of the wiring board (200). For example, the wiring board (200) may include two or more third pad portions (230) connected to the second pad portion (210). For example, the second pad portion (210) may be divided into two or more regions along the first direction (X), and each of the two or more third pad portions (230) may be configured to be connected to each divided region of the second pad portion (210).

[0070] At least one third pad section (230) may include a plurality of input pads (or third pads) spaced apart from each other to have a constant spacing along the first direction (X). At least one third pad section (230) may include a plurality of input pads (or third pads) for receiving a data signal, a gate control signal, a pixel driving power supply, a reference voltage, and a pixel common voltage, etc. from a driving circuit section.

[0071] The link line section (250) may be positioned between the second pad section (210) and at least one third pad section (230). The link line section (250) may include a plurality of link lines configured to connect a plurality of input pads positioned in at least one third pad section (230) with a plurality of second pads positioned in the second pad section (210).

[0072] Some of the plurality of input pads disposed in at least one third pad section (230) may be coupled one-to-one with some of the plurality of second pads disposed in the second pad section (210) through a corresponding link line among the plurality of link lines. For example, among the plurality of input pads, input pads that receive a data signal, a gate control signal, a pixel driving power supply, and a reference voltage, respectively, from a driving circuit section may be connected one-to-one with a corresponding second pad disposed in the second pad section (210) through a corresponding link line.

[0073] The remainder of the plurality of input pads disposed in at least one third pad section (230) may be commonly coupled with the remainder of the plurality of second pads. For example, one or more pixel common voltage input pads among the plurality of input pads that receive a pixel common voltage may be commonly coupled with the plurality of second pads among the plurality of second pads that receive a pixel common voltage through a pixel common power link line (257).

[0074] The pixel common power link line (257) may include a first common link line (257a) and a second common link line (257b).

[0075] The first common link line (257a) can be coupled with one or more pixel common voltage input pads disposed on at least one third pad portion (230). For example, the first common link line (257a) can be disposed on one side of the third pad portion (230) on the rear surface (200b) of the wiring board (200).

[0076] The first common link line (257a) may be arranged or formed to have a relatively large size (or area) on the rear surface (200b) of the wiring board (200) between the second pad portion (210) and at least one third pad portion (230) so that the voltage drop of the applied pixel common power supply can be minimized. The size of the first common link line (257a) according to one embodiment may gradually increase from one side to the other. For example, the size of the first common link line (257a) may gradually increase from at least one third pad portion (230) toward the outer surface (OS) of the wiring board (200).

[0077] The second common link line (257b) may be positioned at the first edge portion of the rear surface (200b) of the wiring board (200) so as to be adjacent to the second pad portion (210). According to one embodiment, the second common link line (257b) may be positioned parallel to the first direction (X) and positioned to face all of the plurality of second pads positioned on the second pad portion (210). For example, the second common link line (257b) may have a bar shape having a relatively large size (or area) to minimize the voltage drop of the pixel common voltage applied to the pixel common power link line (257).

[0078] The second common link line (257b) may be electrically connected to at least a portion of the first common link line (257a) through the link contact hole (257h). The second common link line (257b) may extend (or protrude) toward a plurality of pixel common voltage pads (or rear common voltage pads) disposed in the second pad portion (210) and may be electrically connected to each of the plurality of pixel common voltage pads.

[0079] A bonding member (300) is interposed between the substrate (100) and the wiring substrate (200). Accordingly, the substrate (100) and the wiring substrate (200) can be bonded together through the bonding member (300). The bonding member (300) may be a transparent adhesive member including an optically clear adhesive (OCA) or an optically clear resin (OCR), or a double-sided tape, but is not limited thereto. The bonding member (300) may include glass fibers.

[0080] Alternatively, the wiring board (200) may be omitted. In this case, the second pad portion (210), at least one third pad portion (230), and the link line portion (250) are placed on the rear surface of the board (100), so a redundant description thereof is omitted. Accordingly, if the wiring board (200) is omitted, the coupling member (300) is also omitted.

[0081] The routing section (400) may be described as a side wiring section, an edge wiring section, a side routing section, an edge routing section, a printing line section, a side printing line section, or a side wiring section. The routing section (400) may be arranged to surround the outer surface (OS1a) of the substrate (100) and the outer surface (OS1b) of the wiring board (200). According to one embodiment, the routing section (400) may include a plurality of routing lines (410) arranged on each of the first outer surface (or one side) (OS1a) of the outer surface (OS) of the substrate (100) and the first outer surface (or one side) (OS1b) of the outer surface (OS) of the wiring board (200).

[0082] Alternatively, when the wiring board (200) is omitted, each of the plurality of routing lines (410) is formed to wrap around the first outer surface (or one side) (OS1a) of the outer surface (OS) of the board (100), and can connect the first pads of the first pad portion (110) and the second pads of the second pad portion (210) individually (or one-to-one).

[0083] A light-emitting display device (10) according to one embodiment of the present specification may further include a driving circuit portion (500).

[0084] The driving circuit (500) can display an image corresponding to the image data on the display unit (AA) by driving (or emitting light) pixels (P) placed on the substrate (100) based on digital image data supplied from the display driving system and a synchronization signal. The driving circuit (500) is connected to at least one third pad unit (230) placed on the rear surface (200b) of the wiring board (200), and can output a data signal, a gate control signal, and a driving power supply to at least one third pad unit (230) for driving (or emitting light) pixels (P) placed on the substrate (100).

[0085] A driving circuit section (500) according to one embodiment may include a flexible circuit film (510), a driving integrated circuit (530), a printed circuit board (550), a timing controller (570), and a power circuit section (590).

[0086] The flexible circuit film (510) can be connected to at least one third pad portion (230) placed on the rear surface (200b) of the wiring board (200).

[0087] The driving integrated circuit (530) is mounted on the flexible circuit film (510). The driving integrated circuit (530) receives subpixel data and a data control signal provided by the timing controller (570), and can convert the subpixel data into an analog data signal and output it according to the data control signal.

[0088] The driving integrated circuit (530) can sense the characteristic value of the driving TFT placed in the subpixel (P) through each of the plurality of reference voltage lines (or pixel sensing lines) placed on the substrate (100) during a preset external sensing period, and generate sensing raw data for each subpixel corresponding to the sensing value for each subpixel and provide it to the timing controller (570).

[0089] Additionally, the driving integrated circuit (530) can sense (or receive) a test signal through each of a plurality of reference voltage lines (or pixel sensing lines) in test mode, and generate line-specific line sensing data corresponding to the sensed value (or received value) and provide it to the timing controller (570).

[0090] Additionally, the driving integrated circuit (530) can sense the line resistance of at least some of the multiple routing lines (410) through each of the multiple switching circuit sections during the inspection mode, or sense the line resistance of each of the multiple routing lines (410), and generate line-specific resistance sensing data corresponding to the sensed line resistance and provide it to the timing controller (570). For example, the driving integrated circuit (530) can sense the line resistance of each of the multiple data routing lines connected to each of the multiple data lines through each of the multiple switching circuit sections, generate resistance sensing data corresponding to the line resistance of the sensed data routing lines, and provide it to the timing controller (570).

[0091] According to one embodiment of the present specification, the driving integrated circuit (530) can output a data signal that reflects a line-by-line resistance compensation value provided by the timing controller (570), thereby preventing or minimizing image quality defects caused by resistance deviations between multiple data routings.

[0092] According to another embodiment of the present specification, the driving integrated circuit (530) may include a plurality of signal output circuits that output a data signal. Each of the plurality of signal output circuits may have a current option value (or output current option value) set (or varied) according to a line-by-line resistance compensation value (or bias voltage level) provided by the timing controller (570), thereby allowing the driving integrated circuit (530) to output a data signal that reflects the line-by-line resistance compensation value provided by the timing controller (570).

[0093] The printed circuit board (550) can be connected to the other edge portion of the flexible circuit film (510). The printed circuit board (550) serves to transmit signals and power between the components of the driving circuit portion (500).

[0094] The timing controller (570) is mounted on the printed circuit board (550) and receives digital image data and timing synchronization signals provided from the display driving system through a user connector placed on the printed circuit board (550). Alternatively, the timing controller (570) may not be mounted on the printed circuit board (550) but may be implemented in the display driving system or mounted on a separate control board connected between the printed circuit board (550) and the display driving system.

[0095] The timing controller (570) generates pixel data by aligning digital image data to fit the pixel array structure placed on the display unit (AA) based on the timing synchronization signal, and provides the generated pixel data to the driving integrated circuit (530).

[0096] The timing controller (570) generates a data control signal and a gate control signal, respectively, based on a timing synchronization signal, controls the driving timing of the driving integrated circuit (530) through the data control signal, and controls the driving timing of the gate driving circuit (150) through the gate control signal.

[0097] The timing controller (570) drives the driving integrated circuit (530) and the gate driving circuit (150) in an external sensing mode during a preset external sensing interval, generates subpixel-specific compensation data to compensate for changes in the characteristics of the subpixel-specific driving TFT based on subpixel-specific sensing raw data provided from the driving integrated circuit (530), and modulates the subpixel-specific pixel data based on the subpixel-specific compensation data.

[0098] The timing controller (570) drives the driving integrated circuit (530) and each of the plurality of switching circuits in the inspection mode, determines whether there is a short circuit in the routing line and the location of the short circuit defect based on line-by-line sensing data supplied from the driving integrated circuit (530), and can display the determination result on a separate monitor.

[0099] The timing controller (570) drives the driving integrated circuit (530) and each of the plurality of switching circuits into a test mode, and modulates pixel data per subpixel based on line-by-line resistance sensing data provided by the driving integrated circuit (530), or sets (changes) the current option value (or output current option value or slew rate) of the driving integrated circuit (530), thereby preventing or minimizing image quality defects caused by resistance deviations between multiple data routings. For example, the timing controller (570) can generate a value corresponding to a line-by-line resistance compensation value to compensate for resistance deviations between multiple data routings based on line-by-line resistance sensing data provided by the driving integrated circuit (530), and provide it to the driving integrated circuit (530). For example, the line-by-line resistance compensation value can be stored in a storage circuit in the form of a look-up table.

[0100] The power circuit section (590) is mounted on the printed circuit board (550) and can generate various power voltages necessary to display an image on pixels (P) using input power supplied from the outside and provide them to the corresponding circuit.

[0101] FIG. 3a is a drawing showing one pixel according to one embodiment shown in FIG. 1, FIG. 3b is a drawing showing one pixel according to another embodiment shown in FIG. 1, and FIG. 3c is a drawing showing one pixel according to yet another embodiment shown in FIG. 1.

[0102] Referring to FIG. 1 and FIG. 3a, a pixel (or unit pixel) (P) according to one embodiment of the present specification may include first to fourth subpixels (SP1, SP2, SP3, SP4) arranged in a pixel area (PA).

[0103] Each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may be arranged in a 2×2 form or a quad structure. Each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may include a light-emitting region (EA) and a circuit region (CA). For example, the light-emitting region (EA) may be described as an aperture region, an aperture, or a light-emitting part.

[0104] Each light-emitting region (EA) of the first to fourth subpixels (SP1, SP2, SP3, SP4) may have an equal quad structure having a square shape with equal size. According to one embodiment, the light-emitting region (EA) having the equal quad structure may have a size smaller than a quarter size of the pixel (P) and may be positioned so as to be offset toward the center (CP) of the pixel (P) or concentrated at the center (CP) of the pixel (P) within the subpixel area. According to another embodiment, the light-emitting region (EA) having the equal quad structure may have a size smaller than a quarter size of the pixel (P) and may be positioned at the center of the corresponding subpixel area.

[0105] Each circuit region (CA) of the first to fourth subpixels (SP1, SP2, SP3, SP4) may be positioned around the corresponding light-emitting region (EA). The circuit region (CA) may include circuits and pixel driving lines for emitting light from the corresponding subpixel. For example, the circuit region (CA) may be described as a non-light-emitting region, a non-aperture region, a non-light-emitting part, a non-aperture part, or a peripheral part.

[0106] Referring to FIG. 1 and FIG. 3b, according to another embodiment of the present specification, the light-emitting region (EA) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may be extended onto the circuit region (CA) so as to overlap with part or all of the circuit region (CA). That is, in order to increase the aperture ratio of the subpixels (SP1, SP2, SP3, SP4) corresponding to the size of the light-emitting region (EA) or to reduce the pixel pitch (D1) according to the resolution of the pixel (P), the light-emitting region (EA) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may be extended onto the circuit region (CA) so as to overlap with part or all of the circuit region (CA). For example, since the light-emitting region (EA) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) has an upper light-emitting structure, it may be arranged to overlap with the corresponding circuit region (CA). Accordingly, the light-emitting region (EA) can have a size equal to or larger than the circuit region (CA).

[0107] Referring to FIG. 1 and FIG. 3c, each of the first to fourth subpixels (SP1, SP2, SP3, SP4) according to another embodiment may be arranged in a non-uniform quad structure having different sizes. For example, each light-emitting region (EA) of the first to fourth subpixels (SP1, SP2, SP3, SP4) may be arranged in a non-uniform quad structure having different sizes.

[0108] The size of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) having an unequal quad structure can be set according to resolution, luminous efficiency, or image quality, etc. When the light-emitting area (EA) has an unequal quad structure, among the light-emitting areas (EA) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4), the light-emitting area (EA4) of the fourth subpixel (SP4) may have the smallest size, and the light-emitting area (EA3) of the third subpixel (SP3) may have the largest size. The light-emitting area (EA) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may be extended onto the circuit area (CA) so as to overlap with part or all of the circuit area (CA). For example, since the light-emitting area (EA) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) has an upper light-emitting structure, it may be arranged to overlap with the corresponding circuit area (CA). Accordingly, the light-emitting region (EA) can have a size equal to or larger than the circuit region (CA).

[0109] In FIGS. 3a to 3c, the first subpixel (SP1) may be implemented to emit light of a first color, the second subpixel (SP2) to emit light of a second color, the third subpixel (SP3) to emit light of a third color, and the fourth subpixel (SP4) to emit light of a fourth color, respectively. Each of the first to fourth colors may be different. According to one embodiment of the present specification, the first color may be red, the second color may be blue, the third color may be white, and the fourth color may be green. According to another embodiment of the present specification, some of the first to fourth colors may be the same. For example, the first color may be red, the second color may be first green, the third color may be second green, and the fourth color may be blue.

[0110] Alternatively, each of the first to fourth subpixels (SP1, SP2, SP3, SP4) according to the embodiments of the present specification may have a 1×4 shape, an even stripe structure, or an uneven stripe structure. For example, the light-emitting region (EA) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may have a 1×4 shape, an even stripe structure, or an uneven stripe structure. For example, the light-emitting region (EA) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) having an even stripe structure may have a rectangular shape having a short side parallel to the first direction (X) and a long side parallel to the second direction (Y). Optionally, among the first to fourth subpixels (SP1, SP2, SP3, SP4) having a 1×4 shape, an even stripe structure, or an uneven stripe structure, a white subpixel emitting white light may be omitted.

[0111] Figure 4 is a schematic enlarged view of the 'B1' portion shown in Figure 1, and Figure 5 is an equivalent circuit diagram for a single pixel shown in Figures 1 and 4.

[0112] Referring to FIGS. 1, 4, and 5, a substrate (100) according to one embodiment of the present specification may include pixel driving lines (DL, GL, PL, CVL, RL, GCL), a plurality of pixels (P), a common electrode (CE), a plurality of common electrode connection portions (CECP), a damp portion (104), and a first pad portion (110).

[0113] Pixel driving lines (DL, GL, PL, CVL, RL, GCL) may include a plurality of data lines (DL), a plurality of gate lines (GL), a plurality of pixel driving power lines (PL), a plurality of pixel common voltage lines (CVL), a plurality of reference voltage lines (RL), and a plurality of gate control lines (GCL).

[0114] Each of the multiple data lines (DL) can be extended along the second direction (Y) and arranged on the display portion (AA) of the substrate (100) at a predetermined interval along the first direction (X).

[0115] Each of the multiple gate lines (GL) can be extended along the first direction (X) and arranged on the display portion (AA) of the substrate (100) with a predetermined spacing along the second direction (Y).

[0116] Each of the plurality of pixel driving power lines (PL) can be extended along the second direction (Y) and arranged on the display portion (AA) of the substrate (100) at a predetermined interval along the first direction (X).

[0117] Among a plurality of pixel driving power lines (PL), two adjacent pixel driving power lines (PL) can be connected to each other through a plurality of power sharing lines (PSL) arranged in each pixel area (PA) along the second direction (Y). For example, the plurality of pixel driving power lines (PL) may have a ladder structure or a mesh structure by being electrically connected (or in contact) to each other by the plurality of power sharing lines (PSL). By having the plurality of pixel driving power lines (PL) have a ladder structure or a mesh structure, the voltage drop (IR drop) of the pixel driving power due to the line resistance of the pixel driving power lines (PL) can be prevented or minimized, and as a result, the light-emitting display device according to the embodiment of the present specification can prevent or minimize image quality defects caused by deviations in the pixel driving power supplied to each pixel (P) arranged in the display unit (AA).

[0118] Each of the multiple power sharing lines (PSL) may be branched from an adjacent pixel driving power line (PL) so as to be parallel to the first direction (X) and placed in the middle area of ​​each pixel region (PA), but is not limited thereto.

[0119] Each of the plurality of pixel common voltage lines (CVL) may be extended along the second direction (Y) and arranged on the display portion (AA) of the substrate (100) with a predetermined spacing along the first direction (X). For example, each of the plurality of pixel common voltage lines (CVL) may be arranged at the first edge portion of an even-numbered pixel area (PA) with respect to the first direction (X), but is not limited thereto.

[0120] Each of the plurality of reference voltage lines (RL) may be arranged on the display portion (AA) of the substrate (100) such that it extends along the second direction (Y) and has a predetermined spacing along the first direction (X). Each of the plurality of reference voltage lines (RL) may be arranged in the center area of ​​each pixel area (PA) arranged along the second direction (Y), but is not limited thereto.

[0121] Each of the plurality of reference voltage lines (RL) may be shared with two adjacent subpixels ((SP1, SP2)(SP3, SP4)) along a first direction (X) in each pixel area (PA). To this end, each of the plurality of reference voltage lines (RL) may include a reference branch line (RDL). The reference branch line (RDL) may branch (or protrude) toward two adjacent subpixels ((SP1, SP2)(SP3, SP4)) along a first direction (X) in each pixel area (PA) and may be electrically connected (or contacted) to the two adjacent subpixels ((SP1, SP2)(SP3, SP4)).

[0122] Each of the plurality of gate control lines (GCL) may be arranged on the display portion (AA) of the substrate (100) such that it extends along the second direction (Y) and has a predetermined spacing along the first direction (X). For example, each of the plurality of gate control lines (GCL) may be arranged at the boundary between a plurality of pixel regions (PA) or between two adjacent pixel regions (PA) with respect to the first direction (X).

[0123] Each of the plurality of pixels (P) may include at least three subpixels. For example, each of the plurality of pixels (P) may include first to fourth subpixels (SP1 to SP4). Each of the first to fourth subpixels (SP1 to SP4) may include a pixel circuit (PC) and a light-emitting element layer.

[0124] A pixel circuit (PC) according to one embodiment may be placed in the circuit area of ​​a pixel area (PA) and connected to adjacent gate lines (GLo, GLe), data lines (DLo, DLe), and pixel driving power lines (PL). For example, a pixel circuit (PC) placed in a first subpixel (SP1) may be connected to an odd-numbered data line (DLo) and an odd-numbered gate line (GLo), a pixel circuit (PC) placed in a second subpixel (SP2) may be connected to an even-numbered data line (DLe) and an odd-numbered gate line (GLo), a pixel circuit (PC) placed in a third subpixel (SP3) may be connected to an odd-numbered data line (DLo) and an even-numbered gate line (GLe), and a pixel circuit (PC) placed in a fourth subpixel (SP4) may be connected to an even-numbered data line (DLe) and an even-numbered gate line (GLe).

[0125] Each pixel circuit (PC) of the first to fourth subpixels (SP1 to SP4) can sample a data signal supplied from a corresponding data line (DLo, DLe) in response to a scan signal supplied from a corresponding gate line (GLo, GLe) and control the current flowing from the pixel driving power line (PL) to the light-emitting element layer based on the sampled data signal.

[0126] A pixel circuit (PC) according to one embodiment may include, but is not limited to, a first switching thin film transistor (Tsw1), a second switching thin film transistor (Tsw2), a driving thin film transistor (Tdr), and a storage capacitor (Cst). In the following description, the thin film transistor will be referred to as "TFT".

[0127] The first switching TFT (Tsw1) may include a gate electrode connected to a gate line (GLo, GLe), a first electrode (or first source / drain electrode) connected to a data line (DL), and a second electrode (or second source / drain electrode) connected to a gate node (n1) of a driving TFT (Tdr). This first switching TFT (Tsw1) may supply a data voltage supplied from the data line (DL) to the gate node (n1) of the driving TFT (Tdr) according to a scan signal supplied to the corresponding gate line (GLo, GLe).

[0128] The second switching TFT (Tsw2) may include a gate electrode connected to a gate line (GLo, GLe), a first electrode (or first source / drain electrode) connected to a source node (n2) of a driving TFT (Tdr), and a second electrode (or second source / drain electrode) connected to a reference voltage line (RL). This second switching TFT (Tsw2) may supply a reference voltage supplied to the reference voltage line (RL) to the source node (n2) of the driving TFT (Tdr) according to a scan signal supplied to the corresponding gate line (GLo, GLe).

[0129] A storage capacitor (Cst) may be formed between a gate node (n1) and a source node (n2) of a driving TFT (Tdr). A storage capacitor (Cst) according to one embodiment may include a first capacitor electrode connected to the gate node (n1) of the driving TFT (Tdr), a second capacitor electrode connected to the source node (n2) of the driving TFT (Tdr), and a dielectric layer formed in the overlapping region of the first capacitor electrode and the second capacitor electrode. After charging the differential voltage between the gate node (n1) and the source node (n2) of the driving TFT (Tdr), the storage capacitor (Cst) switches the driving TFT (Tdr) according to the charged voltage.

[0130] The driving TFT (Tdr) may include a gate electrode (or gate node (n1)) commonly connected to the second source / drain electrode of the first switching TFT (Tsw1) and the first capacitor electrode of the storage capacitor (Cst), a first electrode (or first source / drain electrode or source node (n2)) commonly connected to the first electrode of the second switching TFT (Tsw2), the second capacitor electrode of the storage capacitor (Cst), and the pixel electrode (PE) of the light-emitting element layer, and a second electrode (or second source / drain electrode or drain node) connected to the pixel driving power line (PL). This driving TFT (Tdr) can control the amount of current flowing from the pixel driving power line (PL) to the light-emitting element layer by being turned on by the voltage of the storage capacitor (Cst).

[0131] The light-emitting element layer may be disposed in the light-emitting region (EA) of the pixel region (PA) and electrically connected (or in contact) with the pixel circuit (PC). According to one embodiment, the light-emitting element layer may include a pixel electrode (PE) electrically connected (or in contact) with the pixel circuit (PC), a common electrode (CE) electrically connected (or in contact) with the pixel common voltage line (CVL), and a self-emissive element (ED) interposed between the pixel electrode (PE) and the common electrode (CE).

[0132] Each of the plurality of common electrode connection parts (CECP) electrically connects (or contacts) a common electrode (CE) to each of the plurality of pixel common voltage lines (CVL) between the plurality of pixels (P) that overlap with each of the plurality of pixel common voltage lines (CVL). Each of the plurality of common electrode connection parts (CECP) according to one embodiment is electrically connected (or contacts) to each of the plurality of pixel common voltage lines (CVL) between the plurality of pixels (P) or at the boundary between the plurality of pixels with respect to the second direction (Y), and can electrically connect (or contact) the common electrode (CE) to each of the plurality of pixel common voltage lines (CVL) by being electrically connected (or contacted) to a part of the common electrode (CE).

[0133] Each of the plurality of common electrode connection portions (CECP) is disposed between each of the plurality of pixels (P) and electrically connects (or contacts) the common electrode (CE) to each of the plurality of pixel common voltage lines (CVL), thereby preventing or minimizing the voltage drop (IR drop) of the pixel common voltage due to the sheet resistance of the common electrode (CE). According to one embodiment of the present specification, each of the plurality of common electrode connection portions (CECP) may be formed together with a pixel electrode (PE) having at least a two-layer structure so as to be electrically connected (or contacted) to each of the plurality of pixel common voltage lines (CVL). Each of the plurality of common electrode connection portions (CECP) may be electrically connected (or contacted) to the common electrode (CE) through a side contact structure (or side exposure structure).

[0134] The dam (104) is positioned or implemented on the edge portion of the substrate (100) or the outermost pixel (Po) to have a closed-loop line shape (or closed-loop form), and since this is the same as described with reference to FIG. 1, a redundant description thereof is omitted.

[0135] A substrate (100) according to one embodiment of the present specification may further include a separation portion (105). The separation portion (105) is positioned or implemented at the edge portion of the substrate (100) or the outermost pixel (Po) so as to have a closed-loop line shape (or closed-loop form) around the dam portion (104). Since this is the same as described with reference to FIG. 1, a redundant description thereof is omitted.

[0136] The first pad portion (110) may include a plurality of first pads arranged parallel to each other along a first direction (X) on a first edge portion of the substrate (100). The plurality of first pads may be divided (or classified) into a plurality of first data pads (DP1), a plurality of first gate pads (GP1), a plurality of first pixel driving power pads (PPP1), a plurality of first reference voltage pads (RVP1), and a plurality of first pixel common voltage pads (CVP1).

[0137] Each of the plurality of first data pads (DP1) can be individually (or one-to-one) connected to one end of each of the plurality of data lines (DLo, DLe) placed on the substrate (100).

[0138] Each of the plurality of first gate pads (GP1) may be individually (or one-to-one) connected to one end of each of the gate control lines (GCL) disposed on the substrate (100). The plurality of first gate pads (GP1) may be divided (or classified) into a first start signal pad, a plurality of first shift clock pads, a plurality of first carry clock pads, at least one first gate driving power pad, and at least one first gate common power pad, etc.

[0139] Each of the plurality of first pixel driving power pads (PPP1) may be individually (or one-to-one) connected to one end of each of the plurality of pixel driving power lines (PL) disposed on the substrate (100). Each of the plurality of first reference voltage pads (RVP1) may be individually (or one-to-one) connected to one end of each of the plurality of reference voltage lines (RL) disposed on the substrate (100). Each of the plurality of first pixel common voltage pads (CVP1) may be individually (or one-to-one) connected to one end of each of the plurality of pixel common voltage lines (CVL) disposed on the substrate (100).

[0140] A first pad portion (110) according to one embodiment of the present specification may include a plurality of pad groups (PG) arranged along a first direction (X). Each of the plurality of pad groups (PG) may be connected to two adjacent pixels (P) arranged along the first direction (X). For example, each of the plurality of pad groups (PG) may include a first pad group (PG1) and a second pad group (PG2) arranged alternately along the first direction (X). The first pad group (PG1) may include a first pixel driving power pad (PPP1), a first data pad (DP1), a first reference power pad (RVP1), a first data pad (DP1), and a first pixel common voltage pad (CVP1) arranged continuously along the first direction (X) within an odd-numbered pixel area (PA). The second pad group (PG2) may include a first gate pad (GP1), a first data pad (DP1), a first reference power pad (RVP1), a first data pad (DP1), and a first pixel driving power pad (PPP1) arranged continuously along a first direction (X) within an even-numbered pixel area (PA).

[0141] A substrate (100) according to one embodiment of the present specification may further include a plurality of auxiliary voltage lines (SVL) and a plurality of auxiliary line connection parts (SLCP).

[0142] Each of the plurality of auxiliary voltage lines (SVL) may be extended along the second direction (Y) and arranged adjacent to each of the plurality of pixel common voltage lines (CVL). Each of the plurality of auxiliary voltage lines (SVL) may not be electrically connected (or in contact) with the first pixel common voltage pad (CVP), but may be electrically connected (or in contact) with the adjacent pixel common voltage line (CVL) to receive pixel common voltage from the adjacent pixel common voltage line (CVL). To this end, a substrate (100) according to one embodiment of the present specification may further include a plurality of line connection patterns (LCP) that electrically connect (or in contact) the pixel common voltage line (CVL) and the auxiliary voltage line (SVL) that are adjacent to each other.

[0143] Each of the plurality of line connection patterns (LCP) is placed on a substrate (100) to intersect adjacent pixel common voltage lines (CVL) and auxiliary voltage lines (SVL), and can electrically connect (or contact) adjacent pixel common voltage lines (CVL) and auxiliary voltage lines (SVL) through a line jumping structure. For example, one side of each of the plurality of line connection patterns (LCP) can be electrically connected (or contact) to a part of the auxiliary voltage line (SVL) through a first line contact hole formed in an insulating layer on the auxiliary voltage line (SVL), and the other side of each of the plurality of line connection patterns (LCP) can be electrically connected (or contact) to a part of the pixel common voltage line (CVL) through a second line contact hole formed in an insulating layer on the pixel common voltage line (CVL).

[0144] Each of the plurality of auxiliary line connection parts (SLCP) electrically connects (or contacts) a common electrode (CE) to each of the plurality of auxiliary voltage lines (SVL) between each of the plurality of pixels (P) that overlap with each of the plurality of auxiliary voltage lines (SVL). Each of the plurality of auxiliary line connection parts (SLCP) according to one embodiment is electrically connected (or contacts) to each of the plurality of auxiliary voltage lines (SVL) between the plurality of pixels (P) or at the boundary between the plurality of pixels with respect to the second direction (Y), and can electrically connect (or contact) the common electrode (CE) to each of the plurality of auxiliary voltage lines (SVL) by being electrically connected (or contacted) to a part of the common electrode (CE). Accordingly, the common electrode (CE) can be additionally connected to each of the plurality of auxiliary voltage lines (SVL) through the plurality of auxiliary line connection parts (SLCP). As a result, the light-emitting display device according to the embodiment of the present specification can further prevent or further minimize image quality defects caused by deviations in the pixel common voltage supplied to each pixel (P) arranged in the display part (AA). In addition, the light-emitting display device according to the embodiment of the present specification can supply a pixel common voltage to each of the plurality of auxiliary voltage lines (SVL) through each of the pixel common voltage line (CVL) and each of the plurality of line connection patterns (LCP) without additionally arranging (or forming) a first pixel common voltage pad (CVP) connected to each of the plurality of auxiliary voltage lines (SVL).

[0145] A substrate (100) according to one embodiment of the present specification may further include an encapsulation layer.

[0146] The encapsulation layer may be implemented to surround the light-emitting element layer. The encapsulation layer may include a first inorganic encapsulation layer (or the first encapsulation layer) disposed over the light-emitting element layer, the damper (104), and the separation portion (105), a second inorganic encapsulation layer (or the third encapsulation layer) disposed over the first inorganic encapsulation layer, and an organic encapsulation layer (or the second encapsulation layer) interposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer disposed over the encapsulation region defined by the damper (104).

[0147] The organic encapsulation layer may cover the front surface (or upper surface) of the light-emitting element layer and flow toward the end of the substrate (100), and the spreading (or flow) of the organic encapsulation layer may be blocked by a dam (104). The dam (104) may define or limit the placement area (or encapsulation area) of the organic encapsulation layer, and furthermore, may block or prevent the spreading or overflow of the organic encapsulation layer.

[0148] Figure 6 is a diagram showing the gate driving circuit illustrated in Figures 1 and 4.

[0149] Referring to FIGS. 1, FIGS. 4, and FIGS. 6, a gate driving circuit (150) according to one embodiment of the present specification may be implemented (or embedded) within a display portion (AA) of a substrate (100). The gate driving circuit (150) may generate a scan signal based on a gate control signal supplied through a first pad portion (110) and gate control lines (GCL) and sequentially supply it to a plurality of gate lines (GL).

[0150] The gate control lines (GCL) may include a start signal line, a plurality of shift clock lines, at least one gate driving voltage line, and at least one gate common voltage line. The gate control lines (GCL) may be extended along a second direction (Y) and may be placed on a display portion (AA) of the substrate (100) with a predetermined spacing along a first direction (X). For example, the gate control lines (GCL) may be placed between at least one pixel (P) along the first direction (X).

[0151] The gate driving circuit (150) can be implemented as a shift register including a plurality of stage circuits (1501 to 150m).

[0152] Each of the plurality of stage circuits (1501 to 150m) may be individually arranged on each horizontal line on the first surface of the substrate (100) along the first direction (X) and may be connected dependently to each other along the second direction (Y). Each of the plurality of stage circuits (1501 to 150m) may generate a scan signal in a predetermined order in response to a gate control signal supplied through the first pad portion (110) and the gate control lines (GCL) and supply it to the corresponding gate line (GL).

[0153] Each of the plurality of stage circuits (1501 to 150m) may include a plurality of branch circuits (1511 to 151n) and a branch network (153).

[0154] Each of the plurality of branch circuits (1511 to 151n) is selectively connected to gate control lines (GCL) through the branch network (153) and can be electrically connected (or contacted) to each other through the branch network (153). Each of these plurality of branch circuits (1511 to 151n) can generate a scan signal according to the gate control signal supplied through the gate control lines (GCL) and the voltage of the branch network (153) and supply it to the corresponding gate line (GL).

[0155] Each of the plurality of branch circuits (1511 to 151n) may include at least one TFT (or branch TFT) among the plurality of TFTs constituting one stage circuit (1501 to 150m). Any one of the plurality of branch circuits (1511 to 151n) may include a pull-up TFT connected to a gate line (GL). Another of the plurality of branch circuits (1511 to 151n) may include a pull-down TFT connected to a gate line (GL).

[0156] Each of the plurality of branch circuits (1511 to 151n) according to one embodiment may be positioned between two adjacent pixels (P) or between at least two adjacent pixels (P) in each horizontal line of the substrate (100), but is not limited thereto. For example, each of the plurality of branch circuits (1511 to 151n) may be positioned in a circuit area (or boundary) between at least one adjacent pixel (P) depending on the number of TFTs constituting one stage circuit (1501 to 150m) and the number of pixels (P) positioned in one horizontal line.

[0157] A branch network (153) is placed on each horizontal line of the substrate (100) and can electrically connect (or contact) a plurality of branch circuits (1511 to 151n) to each other. The branch network (153) may include a plurality of control node lines and a plurality of network lines.

[0158] A plurality of control node lines are arranged on each horizontal line of the substrate (100) and can be selectively connected to a plurality of branch circuits (1511 to 151n) on one horizontal line. For example, a plurality of control node lines may be arranged on the upper edge region (or lower edge region) among the pixel regions arranged on each horizontal line of the substrate (100), but are not limited thereto.

[0159] A plurality of network lines may be optionally connected to gate control lines (GCL) disposed on a substrate (100) and may be optionally connected to a plurality of branch circuits (1511 to 151n). For example, the plurality of network lines may supply a gate control signal supplied from the gate control lines (GCL) to the corresponding branch circuits (1511 to 151n) and transmit signals between the plurality of branch circuits (1511 to 151n).

[0160] According to an embodiment of the present specification, since the gate driving circuit (150) is positioned within the display portion (AA) of the substrate (100), the second gap (D2) between the center of the outermost pixel (Po) and the outer surfaces (OS) of the substrate (100) may be less than half of the first gap (or pixel pitch) (D1) between adjacent pixels (P). For example, when the gate driving circuit (150) is not positioned within the display portion (AA) of the substrate (100) but is positioned at the edge portion of the substrate (100), the second gap (D2) may not be less than half of the first gap (D1) due to the gate driving circuit (150). Accordingly, the light-emitting display device according to one embodiment of the present specification may have a second gap (D2) implemented to be less than half of the first gap (D1) by having the gate driving circuit (150) placed within the display portion (AA) of the substrate (100), and furthermore, may have an air bezel structure having no bezel area or a zeroed bezel.

[0161] FIG. 7 is a drawing for explaining a plurality of switching circuit sections according to an embodiment of the present specification, and FIG. 8 is a drawing showing a first pad section, a switching circuit section, and a damper section shown in FIG. 7. FIG. 7 and FIG. 8 schematically show a switching circuit section for sensing the resistance of a routing line placed in a routing section according to an embodiment of the present specification and related configurations.

[0162] Referring to FIGS. 1, 7, and 8, in a light-emitting display device (10) according to one embodiment of the present specification, each of a plurality of switching circuit sections (170) is arranged to overlap with a damper section (104) and can be connected to a driving circuit section (500) through a first pad section (110), a routing section (400), a second pad section (210), a link line section (250), and a third pad section (230). Each of the plurality of switching circuit sections (170) can be configured to be driven (or switched) according to a switching control signal supplied from the driving circuit section (500).

[0163] The dam section (104) may include first to third dams (104-1, 104-2, 104-3), and the separation section (105) may include first and second separation structures (105-1, 105-2) disposed between the first to third dams (104-1, 104-2, 104-3).

[0164] Each of the first to third dams (104-1, 104-2, 104-3) may be implemented side by side to have a planar closed-loop line shape (or a continuous line shape or a closed-loop shape). The first dam (104-1) may be arranged to surround the second dam (104-2), and the second dam (104-2) may be arranged to surround the third dam (104-3).

[0165] Each of the first to third dams (104-1, 104-2, 104-3) may include a metal line (104m). The metal line (104m) may be embedded or implemented inside the dam section (104) so ​​as to have a closed-loop line shape (or a continuous line shape or a closed-loop shape) identical to the dam section (104) in planar form.

[0166] Each of the first and second separation structures (105-1, 105-2) may be implemented side by side to have a planar closed-loop line shape (or a continuous line shape or a closed-loop shape). The first separation structure (105-1) may be placed between the first dam (104-1) and the second dam (104-2). The second separation structure (105-2) may be placed between the second dam (104-2) and the third dam (104-3).

[0167] In a light-emitting display device (10) according to one embodiment of the present specification, the first pad portion (110) may further include first to third front sensing control pads (112a, 112b, 112c) and first to third pad connection lines (176, 177, 178).

[0168] Each of the first to third front sensing control pads (112a, 112b, 112c) may be positioned between a plurality of first pads. For example, each of the first to third front sensing control pads (112a, 112b, 112c) may be positioned one by one in the area between the first pad group (PG1) and the second pad group (PG2) described in FIG. 4. Each of the first to third front sensing control pads (112a, 112b, 112c) may receive a corresponding switching control signal from a driving integrated circuit (530) via a flexible circuit film (510), a third pad (230), a link line section (250), a second pad section (210), and a routing section (400) in inspection mode.

[0169] According to one embodiment of the present specification, each of the first to third front sensing control pads (112a, 112b, 112c) may be selected from a plurality of front dummy pads that are arranged at regular intervals on the first pad portion (110) and are not connected to pixel driving voltages. For example, the first pad portion (110) includes a plurality of front pads, and the plurality of front pads may be divided (or classified) into a plurality of first data pads (DP1), a plurality of first gate pads (GP1), a plurality of first pixel driving power pads (PPP1), a plurality of first reference voltage pads (RVP1), a plurality of first pixel common voltage pads (CVP1), and the first to third front sensing control pads (112a, 112b, 112c).

[0170] The first pad connection line (176) may be configured to be electrically coupled to the first front sensing control pad (112a) and the metal line (104m) of the first dam (104-1). The first pad connection line (176) may be extended along the second direction (Y) to overlap the first front sensing control pad (112a) and intersect the metal line (104m) of the first dam (104-1). For example, one side (or one end) of the first pad connection line (176) may be electrically connected to the first front sensing control pad (112a) through a pad contact hole. The metal line (104m) of the first dam (104-1) may be electrically connected to the other side (or other edge portion) of the first pad connection line (176) through a via hole (176h). Accordingly, the first switching control signal supplied from the driving integrated circuit (530) to the first front sensing control pad (112a) in inspection mode can be supplied to the metal line (104m) of the first dam (104-1) through the first pad connection line (176).

[0171] The second pad connection line (177) may be configured to be electrically coupled to the second front sensing control pad (112b) and the metal line (104m) of the second dam (104-2). The second pad connection line (177) may be extended along the second direction (Y) to overlap the second front sensing control pad (112b) and intersect the metal line (104m) of the second dam (104-2). For example, one side (or one end) of the second pad connection line (177) may be electrically connected to the second front sensing control pad (112b) through a pad contact hole. The metal line (104m) of the second dam (104-2) may be electrically connected to the other side (or other edge portion) of the second pad connection line (177) through a via hole (177h). Accordingly, the second switching control signal supplied from the driving integrated circuit (530) to the second front sensing control pad (112b) in inspection mode can be supplied to the metal line (104m) of the second dam (104-2) through the second pad connection line (177).

[0172] The third pad connection line (178) may be configured to be electrically coupled to the third front sensing control pad (112c) and the metal line (104m) of the third dam (104-3). The third pad connection line (178) may be extended along the second direction (Y) to overlap with the third front sensing control pad (112c) and to intersect with the metal line (104m) of the third dam (104-3). For example, one side (or one end) of the third pad connection line (178) may be electrically connected to the third front sensing control pad (112c) through a pad contact hole. The metal line (104m) of the third dam (104-3) may be electrically connected to the other side (or other edge portion) of the third pad connection line (178) through a via hole (178h). Accordingly, the third switching control signal supplied from the driving integrated circuit (530) to the third front sensing control pad (112c) in inspection mode can be supplied to the metal line (104m) of the third dam (104-3) through the third pad connection line (178).

[0173] Each of the plurality of switching circuit sections (170) may be arranged along the first edge portion of the substrate (100) or the first edge portion of the substrate (100). Each of the plurality of switching circuit sections (170) may be configured to be arranged (or included) in each of the plurality of outermost pixels (Po). Each of the plurality of switching circuit sections (170) may be arranged to overlap with the damper (104). Each of the plurality of switching circuit sections (170) may be arranged between the damper (104) and the substrate (100) so as to overlap with the damper (104), thereby preventing an increase in the bezel width caused by the plurality of switching circuit sections (170).

[0174] Each of the plurality of switching circuit sections (170) according to one embodiment of the present specification may include first to third switching circuits (171, 172, 173).

[0175] The first to third switching circuits (171, 172, 173) may be arranged to overlap individually with the first to third dams (104-1, 104-2, 104-3). For example, the first switching circuit (171) may overlap with the first dam (104-1) or be placed below the first dam (104-1). The second switching circuit (172) may overlap with the second dam (104-2) or be placed below the second dam (104-2). The third switching circuit (173) may overlap with the third dam (104-3) or be placed below the third dam (104-3).

[0176] Each of the first to third switching circuits (171, 172, 173) may be a TFT comprising a gate electrode (Sg), a first electrode (Se1) (or a first source / drain electrode), and a second electrode (Se2) (or a second source / drain electrode). Each of the first to third switching circuits (171, 172, 173) having such a configuration may be formed together with a driving TFT (Tdr) of the pixel circuit.

[0177] The first switching circuit (171) may be configured to sense the line resistance of the data routing line connected to the first data line (or odd-numbered data line) among the two data lines (DLo, DLe) placed in one pixel area (PA) in inspection mode, and the line resistance of the reference routing line connected to the reference voltage line (RL). The first switching circuit (171) may be electrically connected to the first data line (DLo) and the reference voltage line (RL) placed in one pixel area (PA), and to the metal line (104m) of the first dam (104-1). The first switching circuit (171) may be turned on according to a first switching control signal supplied through the metal line (104m) of the first dam (104-1) in inspection mode, and output an inspection signal supplied through the first data line (DLo) to the reference voltage line (RL).

[0178] The gate electrode (Sg) of the first switching circuit (171) may overlap with or be positioned below the metal line (104m) of the first dam (104-1) and may be electrically coupled to the metal line (104m) of the first dam (104-1) through the first control line contact hole (CLh1). For example, the metal line (104m) of the first dam (104-1) may be the first switching control line.

[0179] The first electrode (Se1) of the first switching circuit (171) can be electrically coupled to the first data line (or odd-numbered data line) (DLo) among two data lines (DLo, DLe) placed in one pixel area (PA). For example, the first electrode (Se1) of the first switching circuit (171) can be extended to overlap or intersect with the first data line (DLo) and can be electrically coupled to the first data line (DLo) through the first contact hole (CH1).

[0180] The second electrode (Se2) of the first switching circuit (171) can be electrically coupled to a reference voltage line (RL) placed in a pixel area (PA). For example, the second electrode (Se2) of the first switching circuit (171) can be extended to overlap or intersect the reference voltage line (RL) and can be electrically coupled to the reference voltage line (RL) through a second contact hole (CH2). For example, the reference voltage line (RL) can be used as a turn-on sensing line of the first switching circuit (171).

[0181] The second switching circuit (172) may be configured to sense the line resistance of the data routing line connected to the second data line (or even-numbered data line) among the two data lines (DLo, DLe) placed in one pixel area (PA) in inspection mode, and the line resistance of the reference routing line connected to the reference voltage line (RL). The second switching circuit (172) may be electrically connected to the second data line (DLe), the reference voltage line (RL), and the metal line (104m) of the second dam (104-2) placed in one pixel area (PA). The second switching circuit (172) may be turned on according to a second switching control signal supplied through the metal line (104m) of the second dam (104-2) in inspection mode, and output an inspection signal supplied through the second data line (DLe) to the reference voltage line (RL).

[0182] The gate electrode (Sg) of the second switching circuit (172) may overlap with the metal line (104m) of the second dam (104-2) or be positioned below the metal line (104m) of the second dam (104-2), and may be electrically coupled to the metal line (104m) of the second dam (104-2) through the second control line contact hole (CLh2). For example, the metal line (104m) of the second dam (104-2) may be the second switching control line.

[0183] The first electrode (Se1) of the second switching circuit (172) can be electrically coupled to the second data line (DLe) among the two data lines (DLo, DLe) placed in one pixel area (PA). For example, the first electrode (Se1) of the second switching circuit (172) can be extended to overlap or intersect with the second data line (DLe) and can be electrically coupled to the second data line (DLe) through the first contact hole.

[0184] The second electrode (Se2) of the second switching circuit (172) can be electrically coupled to a reference voltage line (RL) placed in a pixel area (PA). For example, the second electrode (Se2) of the second switching circuit (172) can be extended to overlap or intersect with the reference voltage line (RL) and can be electrically coupled to the reference voltage line (RL) through a second contact hole. For example, the reference voltage line (RL) can be used as a turn-on sensing line of the second switching circuit (172).

[0185] The third switching circuit (173) may be configured to sense line resistance for two data routing lines connected to each of the first data line (DLo) and the second data line (DLe) placed in one pixel area (PA) in inspection mode. The third switching circuit (173) may be electrically connected to the first data line (DLo) and the second data line (DLe) placed in one pixel area (PA) and the metal line (104m) of the third dam (104-3). The third switching circuit (173) may be turned on in accordance with a third switching control signal supplied through the metal line (104m) of the third dam (104-3) in inspection mode to output an inspection signal supplied through the first data line (DLo) to the second data line (DLe).

[0186] The gate electrode (Sg) of the third switching circuit (173) may overlap with or be positioned below the metal line (104m) of the third dam (104-3) and may be electrically coupled to the metal line (104m) of the third dam (104-3) through the third control line contact hole (CLh3). For example, the metal line (104m) of the third dam (104-3) may be the third switching control line.

[0187] The first electrode (Se1) of the third switching circuit (173) can be electrically coupled to the first data line (DLo). For example, the first electrode (Se1) of the third switching circuit (173) can be extended to overlap or intersect the first data line (DLo) and can be electrically coupled to the first data line (DLo) through the first contact hole.

[0188] The second electrode (Se2) of the third switching circuit (173) can be electrically coupled to the second data line (DLe). For example, the second electrode (Se2) of the third switching circuit (173) can be extended to overlap or intersect the second data line (DLe) and can be electrically coupled to the second data line (DLe) through a second contact hole.

[0189] FIG. 9 is a cross-sectional view of line I-I' shown in FIG. 2 and FIG. 8, FIG. 10 is an enlarged view of 'B2' shown in FIG. 9, FIG. 11 is an enlarged view of 'B3' shown in FIG. 9, and FIG. 12 is a cross-sectional view of line II-II' shown in FIG. 8. FIG. 9 to 12 schematically show the cross-sectional structure of an outermost pixel including a damper and a plurality of switching circuits, etc., according to an embodiment of the present specification; therefore, in the following description, the description of a configuration identical to the configuration described in FIG. 1 to 8 is omitted or simplified.

[0190] Referring to FIG. 2 and FIG. 8 to FIG. 12, a light-emitting display device (or light-emitting display panel) (10) according to an embodiment of the present specification may further include a substrate (100), a wiring substrate (200), a coupling member (300), and a routing part (400).

[0191] A substrate (100) according to one embodiment of the present specification may include a circuit layer (101), a plurality of switching circuit portions (170), a flattening layer (102), an emitting element layer (EDL), a bank (103), a damp portion (104), and an encapsulation layer (106).

[0192] The circuit layer (101) can be placed on the substrate (100). The circuit layer (101) can be represented as a pixel array layer or a TFT array layer.

[0193] A circuit layer (101) according to one embodiment may include a buffer layer (101a) and a circuit array layer (101b).

[0194] The buffer layer (101a) serves to block substances such as hydrogen contained in the substrate (100) from diffusing into the circuit array layer (101b) during the high-temperature process in the manufacturing process of the TFT. Additionally, the buffer layer (101a) can also serve to prevent external moisture or humidity from penetrating into the light-emitting element layer (EDL). For example, the buffer layer (101a) may be made of an inorganic material.

[0195] The circuit array layer (101b) may include a pixel circuit (PC) having a driving TFT (Tdr) disposed in each pixel area (PA) on the buffer layer (101a), a plurality of switching circuit sections (170), and a passivation layer (PAS).

[0196] A driving TFT (Tdr) placed in the circuit area (CA) of each pixel area (PA) may include an active layer (ACT), a gate insulating film (GI), a gate electrode (GE), an interlayer insulating layer (ILD), a first electrode (SD1), and a second electrode (SD2).

[0197] The active layer (ACT) may be placed on a buffer layer (101a) on each pixel area (PA). The active layer (ACT) may include a channel area that overlaps with a gate electrode (GE), and a first electrode contact area and a second electrode contact area that are parallel to each other with the channel area in between. The active layer (ACT) may be used as a bridge line of a jumping structure that directly connects lines within the display (AA) or electrically connects (or contacts) lines placed on different layers by being conductive through a conductive process.

[0198] A gate insulating film (GI) can be placed over the channel region of an active layer (ACT). The gate insulating film (GI) can insulate the active layer (ACT) and the gate electrode (GE).

[0199] The gate electrode (GE) is placed on the gate insulating layer (GI) and can be connected to the gate line (GL). The gate electrode (GE) can overlap with the channel region of the active layer (ACT) with the gate insulating layer (GI) in between.

[0200] An interlayer insulating layer (ILD) may be disposed on a substrate (100) to cover a gate electrode (GE) and an active layer (ACT). For example, the interlayer insulating layer (ILD) may be made of an inorganic material. An interlayer insulating layer (ILD) according to one embodiment may include a single-layer structure of any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof, but is not necessarily limited thereto. For example, the interlayer insulating layer (ILD) may be represented as an insulating layer or a first insulating layer.

[0201] The first electrode (SD1) is placed on an interlayer insulating layer (ILD) that overlaps with the first electrode contact area of ​​the active layer (ACL), and can be electrically connected (or contacted) with the first electrode contact area of ​​the active layer (ACL) through a first via hole placed in the interlayer insulating layer (ILD). For example, the first electrode (SD1) is the source electrode of the driving TFT (Tdr), and the first electrode contact area of ​​the active layer (ACL) may be the source area.

[0202] The second electrode (SD2) is placed on an interlayer insulating layer (ILD) that overlaps with the second electrode contact area of ​​the active layer (ACL), and can be electrically connected (or contacted) with the second electrode contact area of ​​the active layer (ACL) through a second via hole placed in the interlayer insulating layer (ILD). For example, the second electrode (SD2) is the drain electrode of the driving TFT (Tdr), and the second electrode contact area of ​​the active layer (ACL) may be the drain area.

[0203] As shown in FIG. 5, the first and second switching TFTs (Tsw1, Tsw2) constituting the pixel circuit (PC) are each formed together with the driving TFT (Tdr), so a description thereof is omitted.

[0204] A plurality of switching circuit sections (170) may be formed at the edge portion (MA3) of the outermost pixel (Po). The plurality of switching circuit sections (170) may include first to third switching circuits (171, 172, 173). Since the first to third switching circuits (171, 172, 173) having such a configuration are formed together with the driving TFT (Tdr), a description thereof is omitted.

[0205] A circuit layer (101) according to one embodiment may further include a lower metal layer (BML) disposed between a substrate (100) and a buffer layer (101a). The lower metal layer (BML) may include a light-blocking pattern (LSP) disposed below the active layer (ACT) of TFTs (Tdr, Tsw1, Tsw2) constituting a pixel circuit (PC).

[0206] The light-blocking pattern (LSP) can be arranged in an island shape between the substrate (100) and the active layer (ACT). The light-blocking pattern (LSP) blocks light incident on the active layer (ACT) through the substrate (100), thereby minimizing or preventing changes in the threshold voltage of the TFT caused by external light. Optionally, the light-blocking pattern (LSP) may be electrically coupled to the first electrode (SD1) of the TFT to serve as the lower gate electrode of the corresponding TFT, in which case changes in the threshold voltage of the TFT due to bias voltage as well as changes in characteristics due to light can be minimized or prevented.

[0207] The lower metal layer (BML) can be used as lines arranged parallel to each other among the gate line (GL), data line (DL), pixel driving power line (PL), pixel common voltage line (CVL), and reference voltage line (RL). For example, the lower metal layer (BML) can be used as lines arranged parallel to the second direction (Y) among the pixel driving lines (DL, GL, PL, CVL, RL, GCL) placed on the substrate (100).

[0208] A passivation layer (PAS) may be disposed on a substrate (100) to cover a pixel circuit (PC) including a driving TFT (Tdr). The passivation layer (PAS) may be the top layer of a circuit layer (101) covering a driving TFT (Tdr) disposed in each subpixel area (SPA), but is not limited thereto. The passivation layer (PAS) may be made of an inorganic material that is the same as or different from the interlayer insulating layer (ILD). For example, the passivation layer (PAS) may include a single-layer structure of any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof. For example, the passivation layer (PAS) may be expressed using terms such as a protective layer, a circuit protective layer, a circuit insulating layer, an inorganic insulating layer, a first inorganic insulating layer, or a second insulating layer.

[0209] The planarization layer (102) is placed on a substrate (100) on which a passivation layer (PAS) is placed and can provide a flat surface on the passivation layer (PAS). For example, the passivation layer (PAS) can be placed between an interlayer insulating layer (ILD) and the planarization layer (102).

[0210] The planarization layer (102) may be formed to cover the circuit layer (101) excluding the passivation layer (PAS) disposed at the edge portion of the substrate (100). For example, the planarization layer (102) may be disposed between the substrate (100) and the light-emitting element layer (EDL) or disposed below the light-emitting element layer (EDL). The planarization layer (102) according to one embodiment may be formed of an organic material, but is not limited thereto. For example, the planarization layer (102) may be made of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, but is not limited thereto.

[0211] A light-emitting element layer (EDL) can be disposed on a planarization layer (102). A light-emitting element layer (EDL) according to one embodiment may include a pixel electrode (PE), a self-emissive element (ED), and a common electrode (CE).

[0212] The pixel electrode (PE) may be represented as a reflective electrode, a lower electrode, an anode electrode of a self-luminous element (ED), or a first electrode. The pixel electrode (PE) may be placed on a flattening layer (102) that overlaps with the light-emitting region (EA) of each subpixel (SP). The pixel electrode (PE) may be placed to overlap with at least part or all of the pixel circuit (PC).

[0213] The pixel electrode (PE) may include a plurality of pixel split electrodes (PEa, PEb) disposed in a light-emitting region (EA) so as to overlap at least part or all of the pixel circuit (PC), but is not limited thereto, and may include a single electrode structure formed as a single body in the light-emitting region (EA) so as to overlap at least part or all of the pixel circuit (PC).

[0214] A pixel electrode (PE) according to one embodiment of the present specification may include a first pixel split electrode (PEa) disposed in one side of a light-emitting region (EA) and a first pixel split electrode (PEa) disposed in the other side of a light-emitting region (EA). A plurality of pixel split electrodes (PEa, PEb) may be disposed spaced apart from each other within the corresponding light-emitting region (EA) (or subpixel region (SPA)). One side of each of the plurality of pixel split electrodes (PEa, PEb) may extend (or protrude) onto the first electrode (SD1) of the driving TFT (Tdr) and may be commonly connected to the first electrode (SD1) of the driving TFT (Tdr) through an electrode contact hole (ECH). For example, each of the plurality of pixel split electrodes (PEa, PEb) may branch off from an electrode contact hole (ECH) disposed within the light-emitting region (EA) (or subpixel region (SPA)).

[0215] Multiple pixel division electrodes (PEa, PEb) may be implemented to repair (or normalize) the corresponding subpixel when a defect occurs due to foreign substances during the manufacturing process. For example, if a defect caused by foreign substances occurs in the first pixel division electrode (PEa) among the multiple pixel division electrodes (PEa, PEb), in the repair process, the extension of the first pixel division electrode (PEa) is cut to disconnect the electrical connection (or contact) between the first electrode (SD1) of the driving TFT (Tdr) and the first pixel division electrode (PEa), thereby allowing the corresponding subpixel to be repaired (or normalized) through the remaining pixel division electrodes (PEb) excluding the first pixel division electrode (PEa).

[0216] The pixel electrode (PE) may include a stacked structure of at least two pixel electrode layers (PEL1, PEL2). For example, each of the at least two pixel electrode layers (PEL1, PEL2) may be made of at least one material selected from ITO, IZO, Al, Ag, Mo, Ti, MoTi, and Cu. For example, the at least two pixel electrode layers (PEL1, PEL2) may be sequentially deposited on the planarization layer (102) and then simultaneously patterned, but are not limited thereto.

[0217] A pixel electrode (PE) according to one embodiment of the present specification may have a two-layer structure comprising a first pixel electrode layer (PEL1) (or a first metal layer) disposed on a planarization layer (102), and a second pixel electrode layer (PEL2) (or a second metal layer) disposed (or laminated) on the first pixel electrode layer (PEL1). The first and second pixel electrode layers (PEL1, PEL2) may be sequentially deposited on the planarization layer (102) and then patterned simultaneously, but are not limited thereto.

[0218] The first pixel electrode layer (PEL1) can serve as an adhesive layer with the planarization layer (102) and as an auxiliary electrode for the self-emissive element (ED), and can be made of ITO or IZO material. The second pixel electrode layer (PEL2) can serve as a reflector and reduce the resistance of the pixel electrode (PE), and can be made of any one of Al, Ag, Mo, Ti, MoTi, and Cu.

[0219] A pixel electrode (PE) according to another embodiment of the present specification may have a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO, a four-layer structure of ITO / Cu / MoTi / ITO, or a five-layer structure of ITO / MoTi / ITO / Ag / ITO, but is not limited thereto.

[0220] A self-luminous element (ED) can be placed on a substrate (100). The self-luminous element (ED) can be formed on a pixel electrode (PE) and in direct contact with the pixel electrode (PE). The pixel electrode (PE) can be placed below the self-luminous element (ED).

[0221] The self-luminous element (ED) may be a common layer formed in common on each of a plurality of subpixels (SP) so as not to be distinguished by subpixel (SP). The self-luminous element (ED) may emit white light (or blue light) in response to the current flowing between the pixel electrode (PE) and the common electrode (CE). The self-luminous element (ED) may include an organic light-emitting element, or may include a stacked or mixed structure of an organic light-emitting element and a quantum dot light-emitting element.

[0222] An organic light-emitting device may include two or more organic light-emitting parts for emitting white light (or blue light). For example, an organic light-emitting device may include a first organic light-emitting part and a second organic light-emitting part for emitting white light by mixing a first light and a second light. Here, the first organic light-emitting part may include at least one of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer. The second organic light-emitting part may include at least one light-emitting layer among the blue light-emitting layer, the green light-emitting layer, the red light-emitting layer, the yellow light-emitting layer, and the yellow-green light-emitting layer for emitting a second light that can be mixed with the first light emitted from the first organic light-emitting part to produce white light.

[0223] The organic light-emitting device may further include at least one functional layer to improve luminous efficiency and / or lifespan, etc. For example, the functional layer may be disposed on the upper and / or lower portions of the light-emitting layer, respectively.

[0224] A common electrode (CE) is positioned on a display portion (AA) of a substrate (100) and can be electrically coupled to a self-luminous element (ED) positioned on each of a plurality of subpixels (SP). The common electrode (CE) can be represented as a cathode electrode, a transparent electrode, an upper electrode, a negative electrode, or a second electrode. The common electrode (CE) is formed on the self-luminous element (ED) and can be in direct contact with or electrically in direct contact with the self-luminous element (ED). The common electrode (CE) may include a transparent conductive material so that light emitted from the self-luminous element (ED) can be transmitted.

[0225] Additionally, the light-emitting diode layer (EDL) may further include a capping layer disposed on the common electrode (CE). The capping layer is disposed on the common electrode (CE) and can improve the light emission efficiency by controlling the refractive index of the light emitted from the light-emitting diode layer (EDL).

[0226] A bank (103) may be formed to include an opening that overlaps with the light-emitting region (EA) of a subpixel area (SPA) and is placed on a flattening layer (102). A bank (103) may be placed on a flattening layer (102) to cover the edge portion of a pixel electrode (PE). A bank (103) defines the light-emitting region (or opening) (EA) of each of a plurality of subpixels (SP) and may electrically isolate the pixel electrode (PE) placed in an adjacent subpixel (SP). A bank (103) may be formed to cover the electrode contact hole (ECH) placed in each pixel area (PA). A bank (103) may be covered by a self-luminous element (ED) of a light-emitting element layer (EDL). For example, the self-luminous element (ED) may be placed on the bank (103) as well as on the pixel electrode (PE) of each of the plurality of subpixels (SP).

[0227] The dam portion (104) may be placed on the edge portion of the substrate (100) or on the edge portion of the outermost pixel (Po). The dam portion (104) may be placed on the circuit layer (101) of the display portion (AA) to have a planar closed-loop line shape (or continuous line shape or closed-loop shape) along the third margin area (MA3) of the outermost pixel (Po). For example, the dam portion (104) may be supported by the interlayer insulating layer (ILD) of the circuit layer (101) or placed on the switching circuit portion (170) depending on the formation location. For example, the third margin area (MA3) may be an area containing the dam portion (104).

[0228] The dam (104) may be implemented to separate at least a portion of the light-emitting element layer (EDL) disposed at the edge portion of the substrate (100) or the outermost pixels (Po). This dam (104) may include the function of physically separating the light-emitting element layer (EDL) at the edge portion of the substrate (100) or the outermost pixels (Po), the function of blocking the spreading or overflow of the organic encapsulation layer, and the function of preventing moisture penetration from the lateral direction of the substrate (100). The structure of the dam (104) for separating the light-emitting element layer (EDL) will be described later.

[0229] The encapsulation layer (106) can be implemented to cover the light-emitting element layer (EDL) by being placed over the remaining portion of the substrate (100) excluding the outermost edge portion. The encapsulation layer (106) can be implemented on the substrate (100) to surround both the front surface and the lateral surfaces of the light-emitting element layer (EDL). For example, by implementing the encapsulation layer (106) to surround both the front surface and the lateral surfaces of the light-emitting element layer (EDL), oxygen or moisture can be blocked from penetrating into the light-emitting element layer (EDL), thereby improving the reliability of the light-emitting element layer (EDL) against oxygen or moisture.

[0230] The bag layer (106) may include first to third bag layers (106a, 106b, 106c).

[0231] The first encapsulation layer (106a) may be implemented to block oxygen or moisture from penetrating into the light-emitting element layer (EDL). The first encapsulation layer (106a) may be placed over the common electrode (CE) and surround the light-emitting element layer (EDL). Accordingly, both the front surface and the lateral surfaces of the light-emitting element layer (EDL) may be surrounded by the first encapsulation layer (106a). The first encapsulation layer (106a) may be a first inorganic encapsulation layer comprising an inorganic material. For example, the first encapsulation layer (106a) may comprise a single-layer structure of any one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiONx), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof.

[0232] The second encapsulation layer (106b) may be implemented on the first encapsulation layer (106a) placed in an encapsulation area defined by the dam (104) so ​​as to have a thickness relatively thicker than that of the first encapsulation layer (106a). The second encapsulation layer (106b) may have a thickness sufficient to cover foreign substances (or unnecessary materials or unnecessary structures) that are present or may be present on the first encapsulation layer (106a). The second encapsulation layer (106b) may be surrounded by the dam (104). The second encapsulation layer (106b) may spread to the edge portion of the substrate (100) due to its relatively thick thickness, but the spreading of the second encapsulation layer (106b) may be blocked by the dam (104). The second encapsulation layer (106b) may include an organic material or a liquid organic material. For example, the second encapsulation layer (106b) may be made of an organic material such as silicon oxycarbon (SiOCz), acrylic, or epoxy-based resin. For example, the second encapsulation layer (106b) may be described as a foreign matter cover layer or an organic encapsulation layer.

[0233] The third encapsulation layer (106c) may be implemented to primarily block oxygen or moisture from penetrating into the light-emitting diode layer (EDL). The third encapsulation layer (106c) may be implemented to surround both the second encapsulation layer (106b) disposed on the inner side of the dam portion (104) and the first encapsulation layer (106a) disposed on the outer side of the dam portion (104). According to one embodiment, the third encapsulation layer (106c) may include an inorganic material identical to or different from the first encapsulation layer (106a). The third encapsulation layer (106c) may be a second inorganic encapsulation layer containing an inorganic material.

[0234] A light-emitting display device (10) or substrate (100) according to one embodiment of the present specification may further include a separation part (105).

[0235] The separation portion (105) may be placed or implemented on the edge portion of the substrate (100) or on the edge portion of the outermost pixels (Po). The separation portion (105) may be placed on the edge portion of the substrate (100) or on the edge portion of the outermost pixels (Po) to have a planar closed-loop line shape (or continuous line shape or closed-loop shape) along the periphery of the dam portion (104) within the third margin area (MA3) of the outermost pixels (Po). For example, the separation portion (105) may be placed on the circuit layer (101) and supported by the interlayer insulating layer (ILD) or buffer layer (101a) of the circuit layer (101).

[0236] In the outermost pixels (Po), a first margin region (MA1) may be positioned between the third margin region (MA3) and the light-emitting region (EA). For example, the first margin region (MA1) may be positioned between the end of the light-emitting region (EA) (or bank (103)) of the outermost pixel (Po) and the dam (104), based on the reliability margin of the light-emitting element layer (EDL) due to lateral moisture permeability of moisture. A second margin region (MA1) may be positioned between the third margin region (MA3) and the outer surface (OS1a) of the substrate (100). For example, the second margin region (MA2) may be positioned between the outer surface (OS) of the substrate (100) and the dam (104), based on the reliability margin of the light-emitting element layer (EDL) due to lateral moisture permeability of moisture, and may include a first pad portion (110). The third margin area (MA3) may be positioned between the first margin area (MA1) and the second margin area (MA2) and may include a dam (104).

[0237] The separation unit (105) can be implemented to separate the self-luminous element (ED) placed at the edge portion of the outermost pixels (Po). The separation unit (105) can be implemented to prevent moisture penetration from the lateral direction of the substrate (100) so as to prevent deterioration of the self-luminous element (ED) due to lateral moisture penetration. The separation unit (105) can prevent lateral moisture penetration by separating (or disconnecting) the self-luminous element (ED) of the light-emitting element layer (EDL) at least once around the dam unit (104). Such a separation unit (105) will be described later.

[0238] Referring to FIGS. 2, FIGS. 4, FIGS. 8, and FIGS. 10, a light-emitting display device or substrate (100) according to one embodiment of the present specification may further include a first pad portion (110).

[0239] The first pad portion (110) is positioned on one edge portion of the substrate (100) and can be electrically connected one-to-one with pixel driving lines (DL, GL, PL, CVL, RL, GCL).

[0240] A first pad portion (110) according to one embodiment may include a plurality of first pads (111) disposed within a circuit layer (101). The plurality of first pads (111) may be divided (or classified) into first data pads (DP), first gate pads (GP), first pixel driving power pads (PPP), first reference voltage pads (RVP), and first pixel common voltage pads (CVP). A first pad portion (110) according to one embodiment may further include first to third front sensing control pads (112a, 112b, 112c), and first to third pad connection lines (176, 177, 178).

[0241] Each of the plurality of first pads (111) and first to third front sensing control pads (112a, 112b, 112c) is disposed on an interlayer insulating layer (ILD) and can be electrically connected (or contacted) with a corresponding line among pixel driving lines (DL, GL, PL, CVL, RL, GCL) through a pad contact hole (PCH) penetrating the interlayer insulating layer (ILD) and the buffer layer (101a). Each of the plurality of first pads (111) and first to third front sensing control pads (112a, 112b, 112c) according to one embodiment is made of the same material as the pixel electrode (PE) and can be formed together with the pixel electrode (PE). Each of the plurality of first pads (111) according to another embodiment is made of the same material as the source / drain electrode of the TFT and can be formed together with the source / drain electrode of the TFT.

[0242] At least a portion of each of the plurality of first pads (111) and first to third front sensing control pads (112a, 112b, 112c) may be exposed on the substrate (100) through a pad open hole (POH) formed in the passivation layer (PAS).

[0243] Referring to FIG. 9, a light-emitting display device (10) or substrate (100) according to one embodiment of the present specification may further include a wavelength conversion layer (107) disposed on an encapsulation layer (106).

[0244] The wavelength conversion layer (107) can convert white light (or blue light) incident from the light-emitting region (EA) of each subpixel region (SPA) into color light corresponding to the subpixel (SP), or allow only color light corresponding to the subpixel (SP) to pass through. For example, the wavelength conversion layer (107) may include at least one of a wavelength conversion member and a color filter layer.

[0245] The wavelength conversion layer (107) may include a plurality of wavelength conversion members (107a) and a protective layer (107b).

[0246] A plurality of wavelength conversion members (107a) may be placed on the encapsulation layer (106) on the light-emitting region (EA) of each subpixel (SP). For example, the plurality of wavelength conversion members (107a) may have a size equal to or larger than the light-emitting region (EA) of each subpixel (SP). The plurality of wavelength conversion members (107a) may be divided (or classified) into a red color filter placed on the encapsulation layer (106) on the light-emitting region (EA) of a red subpixel (SP), a green color filter placed on the encapsulation layer (106) on the light-emitting region (EA) of a green subpixel (SP), and a blue color filter placed on the encapsulation layer (106) on the light-emitting region (EA) of a blue subpixel (SP).

[0247] The protective layer (107b) may be implemented to cover the wavelength conversion members (107a) and provide a flat surface over the wavelength conversion members (107a). For example, the protective layer (107b) may be positioned to cover the wavelength conversion members (107a) and the encapsulation layer (106) on which the wavelength conversion members (107a) are not placed. The protective layer (107b) according to one embodiment may comprise an organic material. Optionally, the protective layer (107b) may further comprise a getter material capable of adsorbing moisture and / or oxygen.

[0248] Alternatively, the wavelength conversion layer (107) according to one embodiment of the present specification may be changed to a wavelength conversion sheet having a sheet form and disposed on the encapsulation layer (106). In this case, the wavelength conversion sheet (or quantum dot sheet) may include wavelength conversion members (107a) interposed between a pair of films. For example, when the wavelength conversion layer (107) includes quantum dots that re-emit color light set in the subpixel (SP), the light-emitting element layer (EDL) of the subpixel (SP) may be implemented to emit white light or blue light.

[0249] A light-emitting display device or substrate (100) according to one embodiment of the present specification may further include a functional film (108). The functional film (108) may be disposed on a wavelength conversion layer (107). For example, the functional film (108) may be bonded on the wavelength conversion layer (107) via a transparent adhesive member. A functional film (108) according to one embodiment may include at least one of an anti-reflection layer (or anti-reflection film), a barrier layer (or barrier film), a touch sensing layer, and a light path control layer (or light path control film).

[0250] The anti-reflection layer may include a circularly polarized layer (or circularly polarized film) that blocks reflected light that is reflected by TFTs and / or pixel driving lines placed on the substrate (100) and travels outward. The barrier layer may primarily prevent moisture or oxygen penetration by being made of a material with low moisture permeability, for example, a polymer material. The touch sensing layer may include a touch electrode layer based on mutual capacitance or magnetic capacitance, thereby outputting touch data corresponding to a user touch through the touch electrode layer. The light path control layer may include a structure in which a high-refractive index layer and a low-refractive index layer are alternately stacked, thereby changing the path of light incident from each pixel (P) to minimize color shift phenomena according to the viewing angle.

[0251] A light-emitting display device (10) or substrate (100) according to one embodiment of the present specification may further include a side sealing member (109).

[0252] A side sealing member (109) is formed between the substrate (100) and the functional film (108) and can cover both sides of the circuit layer (101) and the wavelength conversion layer (107). For example, the side sealing member (109) can cover both sides of the circuit layer (101) and the wavelength conversion layer (107) that are exposed to the outside of the light-emitting display device between the functional film (108) and the substrate (100). Additionally, the side sealing member (109) can cover a portion of the routing portion (400) connected to the first pad portion (110) of the substrate (100). This side sealing member (109) can serve to prevent side light leakage caused by light traveling toward the outer side within the wavelength conversion layer (107) among the light emitted from the self-emissive element (ED) of each subpixel (SP). In particular, the side sealing member (109) overlapping with the first pad portion (110) of the substrate (100) can serve to prevent or minimize the reflection of external light by the first pad (111) placed on the first pad portion (110). Optionally, the side sealing member (109) may further include a getter material capable of adsorbing moisture and / or oxygen.

[0253] In a light-emitting display device (10) according to one embodiment of the present specification, the substrate (100) may further include a first chamfer (100c) formed in the corner portion between the first surface (100a) and the outer surface (OS). The first chamfer (100c) may serve to prevent the routing portion (400) from being severed along the corner portion of the substrate (100) while minimizing damage to the corner portion of the substrate (100) due to physical impact from the outside. For example, the first chamfer may have a 45-degree angle, but is not necessarily limited thereto. Such a first chamfer (100c) may be implemented by a cutting wheel, a grinding wheel, or a chamfering process using a laser. Accordingly, the outer surface of the pad electrodes (111) of the first pad portion (110) arranged to be in contact with the first chamfer (100c) may include an inclined surface inclined at an angle corresponding to the angle of the first chamfer (100c) by removing or grinding together with the corner portion of the substrate (100) by a chamfering process. For example, when the first chamfer (100c) is formed at a 45-degree angle between the first surface (100a) and the outer surface (OS) of the substrate (100), the outer surface (or one end) of the pad electrodes (111) of the first pad portion (110) may also be formed at a 45-degree angle.

[0254] Referring to FIGS. 2, FIGS. 4, FIGS. 7, and FIGS. 9, a wiring board (200) according to one embodiment of the present specification may include a second pad portion (210), at least one third pad portion (230), and a link line portion (250).

[0255] The second pad portion (210) may include a plurality of second pads (211) disposed on the rear surface (200b) of the wiring board (200) so as to overlap one-to-one with each of the plurality of first pads disposed in the first pad portion (110). The plurality of second pads (211) may be divided (or classified) into a plurality of second pixel driving power pads, a plurality of second data pads, a plurality of second reference voltage pads, a plurality of second gate pads, and a plurality of second pixel common voltage pads.

[0256] Each of the plurality of second pixel driving power pads may overlap with each of the plurality of first pixel driving power pads (PPP1) disposed in the first pad section (110). Each of the plurality of second data pads may overlap with each of the plurality of first data pads (DP1) disposed in the first pad section (110). Each of the plurality of second reference voltage pads may overlap with each of the plurality of first reference voltage pads (RVP1) disposed in the first pad section (110). Each of the plurality of second gate pads may overlap with each of the plurality of first gate pads (GP1) disposed in the first pad section (110). Each of the plurality of second pixel common voltage pads may overlap with each of the plurality of first pixel common voltage pads (CVP1) disposed in the first pad section (110).

[0257] The second pad section (210) may further include first to third rear sensing control pads that overlap with each of the first to third front sensing control pads (112a, 112b, 112c) disposed in the first pad section (110). According to one embodiment of the present specification, each of the first to third rear sensing control pads may be selected from a plurality of rear dummy pads that overlap with each of the plurality of front dummy pads. For example, the second pad section (110) includes a plurality of rear pads, and the plurality of rear pads may be divided (or classified) into a plurality of second pixel driving power pads, a plurality of second data pads, a plurality of second reference voltage pads, a plurality of second gate pads, a plurality of second pixel common voltage pads, and first to third rear sensing control pads.

[0258] At least one third pad section (230) may include a plurality of third pads (or input pads) (231) spaced apart from each other to have a constant spacing. For example, the plurality of third pads (231) may be divided (or classified) into a plurality of third pixel driving power pads, a plurality of third data pads, a plurality of third reference voltage pads, a plurality of third gate pads, and at least one third pixel common voltage pad. At least one third pad section (230) is coupled with a driving circuit section (500) and can receive a pixel driving power, a data signal, a reference voltage, a gate control signal, and a pixel common voltage supplied from the driving circuit section (500).

[0259] And, at least one third pad section (230) may further include first to third switching control signal pads that receive first to third switching control signals from the driving circuit section (500).

[0260] The link line section (250) may include a plurality of link lines disposed between a second pad section (210) and at least one third pad section (230) on the rear surface (200b) of the wiring board (200).

[0261] A plurality of link lines can be divided (or classified) into a plurality of pixel driving power link lines, a plurality of data link lines, a plurality of reference voltage link lines, a plurality of gate link lines, and at least one pixel common voltage link line.

[0262] Each of the plurality of pixel driving power link lines may be individually (or one-to-one) connected (or coupled) to each of the plurality of second pixel driving power pads and each of the plurality of third pixel driving power pads. Each of the plurality of data link lines may be individually (or one-to-one) connected (or coupled) to each of the plurality of second data pads and each of the plurality of third data pads. Each of the plurality of reference voltage link lines may be individually (or one-to-one) connected (or coupled) to each of the plurality of second reference voltage pads and each of the plurality of third reference voltage pads. Each of the plurality of gate link lines may be individually (or one-to-one) connected (or coupled) to each of the plurality of second gate pads and each of the plurality of third gate pads. At least one pixel common voltage link line (257) may be commonly connected (or coupled) to each of the plurality of second pixel common voltage pads and at least one third pixel common voltage pad.

[0263] Additionally, in the link line section (250), a plurality of link lines may be further divided (or classified) into first to third sensing control link lines. For example, the link line section (250) may further include first to third sensing control link lines. Each of the first to third sensing control link lines may be individually (or one-to-one) connected to each of the first to third rear sensing control pads disposed in the second pad section (210) and each of the first to third switching control signal pads disposed in at least one third pad section (250).

[0264] A light-emitting display device (10) or wiring board (200) according to one embodiment of the present specification may further include a metal pattern layer and an insulating layer.

[0265] The metal pattern layer (or conductive pattern layer) may include a plurality of metal layers. The metal pattern layer may include a first metal layer (201), a second metal layer (203), and a third metal layer (205). The insulating layer may include a plurality of insulating layers. For example, the insulating layer may include a first insulating layer (202), a second insulating layer (204), and a third insulating layer (206). The insulating layer may also be described as a back insulating layer or a pattern insulating layer.

[0266] The first metal layer (201) may be implemented on the back surface (200b) of the wiring board (200). The first metal layer (201) may include a first metal pattern. For example, the first metal layer (201) may be represented as a first link layer or a link line layer. Such a first metal pattern may be used as link lines of the link line portion (250).

[0267] The first insulating layer (202) may be implemented on the back surface (200b) of the wiring board (200) to cover the first metal layer (201). According to one embodiment, the first insulating layer (202) may be made of an inorganic material.

[0268] The second metal layer (203) may be implemented on the first insulating layer (202). According to one embodiment, the second metal layer (203) may include a second metal pattern. For example, the second metal layer (203) may be represented as a second link layer, a jumping line layer, or a bridge line layer. Such a second metal pattern may be used as gate link lines among the link lines of the link line section, but is not necessarily limited thereto. For example, the second metal layer (203) may be used as a jumping line (or bridge line) for electrically connecting (or contacting) link lines made of different layers or different metal materials in the link line section.

[0269] Optionally, the link lines (e.g., a plurality of first link lines) disposed in the second metal layer (203) may be disposed in the first metal layer (201), and the link lines (e.g., a plurality of second link lines) disposed in the first metal layer (201) may be changed to be disposed in the second metal layer (203).

[0270] The second insulating layer (204) may be implemented on the back surface (200b) of the wiring board (200) to cover the second metal layer (203). According to one embodiment, the second insulating layer (204) may be made of an inorganic material.

[0271] A third metal layer (205) may be implemented on the second insulating layer (204). According to one embodiment, the third metal layer (205) may include a third metal pattern. For example, the third metal layer (205) may be represented as a third link layer or a pad electrode layer. Such a third metal pattern may be used as pads of the second pad portion (210). For example, the pads of the second pad portion (210) made of the third metal layer (205) may be electrically connected (or contacted) with the first metal layer (201) through pad contact holes formed in the first and second insulating layers (202, 204).

[0272] A third insulating layer (206) may be implemented on the rear surface (200b) of the wiring board (200) to cover the third metal layer (205). According to one embodiment, the third insulating layer (206) may be made of an organic material. For example, the third insulating layer (206) may be made of an insulating material such as photoacrylic. This third insulating layer (206) can prevent external exposure of the third metal layer (205) by covering the third metal layer (205). The third insulating layer (206) may also be described as an organic insulating layer, a protective layer, a rear protective layer, an organic protective layer, a rear coating layer, or a rear cover layer.

[0273] The routing section (400) may include a plurality of routing lines (410) disposed on each of the first outer surface (OS1a) of the outer surface (OS) of the substrate (100) and the first outer surface (OS1b) of the wiring substrate (200).

[0274] Each of the plurality of routing lines (410) can be electrically connected one-to-one to each of the first pads (111) of the first pad section (110) and each of the second pads (211) of the second pad section (210). The plurality of routing lines (410) can be classified (or distinguished) into a plurality of pixel power routing lines, a plurality of data routing lines, a plurality of reference voltage routing lines, a plurality of gate routing lines, and a plurality of pixel common voltage routing lines.

[0275] Each of the plurality of pixel power routing lines may be individually (or one-to-one) connected (or combined) to each of the plurality of first pixel driving power pads (PPP1) disposed in the first pad section (110) and each of the plurality of second pixel driving power pads disposed in the second pad section (210). Each of the plurality of data routing lines may be individually (or one-to-one) connected (or combined) to each of the plurality of first data pads (DP1) disposed in the first pad section (110) and each of the plurality of second data pads disposed in the second pad section (210). Each of the plurality of reference voltage routing lines (415) may be individually (or one-to-one) connected (or combined) to each of the first reference voltage pads (RVP1) of the first pad section (110) and each of the second reference voltage pads of the second pad section (210). Each of the plurality of gate routing lines may be individually (or one-to-one) connected (or combined) to each of the plurality of first gate pads disposed in the first pad section (110) and each of the plurality of second gate pads disposed in the second pad section (210). Each of the plurality of pixel common voltage routing lines may be individually (or one-to-one) connected (or combined) to each of the plurality of first pixel common voltage pads disposed in the first pad section (110) and each of the plurality of second pixel common voltage pads disposed in the second pad section (210).

[0276] In the routing section (400), a plurality of routing lines (410) may be further classified (divided) into first to third sensing control routing lines. For example, the routing section (400) may further include first to third sensing control routing lines. Each of the first to third sensing control routing lines may be individually (or one-to-one) connected (or combined) to each of the first to third front sensing control pads (112a, 112b, 112c) disposed in the first pad section (110) and each of the first to third rear sensing control pads disposed in the second pad section (210).

[0277] Each of the plurality of routing lines (410) and the first to third sensing control routing lines may be formed to wrap around the outer surface (OS1a) of the substrate (100) and the outer surface (OS1b) of the wiring board (200). According to one embodiment of the present specification, each of the plurality of routing lines (410) and the first to third sensing control routing lines may be formed by a printing process using a conductive paste. According to another embodiment of the present specification, each of the plurality of routing lines (410) and the first to third sensing control routing lines may be formed by a transfer process in which a conductive paste pattern is transferred onto a transfer pad made of a flexible material. For example, the conductive paste may include silver (Ag) paste, but is not limited thereto.

[0278] A light-emitting display device or routing unit (400) according to one embodiment of the present specification may further include an edge coating layer (430).

[0279] The edge coating layer (430) can be implemented to cover the routing section (400). The edge coating layer (430) can be implemented to cover each of the plurality of routing lines (410) and the first to third sensing control routing lines. For example, the edge coating layer (430) may be an edge protection layer or an edge insulation layer.

[0280] An edge coating layer (430) according to one embodiment may be implemented to cover not only a plurality of routing lines (410) but also the entire first edge portion and first outer surface (OS1a) of the substrate (100) and the first edge portion and first outer surface (OS1b) of the wiring board (200). The edge coating layer (430) can prevent corrosion of each of the plurality of routing lines (410) and the first to third sensing control routing lines made of a metal material, or electrical short circuits between the plurality of routing lines (410) and the first to third sensing control routing lines. Additionally, the edge coating layer (430) can prevent or minimize reflection of external light by the plurality of routing lines (410), the first to third sensing control routing lines, and the first pads (111) of the first pad portion (110). The edge coating layer (430) may be made of a light-blocking material including black ink. Since the edge coating layer (430) forms (or constitutes) the outermost side (or side wall) of the display device (or display panel), it may include a shock-absorbing material (or material) or a soft material to prevent damage to the outer surface (OS) of the substrate (100, 200) due to external impact. The edge coating layer (430) may include a mixture of a light-blocking material and a shock-absorbing material.

[0281] Referring to FIGS. 9, 11, and 12, the damper (104), a plurality of switching circuits (170), and a separation unit (105) according to an embodiment of the present specification are described as follows.

[0282] Each of the first to third dams (104-1, 104-2, 104-3) of the dam section (104) according to the embodiment of the present specification may include a first dam pattern (or lower dam) (104a), a second dam pattern (or middle dam) (104b), a metal line (104m), and a third dam pattern (or upper dam) (104c).

[0283] The first dam pattern (104a) may be placed on the circuit layer (101) of the third margin area (MA3) of the substrate (100) or the outermost pixel (Po). A portion of the first dam pattern (104a) may be placed on the electrostatic protection circuit (EPC). The first dam pattern (104a) may be made of an inorganic material.

[0284] According to one embodiment of the present specification, the first dam pattern (104a) may be made of the same material as the passivation layer (PAS). The first dam pattern (104a) may be implemented as a single-layer structure of the passivation layer (PAS). In this case, the first dam pattern (104a) may be formed or implemented by a part of the passivation layer (PAS) (or a non-patterned area) that remains intact without being patterned (or removed) by the patterning process of the passivation layer (PAS) placed on the interlayer insulation layer (ILD) of the third margin region (MA3).

[0285] According to another embodiment of the present specification, the first dam pattern (104a) may be implemented as a stacked structure of a passivation layer (PAS) and an interlayer insulation layer (ILD). In this case, the first dam pattern (104a) may be formed or implemented by a portion (or non-patterned area) of the interlayer insulation layer (ILD) and the passivation layer (PAS) that remains intact without being patterned (or removed) by the patterning process of the interlayer insulation layer (ILD) and the passivation layer (PAS) placed on the buffer layer (101a) of the third margin region (MA3).

[0286] The side of the first dam pattern (104a) can be implemented as a slanted structure or a regular taper structure. For example, the cross-section of the first dam pattern (104a) cut along the width direction can have a trapezoidal cross-sectional structure in which the upper side is narrower than the lower side.

[0287] A second dam pattern (104b) may be placed on top of a first dam pattern (104a). According to one embodiment, the second dam pattern (104b) may be made of an organic material. For example, the second dam pattern (104b) may be made of the same material as the flattening layer (102). For example, the second dam pattern (104b) may have the same height (or thickness) as the flattening layer (102) or may have a higher height than the flattening layer (102). For example, the height (or thickness) of the second dam pattern (104b) may be twice the height (or thickness) of the flattening layer (102) depending on the second deposition of the flattening layer (102). This second dam pattern (104b) can be formed or implemented by a part (or non-patterned area) of the flattening layer (102) that remains as is without being patterned (or removed) by the patterning process of the flattening layer (102).

[0288] The side of the second dam pattern (104b) can be implemented as a slanted structure or a regular taper structure. For example, the second dam pattern (104b) cut along the width direction can have a trapezoidal cross-sectional structure identical to that of the first dam pattern (104a). Based on the width direction, one edge portion and the other edge portion of the second dam pattern (104b) can each protrude outside the side of the first dam pattern (104a). For example, the distance between the side end of the second dam pattern (104b) and the side of the first dam pattern (104a) can be greater than the combined thickness of the self-luminescent element (ED) and the common electrode (CE).

[0289] The side (104as) of the first dam pattern (104a) may have an undercut structure with respect to the second dam pattern (104b). For example, the dam portion (104) may include an undercut region disposed at the boundary between the first dam pattern (104a) and the second dam pattern (104b) or on the upper side of the first dam pattern (104a). The undercut region between the first dam pattern (104a) and the second dam pattern (104b) may be a structure for separating (or severing) at least some layer of the light-emitting element layer (EDL) disposed on the dam portion (104). For example, the undercut region between the first dam pattern (104a) and the second dam pattern (104b) may be formed or realized by an over-etching process of the passivation layer (PAS). This second dam pattern (104b) can cover the side of the first dam pattern (104a) by protruding outward from the side of the first dam pattern (104a) through the undercut structure of the first dam pattern (104a). By doing so, the second dam pattern (104b) can have an eaves structure relative to the first dam pattern (104a).

[0290] A metal line (104m) may be placed on the second dam pattern (104b). The metal line (104m) may be laminated on the second dam pattern (104b) with the same material or structure as the pixel electrode (PE). This metal line (104m) may be formed or implemented by a portion of the pixel electrode material (or a non-patterned area) that remains on the second dam pattern (104b) without being patterned (or removed) by the patterning process of the pixel electrode (PE).

[0291] A third dam pattern (104c) can be placed over the second dam pattern (104b) to wrap around the metal line (104m). The sides of the third dam pattern (104c) can be implemented as a slanted structure or a regular taper structure. For example, the third dam pattern (104c) cut along the width direction can have a trapezoidal cross-sectional structure identical to that of the second dam pattern (104b).

[0292] The third dam pattern (104c) may include organic or inorganic materials. For example, the third dam pattern (104c) may be laminated on the second dam pattern (104b) with the same material as the bank (103). This third dam pattern (104c) may be formed or realized by a part of the bank (103) (or a non-patterned area) that remains intact without being patterned (or removed) by the patterning process of the bank (103).

[0293] According to one embodiment of the present specification, a material layer of a self-luminescent element (ED) placed on each of the first to third dams (104-1, 104-2, 104-3) can be automatically separated (or severed) during the deposition process by an undercut region (or eaves structure) between the first dam pattern (104a) and the second dam pattern (104b). For example, since the deposition material of the self-emissive element (ED) has linearity, it cannot be deposited on the side (104as) of the first dam pattern (104a) which is covered by the second dam pattern (104b) in each of the first to third dams (104-1, 104-2, 104-3), and can be separated (or severed) in the undercut area between the first dam pattern (104a) and the second dam pattern (104b) of each of the first to third dams (104-1, 104-2, 104-3) by being deposited on the top surface and side surface of each of the first to third dams (104-1, 104-2, 104-3) and on the circuit layer (101). Accordingly, the self-luminous element (ED) can be automatically separated (or disconnected) from each of the first to third dams (104-1, 104-2, 104-3) during the deposition process, and thus a separate patterning process for separating (or disconnecting) the self-luminous element (ED) can be omitted. Accordingly, the self-luminous element (ED) placed on the substrate (100) is separated (or disconnected) from each of the first to third dams (104-1, 104-2, 104-3), and thus the lateral moisture permeability path of the substrate (100) can be blocked by each of the first to third dams (104-1, 104-2, 104-3).

[0294] Additionally, the common electrode (CE) placed on the self-luminous element (ED) may be formed to surround each of the first to third dams (104-1, 104-2, 104-3) and each of the island-shaped light-emitting elements (EDi) separated by each of the first to third dams (104-1, 104-2, 104-3) during the deposition process according to the deposition method, so as to be automatically separated (or disconnected) by the undercut area of ​​each of the first to third dams (104-1, 104-2, 104-3) in the same way as the self-luminous element (ED), or not separated by the undercut area of ​​each of the first to third dams (104-1, 104-2, 104-3).

[0295] Referring to FIGS. 8, 9, and 11, the metal line (104m) of the first dam (104-1) may overlap or intersect with the first pad connection line (176) and each of the gate electrodes (Sg) of the first switching circuit (171) of each of the plurality of switching circuit sections (170). The metal line (104m) of the first dam (104-1) may be electrically connected (or in contact) with the first pad connection line (176) through a via hole (176h) formed in the intersection area of ​​the first pad connection line (176) and the first dam (104-1). The metal line (104m) of the first dam (104-1) can be electrically connected (or contacted) with the gate electrode (Sg) of the first switching circuit (171) through the first control line contact hole (CLh1) formed in the intersection area of ​​the first dam (104-1) and the gate electrode (Sg) of the first switching circuit (171). By doing so, the metal line (104m) embedded in the first dam (104-1) is arranged in the shape of a closed-loop line continuously placed in the edge portion of the substrate (100), thereby supplying the first switching control signal supplied through the first front sensing control pad (112a) and the first pad connection line (176) to the gate electrode (Sg) of the first switching circuit (171) of each of the plurality of switching circuit sections (170). For example, the metal line (104m) embedded in the first dam (104-1) can be used as the first switching control line.

[0296] The metal line (104m) of the second dam (104-2) may overlap or intersect with the second pad connection line (177) and each of the gate electrodes (Sg) of the second switching circuit (172) of each of the plurality of switching circuit sections (170). The metal line (104m) of the second dam (104-2) may be electrically connected (or in contact) with the second pad connection line (177) through a via hole (177h) formed in the intersection area of ​​the second pad connection line (177) and the second dam (104-2). The metal line (104m) of the second dam (104-2) can be electrically connected (or contacted) with the gate electrode (Sg) of the second switching circuit (172) through a second control line contact hole (CLh2) formed in the intersection area of ​​the second dam (104-2) and the gate electrode (Sg) of the second switching circuit (172). By doing so, the metal line (104m) embedded in the second dam (104-2) is arranged in the shape of a closed-loop line continuously placed on the edge portion of the substrate (100), thereby supplying a second switching control signal supplied through the second front sensing control pad (112b) and the second pad connection line (177) to the gate electrode (Sg) of the second switching circuit (172) of each of the plurality of switching circuit sections (170). For example, the metal line (104m) embedded in the second dam (104-2) can be used as the second switching control line.

[0297] The metal line (104m) of the third dam (104-3) may overlap or intersect with the gate electrode (Sg) of each of the third switching circuits (173) of the third pad connection line (178) and each of the plurality of switching circuit sections (170). The metal line (104m) of the third dam (104-3) may be electrically connected (or in contact) with the third pad connection line (178) through a via hole (178h) formed in the intersection area of ​​the third pad connection line (178) and the third dam (104-3). The metal line (104m) of the third dam (104-3) can be electrically connected (or contacted) with the gate electrode (Sg) of the third switching circuit (173) through the third control line contact hole (CLh3) formed in the intersection area of ​​the third dam (104-3) and the gate electrode (Sg) of the third switching circuit (173). By doing so, the metal line (104m) embedded in the third dam (104-3) is arranged in the shape of a closed-loop line continuously placed on the edge portion of the substrate (100), thereby supplying the third switching control signal supplied through the third front sensing control pad (112C) and the third pad connection line (178) to the gate electrode (Sg) of the third switching circuit (173) of each of the plurality of switching circuit sections (170). For example, the metal line (104m) embedded in the third dam (104-3) can be used as the third switching control line.

[0298] Additionally, the metal line (104m) embedded in each of the first to third dams (104-1, 104-2, 104-3) can be used as a switching control line to supply a switching control signal supplied from the driving circuit unit (500) to a plurality of switching circuit units (170) in the inspection mode of the light-emitting display device, and can be used as an electrostatic protection line or an electrostatic cutoff line in the normal driving mode or image display mode of the light-emitting display device. For example, in the normal driving mode or image display mode of the light-emitting display device, the driving circuit unit (500) can supply electrostatic protection power to the metal line (104m) embedded in each of the first to third dams (104-1, 104-2, 104-3). For example, the electrostatic protection power may be a ground voltage, a ground voltage, or a pixel common voltage. Accordingly, the metal line (104m) embedded in each of the first to third dams (104-1, 104-2, 104-3) can block static electricity flowing from the outside to the inside of the display unit (AA), thereby preventing defects caused by static electricity.

[0299] Additionally, in the intersection area between the metal line (104m) embedded in each of the first to third dams (104-1, 104-2, 104-3) and the first to third pad connection lines (176, 177, 178), it may be difficult to form via holes (176h, 177h, 178h) to expose the pad connection lines (176, 177, 178) due to the distance (or height) between the metal line (104m) and the pad connection lines (176, 177, 178). Accordingly, an intermediate metal layer may be additionally disposed between the metal line (104m) and the pad connection lines (176, 177, 178). The intermediate metal layer may be implemented on the interlayer insulating layer (ILD) together with the first electrode (SD1) of the driving TFT (Tdr). For example, the intermediate metal layer can be electrically connected (or contacted) with the pad connection lines (176, 177, 178) through an intermediate via hole formed by penetrating the interlayer insulation layer (ILD) and the buffer layer (101a). Also, a portion of the metal line (104m) can be electrically connected (or contacted) with the intermediate metal layer through a via hole (176h, 177h, 178h) that penetrates the second dam pattern (104b) and exposes the intermediate metal layer. Accordingly, the metal line (104m) can be electrically connected (or contacted) with the pad connection lines (176, 177, 178) through the intermediate metal layer.

[0300] A separation portion (105) according to one embodiment of the present specification may be implemented around the dam portion (104) to separate a self-luminous element (ED) disposed around the dam portion (104). The separation portion (105) may be implemented to prevent moisture penetration from the lateral direction of the substrate (100) and to prevent deterioration of the self-luminous element (ED) due to lateral moisture penetration. The separation portion (105) may prevent lateral moisture penetration by separating (or disconnecting) the self-luminous element (ED) of the light-emitting element layer (EDL) at least once around the dam portion (105). For example, the separation portion (105) may be defined as a separation area, separation line, disconnection area, or disconnection line of the self-luminous element (ED).

[0301] The separation section (105) may be implemented on the buffer layer (101a) or interlayer insulation layer (ILD) of the circuit layer (101) surrounding the dam section (104). The separation section (105) may include a plurality of separation structures (105-1, 105-2) disposed around the dam section (104). For example, the separation section (105) may include a first separation structure (105-1) disposed between the first dam (104-1) and the second dam (104-2), and a second separation structure (105-2) disposed between the second dam (104-2) and the third dam (104-3).

[0302] Each of the first and second separation structures (105-1, 105-2) may be placed on the circuit layer (101) of the display unit (AA) to have a planar closed-loop line shape (or a continuous line shape or a closed-loop shape). The first separation structure (105-1) may be placed to surround the first dam (104-1). The second separation structure (105-2) may be placed to surround the second dam (104-2).

[0303] Each of the first and second separation structures (105-1, 105-2) may include a lower structure (105a) and an upper structure (105b).

[0304] The substructure (105a) may be implemented as a single-layer structure by the passivation layer (101d) or as a laminated structure of the passivation layer (PAS) and the interlayer insulation layer (ILD). The sides of the substructure (105a) may be implemented as a slanted structure or a regular taper structure. For example, the substructure (105a) may be described using terms such as a base separation structure, a lower taper structure, or a first taper structure. This substructure (105a) may be implemented to have the same structure as the first dam pattern (104a) together with the first dam pattern (104a).

[0305] The upper structure (105b) may be placed on the lower structure (105a). The upper structure (105b) may contain an organic material. The upper structure (105b) may be made of the same material as the bank (103), but is not limited thereto. The sides of the upper structure (105b) may be implemented as a slanted structure or a regular taper structure. Based on the width direction, one side edge portion and the other side edge portion of the upper structure (105b) may each protrude outside the side of the lower structure (105a). For example, the upper structure (105b) may be described using terms such as an upper taper structure or a second taper structure.

[0306] The side (105as) of the lower structure (105a) may have an undercut structure with respect to the upper structure (105b). For example, each of the first and second separation structures (105-1, 105-2) may include an undercut region located at the boundary between the lower structure (105a) and the upper structure (105b) or on the upper side of the lower structure (105a). The undercut region between the lower structure (105a) and the upper structure (105b) may be a structure for separating (or severing) at least some layer of the light-emitting element layer (EDL) placed on the separation portion (105). For example, the undercut region between the lower structure (105a) and the upper structure (105b) may be formed or realized by an over-etching process of the passivation layer (PAS). This upper structure (105b) can cover the side of the lower structure (105a) by protruding outward from the side of the lower structure (105a) through the undercut structure of the lower structure (105a). By doing so, the upper structure (105b) can be placed on the lower structure (105a) to have an eaves structure for the lower structure (105a).

[0307] At least one of the first and second separation structures (105-1, 105-2) may further include a metal structure (105m) placed between the lower structure (105a) and the upper structure (105b).

[0308] A metal structure (105m) may be placed on a substructure (105a). The metal structure (105m) may be laminated on the substructure (105a) to have the same material or the same structure as the pixel electrode (PE) or the metal line (104m) of the dam (104). The metal structure (105m) may be formed together with the metal line (104m) of the dam (104). The sides of the metal structure (105m) may be implemented as a slanted structure or a regular tapered structure. Based on the width direction, one side edge portion and the other side edge portion of the metal structure (105m) may each protrude outside the side of the substructure (105a). For example, the metal structure (105m) may be described using terms such as a metal pattern layer or an intermediate structure.

[0309] The upper structure (105b) may be placed on top of the metal structure (105m). The upper structure (105b) may be stacked on the upper surface of the metal structure (105m). Although FIGS. 9, 11, and 12 show the upper structure (105b) being placed only on the upper surface of the metal structure (105m), it is not limited thereto, and the upper structure (105b) may be stacked on the lower structure (105a) to surround or cover both the side and upper surfaces of the metal structure (105m). In this case, the metal structure (105m) may be embedded inside the upper structure (105b) in the same way as the metal line (104m) of the dam section (104).

[0310] The side of the substructure (105a) may have an undercut structure with respect to the metal structure (105m). For example, each of the first and second separation structures (105-1, 105-2) may include an undercut area located at the boundary between the substructure (105a) and the metal structure (105m) or on the upper side of the substructure (105a). For example, the undercut area between the substructure (105a) and the metal structure (105m) may be formed or realized by an over-etching process of the passivation layer (PAS). This metal structure (105m) may cover the side of the substructure (105a) by protruding outside the side of the substructure (105a) due to the undercut structure of the substructure (105a). By doing so, the metal structure (105m) may have an eaves structure with respect to the substructure (105a).

[0311] According to one embodiment of the present specification, a material layer of a self-luminous element (ED) placed on a separation part (105) can be automatically separated (or severed) during the deposition process by an undercut area (or eaves structure) between a lower structure (105a) and an upper structure (105b) (or a metal structure (105m)). For example, since the deposition material of the self-luminous element (ED) has a linearity, it cannot be deposited on the side (105as) of the lower structure (105a) which is obscured by the upper structure (105b) (or a metal structure (105m)), but can be separated (or severed) by being deposited on the upper surface and side of the upper structure (105b) and on the circuit layer (101) around the separation part (105) by an undercut area between the lower structure (105a) and the upper structure (105b) (or a metal structure (105m)). Accordingly, the self-luminous element (ED) can be automatically separated (or disconnected) by the first and second separation structures (105-1, 105-2) of the separation unit (105) during the deposition process, and thus a separate patterning process for separating (or disconnecting) the self-luminous element (ED) can be omitted. Accordingly, the self-luminous element (ED) placed on the substrate (100) is further separated (or disconnected) from the periphery of the dam unit (104) by the separation unit (105), and the lateral moisture permeability path of the substrate (100) can be further blocked by each of the first and second separation structures (105-1, 105-2) of the separation unit (105).

[0312] Additionally, the common electrode (CE) placed on the self-luminous element (ED) may be formed to be automatically separated (or severed) by the undercut area of ​​the separation part (105) in the same way as the self-luminous element (ED) during the deposition process according to the deposition method, or not separated by the undercut area of ​​the separation part (105), and to surround both the first and second separation structures (105-1, 105-2) and the island-shaped light-emitting element (EDi) separated by each of the first and second separation structures (105-1, 105-2).

[0313] Additionally, at least one metal structure (105m) of the first and second separation structures (105-1, 105-2) may be implemented to have an eaves structure for the lower structure (105a) and to block static electricity flowing from the outside into the inside of the display (AA). To this end, the metal structure (105m) of each of the first and second separation structures (105-1, 105-2) may be implemented to be electrically coupled to the pixel common voltage line (CVL). For example, as shown in FIGS. 8 and 12, a portion of the metal structure (105m) overlapping with the pixel common voltage line (CVL) may be electrically connected (or in contact) with the pixel common voltage line (CVL) through a via hole (105h) formed through the lower structure (105a) and the buffer layer (101a). Accordingly, the metal structure (105m) of each of the first and second separation structures (105-1, 105-2) is arranged in a closed-loop line shape that is continuously arranged on the edge portion of the substrate (100), thereby blocking static electricity flowing from the outside into the inside of the display portion (AA) and preventing defects caused by static electricity. For example, at least one metal structure (105m) of the first and second separation structures (105-1, 105-2) can prevent defects caused by static electricity by discharging static electricity flowing from the outside into the pixel common voltage line (CVL).

[0314] Referring to FIGS. 9, FIGS. 11, and FIGS. 12, a light-emitting display device (10) or substrate (100) according to one embodiment of the present specification may further include a groove line (GRV).

[0315] A groove line (GRV) can be implemented between the dam portion (104) and the leveling layer (102). The groove line (GRV) can be formed or implemented together with the dam portion (104).

[0316] The groove line (GRV) can be implemented by removing both the passivation layer (PAS) and the flattening layer (102) in the inner region of the dam portion (104). For example, the groove line (GRV) may be an area in which a single structure or a multilayer structure, such as one comprising at least one of the interlayer insulating layer (ILD), passivation layer (PAS), flattening layer (102), pixel electrode material layer, and bank (103), which are disposed on the buffer layer (101a) between the dam portion (104) and the bank (103), are all removed. For example, the groove line (GRV) may be formed or implemented by patterning (or removal) of the bank (103), flattening layer (102), passivation layer (PAS), and interlayer insulating layer (ILD), respectively, which are disposed in the first margin region (MA1) of the substrate (100) or the outermost pixel (Po). Accordingly, the groove line (GRV) defines or forms the side (102s) of the flattening layer (102) and can be implemented as a closed-loop line shape (or continuous line shape or closed-loop shape) surrounding the side (102s) of the flattening layer (102).

[0317] The groove line (GRV) can define or form sides (102s) of the flattening layer (102) and sides (PASs) of the passivation layer (PAS) and sides (ILDs) of the interlayer insulation layer (ILD) that are commonly placed on the inner pixel (Pi) and the outermost pixel (Po). For example, the groove line (GRV) can define or form ends (102e) of the flattening layer (102) and sides (PASs) of the passivation layer (PAS) and sides (ILDs) of the interlayer insulation layer (ILD) that are commonly placed on the inner pixel (Pi) and the outermost pixel (Po). For example, the side (102s) of the flattening layer (102), the side (PASs) of the passivation layer (PAS), and the side (ILDs) of the interlayer insulation layer (ILD) can each be exposed to the groove line (GRV) to form one side wall of the groove line (GRV).

[0318] The side end (102e) of the flattening layer (102) may protrude from the side (PASs) of the passivation layer (PAS) toward the center of the groove line (GRV) (or the dam portion (104)). For example, the distance between the side end (102e) of the flattening layer (102) and the outer surface (OS) of the substrate (100) may be smaller than the distance between the side (PASs) of the passivation layer (PAS) and the outer surface (OS) of the substrate (100). The distance between the side end (102e) of the flattening layer (102) and the side (PASs) of the passivation layer (PAS), or the distance between the side (PASs) of the passivation layer (PAS) and the side end (102e) of the flattening layer (102), may be greater than the combined thickness of the self-luminescent element (ED) and the common electrode (CE). Accordingly, the edge portion of the flattening layer (102), including the side (102s) and the side end (102e) of the flattening layer (102), can cover the side (PASs) of the passivation layer (PAS) and face directly with the upper surface of the buffer layer (101a). Thus, the edge portion of the flattening layer (102) can have an eaves structure with respect to the side (PASs) of the passivation layer (PAS).

[0319] The side (PASs) of the passivation layer (PAS) can be implemented as a slanted structure or a regular taper structure. Accordingly, the side (PASs) of the passivation layer (PAS) may have an undercut structure with respect to the edge portion of the flattening layer (102). For example, the boundary portion between the flattening layer (102) and the passivation layer (PAS) located on one side of the groove line (GRV), or the upper side of the passivation layer (PAS), may have an undercut structure with respect to the flattening layer (102). For example, due to the groove line (GRV), an undercut region may be formed between the side (PASs) of the passivation layer (PAS) adjacent to the groove line (GRV) and the side (102s) of the planarization layer (102) adjacent to the groove line (GRV), and the undercut region may be a structure for separating (or severing) at least some layer of the light-emitting element layer (EDL) placed on the groove line (GRV) from the edge portion of the planarization layer (102). For example, the undercut region between the side (PASs) of the passivation layer (PAS) and the side (102s) of the planarization layer (102) may be formed or formed by an over-etching process of the passivation layer (PAS). The side (102s) of the flattening layer (102) can cover the side (PASs) of the passivation layer (PAS) by protruding outside the side (PASs) of the passivation layer (PAS) through an undercut structure of the side (PASs) of the passivation layer (PAS). By doing so, the side (102s) of the flattening layer (102) can have an eaves structure with respect to the side (PASs) of the passivation layer (PAS).

[0320] According to one embodiment of the present specification, a material layer of a self-luminescent element (ED) placed on the edge portion of the planarization layer (102) and the groove line (GRV) can be automatically separated (or severed) during the deposition process by an undercut area (or eaves structure) between the side (102s) of the planarization layer (102) and the side (PASs) of the passivation layer (PAS). For example, since the deposition material of the self-emissive element (ED) has a linearity, it cannot be deposited on the side (PASs) of the passivation layer (PAS) which is obscured by the side (102s) of the planarization layer (102), and can be further separated (or severed) in the undercut area between the side (102s) of the planarization layer (102) and the side (PASs) of the groove line (GRV) by being deposited on the side (102s) of the planarization layer (102).

[0321] Additionally, the common electrode (CE) placed on the self-luminous element (ED) may be formed to cover all of the side (102s) of the planarization layer (102), the side (PASs) of the passivation layer (PAS), and the buffer layer (101a) of the groove line (GRV) without being separated by an undercut area between the side (102s) of the planarization layer (102) and the side (PASs) of the passivation layer (PAS) during the deposition process according to the deposition method, just like the self-luminous element (ED).

[0322] According to one embodiment of the present specification, a pad portion (110) of a substrate (100) is disposed (or included) inside the outermost pixel (Po), and a routing portion (400) electrically coupled to the pad portion (110) is formed on the side of the substrate (100), thereby enabling the implementation of a light-emitting display device having an air bezel structure with no bezel area or a zeroed bezel. According to one embodiment of the present specification, an electrical short circuit between routing lines can be easily detected, and by controlling the switching of each of a plurality of switching circuit portions (170) arranged to overlap with the dam portion (104) through a metal line (104m) embedded in the dam portion (104), the line resistance of the routing lines is sensed, and the resistance deviation of the routing lines is compensated, thereby preventing or minimizing image quality defects caused by the resistance deviation of the routing lines. In addition, according to one embodiment of the present specification, the self-luminous element (ED) is separated by an undercut structure of the dam portion (104), thereby preventing a decrease in the reliability of the self-luminous element (ED) due to lateral moisture penetration. In addition, according to one embodiment of the present specification, the self-luminous element (ED) is further separated at least twice by an undercut area and a groove line (GRV) implemented in the separation structure (105-1, 105-2) of the separation portion (105) disposed around the dam portion (104), and by an undercut area implemented between the side (102s) of the flattening layer (102) and the side (PASs) of the passivation layer (PAS), thereby further preventing a decrease in the reliability of the self-luminous element (ED) due to lateral moisture penetration. And, according to one embodiment of the present specification, a pixel circuit placed in the outermost pixel can be protected from static electricity by including a metal structure placed in the separation structure (105-1, 105-2) and / or a metal line (104m) embedded in the dam part (104).

[0323] FIG. 13 is a drawing for explaining the first and second pad portions and routing portions according to another embodiment of the present specification.

[0324] Referring to FIG. 13, a first pad portion (110) according to another embodiment of the present specification may include a first pad group (PG1), a second pad group (PG2), and a plurality of first to third front sensing control pads (112a, 112b, 112c).

[0325] The first pad group (PG1) and the second pad group (PG2) of the first pad section (110) may be arranged alternately along the first direction (X). Since the first pad group (PG1) and the second pad group (PG2) of the first pad section (110) are the same as those described in FIG. 4, a redundant description thereof is omitted.

[0326] Each of the plurality of first to third front sensing control pads (112a, 112b, 112c) may be positioned between at least two pad groups (PG1, PG2). For example, each of the plurality of first to third front sensing control pads (112a, 112b, 112c) may be positioned one between each of the first and second pad groups (PG1, PG2).

[0327] The second pad section (210) may include a first pad group (PG1), a second pad group (PG2), and a plurality of first to third rear sensing control pads (212a, 212b, 212c).

[0328] The first pad group (PG1) and the second pad group (PG2) of the second pad section (210) can be arranged alternately along the first direction (X).

[0329] The first pad group (PG1) of the second pad section (210) may include a second pixel driving power pad (PPP2), a second data pad (DP2), a second reference power pad (RVP2), a second data pad (DP2), and a second pixel common voltage pad (CVP2) that overlap one-to-one with each of the first pixel driving power pad (PPP1), the first data pad (DP1), the first reference power pad (RVP1), the first data pad (DP1), and the first pixel common voltage pad (CVP1) disposed in the first pad group (PG1) of the first pad section (110).

[0330] The second pad group (PG2) of the second pad section (210) may include a second gate pad, a second data pad (DP2), a second reference power pad (RVP2), a second data pad (DP2), and a second pixel driving power pad (PPP2) that overlap one-to-one with each of the first gate pad, the first data pad (DP1), the first reference power pad (RVP1), the first data pad (DP1), and the first pixel driving power pad (PPP1) disposed in the second pad group (PG2) of the first pad section (110).

[0331] Each of the plurality of first to third rear sensing control pads (212a, 212b, 212c) may be positioned between at least two pad groups (PG1, PG2). For example, each of the plurality of first to third rear sensing control pads (212a, 212b, 212c) may be positioned one between each of the first and second pad groups (PG1, PG2).

[0332] A plurality of first rear sensing control pads (212a) may be commonly connected to or connected in parallel to the first sensing control link line (252a) of the link line section (250). A plurality of second rear sensing control pads (212b) may be commonly connected to or connected in parallel to the second sensing control link line (252b) of the link line section (250). A plurality of third rear sensing control pads (212c) may be commonly connected to or connected in parallel to the third sensing control link line (252c) of the link line section (250).

[0333] The routing unit (400) may include a plurality of routing lines (410) and a plurality of first to third sensing control routing lines (412a, 412b, 412c).

[0334] Each of the plurality of routing lines (410) can be formed to be connected one-to-one to each of the pads (PPP1, DP1, RVP1, CVP1) placed in the first pad group (PG1) and the second pad group (PG2) of the first pad section (110) and each of the pads (PPP2, DP2, RVP2, CVP2) placed in the first pad group (PG1) and the second pad group (PG2) of the second pad section (210).

[0335] Each of the plurality of first sensing control routing lines (412a) may be formed to be connected one-to-one to each of the plurality of first front sensing control pads (112a) and each of the plurality of first rear sensing control pads (212a). Each of the plurality of second sensing control routing lines (412b) may be formed to be connected one-to-one to each of the plurality of second front sensing control pads (112b) and each of the plurality of second rear sensing control pads (212b). Each of the plurality of third sensing control routing lines (412c) may be formed to be connected one-to-one to each of the plurality of third front sensing control pads (112c) and each of the plurality of third rear sensing control pads (212c).

[0336] According to another embodiment of the present specification, the first to third sensing control routing lines (412a, 412b, 412c) are each configured in a plurality to have a parallel connection structure, so that even if a line failure occurs in some of the lines among the plurality of parallel-connected sensing control routing lines, a switching control signal can be supplied through the remaining lines.

[0337] FIG. 14 is a plan view showing a light-emitting display device according to another embodiment of the present specification, and FIG. 15 is a rear view showing a light-emitting display device according to another embodiment of the present specification. FIG. 14 and FIG. 15 additionally configure an auxiliary pad portion in the light-emitting display device illustrated in FIG. 1 to FIG. 13. Accordingly, in the following description, the same reference numerals are assigned to the remaining components excluding the auxiliary pad portion and related components, and redundant descriptions thereof are omitted.

[0338] Referring to FIGS. 14 and 15, a light-emitting display device (10) according to another embodiment of the present specification may further include a front auxiliary pad portion (1110), a rear auxiliary pad portion (1110), and an auxiliary link line portion (1250).

[0339] The front auxiliary pad portion (1110) may be disposed on a second edge portion (or other edge portion) parallel to the first edge portion of the substrate (100). The front auxiliary pad portion (1110) may include at least one front auxiliary pad (1112a, 1112b, 1112c). For example, the front auxiliary pad portion (1110) may include a plurality of first to third front auxiliary pads (1112a, 1112b, 1112c) spaced apart from each other along a first direction (X).

[0340] Each of the plurality of first to third front auxiliary pads (1112a, 1112b, 1112c) may be configured to be electrically connected to a metal line (104m) of a dam portion (104) disposed on the second edge portion of the substrate (100). Since each of these plurality of first to third front auxiliary pads (1112a, 1112b, 1112c) is configured to have substantially the same structure as each of the first to third front sensing control pads (112a, 112b, 112c) disposed on the first pad portion (110), except that they are disposed on the second edge portion of the substrate (100), a description thereof is omitted.

[0341] The rear auxiliary pad portion (1210) may be positioned on the rear side of the wiring board (100) so as to overlap with the front auxiliary pad portion (1110). The rear auxiliary pad portion (1210) may include at least one rear auxiliary pad (1212a, 1212b, 1212c) that overlaps with at least one front auxiliary pad (1112a, 1112b, 1112c) positioned on the front auxiliary pad portion (1110). For example, the rear auxiliary pad portion (1210) may include a plurality of first to third rear auxiliary pads (1212a, 1212b, 1212c) positioned on the rear side of the wiring board (100) so as to overlap one-to-one with each of the plurality of first to third front auxiliary pads (1112a, 1112b, 1112c) positioned on the front auxiliary pad portion (1110). Each of these multiple first to third rear auxiliary pads (1212a, 1212b, 1212c) is configured to have a structure substantially identical to each of the first to third rear sensing control pads (212a, 212b, 212c) disposed on the second pad portion (210), except that they are disposed on the second edge portion of the wiring board (200), so a description thereof is omitted.

[0342] The auxiliary link line section (1250) may be positioned between the rear auxiliary pad section (1210) and at least one third pad section (230). The auxiliary link line section (1250) may include at least one auxiliary link line (1252a, 1252b, 1252c) electrically coupled to at least one rear auxiliary pad (1212a, 1212b, 1212c). For example, the auxiliary link line section (1250) may include first to third auxiliary link lines (1252a, 1252b, 1252c).

[0343] The first auxiliary link line (1252a) may be connected in common or in parallel with a plurality of first rear auxiliary pads (1212a) and may be connected to a first switching control signal pad placed in at least one third pad section (250).

[0344] The second auxiliary link line (1252b) may be connected in common or in parallel with a plurality of second rear auxiliary pads (1212b) and may be connected to a second switching control signal pad placed in at least one third pad section (250).

[0345] The third auxiliary link line (1252c) is connected in common or in parallel with a plurality of third rear auxiliary pads (1212c) and can be connected to a third switching control signal pad placed in at least one third pad section (250).

[0346] A light-emitting display device (10) according to another embodiment of the present specification may further include an auxiliary routing unit.

[0347] The auxiliary routing section may include a plurality of auxiliary routing lines arranged to surround the second outer surface (OS2) of the substrate (100) and the wiring board (200).

[0348] Each of the plurality of auxiliary routing lines may be individually (or one-to-one) connected (or combined) to each of the plurality of first to third front auxiliary pads (1112a, 1112b, 1112c) and each of the plurality of first to third rear auxiliary pads (1212a, 1212b, 1212c). Since each of these plurality of auxiliary routing lines is configured to have a structure substantially identical to each of the plurality of sensing control routing lines (412a, 412b, 412c), except that they are arranged to wrap around the second outer surface (OS2) of the substrate (100) and the wiring board (200), a description thereof is omitted.

[0349] According to another embodiment of the present specification, a switching control signal can be additionally supplied to a metal line (104m) placed in a dam (104) through an auxiliary link line section (1250), a rear auxiliary pad section (1110), an auxiliary routing section, and a front auxiliary pad section (1110).

[0350] Alternatively, according to another embodiment of the present specification, the metal line (104m) placed in the dam portion (104) has a closed-loop line shape that is continuously connected without interruption on the substrate (100) in a planar manner, so that a switching control signal can be supplied to the metal line (104m) placed in the dam portion (104) through the front auxiliary pad portion (1110) without front sensing control pads (112a, 112b, 112c). Accordingly, when a light-emitting display device according to another embodiment of the present specification includes an auxiliary link line section (1250), a rear auxiliary pad section (1110), an auxiliary routing section, and a front auxiliary pad section (1110), the front sensing control pads (112a, 112b, 112c), the rear sensing control pads (212a, 212b, 212c), the sensing control routing lines (412a, 412b, 412c), and the sensing control link lines (252a, 252b, 252c) may each be omitted. In this case, since the number of pads of the first pad section (110) is reduced, the design of pixels for high resolution may be easy.

[0351] FIG. 16 is a schematic diagram showing a switching circuit, a driving integrated circuit, and a timing controller according to one embodiment of the present specification, which is a diagram for explaining the sensing of a short circuit of a routing line or a line resistance of a routing line through the switching circuit.

[0352] Referring to FIG. 16, a driving integrated circuit (530) according to one embodiment of the present specification may include a data driving unit (531), a sensing unit (533), and a line selection unit (535).

[0353] The data driving unit (531) receives subpixel data and a data control signal provided by the timing controller (570), and can convert the subpixel data into an analog data signal according to the data control signal and output it. For example, in inspection mode, the data driving unit (531) can convert inspection data from the timing controller (570) into an analog inspection data signal and output it.

[0354] A data driving unit (531) according to one embodiment of the present specification may include a data signal generating unit (531a) and a plurality of signal output circuits (531o, 531e).

[0355] The data signal generation unit (531a) may be configured to convert pixel data or inspection data provided from the timing controller (570) into an analog data signal and output it.

[0356] Each of the plurality of signal output circuits (531o, 531e) can be connected to data lines (DLo, DLe) through a data link line, a second data pad (DP2) of the second pad section, a data routing line, and a first data pad (DP1) of the first pad section. Each of the plurality of signal output circuits (531o, 531e) can buffer a data signal output from a data signal generation section (531a) and output it to the corresponding data lines (DLo, DLe). For example, each of the plurality of signal output circuits (531o, 531e) may be an output buffer and may be implemented as a differential amplifier, etc. For example, each of the plurality of signal output circuits (531o, 531e) may be a voltage follower in which the output voltage is fed back to an input terminal. The static current of each of the plurality of signal output circuits (531o, 531e) can be varied (or changed) according to a current option value (or amplifier current option value or bias voltage level) supplied to the bias terminal. For example, the static current of each of the plurality of signal output circuits (531o, 531e) can be increased or decreased according to a bias voltage level supplied to the bias terminal.

[0357] The sensing unit (533) can be optionally connected to the reference line (RL) through the data link line, the second reference voltage pad (RVP2) of the second pad unit, the reference routing line, and the first reference voltage pad (RVP1) of the first pad unit. The sensing unit (533) can be configured to convert a sensing value corresponding to a current (or test signal) input through the reference line (RL) into sensing data and provide it to the timing controller (570). For example, the sensing unit (533) can generate sensing data by converting the sensing voltage corresponding to the current (or test signal) input through the reference line (RL) into analog-to-digital, and provide the sensed sensing data to the timing controller (570).

[0358] The sensing unit (533) may be configured with a number equal to the number of reference lines disposed on the substrate (100). A sensing unit (533) according to one embodiment of the present specification may include a plurality of sensing circuits and a plurality of analog-to-digital converters.

[0359] Each of the plurality of sensing circuits may be composed of an integrator including an operational amplifier and a capacitor. For example, the operational amplifier of the sensing circuit may include an inverting input terminal (-) optionally connected to a reference line (RL), a non-inverting input terminal (+) to which a reference voltage is supplied, and an output terminal connected to an analog-to-digital converter. The capacitor may be a feedback capacitor connected between the inverting input terminal (-) and the output terminal of the operational amplifier. Additionally, each of the plurality of sensing circuits may further include a feedback switch (or reset switch) connected between the inverting input terminal (-) and the output terminal of the operational amplifier. The current flowing through the feedback capacitor may be the same as the current flowing through the reference line (RL).

[0360] Each of the plurality of analog-to-digital converters can generate sensing data by converting the output voltage (or sensing voltage) of the corresponding sensing circuit among the plurality of sensing circuits from analog to digital and provide the generated sensing data to the timing controller (570). For example, each of the plurality of analog-to-digital converters can generate sensing data by converting the output voltage (or sensing voltage) of the corresponding sensing circuit, based on the current flowing through the feedback capacitor of the corresponding sensing circuit, from analog to digital.

[0361] The line selection unit (535) may be configured to connect a data link line connected to an even-numbered data line (DLe) to a sensing unit (533) or to a signal output circuit (531o, 531e) according to a line selection signal provided from the timing controller (570). For example, the line selection unit (535) may be a multiplexer.

[0362] The timing controller (570) can generate first to third switching control signals in inspection mode to control the switching of each of the first to third switch circuits (171, 172, 173) of the switching circuit unit (170), and can generate inspection data and line selection signals and provide them to the data driving unit (531). In inspection mode, the timing controller (570) can determine whether there is a short circuit in the routing line and the location of the short circuit defect based on line-by-line sensing data provided from the sensing unit (533) of the driving integrated circuit (530), and can display the determination result on a separate monitor. Additionally, the timing controller (570) can generate a line-by-line resistance compensation value to compensate for resistance deviations between multiple data routings based on line-by-line resistance sensing data provided from the sensing unit (533) of the driving integrated circuit (530) in the inspection mode, and generate a bias voltage corresponding to the line-by-line resistance compensation value and supply it to the bias terminal of the corresponding signal output circuit (531o, 531e) of the driving integrated circuit (530). Accordingly, the signal output circuit (531o, 531e) can output a data signal in which the resistance compensation value is compensated according to the bias voltage level.

[0363] According to one embodiment of the present specification, since the current flowing through the routing line and the current flowing through the padback capacitor of the sensing circuit are the same, the timing controller (570) can calculate the line resistance according to the sensing voltage corresponding to the resistance sensing data, the current flowing through the routing line (Current 1), and the current flowing through the padback capacitor (Cf) of the sensing circuit (Current 2), as shown in Equation 1 below.

[0364] [Equation 1]

[0365] Current 1=(Vdata-Vinv) / R

[0366] Current 2=Cf(Vinv-Vsen) / ΔTsen

[0367] Current 1=Current 2, (Vdata-Vinv) / R=Cf(Vinv-Vsen) / Δtsen

[0368] R=(ΔTsen×(Vdata-Vinv)) / Cf(Vinv-Vsen)

[0369] In Equation 1, Vdata represents the voltage level of the check signal, Cf represents the capacitance of the feedback capacitor, Vinv represents the voltage level of the inverting terminal (-) of the operational amplifier, Vsen represents the sensing voltage (or output voltage of the sensing circuit) corresponding to the resistance sensing data, and Δtsen represents the time during which current flows. Vinv has a voltage level equal to the reference voltage applied to the non-inverting terminal (+) when the feedback switch of the sensing circuit is turned on. For example, when the feedback switch of the sensing circuit is turned on and the gain value (or gain value) of the operational amplifier is infinite, Vinv has a voltage level equal to the voltage level of the non-inverting terminal (+). In Equation 1, the voltage level of the check signal (Vdata), the capacitance of the feedback capacitor (Cf), the time during which current flows (Δtsen), and the voltage level of the inverting terminal of the operational amplifier (Vinv) are each constants. Accordingly, the timing controller (570) can calculate a sensing voltage (Vsen) corresponding to the resistance sensing data and calculate the line resistance of the routing line through the operation of Equation 1. For example, the timing controller (570) can calculate the line resistance of the routing line based on Equation 1 when the feedback switch is turned on and current flows through the feedback capacitor (Cf) in the sensing circuit.

[0370] Optionally, the timing controller (570) may not generate a bias voltage corresponding to the line-by-line resistance compensation value, but may provide the line-by-line resistance compensation value to the driving integrated circuit (530). In this case, the driving integrated circuit (530) may further include a bias voltage generating unit (537). The bias voltage generating unit (537) may generate a line-by-line bias voltage corresponding to each line-by-line resistance compensation value supplied from the timing controller (570), and supply the generated line-by-line bias voltage to the bias terminals of the corresponding signal output circuits (531o, 531e).

[0371] Additionally, the driving integrated circuit (530) or driving circuit section (500) according to one embodiment of the present specification may further include a voltage selection section (539).

[0372] The voltage selection unit (539) can select and output either the switching control signal supplied from the timing controller (570) or the ground voltage according to the voltage selection signal of the timing controller (570).

[0373] The voltage selection unit (539) can output each of the first to third switching control signals supplied from the timing controller (570) according to the voltage selection signal of the first voltage level supplied from the timing controller (570) in the inspection mode, and accordingly, each of the first to third switch circuits (171, 172, 173) of the switching circuit unit (170) can be switched according to the corresponding switching control signal supplied from the voltage selection unit (539) through each of the first to third front sensing control pads (112a, 112b, 112c).

[0374] The voltage selection unit (539) can output a ground voltage (GND) supplied from the timing controller (570) according to a voltage selection signal of a second voltage level supplied from the timing controller (570) in a non-test mode or normal driving mode, and thereby each of the first to third switch circuits (171, 172, 173) of the switching circuit unit (170) is kept off by the ground voltage (GND) supplied from the voltage selection unit (539) through the first to third front sensing control pads (112a, 112b, 112c) and the metal line (104m) of the dam unit, and the metal line (104m) of the dam unit is kept at the ground voltage (GND) and can be used as an electrostatic protection line or an electrostatic cutoff line.

[0375] A driving method for inspecting a short circuit in a routing line in a light-emitting display device according to one embodiment of the present specification is described as follows.

[0376] First, each of the first to third switching control signals having a first logic level (or gate off voltage level) is output from the timing controller (570), and thereby each of the first to third switch circuits (171, 172, 173) of the switching circuit section (170) is turned off.

[0377] Next, a test data signal is supplied from the driving integrated circuit (530) to the data lines (DLo, DLe), and the sensing unit (533) of the driving integrated circuit (530) senses the current input through the reference line (RL) and the line selection unit (535) and outputs line sensing data.

[0378] Next, the timing controller (570) determines whether there is a short circuit between routing lines based on line sensing data. For example, if a short circuit occurs between adjacent reference lines (RL) and data lines (DLo, DLe), the current flowing through the data lines (DLo, DLe) flows to the reference lines (RL) through the short circuit portion, and the current flowing through the reference lines (RL) is sensed to detect whether there is a short circuit between the lines. For example, the timing controller (570) can determine that a short circuit has occurred between routing lines if the line sensing data is greater than or equal to a reference threshold voltage value.

[0379] Accordingly, according to one embodiment of the present specification, a short circuit defect between a plurality of routing lines can be detected by turning off the first to third switching circuits (171, 172, 173) of each of the plurality of switching circuits (170), supplying a test signal to each of the plurality of data lines (DLo, DLe), and sensing the current flowing through each of the plurality of reference lines (RL).

[0380] A driving method for sensing the line resistance of a routing line in a light-emitting display device according to one embodiment of the present specification is described as follows.

[0381] First, during the first inspection period of the inspection mode, the line resistance values ​​of the odd-numbered data routing lines and reference routing lines can be sensed. According to one embodiment of the present specification, a first switching control signal having a second logic level (or gate-on voltage level) and second and third switching control signals of the first logic level are output from the driving integrated circuit (530), thereby turning on the first switch circuit (171) of the switching circuit section (170) and turning off the second and third switch circuits (172, 173) of the switching circuit section (170), respectively. Subsequently, a test data signal from the driving integrated circuit (530) is supplied to the odd-numbered data line (DLo), and thereby the sensing unit (533) of the driving integrated circuit (530) senses the current input through the line selection unit (535) and the first current path (CP1) which includes the odd-numbered data line (DLo), the first switch circuit (171), and the reference line (RL), and generates resistance sensing data. Subsequently, the timing controller (570) can generate line resistance values ​​of the odd-numbered data routing line and the reference routing line based on the resistance sensing data and store them in the storage circuit.

[0382] Next, during the second inspection period of the inspection mode, the line resistance values ​​of the even-numbered data routing lines and reference routing lines can be sensed. According to one embodiment of the present specification, a second switching control signal having a second logic level and first and third switching control signals having a first logic level are output from the driving integrated circuit (530), thereby turning on the second switch circuit (172) of the switching circuit section (170) and turning off the first and third switch circuits (171, 173) of the switching circuit section (170), respectively. Subsequently, a test data signal from the driving integrated circuit (530) is supplied to the even-numbered data line (DLe), and thereby the sensing unit (533) of the driving integrated circuit (530) senses the current input through the line selection unit (535) and the second current path (CP2) which includes the even-numbered data line (DLe), the second switch circuit (172), and the reference line (RL), thereby generating resistance sensing data. Subsequently, the timing controller (570) can generate line resistance values ​​of the even-numbered data routing line and the reference routing line based on the resistance sensing data and store them in the storage circuit.

[0383] Next, during the third inspection period of the inspection mode, the line resistance values ​​of the odd-numbered data routing lines and the even-numbered data routing lines can be sensed. According to one embodiment of the present specification, a third switching control signal having a second logic level and first and second switching control signals having a first logic level are output from the driving integrated circuit (530), thereby turning on the third switch circuit (173) of the switching circuit unit (170) and turning off the first and second switch circuits (171, 172) of the switching circuit unit (170), respectively. Subsequently, a test data signal from the driving integrated circuit (530) is supplied to the odd-numbered data line (DLo), and thereby the sensing unit (533) of the driving integrated circuit (530) senses the current input through the line selection unit (535) and the third current path (CP3) which includes the odd-numbered data line (DLo), the third switch circuit (173), and the even-numbered data line (DLe), thereby generating resistance sensing data. Subsequently, the timing controller (570) can generate line resistance values ​​for the odd-numbered data routing line and the even-numbered data routing line based on the resistance sensing data and store them in the storage circuit.

[0384] Next, the timing controller (570) can generate line resistance values ​​for odd-numbered data routing lines and even-numbered data routing lines, and additionally generate line resistance values ​​for reference routing lines, based on line resistance values ​​generated in each of the first to third inspection periods, through the operation of Equation 2 below.

[0385] [Equation 2]

[0386] Rl+R3=Rsum1, R2+R3=Rsum2, R1+R2=Rsum3

[0387] Rsum1+Rsum2+Rsum3=Rtot, 2(R1+R2+R3)=Rtot, R1+R2+R3=Rtot / 2

[0388] R1=(Rtot / 2)-Rsum2, R2=(Rtot / 2)-Rsum1, R3=(Rtot / 2)-Rsum3

[0389] In Equation 2, R1 represents the line resistance value of the odd-numbered data routing line, R2 represents the line resistance value of the even-numbered data routing line, and R3 represents the line resistance value of the reference routing line. Also, Rsum1 represents the line resistance value of the odd-numbered data routing line and the reference routing line generated in the first inspection period, Rsum2 represents the line resistance value of the even-numbered data routing line and the reference routing line generated in the second inspection period, and Rsum3 represents the line resistance value of the odd-numbered data routing line and the even-numbered data routing line generated in the third inspection period.

[0390] Next, the timing controller (570) calculates a line-specific resistance compensation value to compensate for line-specific resistance deviations based on line-specific resistance values, and stores the line-specific resistance compensation value in the form of a look-up table in the storage circuit. In one embodiment of the present specification, the timing controller (570) modulates pixel data to be supplied to each of the plurality of data lines according to the resistance compensation value of each of the plurality of data routing lines stored in the storage circuit, and can provide the modulated pixel data to the driving integrated circuit (530). In another embodiment of the present specification, the timing controller (570) sets a current option value (or bias voltage level) for each of the plurality of signal output circuits (531o, 531e) corresponding to each of the plurality of data lines according to the resistance compensation value of each of the plurality of data routing lines stored in the storage circuit, stores it in the storage circuit, and supplies the current option value stored in the storage circuit to the corresponding signal output circuits (531o, 531e). Accordingly, each of the plurality of signal output circuits (531o, 531e) can output a data signal in which the resistance value of the corresponding data routing line is compensated according to the bias voltage level corresponding to the current option value supplied from the timing controller (570), and thereby the resistance deviation between the line resistance values ​​of each of the plurality of data routing lines can be compensated.

[0391] Accordingly, according to another embodiment of the present specification, the first to third switching circuits (171, 172, 173) of each of the plurality of switching circuit sections (170) can be selectively turned on, and the line resistance of each of the plurality of data routing lines can be detected by selectively supplying a test signal to each of the plurality of data lines (DLo, DLe) and sensing the current flowing through the reference line (RL), and the resistance deviation between the line resistance values ​​of each of the plurality of data routing lines can be compensated.

[0392] FIG. 17 is a drawing for explaining a plurality of switching circuits according to another embodiment of the present specification, and FIG. 18 is a cross-sectional view along line III-III' shown in FIG. 17. FIG. 17 and FIG. 18 are modified versions of the damper and the plurality of switching circuits in the light-emitting display device described in FIG. 1 to FIG. 16. Accordingly, in the following description, the same reference numerals are assigned to the remaining components, excluding the damper, the plurality of switching circuits, and the components related thereto, and redundant descriptions thereof are omitted or simplified.

[0393] Referring to FIGS. 17 and 18, a dam portion (104) according to another embodiment of the present specification may include a first and second dam (104-1, 104-2).

[0394] Each of the first and second dams (104-1, 104-2) may include a metal line (104m). The metal line (104m) may be embedded or implemented inside the dam section (104) to have a closed-loop line shape (or a continuous line shape or a closed-loop shape) identical to the dam section (104) in planar form. Since the dam section (104) is configured to have a structure substantially identical to the dam section (104) described in FIGS. 1 through 12, except for having the first and second dams (104-1, 104-2), a description thereof is omitted.

[0395] The separation section (105) may include a first separation structure (105-1) disposed between the first and second dams (104-1, 104-2), and second and third separation structures (105-2, 105-3) disposed in the inner region of the second dam (104-2). Since this separation section (105) is configured to have substantially the same structure as the separation section (105) described in FIGS. 1 to 13, except that it further includes a third separation structure (105-3), a description thereof is omitted.

[0396] Additionally, each metal structure of the first to third separation structures (105-1, 105-2, 105-3) can be electrically connected (or contacted) with the pixel common voltage line (CVL) through the via hole (105h).

[0397] The first pad section (110) may include first and second front sensing control pads (112a, 112b) and first and second pad connection lines (176, 177). Since this first pad section (110) has a configuration in which the third front sensing control pad (112c) and the third pad connection line are omitted from the pad section (110) described in FIGS. 1 to 13, a redundant description thereof is omitted.

[0398] Each of the plurality of switching circuit sections (170) according to one embodiment of the present specification may include a first and second switching circuit (171, 172).

[0399] The first and second switching circuits (171, 172) may be arranged to overlap individually with the first and second dams (104-1, 104-2). For example, the first switching circuit (171) may overlap with the first dam (104-1) or be placed below the first dam (104-1). The second switching circuit (172) may overlap with the second dam (104-2) or be placed below the second dam (104-2). Since each of these first and second switching circuits (171, 172) is substantially identical to the first and second switching circuits (171, 172) described in FIGS. 1 through 13, a redundant description thereof is omitted.

[0400] Additionally, the front auxiliary pad portion (1110), the rear auxiliary pad portion (1110), and the auxiliary link line portion (1250) described in FIGS. 14 and 15, respectively, can be applied to the embodiments illustrated in FIGS. 17 and 18.

[0401] According to another embodiment of the present specification as such, it can have the same effect as the light-emitting display device described in FIGS. 1 to 16, and as the area occupied by the damper (104) is reduced compared to the light-emitting display device described in FIGS. 1 to 16, the design of the pixel for high resolution can be made easier.

[0402] FIG. 19 is a schematic diagram showing a switching circuit, a driving integrated circuit, and a timing controller according to another embodiment of the present specification, which is a diagram for explaining the sensing of a short circuit of a routing line or a line resistance of a routing line through the switching circuit.

[0403] Referring to FIGS. 17 through 19, a driving integrated circuit (530) according to another embodiment of the present specification may include a data driving unit (531), a sensing unit (533), and a line selection unit (535). Since the driving integrated circuit (530) including such a configuration is substantially the same as the driving integrated circuit (530) described in FIG. 16, except that it is configured to output first and second switching control signals supplied from a timing controller (570) in a test mode, a redundant description thereof is omitted.

[0404] The timing controller (570) can generate first and second switching control signals in a test mode to control the switching of each of the first and second switch circuits (171, 172) of the switching circuit unit (170), and generate test data and line selection signals to provide to the data driving unit (531). Since this timing controller (570) is substantially the same as the timing controller (570) described in FIG. 16 except that it generates first and second switching control signals in a test mode to control the switching of each of the first and second switch circuits (171, 172) of the switching circuit unit (170), a redundant description thereof is omitted.

[0405] Optionally, the timing controller (570) may not generate a bias voltage corresponding to the line-by-line resistance compensation value, but may provide the line-by-line resistance compensation value to the driving integrated circuit (530). In this case, the driving integrated circuit (530) may further include a bias voltage generating unit (537). The bias voltage generating unit (537) may generate a line-by-line bias voltage corresponding to each line-by-line resistance compensation value supplied from the timing controller (570), and supply the generated line-by-line bias voltage to the bias terminals of the corresponding signal output circuits (531o, 531e).

[0406] Additionally, a driving integrated circuit (530) or a driving circuit part (500) according to another embodiment of the present specification may further include a voltage selection part (539).

[0407] The voltage selection unit (539) can select and output either the switching control signal supplied from the timing controller (570) or the ground voltage according to the voltage selection signal of the timing controller (570).

[0408] The voltage selection unit (539) can output each of the first and second switching control signals supplied from the timing controller (570) according to the voltage selection signal of the first logic level supplied from the timing controller (570) in the inspection mode, and thereby each of the first and second switch circuits (171, 172) of the switching circuit unit (170) can be switched according to the corresponding switching control signal supplied from the voltage selection unit (539) through the first and second front sensing control pads (112a, 112b), respectively.

[0409] The voltage selection unit (539) can output a ground voltage (GND) supplied from the timing controller (570) according to a voltage selection signal of a second logic level supplied from the timing controller (570) in a non-test mode or normal driving mode, and thereby each of the first and second switch circuits (171, 172) of the switching circuit unit (170) is kept off by the ground voltage (GND) supplied from the voltage selection unit (539) through the first and second front sensing control pads (112a, 112b) and the metal line (104m) of the dam unit, and the metal line (104m) of the dam unit is kept at the ground voltage (GND) and can be used as an electrostatic protection line or an electrostatic cutoff line.

[0410] A driving method for inspecting a short circuit in a routing line in a light-emitting display device according to one embodiment of the present specification is described as follows.

[0411] First, each of the first and second switching control signals having a first logic level is output from the timing controller (570), and thereby the first and second switch circuits (171, 172) of the switching circuit section (170) are each turned off.

[0412] Next, a test data signal is supplied from the driving integrated circuit (530) to the data lines (DLo, DLe), and the sensing unit (533) of the driving integrated circuit (530) senses the current input through the reference line (RL) and the line selection unit (535) and outputs line sensing data.

[0413] Next, the timing controller (570) determines whether there is a short circuit between routing lines based on line sensing data. For example, if a short circuit occurs between adjacent reference lines (RL) and data lines (DLo, DLe), the current flowing through the data lines (DLo, DLe) flows to the reference lines (RL) through the short circuit portion, and the current flowing through the reference lines (RL) is sensed to detect whether there is a short circuit between the lines. For example, the timing controller (570) can determine that a short circuit has occurred between routing lines if the line sensing data is greater than or equal to a reference threshold voltage value.

[0414] Accordingly, according to one embodiment of the present specification, a short circuit defect between a plurality of routing lines can be detected by turning off the first and second switching circuits (171, 172) of each of the plurality of switching circuits (170), supplying a test signal to each of the plurality of data lines (DLo, DLe), and sensing the current flowing through each of the plurality of reference lines (RL).

[0415] A driving method for sensing the line resistance of a routing line in a light-emitting display device according to another embodiment of the present specification is described as follows.

[0416] First, during the first inspection period of the inspection mode, the line resistance values ​​of the odd-numbered data routing lines and reference routing lines can be sensed. According to one embodiment of the present specification, a first switching control signal having a second logic level and a second switching control signal of the first logic level are output from the driving integrated circuit (530), and thereby the first switch circuit (171) of the switching circuit unit (170) is turned on and the second switch circuit (172) of the switching circuit unit (170) is turned off. Subsequently, a test data signal from the driving integrated circuit (530) is supplied to the odd-numbered data line (DLo), and thereby the sensing unit (533) of the driving integrated circuit (530) senses the current input through the line selection unit (535) and the first current path (CP1) which includes the odd-numbered data line (DLo), the first switch circuit (171), and the reference line (RL), and generates resistance sensing data. Subsequently, the timing controller (570) can generate line resistance values ​​of the odd-numbered data routing line and the reference routing line based on the resistance sensing data and store them in the storage circuit.

[0417] Next, during the second inspection period of the inspection mode, the line resistance values ​​of the even-numbered data routing lines and reference routing lines can be sensed. According to one embodiment of the present specification, a second switching control signal having a second logic level and a first switching control signal having a first logic level are output from the driving integrated circuit (530), thereby turning on the second switch circuit (172) of the switching circuit unit (170) and turning off the first switch circuit (171) of the switching circuit unit (170). Subsequently, a test data signal from the driving integrated circuit (530) is supplied to the even-numbered data line (DLe), and thereby the sensing unit (533) of the driving integrated circuit (530) senses the current input through the line selection unit (535) and the second current path (CP2) which includes the even-numbered data line (DLe), the second switch circuit (172), and the reference line (RL), thereby generating resistance sensing data. Subsequently, the timing controller (570) can generate line resistance values ​​of the even-numbered data routing line and the reference routing line based on the resistance sensing data and store them in the storage circuit.

[0418] Next, during the third inspection period of the inspection mode, the line resistance values ​​of the odd-numbered data routing lines and even-numbered data routing lines can be sensed. According to one embodiment of the present specification, first and second switching control signals of a second logic level are output from the driving integrated circuit (530), and thereby the first and second switch circuits (171, 172) of the switching circuit unit (170) are each turned on. Subsequently, an inspection data signal is supplied from the driving integrated circuit (530) to the odd-numbered data line (DLo), and thereby the sensing unit (533) of the driving integrated circuit (530) senses the current input through the line selection unit (535) and the third current path (CP3) which includes the odd-numbered data line (DLo), the first and second switch circuits (171, 172), and the even-numbered data line (DLe), thereby generating resistance sensing data. Next, the timing controller (570) can generate line resistance values ​​for odd-numbered data routing lines and even-numbered data routing lines based on resistance sensing data and store them in a storage circuit.

[0419] Next, the timing controller (570) can generate line resistance values ​​for odd-numbered data routing lines and even-numbered data routing lines, and additionally generate line resistance values ​​for reference routing lines, based on line resistance values ​​generated in each of the first to third inspection periods, through the operation of the aforementioned equations 1 and 2.

[0420] Next, the timing controller (570) calculates a line-specific resistance compensation value to compensate for line-specific resistance deviations based on line-specific resistance values, and stores the line-specific resistance compensation value in the form of a look-up table in the storage circuit. In one embodiment of the present specification, the timing controller (570) modulates pixel data to be supplied to each of the plurality of data lines according to the resistance compensation value of each of the plurality of data routing lines stored in the storage circuit, and can provide the modulated pixel data to the driving integrated circuit (530). In another embodiment of the present specification, the timing controller (570) sets a current option value (or bias voltage level) for each of the plurality of signal output circuits (531o, 531e) corresponding to each of the plurality of data lines according to the resistance compensation value of each of the plurality of data routing lines stored in the storage circuit, stores it in the storage circuit, and supplies the current option value stored in the storage circuit to the corresponding signal output circuits (531o, 531e). Accordingly, each of the plurality of signal output circuits (531o, 531e) can output a data signal in which the resistance value of the corresponding data routing line is compensated according to the bias voltage level corresponding to the current option value supplied from the timing controller (570), and thereby the resistance deviation between the line resistance values ​​of each of the plurality of data routing lines can be compensated.

[0421] Accordingly, according to one embodiment of the present specification, the first and second switching circuits (171, 172) of each of the plurality of switching circuit sections (170) can be selectively turned on, and the line resistance of each of the plurality of data routing lines can be detected by selectively supplying a test signal to each of the plurality of data lines (DLo, DLe) and sensing the current flowing through the reference line (RL), and the resistance deviation between the line resistance values ​​of each of the plurality of data routing lines can be compensated.

[0422] FIG. 20 is a drawing for explaining a plurality of switching circuits according to another embodiment of the present specification, FIG. 21 is a cross-sectional view along line IV-IV' shown in FIG. 20, and FIG. 22 is a cross-sectional view along line V-V' shown in FIG. 20. FIG. 22 shows a plurality of switching circuits arranged to overlap with a single damper in the light-emitting display device described in FIG. 17 and FIG. 18. Accordingly, in the following description, the same reference numerals are assigned to the remaining components, excluding the single damper, the plurality of switching circuits, and the related configurations, and redundant descriptions thereof are omitted or simplified.

[0423] Referring to FIGS. 20 to 22, a dam portion (104) according to another embodiment of the present specification may be configured to have a planar closed-loop line shape (or continuous line shape or closed-loop shape) along the edge portion of the outermost pixel (Po). Since such a dam portion (104) is configured to have substantially the same structure as the dam portion (104) described in FIGS. 1 to 14, except that it is composed of a dam (or a single dam) having a metal line (104m), a description thereof is omitted.

[0424] The separation section (105) may include at least one outer separation structure (or first and second separation structures) (105-1, 105-2) disposed in an outer area of ​​the dam section (or dam) (104). The separation section (105) may further include at least one outer separation structure (or third and fourth separation structures) (105-3, 105-4) disposed in an inner area of ​​the dam section (104). At least one outer separation structure (105-1, 105-2) may be disposed to surround the dam section (104). At least one inner separation structure (105-3, 105-4) may be disposed to be surrounded by the dam section (104). Since this separation part (105) is configured to have substantially the same structure as the separation part (105) described in FIGS. 1 to 13, except that it includes at least one outer separation structure (105-1, 105-2) and at least one inner separation structure (105-3, 105-4), a description thereof is omitted.

[0425] Additionally, each metal structure of at least one outer separation structure (105-1, 105-2) and at least one inner separation structure (105-3, 105-4) can be electrically connected (or contacted) with the pixel common voltage line (CVL) through the via hole (105h).

[0426] The first pad section (110) may include first and second front sensing control pads (112a, 112b) and first and second pad connection lines (176, 177). The first pad connection line (176) may be electrically connected to a metal line (104m) through a via hole (176h), and the second pad connection line (177) may be electrically connected to a metal line (104m) through a via hole (177h). By doing so, the metal line (104m) may be commonly connected to the first and second pad connection lines (176, 177). Additionally, the first pad section (110) may be composed of only one front sensing control pad (112a) and one pad connection line (176), but is not limited thereto, and may include a plurality of first front sensing control pads (112a) as shown in FIG. 13.

[0427] Each of the plurality of switching circuit sections (170) according to another embodiment of the present specification may include a first and second switching circuit (171, 172). Since the first and second switching circuits (171, 172) are substantially identical to the first and second switching circuits (171, 172) described in FIG. 17 and FIG. 18, respectively, except that they are commonly connected to a single metal line (104m), a redundant description thereof is omitted.

[0428] Additionally, the front auxiliary pad portion (1110), the rear auxiliary pad portion (1110), and the auxiliary link line portion (1250) described in FIGS. 14 and 15, respectively, can be applied to the embodiments illustrated in FIGS. 20 to 22.

[0429] According to another embodiment of the present specification as such, it can have the same effect as the light-emitting display device described in FIG. 17 and FIG. 18, and as the area occupied by the damper (104) is further reduced compared to the light-emitting display device described in FIG. 17 and FIG. 18, the design of the pixel for high resolution can be made easier.

[0430] FIG. 23 is a schematic diagram showing a switching circuit, a driving integrated circuit, and a timing controller according to another embodiment of the present specification, which is a diagram for explaining the sensing of a short circuit of a routing line or a line resistance of a routing line through the switching circuit.

[0431] Referring to FIGS. 20 through 23, a driving integrated circuit (530) according to another embodiment of the present specification may include a data driving unit (531), a sensing unit (533), and a line selection unit (535). Since the driving integrated circuit (530) including such a configuration is substantially the same as the driving integrated circuit (530) described in FIG. 16, except that it is configured to output a single switching control signal supplied from a timing controller (570) in a test mode, a redundant description thereof is omitted.

[0432] The timing controller (570) can generate a single switching control signal in test mode to control the switching of each of the first and second switch circuits (171, 172) of the switching circuit unit (170), and generate test data and line selection signals to provide to the data driving unit (531). Since this timing controller (570) is substantially the same as the timing controller (570) described in FIG. 16 except that it generates a single switching control signal in test mode to control the switching of each of the first and second switch circuits (171, 172) of the switching circuit unit (170), a redundant description thereof is omitted.

[0433] Optionally, the timing controller (570) may not generate a bias voltage corresponding to the line-by-line resistance compensation value, but may provide the line-by-line resistance compensation value to the driving integrated circuit (530). In this case, the driving integrated circuit (530) may further include a bias voltage generating unit (537). The bias voltage generating unit (537) may generate a line-by-line bias voltage corresponding to each line-by-line resistance compensation value supplied from the timing controller (570), and supply the generated line-by-line bias voltage to the bias terminals of the corresponding signal output circuits (531o, 531e).

[0434] Additionally, a driving integrated circuit (530) or a driving circuit part (500) according to another embodiment of the present specification may further include a voltage selection part (539).

[0435] The voltage selection unit (539) can select and output either the switching control signal supplied from the timing controller (570) or the ground voltage according to the voltage selection signal of the timing controller (570).

[0436] The voltage selection unit (539) can output a switching control signal supplied from the timing controller (570) according to a voltage selection signal of a first logic level supplied from the timing controller (570) in test mode, and thereby each of the first and second switch circuits (171, 172) of the switching circuit unit (170) can be switched according to the switching control signal supplied from the voltage selection unit (539) through the first and second front sensing control pads (112a, 112b), respectively.

[0437] The voltage selection unit (539) can output a ground voltage (GND) supplied from the timing controller (570) according to a voltage selection signal of a second logic level supplied from the timing controller (570) in a non-test mode or normal driving mode, and thereby each of the first and second switch circuits (171, 172) of the switching circuit unit (170) is kept off by the ground voltage (GND) supplied from the voltage selection unit (539) through the first and second front sensing control pads (112a, 112b) and the metal line (104m) of the damp unit (104), and the metal line (104m) of the damp unit (104) is kept at the ground voltage (GND) and can be used as an electrostatic protection line or an electrostatic cutoff line.

[0438] A driving method for inspecting a short circuit in a routing line in a light-emitting display device according to one embodiment of the present specification is described as follows.

[0439] First, a switching control signal having a first logic level is output from the timing controller (570), and thereby, the first and second switch circuits (171, 172) of the switching circuit section (170) are each turned off.

[0440] Next, a test data signal is supplied from the driving integrated circuit (530) to the data lines (DLo, DLe), and the sensing unit (533) of the driving integrated circuit (530) senses the current input through the reference line (RL) and the line selection unit (535) and outputs line sensing data.

[0441] Next, the timing controller (570) determines whether there is a short circuit between routing lines based on line sensing data. For example, if a short circuit occurs between adjacent reference lines (RL) and data lines (DLo, DLe), the current flowing through the data lines (DLo, DLe) flows to the reference lines (RL) through the short circuit portion, and the current flowing through the reference lines (RL) is sensed to detect whether there is a short circuit between the lines. For example, the timing controller (570) can determine that a short circuit has occurred between routing lines if the line sensing data is greater than or equal to a reference threshold voltage value.

[0442] Accordingly, according to one embodiment of the present specification, a short circuit defect between a plurality of routing lines can be detected by turning off the first and second switching circuits (171, 172) of each of the plurality of switching circuits (170), supplying a test signal to each of the plurality of data lines (DLo, DLe), and sensing the current flowing through each of the plurality of reference lines (RL).

[0443] A driving method for sensing the line resistance of a routing line in a light-emitting display device according to another embodiment of the present specification is described as follows.

[0444] First, during the first inspection period of the inspection mode, the odd-numbered signal output circuit (531o) of the driving integrated circuit (530) is enabled and the even-numbered signal output circuit (531e) is disabled, thereby allowing the line resistance values ​​of the odd-numbered data routing line and the reference routing line to be sensed. According to one embodiment of the present specification, a switching control signal having a second logic level is output from the driving integrated circuit (530), thereby turning on the first and second switch circuits (171, 172) of the switching circuit unit (170) simultaneously. Subsequently, a test data signal is supplied to the odd-numbered data line (DLo) from the odd-numbered signal output circuit (531o) of the driving integrated circuit (530), and thereby the sensing unit (533) of the driving integrated circuit (530) senses the current input through the line selection unit (535) and the first current path (CP1) which includes the odd-numbered data line (DLo), the first and second switch circuits (171, 172), and the reference line (RL), thereby generating resistance sensing data. Subsequently, the timing controller (570) can generate line resistance values ​​of the odd-numbered data routing line and the reference routing line based on the resistance sensing data and store them in the storage circuit.

[0445] Next, during the second inspection period of the inspection mode, the odd-numbered signal output circuit (531o) of the driving integrated circuit (530) is disabled and the even-numbered signal output circuit (531e) is enabled, thereby allowing the line resistance values ​​of the even-numbered data routing line and the reference routing line to be sensed. According to one embodiment of the present specification, a switching control signal having a second logic level is output from the driving integrated circuit (530), thereby turning on the first and second switch circuits (171, 172) of the switching circuit section (170) simultaneously. Subsequently, a test data signal from the driving integrated circuit (530) is supplied to the even-numbered data line (DLe), and thereby the sensing unit (533) of the driving integrated circuit (530) senses the current input through the even-numbered data line (DLe), the second current path (CP2) including the first and second switch circuits (171, 172) and the reference line (RL), and the line selection unit (535) to generate resistance sensing data. Subsequently, the timing controller (570) can generate line resistance values ​​of the even-numbered data routing line and the reference routing line based on the resistance sensing data and store them in the storage circuit.

[0446] Next, during the third inspection period of the inspection mode, the odd-numbered signal output circuit (531o) of the driving integrated circuit (530) is enabled and the even-numbered signal output circuit (531e) is disabled, thereby allowing the line resistance values ​​of the odd-numbered data routing line and the even-numbered data routing line to be sensed. According to one embodiment of the present specification, a switching control signal of a second logic level is output from the driving integrated circuit (530), thereby turning on the first and second switch circuits (171, 172) of the switching circuit unit (170) simultaneously. Subsequently, a test data signal from the driving integrated circuit (530) is supplied to the odd-numbered data line (DLo), and thereby the sensing unit (533) of the driving integrated circuit (530) senses the current input through the line selection unit (535) and the third current path (CP3) which includes the odd-numbered data line (DLo), the first and second switch circuits (171, 172), and the even-numbered data line (DLe), thereby generating resistance sensing data. Subsequently, the timing controller (570) can generate line resistance values ​​for the odd-numbered data routing line and the even-numbered data routing line based on the resistance sensing data and store them in the storage circuit.

[0447] Next, the timing controller (570) can generate line resistance values ​​for odd-numbered data routing lines and even-numbered data routing lines, and additionally generate line resistance values ​​for reference routing lines, based on line resistance values ​​generated in each of the first to third inspection periods, through the operation of the aforementioned equations 1 and 2.

[0448] Next, the timing controller (570) calculates a line-specific resistance compensation value to compensate for line-specific resistance deviations based on line-specific resistance values, and stores the line-specific resistance compensation value in the form of a look-up table in the storage circuit. In one embodiment of the present specification, the timing controller (570) modulates pixel data to be supplied to each of the plurality of data lines according to the resistance compensation value of each of the plurality of data routing lines stored in the storage circuit, and can provide the modulated pixel data to the driving integrated circuit (530). In another embodiment of the present specification, the timing controller (570) sets a current option value (or bias voltage level) for each of the plurality of signal output circuits (531o, 531e) corresponding to each of the plurality of data lines according to the resistance compensation value of each of the plurality of data routing lines stored in the storage circuit, stores it in the storage circuit, and supplies the current option value stored in the storage circuit to the corresponding signal output circuits (531o, 531e). Accordingly, each of the plurality of signal output circuits (531o, 531e) can output a data signal in which the resistance value of the corresponding data routing line is compensated according to the bias voltage level corresponding to the current option value supplied from the timing controller (570), and thereby the resistance deviation between the line resistance values ​​of each of the plurality of data routing lines can be compensated.

[0449] Accordingly, according to another embodiment of the present specification, the first and second switching circuits (171, 172) of each of the plurality of switching circuit sections (170) are turned on simultaneously, and the line resistance of each of the plurality of data routing lines can be detected by sensing the current flowing through the reference line (RL) while selectively supplying a test signal to each of the plurality of data lines (DLo, DLe), and the resistance deviation between the line resistance values ​​of each of the plurality of data routing lines can be compensated.

[0450] FIG. 24 is a drawing showing a multi-screen display device according to one embodiment of the present specification, and FIG. 25 is a schematic cross-sectional view of line VI-VI' shown in FIG. 24. FIG. 24 and FIG. 25 show a multi-screen display device implemented by tiling the light-emitting display devices according to the present specification described in FIG. 1 to FIG. 23.

[0451] Referring to FIGS. 24 and 25, a multi-screen display device (or tiling light-emitting display device) according to one embodiment of the present specification may include a plurality of display devices (DA1, DA2, DA3, DA4).

[0452] Each of the plurality of display devices (DA1, DA2, DA3, DA4) can display individual images or divide and display a single image. Each of these plurality of display devices (DA1, DA2, DA3, DA4) includes a light-emitting display device according to the present specification described in FIGS. 1 to 23, and a redundant description thereof may be omitted.

[0453] Each of the multiple display devices (DA1, DA2, DA3, DA4) can be tiled on a separate tiling frame so that their sides are in contact with each other. For example, each of the multiple display devices (DA1, DA2, DA3, DA4) can be tiled to have an N×M shape to realize a large-screen multi-screen display device. For example, N can be a positive integer greater than or equal to 1, and M can be a positive integer greater than or equal to 2. For example, N can be a positive integer greater than or equal to 2, and M can be a positive integer greater than or equal to 1.

[0454] Each of the plurality of display devices (DA1, DA2, DA3, DA4) does not include a bezel area (or non-display area) surrounding the entire display portion (AA) where an image is displayed, and has an air-bezel structure in which the display portion (AA) is surrounded by air. That is, for each of the plurality of display devices (DA1, DA2, DA3, DA4), the entire first surface of the first substrate (100) can be implemented as the display portion (AA).

[0455] According to an embodiment of the present specification, in each of the plurality of display devices (DA1, DA2, DA3, DA4), the second gap (D2) between the center (CP) of the outermost pixel (Po) and the outermost outer surface (VL) of the substrate (100) is implemented to be less than half of the first gap (D1) (or pixel pitch) between adjacent pixels. Accordingly, in two adjacent display devices (DA1, DA2, DA3, DA4) that are side-connected (or in contact) along at least one of the first direction (X) and the second direction (Y) according to the side-connection method, the gap (D2+D2) between adjacent outermost pixels (Po) may be equal to or smaller than the first gap (D1) between two adjacent pixels.

[0456] For example, in FIG. 24, in a first display device (DA1) and a third display device (DA3) that are connected (or in contact) side by side along a second direction (Y), the gap (D2+D2) between the center (CP) of the outermost pixel (Po) of the first display device (DA1) and the center (CP) of the outermost pixel (Po) of the third display device (DA3) may be equal to or smaller than the first gap (D1) (or pixel pitch) between two adjacent pixels (Po, Pi) placed in each of the first display device (DA1) and the third display device (DA3).

[0457] Accordingly, since the gap (D2+D2) between the center (CP) of the outermost pixel (Po) of each of two adjacent display devices (DA1, DA2, DA3, DA4) that are connected (or in contact) side by side along at least one of the first direction (X) and the second direction (Y) is equal to or smaller than the first gap (D1) between two adjacent pixels (Po, Pi) placed in each display device (DA1, DA2, DA3, DA4), there is no boundary or seam between two adjacent display devices (DA1, DA2, DA3, DA4), and as a result, there is no dark area caused by the boundary between the multiple display devices (DA1, DA2, DA3, DA4). As a result, the image displayed on the multi-screen display device, which is tiled in an N×M form with multiple display devices (DA1, DA2, DA3, DA4), can be displayed continuously without a sense of discontinuity (or breakage) at the boundary between the multiple display devices (DA1, DA2, DA3, DA4).

[0458] FIGS. 24 and 25 show a plurality of display devices (DA1, DA2, DA3, DA4) tiled in a 2×2 configuration, but are not limited thereto, and the plurality of display devices (DA1, DA2, DA3, DA4) may be tiled in an x×1 configuration, a 1×y configuration, or an x×y configuration. For example, x and y may be two or more natural numbers that are equal to or different from each other. For example, x may be a natural number of 2 or more, or a natural number equal to y. y may be a natural number of 2 or more, or a natural number greater than or less than x.

[0459] The multi-screen display device according to the embodiment of the present specification can display a single image by making each of the display portions (AA) of the plurality of display devices (DA1, DA2, DA3, DA4) into a single screen, and can display a continuously connected image without being interrupted at the boundary portion between the plurality of display devices (DA1, DA2, DA3, DA4), thereby improving the immersion of the viewer watching the image displayed on the multi-screen display device.

[0460] A light-emitting display device according to the present specification and a multi-screen display device using the same can be described as follows.

[0461] A light-emitting display device according to one embodiment of the present specification comprises a substrate, a display unit including a plurality of pixel driving lines disposed on the substrate and a plurality of pixels selectively connected to the plurality of pixel driving lines, a light-emitting element layer including a self-luminous element disposed on the display unit, a dam unit including at least one dam having a metal line disposed along an edge portion of the substrate, an encapsulation layer having an organic encapsulation layer disposed to cover the light-emitting element layer and surrounded by the dam unit, a plurality of switching circuit units disposed to overlap with at least one dam and selectively connected to the plurality of pixel driving lines, and a front pad unit including a plurality of front pads disposed on one edge portion of the substrate and electrically coupled to the plurality of pixel driving lines and the metal line of at least one dam, wherein each of the plurality of switching circuit units may include a first and second switching circuit having a gate electrode electrically coupled to the metal line of at least one dam.

[0462] According to some embodiments of the present specification, each of the plurality of switching circuit portions may be disposed between a substrate and at least one dam.

[0463] According to some embodiments of the present specification, each of the plurality of switching circuits may be disposed in each of the plurality of outermost pixels disposed in the first edge portion of the substrate among the plurality of pixels.

[0464] According to some embodiments of the present specification, a metal line of at least one dam may be electrically connected to at least one of a plurality of front pads.

[0465] According to some embodiments of the present specification, the dam portion includes first to third dams arranged side by side to surround the display portion and each having a metal line, and each of the plurality of switching circuit portions further includes a third switching circuit, the first switching circuit is arranged to overlap with the first dam and includes a gate electrode connected to the metal line of the first dam, the second switching circuit is arranged to overlap with the second dam and includes a gate electrode connected to the metal line of the second dam, and the third switching circuit is arranged to overlap with the third dam and includes a gate electrode connected to the metal line of the third dam.

[0466] According to some embodiments of the present specification, each of the plurality of switching circuits is selectively connected to an odd-numbered data line, a reference voltage line, and an even-numbered data line that are arranged adjacently among the plurality of pixel driving lines, and the first switching circuit further includes a first electrode electrically coupled to the odd-numbered data line and a second electrode electrically coupled to the reference voltage line, the second switching circuit further includes a first electrode electrically coupled to the even-numbered data line and a second electrode electrically coupled to the reference voltage line, and the third switching circuit may further include a first electrode electrically coupled to the odd-numbered data line and a second electrode electrically coupled to the even-numbered data line.

[0467] According to some embodiments of the present specification, the dam portion may include first and second dams arranged side by side to surround the display portion and each having a metal line, the first switching circuit may include a gate electrode arranged to overlap with the first dam and connected to the metal line of the first dam, and the second switching circuit may include a gate electrode arranged to overlap with the second dam and connected to the metal line of the second dam.

[0468] According to some embodiments of the present specification, each of the plurality of switching circuits is selectively connected to an odd-numbered data line, a reference voltage line, and an even-numbered data line that are arranged adjacently among the plurality of pixel driving lines, and the first switching circuit further includes a first electrode electrically coupled to the odd-numbered data line and a second electrode electrically coupled to the reference voltage line, and the second switching circuit may further include a first electrode electrically coupled to the even-numbered data line and a second electrode electrically coupled to the reference voltage line.

[0469] According to some embodiments of the present specification, the dam portion may include a dam having a metal line arranged to surround the display portion, a first switching circuit may include a gate electrode arranged to overlap with the dam and connected to the metal line of the dam, and a second switching circuit may include a gate electrode arranged parallel to the first switching circuit to overlap with the dam and connected to the metal line of the dam.

[0470] According to some embodiments of the present specification, each of the plurality of switching circuits is selectively connected to an odd-numbered data line, a reference voltage line, and an even-numbered data line that are arranged adjacently among the plurality of pixel driving lines, and the first switching circuit further includes a first electrode electrically coupled to the odd-numbered data line and a second electrode electrically coupled to the reference voltage line, and the second switching circuit may further include a first electrode electrically coupled to the even-numbered data line and a second electrode electrically coupled to the reference voltage line.

[0471] According to some embodiments of the present specification, the light-emitting display device may further include a driving circuit that supplies a ground voltage to a metal line.

[0472] According to some embodiments of the present specification, the light-emitting display device may further include a rear pad portion comprising a plurality of rear pads that overlap each of a plurality of front pads, a link line portion having a plurality of link lines electrically coupled to a plurality of rear pads, an input pad portion comprising a plurality of input pads electrically coupled to a plurality of link lines, a driving circuit portion connected to the input pad portion, and a routing portion comprising a plurality of routing lines that wrap around the outer surface of a substrate and are electrically coupled to each of a plurality of front pads and each of a plurality of rear pads.

[0473] According to some embodiments of the present specification, each of the plurality of switching circuits is selectively connected to an odd-numbered data line, a reference voltage line, and an even-numbered data line that are arranged adjacently among the plurality of pixel driving lines, and the driving circuit may include a driving integrated circuit comprising a data driving unit having a plurality of signal output circuits that output a test signal to the odd-numbered data line or the even-numbered data line, and a sensing unit that senses a current flowing in the reference voltage line through at least one of the first and second switching circuits according to the test signal; and a timing controller that provides test data to the driving integrated circuit and sets a bias voltage level input to the bias terminal of each of the plurality of signal output circuits based on the sensing data provided from the sensing unit.

[0474] According to some embodiments of the present specification, a timing controller may determine whether there is a short circuit between a plurality of routing lines based on sensing data, or generate a line resistance value of a data routing line connected to a data line among a plurality of routing lines based on sensing data, and set a bias voltage level according to the generated line resistance value.

[0475] According to some embodiments of the present specification, the light-emitting display device further comprises a front auxiliary pad portion having at least one front auxiliary pad disposed on the other edge portion of a substrate and electrically coupled to a metal line of at least one dam, a rear auxiliary pad portion including at least one rear auxiliary pad that overlaps with at least one front auxiliary pad, and an auxiliary link line portion having at least one auxiliary link line electrically coupled to at least one rear auxiliary pad, wherein the at least one auxiliary link line may be electrically coupled to at least one of a plurality of input pads.

[0476] According to some embodiments of the present specification, at least one dam comprises a first dam pattern disposed on a substrate, a second dam pattern disposed on the first dam pattern, and a third dam pattern disposed on the second dam pattern, and a metal line may be disposed between the second dam pattern and the third dam pattern.

[0477] According to some embodiments of the present specification, at least one dam further includes an undercut region implemented between the side of a first dam pattern and a second dam pattern, and a self-luminous element placed on the dam portion can be separated from the undercut region.

[0478] According to some embodiments of the present specification, the light-emitting display device further comprises a separation section having a plurality of separation structures disposed around at least one dam, each of the plurality of separation structures comprising a lower structure and an upper structure disposed above the lower structure to have an eaves structure for the lower structure, and a self-luminous element disposed above the separation section may be separated by the eaves structure of each of the plurality of separation structures.

[0479] According to some embodiments of the present specification, the light-emitting display device further comprises a separation section having a plurality of separation structures disposed around at least one dam, each of the plurality of separation structures comprising a lower structure and an upper structure disposed above the lower structure to have an eave structure with respect to the lower structure, at least one of the plurality of separation structures further comprises a metal structure disposed between the lower structure and the upper structure, the metal structure disposed above the lower structure to have an eave structure with respect to the lower structure, and a self-luminous element disposed above the separation section may be separated by the eave structure of the metal structure.

[0480] According to some embodiments of the present specification, each of the plurality of separation structures intersects with a plurality of pixel driving lines, and a metal structure may be electrically coupled to at least one pixel common voltage line among the plurality of pixel driving lines.

[0481] According to some embodiments of the present specification, the light-emitting display device further comprises a planarization layer disposed between a substrate and a light-emitting element layer, a passivation layer disposed between a substrate and a planarization layer, a groove line disposed in an inner region of a dam portion and implemented by removing both the planarization layer and the passivation layer, and an undercut region implemented between the side of the passivation layer adjacent to the groove line and the side of the planarization layer adjacent to the groove line, wherein a self-luminous element disposed on the groove line and the side of the planarization layer can be separated in the undercut region.

[0482] A multi-screen display device according to one embodiment of the present specification comprises a plurality of display devices arranged along at least one of a first direction and a second direction crossing the first direction and including a light-emitting display device, wherein the light-emitting display device comprises a substrate, a display portion including a plurality of pixel driving lines arranged on the substrate and a plurality of pixels selectively connected to the plurality of pixel driving lines, a light-emitting element layer including a self-luminous element arranged on the display portion, a dam portion including at least one dam arranged along an edge portion of the substrate and having a metal line, an encapsulation layer having an organic encapsulation layer arranged to cover the light-emitting element layer and surrounded by the dam portion, a plurality of switching circuit portions arranged to overlap with at least one dam and selectively connected to the plurality of pixel driving lines, and a front pad portion including a plurality of front pads arranged on one edge portion of the substrate and electrically coupled to the plurality of pixel driving lines and the metal line of at least one dam, wherein each of the plurality of switching circuit portions may include a first and second switching circuit having a gate electrode electrically coupled to the metal line of at least one dam.

[0483] According to some embodiments of the present specification, in each of the light-emitting displays of a plurality of displays, a plurality of pixels are arranged on a substrate along a first direction and a second direction, and in a first display device and a second display device adjacent along at least one of the first direction and the second direction, the distance between the center of the outermost pixel of the first display device and the center of the outermost pixel of the second display device is equal to or smaller than the pixel pitch, and the pixel pitch may be the distance between the centers of two adjacent pixels.

[0484] The light-emitting display device according to the embodiments of the present specification may be applied to any electronic device including a light-emitting display panel. For example, the light-emitting display device according to the embodiments of the present specification may be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, electronic notebooks, e-books, PMPs (portable multimedia players), PDAs (personal digital assistants), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation systems, in-vehicle navigation systems, in-vehicle display devices, televisions, wallpaper display devices, signage devices, game devices, laptops, monitors, cameras, camcorders, and home appliances.

[0485] It will be obvious to those skilled in the art that the above-described specification is not limited to the aforementioned embodiments and attached drawings, and that various substitutions, modifications, and changes are possible within the scope of the technical concept of the specification. Therefore, the scope of the specification is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the specification. Explanation of the symbols

[0486] 10: Light-emitting display device 100: Substrate 101: Circuit layer 102: Planarization layer 103: Bank 104: Dam 105: Separation section 106: Bag layer 110: 1st pad section 150: Gate driving circuit 170: Switching circuit section 171, 172, 173: Switching circuit 210: 2nd pad section 230: 3rd pad section 400: Routing section 500: Driving circuit section 530: Driving integrated circuit 531: Data driver 533: Sensing unit 535: Line selection unit 539: Voltage selector 570: Timing controller

Claims

Claim 1 A light-emitting display device comprising: a substrate; a display unit including a plurality of pixel driving lines disposed on the substrate and a plurality of pixels selectively connected to the plurality of pixel driving lines; a light-emitting element layer including a self-luminous element disposed on the display unit; a dam portion including at least one dam having a metal line disposed along an edge portion of the substrate; an encapsulation layer having an organic encapsulation layer disposed to cover the light-emitting element layer and surrounded by the dam portion; a plurality of switching circuit portions disposed to overlap with the at least one dam and selectively connected to the plurality of pixel driving lines; a plurality of front pads disposed on one edge portion of the substrate and electrically coupled to the plurality of pixel driving lines and the metal line of the at least one dam; and a driving circuit portion supplying a ground voltage to the metal line, wherein each of the plurality of switching circuit portions includes a first and second switching circuit having a gate electrode electrically coupled to the metal line of the at least one dam. Claim 2 A light-emitting display device according to claim 1, wherein each of the plurality of switching circuit sections is disposed between the substrate and the at least one dam. Claim 3 A light-emitting display device according to claim 1, wherein each of the plurality of switching circuit portions is disposed at each of the plurality of outermost pixels disposed at the first edge portion of the substrate among the plurality of pixels. Claim 4 A light-emitting display device according to claim 1, wherein the metal line of the at least one dam is electrically connected to at least one of the plurality of front pads. Claim 5 A light-emitting display device according to claim 1, wherein the dam portion comprises first to third dams arranged parallel to each other to surround the display portion and each having the metal line, and each of the plurality of switching circuit portions further comprises a third switching circuit, wherein the first switching circuit comprises a gate electrode arranged to overlap with the first dam and connected to the metal line of the first dam, the second switching circuit comprises a gate electrode arranged to overlap with the second dam and connected to the metal line of the second dam, and the third switching circuit comprises a gate electrode arranged to overlap with the third dam and connected to the metal line of the third dam. Claim 6 A light-emitting display device according to claim 5, wherein each of the plurality of switching circuits is selectively connected to an odd-numbered data line, a reference voltage line, and an even-numbered data line that are arranged adjacently among the plurality of pixel driving lines, the first switching circuit further includes a first electrode electrically coupled to the odd-numbered data line and a second electrode electrically coupled to the reference voltage line, the second switching circuit further includes a first electrode electrically coupled to the even-numbered data line and a second electrode electrically coupled to the reference voltage line, and the third switching circuit further includes a first electrode electrically coupled to the odd-numbered data line and a second electrode electrically coupled to the even-numbered data line. Claim 7 A light-emitting display device according to claim 1, wherein the dam portion comprises first and second dams arranged parallel to each other to surround the display portion and each having the metal line, the first switching circuit comprises a gate electrode arranged to overlap with the first dam and connected to the metal line of the first dam, and the second switching circuit comprises a gate electrode arranged to overlap with the second dam and connected to the metal line of the second dam. Claim 8 A light-emitting display device according to claim 7, wherein each of the plurality of switching circuits is selectively connected to an odd-numbered data line, a reference voltage line, and an even-numbered data line that are arranged adjacently among the plurality of pixel driving lines, and the first switching circuit further includes a first electrode electrically coupled to the odd-numbered data line and a second electrode electrically coupled to the reference voltage line, and the second switching circuit further includes a first electrode electrically coupled to the even-numbered data line and a second electrode electrically coupled to the reference voltage line. Claim 9 A light-emitting display device according to claim 1, wherein the dam portion is arranged to surround the display portion and includes a dam having the metal line, the first switching circuit is arranged to overlap with the dam and includes a gate electrode connected to the metal line of the dam, and the second switching circuit is arranged parallel to the first switching circuit to overlap with the dam and includes a gate electrode connected to the metal line of the dam. Claim 10 A light-emitting display device according to claim 9, wherein each of the plurality of switching circuits is selectively connected to an odd-numbered data line, a reference voltage line, and an even-numbered data line that are arranged adjacently among the plurality of pixel driving lines, and the first switching circuit further includes a first electrode electrically coupled to the odd-numbered data line and a second electrode electrically coupled to the reference voltage line, and the second switching circuit further includes a first electrode electrically coupled to the even-numbered data line and a second electrode electrically coupled to the reference voltage line. Claim 11 A light-emitting display device according to claim 1, wherein the driving circuit is configured to supply the ground voltage to the metal line in a normal driving mode or image display mode, and to supply a switching control signal to the metal line in an inspection mode. Claim 12 A light-emitting display device according to claim 11, further comprising: a rear pad portion including a plurality of rear pads overlapping each of the plurality of front pads; a link line portion having a plurality of link lines electrically coupled to the plurality of rear pads; an input pad portion including a plurality of input pads electrically coupled to the plurality of link lines; and a routing portion including a plurality of routing lines covering the outer surface of the substrate and electrically coupled to each of the plurality of front pads and each of the plurality of rear pads, wherein the driving circuit portion is connected to the input pad portion. Claim 13 In claim 12, each of the plurality of switching circuits is selectively connected to an odd-numbered data line, a reference voltage line, and an even-numbered data line that are arranged adjacently among the plurality of pixel driving lines, and the driving circuit comprises: a driving integrated circuit including a data driving unit having a plurality of signal output circuits that output a test signal to the odd-numbered data line or the even-numbered data line, and a sensing unit that senses a current flowing in the reference voltage line through at least one of the first and second switching circuits according to the test signal; and a timing controller that provides test data to the driving integrated circuit and sets a bias voltage level input to each of the plurality of signal output circuits based on the sensing data provided from the sensing unit. Claim 14 In claim 13, the timing controller determines whether there is a short circuit between the plurality of routing lines based on the sensing data, or generates a line resistance value of a data routing line connected to a data line among the plurality of routing lines based on the sensing data, and sets the bias voltage level according to the generated line resistance value, a light-emitting display device. Claim 15 A light-emitting display device according to claim 10, further comprising: a front auxiliary pad portion having at least one front auxiliary pad disposed on the other edge portion of the substrate and electrically coupled to a metal line of at least one dam; a rear auxiliary pad portion including at least one rear auxiliary pad overlapping with the at least one front auxiliary pad; and an auxiliary link line portion having at least one auxiliary link line electrically coupled to the at least one rear auxiliary pad, wherein the at least one auxiliary link line is electrically coupled to at least one of the plurality of input pads. Claim 16 A light-emitting display device according to claim 1, wherein the at least one dam comprises a first dam pattern disposed on the substrate; a second dam pattern disposed on the first dam pattern; and a third dam pattern disposed on the second dam pattern, and the metal line disposed between the second dam pattern and the third dam pattern. Claim 17 In claim 16, the at least one dam further comprises an undercut region implemented between the side of the first dam pattern and the second dam pattern, and the self-luminous element disposed on the dam portion is separated from the undercut region, forming a light-emitting display device. Claim 18 A substrate; a display unit comprising a plurality of pixel driving lines disposed on the substrate and a plurality of pixels selectively connected to the plurality of pixel driving lines; a light-emitting element layer comprising a self-luminous element disposed on the display unit; a dam portion comprising at least one dam disposed along an edge portion of the substrate and having a metal line; an encapsulation layer having an organic encapsulation layer disposed to cover the light-emitting element layer and surrounded by the dam portion; a plurality of switching circuit portions disposed to overlap with the at least one dam and selectively connected to the plurality of pixel driving lines; a front pad portion comprising a plurality of front pads disposed on one edge portion of the substrate and electrically coupled to the plurality of pixel driving lines and the metal line of the at least one dam; and a separation portion comprising a plurality of separation structures disposed around the at least one dam, wherein each of the plurality of switching circuit portions comprises a first and second switching circuit having a gate electrode electrically coupled to the metal line of the at least one dam, and each of the plurality of separation structures comprises a lower structure; A light-emitting display device comprising an upper structure disposed above the lower structure to have an eaves structure for the lower structure, wherein the self-luminous element disposed above the separation part is separated by the eaves structure of each of the plurality of separation structures. Claim 19 A light-emitting display device according to claim 1, further comprising a separation section having a plurality of separation structures disposed around at least one dam, wherein each of the plurality of separation structures comprises: a lower structure; and an upper structure disposed above the lower structure to have an eave structure with respect to the lower structure, wherein at least one of the plurality of separation structures further comprises a metal structure disposed between the lower structure and the upper structure, wherein the metal structure is disposed above the lower structure to have an eave structure with respect to the lower structure, and the self-luminous element disposed above the separation section is separated by the eave structure of the metal structure. Claim 20 A light-emitting display device according to claim 19, wherein each of the plurality of separated structures intersects the plurality of pixel driving lines, and the metal structure is electrically coupled to at least one pixel common voltage line among the plurality of pixel driving lines. Claim 21 A light-emitting display device according to claim 1, further comprising: a planarization layer disposed between the substrate and the light-emitting element layer; a passivation layer disposed between the substrate and the planarization layer; a groove line disposed in the inner region of the dam portion and implemented by removing both the planarization layer and the passivation layer; and an undercut region implemented between the side of the passivation layer adjacent to the groove line and the side of the planarization layer adjacent to the groove line, wherein the self-luminous element disposed on the groove line and the side of the planarization layer is separated from the undercut region. Claim 22 A multi-screen display device comprising a plurality of display devices arranged along at least one of a first direction and a second direction crossing the first direction, wherein each of the plurality of display devices comprises a light-emitting display device according to any one of claims 1 to 21. Claim 23 A multi-screen display device according to claim 22, wherein in each of the plurality of display devices, the plurality of pixels are arranged on the substrate along the first direction and the second direction, and in the first display device and the second display device adjacent along at least one of the first direction and the second direction, the distance between the center of the outermost pixel of the first display device and the center of the outermost pixel of the second display device is equal to or smaller than the pixel pitch, and the pixel pitch is the distance between the centers of two adjacent pixels.

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