Storage device and operating method of the same

Abstract

A storage device according to an embodiment of the present invention includes: a non-volatile memory comprising a plurality of first blocks composed of memory cells storing 1 bit of data and a plurality of second blocks composed of memory cells storing 2 bits or more of data; and a controller that determines whether the number of used second blocks having valid pages less than or equal to a first threshold number among the used second blocks among the plurality of second blocks is greater than or equal to a second threshold number, and, according to the determination result, selects a victim block to perform garbage collection among the first blocks among the plurality of first blocks or the used second blocks having valid pages less than or equal to the first threshold number.

Description

Technology Field

[0001] The present invention relates to a storage device, and more specifically, to a storage device and a method of operating the storage device. Background Technology

[0002] Recently, the paradigm of the computing environment is shifting toward ubiquitous computing, which enables the use of computer systems anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and laptop computers is surging. These portable electronic devices generally utilize data storage devices that employ memory. Data storage devices are used to store data used by portable electronic devices.

[0003] Data storage devices utilizing memory components have the advantages of excellent stability and durability due to the absence of mechanical moving parts, very fast information access speeds, and low power consumption. Data storage devices possessing these advantages include USB (Universal Serial Bus) memory devices, memory cards with various interfaces, UFS (Universal Flash Storage) devices, and Solid State Drives. The problem to be solved

[0004] An embodiment of the present invention provides a storage device and a method of operating the storage device that can prevent performance degradation and improve spatial efficiency. means of solving the problem

[0005] A storage device according to an embodiment of the present invention includes: a non-volatile memory comprising a plurality of first blocks composed of memory cells storing 1 bit of data and a plurality of second blocks composed of memory cells storing 2 bits or more of data; and a controller that determines whether the number of used second blocks having valid pages less than or equal to a first threshold number among the used second blocks among the plurality of second blocks is greater than or equal to a second threshold number, and, according to the determination result, selects a victim block to perform garbage collection among the first blocks among the plurality of first blocks or the used second blocks having valid pages less than or equal to the first threshold number.

[0006] A method of operation of a storage device according to an embodiment of the present invention is a method of operation of a storage device comprising a plurality of first blocks composed of memory cells storing 1 bit of data and a plurality of second blocks composed of memory cells storing 2 bits or more of data, and a controller for controlling the non-volatile memory, the method comprising: a step of determining whether a garbage collection trigger condition for the non-volatile memory has been reached; a step of determining whether the number of used second blocks having valid pages less than or equal to a first threshold number among the used second blocks among the plurality of second blocks is greater than or equal to a second threshold number; and a step of selecting a victim block to perform garbage collection among the first blocks among the plurality of first blocks or the used second blocks having valid pages less than or equal to the first threshold number according to the determination result.

[0007] A storage device according to an embodiment of the present invention includes a non-volatile memory comprising a plurality of SLC (single level cell) blocks and a plurality of XLC (extra level cell) blocks; and a controller that selects a victim block to perform garbage collection among the plurality of SLC blocks or the plurality of XLC blocks based on the number of used XLC blocks having K (where K is a natural number greater than or equal to 1) or fewer valid pages for each of the used XLC blocks among the plurality of XLC blocks. Effects of the invention

[0008] According to the present embodiments, garbage collection (i.e., migration) of SLC blocks is performed to increase the write speed until the number of XLC blocks having valid pages of a predetermined number or less exceeds a predetermined number, and when the number of XLC blocks having valid pages of a predetermined number or less exceeds a predetermined number, garbage collection of XLC blocks is performed to maintain the number of free blocks at a certain level. That is, according to the present embodiments, a certain number of free blocks can be continuously secured while preventing a decrease in the write performance of the storage device. Brief explanation of the drawing

[0009] FIG. 1 is a drawing showing an electronic device according to an embodiment of the present invention. FIG. 2 is a diagram showing the configuration of a controller of a storage device according to an embodiment of the present invention. FIG. 3 is a diagram showing the configuration of a non-volatile memory of a storage device according to an embodiment of the present invention. Figure 4 is a diagram showing the configuration of the memory chip of Figure 3. Figure 5 is a diagram showing the configuration of the volatile memory of Figure 2. Figure 6 is a diagram showing the configuration of a flash translation layer (FTL). FIG. 7 is a flowchart illustrating the operation method of a storage device according to an embodiment of the present invention. FIG. 8 is a diagram illustrating an exemplary data processing system including a solid-state drive (SSD) according to an embodiment of the present invention. Figure 9 is a diagram illustrating the configuration of the controller of Figure 8 in an exemplary manner. FIG. 10 is a diagram illustrating an exemplary data processing system including a storage device according to an embodiment of the present invention. FIG. 11 is a diagram illustrating an exemplary data processing system including a storage device according to an embodiment of the present invention. FIG. 12 is a diagram illustrating an exemplary network system including a storage device according to an embodiment of the present invention. FIG. 13 is a block diagram exemplarily showing the configuration of a non-volatile memory included in a storage device according to an embodiment of the present invention. Specific details for implementing the invention

[0010] Hereinafter, preferred embodiments of the present invention will be described based on the attached drawings.

[0011] FIG. 1 is a drawing showing an electronic device (10) according to an embodiment of the present invention.

[0012] Referring to FIG. 1, the electronic device (10) according to the present embodiment may include a host (100) and a storage device (200).

[0013] The host (100) may be a device such as a mobile phone, MP3 player, laptop computer, desktop computer, game console, TV, or in-vehicle infotainment system. The host (100) may include a file system (110). Additionally, although not shown in FIG. 1, the host (100) may include a processing unit (e.g., a central processing unit) and a driving unit. The processing unit may control the overall operation of the host (100), and the driving unit may drive a data storage device (200) under the control of the processing unit. In one embodiment, the driving unit of the host (100) may include an application (not shown), a file system (110), and a host memory (not shown), etc.

[0014] An application is also called an application program and may be software that runs on an operating system (OS). An application can process data in response to user input. For example, an application can process user data in response to user input and transmit a command to the file system (110) to store the processed user data in the non-volatile memory (210) of the storage device (200).

[0015] The file system (110) may assign a logical block address (LBA) to store user data in response to a command transmitted from an application. In this embodiment, the file system (110) may be F2FS (Flash-Friendly Fine System), EXT4 (ext-ended file system 4), or other types of file systems made similarly, but is not specifically limited thereto.

[0016] The host memory can temporarily store data to be written to the non-volatile memory (210) of the storage device (200) or data read from the non-volatile memory (210) of the storage device (200). Additionally, the host memory can be used as a working memory for running (or executing) an application, a file system (110), etc.

[0017] Referring again to FIG. 1, the storage device (200) can store data accessed by the host (100). The storage device (200) may be called a data storage device or a memory system.

[0018] The storage device (200) may include any one of various types of storage devices depending on the interface protocol connected to the host (100). For example, the storage device (200) may include any one of various types of storage devices such as a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, micro-MMC, a secure digital card in the form of SD, mini-SD, micro-SD, a USB (universal storage bus) storage device, a UFS (universal flash storage) device, a PCMCIA (personal computer memory card international association) card storage device, a PCI (peripheral component interconnection) card storage device, a PCI-E (PCI-express) card storage device, a CF (compact flash) card, a smart media card, a memory stick, etc.

[0019] The storage device (200) can be manufactured in any one of various types of package forms. For example, the storage device (200) can be manufactured in any one of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), WSP (wafer-level stack package), etc.

[0020] FIGS. 2 and FIGS. 3 are drawings showing the configuration of a storage device (200) according to an embodiment of the present invention. FIGS. 2 is a drawing showing the configuration of a controller (220) of the storage device (200), and FIGS. 3 is a drawing showing a non-volatile memory (210) of the storage device (200).

[0021] Referring to FIGS. 2 and FIGS. 3, the storage device (200) may include a non-volatile memory (210) and a controller (220).

[0022] The non-volatile memory (210) can operate as a storage medium of the storage device (200). Depending on the memory cell, the non-volatile memory (210) may include any one of various types of non-volatile memories, such as a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a magnetic random access memory (MRAM) using a tunneling magneto-resistive (TMR) film, a phase change random access memory (PRAM) using chalcogenide alloys, or a resistive random access memory (ReRAM) using a transition metal oxide.

[0023] The non-volatile memory (210) may include a memory cell array (not shown) having a plurality of memory cells each disposed in regions where a plurality of bit lines (not shown) and a plurality of word lines (not shown) intersect.

[0024] For example, each memory cell of a memory cell array may include at least one of a single-level cell (SLC) capable of storing 1 bit of data and an extra-level cell (XLC) capable of storing 2 bits or more of data. The extra-level cell (XLC) may include a multi-level cell (MLC) capable of storing 2 bits of data, a triple-level cell (TLC) capable of storing 3 bits of data, or a quad-level cell (QLC) capable of storing 4 bits of data. Additionally, the memory cell array may include memory cells with a two-dimensional horizontal structure or memory cells with a three-dimensional vertical structure.

[0025] The controller (220) can control the overall operation of the storage device (200) by driving (or executing) firmware or software loaded into the volatile memory (250). The controller (220) can decode and drive (or execute) instructions or algorithms in the form of code, such as firmware or software. The controller (220) can be implemented in hardware, or in a combined form of hardware and software.

[0026] The controller (220) may include a host interface (230), a processor (240), a volatile memory (250), and a memory interface (260). Although not shown in FIG. 2, the controller (220) may further include an ECC (error correction code) circuit that generates parity information by encoding data provided from the host (100) with ECC, and decodes data read from the non-volatile memory (210) using the parity information with ECC.

[0027] The host interface (230) can interface between the host (100) and the storage device (200) in accordance with the protocol of the host (100). For example, the host interface (230) can communicate with the host (100) through any one of the following protocols: USB (universal serial bus), UFS (universal flash storage), MMC (multimedia card), PATA (parallel advanced technology attachment), SATA (serial advanced technology attachment), SCSI (small computer system interface), SAS (serial attached SCSI), PCI (peripheral component interconnection), and PCI-E (PCI express).

[0028] The processor (240) may be composed of a micro control unit (MCU), a central processing unit (CPU), etc. The processor (240) can process requests transmitted from the host (100). To process requests transmitted from the host (100), the processor (240) can drive (or execute) instructions or algorithms in the form of code, i.e., firmware, loaded into volatile memory (250), and control internal functional blocks such as the host interface (230), volatile memory (250), and memory interface (260), as well as non-volatile memory (210).

[0029] The processor (240) can generate a command to control the operation of the non-volatile memory (210) based on a request transmitted from the host (100), and provide the generated command to the non-volatile memory (210) through the memory interface (260).

[0030] Volatile memory (250) may be composed of dynamic random access memory (DRAM) or static random access memory (SRAM). Volatile memory (250) may store firmware driven by the processor (240). Additionally, volatile memory (250) may store data required for the operation of the firmware, such as metadata. That is, volatile memory (250) may function as working memory for the processor (240).

[0031] Volatile memory (250) can temporarily store data to be transferred from the host (100) to the non-volatile memory (210) (e.g., write data) or data to be transferred from the non-volatile memory (210) to the host (100) (e.g., read data). That is, volatile memory (250) can operate as a buffer memory.

[0032] The memory interface (260) can control the non-volatile memory (210) under the control of the processor (240). The memory interface (260) can provide commands generated by the processor (240) to the non-volatile memory (210). The memory interface (260) can provide write data temporarily stored in the volatile memory (250) to the non-volatile memory (210), and receive read data from the non-volatile memory (210) and temporarily store it in the volatile memory (250).

[0033] Referring to FIG. 3, the non-volatile memory (210) may include a plurality of memory chips (211). The plurality of memory chips (211) may include a plurality of memory chip groups (2111~211 m It may be grouped into ), but is not specifically limited thereto. Multiple memory chip groups (2111~211 m Each ) may include n (n is a natural number greater than or equal to 1) memory chips. Multiple memory chip groups (2111~211 m) can communicate with the memory controller (220) through corresponding channels (CH1~CHm) (m is a natural number greater than or equal to 1).

[0034] For example, each channel (CH1~CHm) has each memory chip group (2111~211 m Multiple memory chips (2111-1 to 2111-n to 211) included in ) m -1~211 m -n) can be electrically connected. Each channel (CH1~CHm) has corresponding memory chips (2111-1~2111-n to 211 m -1~211 m -n) can refer to an independent bus capable of transmitting and receiving commands, addresses, and data. Memory chips connected to different channels can each operate independently.

[0035] FIG. 4 is a diagram showing the configuration of the memory chip of FIG. 3. In FIG. 4, the first memory chip (2111-1) of the first memory chip group (2111) is illustrated as an example, but the configuration of the remaining memory chips included in the non-volatile memory (210) may be the same as the configuration shown in FIG. 4.

[0036] Referring to FIG. 4, the memory chip (2111-1) may include a plurality of memory blocks (BLK1 to BLKi). Each of the memory blocks (BLK1 to BLKi) is composed of a plurality of pages (PG1 to PGj). Although not shown in FIG. 4, the memory chip (2111-1) may be composed of a plurality of planes, and each plane may include a plurality of memory blocks. In this embodiment, memory block and block may be used as terms indicating the same configuration.

[0037] Although not shown in FIG. 4, a plurality of memory blocks included in the non-volatile memory (210) can be divided into SLC blocks for writing data in SLC (single level cell) mode and XLC blocks for writing data in XLC (extra level cell) mode.

[0038] SLC blocks can be used to store write data provided from the host (100) in a short period of time. That is, SLC blocks can be used as a type of buffer block. Data stored in the SLC blocks can then be migrated to XLC blocks. For example, if the XLC block is a triple-level cell (TLC) block in which 3 bits of data are stored in each memory cell, data stored in three physical pages consisting of memory cells connected to each of the three word lines in the SLC block can be moved to one physical page consisting of memory cells connected to one word line in the XLC block. This process can be called data migration or garbage collection for the SLC blocks.

[0039] If data provided by the host (100) is stored directly in the XLC block, the write speed is significantly reduced, resulting in reduced write performance. Accordingly, data provided by the host (100) is quickly stored in the SLC block, and then the data stored in the SLC block is moved to the XLC block.

[0040] Generally, the maximum number of SLC blocks that can be used within non-volatile memory (210) is fixed. Accordingly, if only SLC blocks are continuously used to increase write performance, the number of times garbage collection is performed on SLC blocks may increase.

[0041] In this case, the number of garbage collection operations performed on XLC blocks is relatively reduced, and as the number of XLC blocks with very few valid pages increases, the number of free blocks, i.e., available XLC blocks, may be significantly reduced. If the number of garbage collection operations performed on XLC blocks increases to secure free blocks, the time to process requests received from the host (100) is delayed, which may result in a decrease in the performance of the storage device (200).

[0042] In other words, if garbage collection for SLC blocks is performed relatively frequently, high write performance can be maintained, but the number of free blocks among XLC blocks may decrease rapidly. On the other hand, if garbage collection for XLC blocks is performed relatively frequently, many free blocks can be secured quickly, but the securing of empty SLC blocks is delayed, which may lead to a decline in write performance.

[0043] Therefore, it is required to perform garbage collection on each of the SLC block and XLC block at an appropriate point so that free blocks can be easily secured at the same time while preventing performance degradation of the storage device (200).

[0044] According to the present embodiment, the processor (240) of the controller (220) counts the number of XLC blocks among the used XLC blocks that have an effective page count of K (K is a natural number greater than or equal to 1), performs garbage collection on the SLC blocks until the number of XLC blocks with an effective page count of K or less becomes equal to P (P is a natural number greater than or equal to 1), and performs garbage collection on the XLC blocks when the number of XLC blocks with an effective page count of K or less becomes equal to P.

[0045] FIG. 5 is a diagram showing the configuration of the volatile memory (250) of FIG. 2.

[0046] Referring to FIG. 5, the volatile memory (250) may include a first region (251) where a flash translation layer (FTL) is stored, a second region (252) used as a meta region where metadata is stored, a third region (255) used as a write data buffer (WDB) where write data is temporarily stored, and a fourth region (256) used as a read data buffer (RDB) where read data is temporarily stored. It will be obvious to those skilled in the art that the volatile memory (250) may include regions used for various purposes in addition to the regions described above.

[0047] When the non-volatile memory (210) is configured as flash memory, the processor (240) may drive (or execute) software called a flash conversion layer (FTL) to control the unique operation of the non-volatile memory (210) and to provide device compatibility to the host (100). Through the driving (or execution) of this flash conversion layer (FTL), the host (100) can recognize and use the storage device (200) as a general data storage device, such as a hard disk. The flash conversion layer (FTL) may include modules for performing various functions and metadata required for the driving of the modules. The flash conversion layer (FTL) may be stored in a system area (not shown) of the non-volatile memory (210), and when the storage device (200) is powered on, it may be read from the system area of ​​the non-volatile memory (210) and stored in a first area (251) of the volatile memory (250).

[0048] Figure 6 is a diagram showing the configuration of the Flash Transformation Layer (FTL).

[0049] Referring to FIG. 6, the flash conversion layer (FTL) may include a garbage collection module (GCM), a wear-leveling module (WLM), etc., but is not specifically limited thereto. For example, the flash conversion layer (FTL) may further include a write module, a read module, a bad block management module, an address map, etc.

[0050] The garbage collection module (GCM) can manage the non-volatile memory (210) and the volatile memory (250) to perform the operation of collecting valid data stored in the memory blocks of the non-volatile memory (210) into one memory block and erasing invalid data.

[0051] A non-volatile memory (210) composed of flash memory does not support data overwriting due to its structural characteristics. This is because if data is rewritten in a memory cell where data is stored, the reliability of the data stored in that memory cell is not guaranteed. Accordingly, in order to write data to a memory cell where data is stored, an erase operation on the memory cell where data is stored must be performed beforehand.

[0052] Since the erase operation for non-volatile memory (210) is performed in memory block units, it requires a considerably long time. Accordingly, if the memory cell corresponding to the write address is in a written state, the processor (240) writes data to another memory cell that is already in an erased state, instead of erasing the memory cell and writing data. In this case, the data stored in the memory cell corresponding to the original write address becomes invalid data as old data, and the data stored in the other memory cell becomes valid data as new data.

[0053] Accordingly, valid data and invalid data are mixed within the blocks of the non-volatile memory (210). If necessary, that is, when the number of free blocks falls below a preset threshold, the processor (240) may run (or execute) a garbage collection module (GCM) to select a memory block containing less valid data as a victim block (or source block) and perform a garbage collection operation to move the valid data within the victim block to another memory block (e.g., a destination block). Accordingly, the source block may be classified as a free block containing only invalid data. A free block may represent a usable memory block.

[0054] Referring again to FIG. 5, the meta area (252) of the volatile memory (250) may store a valid page count table (VPCT) (253) configured to store the number of valid pages for each of the plurality of memory blocks included in the non-volatile memory (210), and a low valid page block counter (LVPC) (254) configured to store the number of memory blocks having K or fewer valid pages.

[0055] The valid page count table (VPCT) (253) and the low valid page block counter (LVPC) (254) can each be generated and stored by the processor (240). Additionally, the values ​​stored in the valid page count table (VPCT) (253) and the low valid page block counter (LVPC) (254) can be updated whenever a map update is performed.

[0056] For example, the processor (240) can check the number of valid pages in each memory block of the non-volatile memory (210) and store or update the number of valid pages of each memory block at a location corresponding to each memory block in the valid page count table (VPCT). Additionally, the processor (240) can check the number of XLC blocks having K (where K is a natural number greater than or equal to 1) or fewer valid pages by referring to the valid page count table (VPCT) (253) and update the value stored in the low valid page block counter (LVPC) (254) with the checked value.

[0057] Additionally, the processor (240) can determine whether a garbage collection trigger condition for non-volatile memory (210) has been reached. For example, the processor (240) can determine that a garbage collection trigger condition has been reached if the number of free blocks (or free memory blocks) contained within the non-volatile memory (210) is below a threshold value. Here, free blocks may represent available blocks among the extra level cell (XLC) blocks, or blocks in which data is not stored.

[0058] In another embodiment, the processor (240) may determine that a garbage collection trigger condition has been reached if the size of the data written to the non-volatile memory (210) in response to a request from the host (100) is greater than or equal to a threshold value. In yet another embodiment, the processor (240) may determine that a garbage collection trigger condition has been reached if the time during which no request is received from the host (100), i.e., the idle time, is greater than or equal to a threshold value. In addition, it will be obvious to those skilled in the art that there are various other conditions for triggering garbage collection.

[0059] When it is determined that a garbage collection trigger condition has been reached, the processor (240) can determine whether the number of XLC blocks having K or fewer valid pages is P (where P is a natural number greater than or equal to 1). For example, the controller (220) can determine whether the number of XLC blocks having K or fewer valid pages is P or more by comparing P with the value stored in the low valid page block counter (LVPC) (254) stored in the meta area (252) of the volatile memory (250).

[0060] If the number of XLC blocks having K or fewer valid pages is P or more, the processor (240) may select a victim block among the XLC blocks having K or fewer valid pages and perform garbage collection on the selected victim block. For example, the controller (220) may select the XLC block having the fewest number of valid pages among the XLC blocks having K or fewer valid pages as the victim block, but is not specifically limited thereto.

[0061] Meanwhile, if the number of XLC blocks having K or fewer valid pages is less than P, the processor (240) can select a victim block among the SLC (single level cell) blocks where data (i.e., light data) is stored, and perform garbage collection on the selected victim block. For example, the processor (240) can perform garbage collection on the SLC block by migrating the data stored in the SLC block selected as the victim block to the XLC block.

[0062] Accordingly, according to the present embodiment, garbage collection (i.e., migration) of SLC blocks is performed to increase the write speed until the number of XLC blocks having a predetermined number (i.e., K) or fewer valid pages becomes a predetermined number (i.e., P) or more, and when the number of XLC blocks having a predetermined number (i.e., K) or fewer valid pages becomes a predetermined number (i.e., P) or more, garbage collection of XLC blocks is performed to continuously secure free blocks. In other words, a certain number of free blocks or more can be easily secured while maintaining high write performance.

[0063] FIG. 7 is a flowchart illustrating the operation method of a storage device (200) according to an embodiment of the present invention. In describing the operation method of a storage device (200) according to the present embodiment with reference to FIG. 7, at least one of FIG. 2 to FIG. 6 may be referenced.

[0064] In step S710, the controller (220) may determine whether a garbage collection trigger condition for non-volatile memory (210) has been reached. For example, the controller (220) may determine that a garbage collection trigger condition has been reached if the number of free blocks (or free memory blocks) contained within the non-volatile memory (210) is below a threshold value. In another embodiment, the controller (220) may determine that a garbage collection trigger condition has been reached if the size of the data written to the non-volatile memory (210) in response to a request from the host (100) is above a threshold value. In yet another embodiment, the controller (220) may determine that a garbage collection trigger condition has been reached if the time during which no request is received from the host (100), i.e., the idle time, is above a threshold value. In addition, it will be obvious to those skilled in the art that various other conditions for triggering garbage collection may be included.

[0065] If it is determined that the garbage collection trigger condition has been reached, the process can proceed to S720. On the other hand, if it is determined that the garbage collection trigger condition has not been reached, the process can proceed back to S710. That is, step S710 can be performed repeatedly until the garbage collection trigger condition is reached.

[0066] In step S720, the controller (220) can determine whether the number of extra level cell (XLC) blocks having K or fewer effective pages is P or more. For example, the controller (220) can determine whether the number of extra level cell (XLC) blocks having K or fewer effective pages is P or more by comparing P with the value stored in the low effective page block counter (LVPC) (254) stored in the meta area (252) of the volatile memory (250).

[0067] If the number of XLC (extra level cell) blocks having K or fewer valid pages is P or more, the process can proceed to step S730. Meanwhile, if the number of XLC (extra level cell) blocks having K or fewer valid pages is less than P, the process can proceed to step S740.

[0068] In step S730, the controller (220) may select a victim block among the extra level cell (XLC) blocks having K or fewer valid pages and perform garbage collection on the selected victim block. For example, the controller (220) may select the XLC block having the fewest number of valid pages among the extra level cell (XLC) blocks having K or fewer valid pages as the victim block, but is not specifically limited thereto.

[0069] In step S740, the controller (220) can select a victim block among the single-level cell (SLC) blocks where data (i.e., light data) is stored, and perform garbage collection on the selected victim block. For example, the controller (220) can perform garbage collection on the SLC blocks by migrating the data stored in the SLC block selected as the victim block to an XLC block.

[0070] FIG. 8 is a diagram illustrating an exemplary data processing system including a solid state drive (SSD) according to an embodiment of the present invention. Referring to FIG. 8, the data processing system (2000) may include a host device (2100) and a solid state drive (2200) (hereinafter referred to as SSD).

[0071] The SSD (2200) may include a controller (2210), a buffer memory device (2220), non-volatile memory devices (2231 to 223n), a power supply (2240), a signal connector (2250), and a power connector (2260).

[0072] The controller (2210) can control the general operation of the SSD (2200).

[0073] The buffer memory device (2220) can temporarily store data to be stored in the non-volatile memory devices (2231–223n). Additionally, the buffer memory device (2220) can temporarily store data read from the non-volatile memory devices (2231–223n). Data temporarily stored in the buffer memory device (2220) can be transferred to the host device (2100) or the non-volatile memory devices (2231–223n) under the control of the controller (2210).

[0074] Non-volatile memory devices (2231–223n) can be used as storage media for the SSD (2200). Each of the non-volatile memory devices (2231–223n) can be connected to the controller (2210) through multiple channels (CH1–CHn). One or more non-volatile memory devices can be connected to a single channel. Non-volatile memory devices connected to a single channel can be connected to the same signal bus and data bus.

[0075] The power supply (2240) can provide power (PWR) input through the power connector (2260) to the SSD (2200). The power supply (2240) may include an auxiliary power supply (2241). The auxiliary power supply (2241) can supply power so that the SSD (2200) can shut down normally in the event of a sudden power off. The auxiliary power supply (2241) may include large-capacity capacitors capable of charging the power (PWR).

[0076] The controller (2210) can exchange signals (SGL) with the host device (2100) through the signal connector (2250). Here, the signal (SGL) may include commands, addresses, data, etc. The signal connector (2250) may be configured as various types of connectors depending on the interface method between the host device (2100) and the SSD (2200).

[0077] FIG. 9 is a diagram illustrating the configuration of the controller of FIG. 8 as an example. Referring to FIG. 9, the controller (2210) may include a host interface unit (2211), a control unit (2212), a random access memory (2213), an error correction code (ECC) unit (2214), and a memory interface unit (2215).

[0078] The host interface unit (2211) can interface the host device (2100) and the SSD (2200) according to the protocol of the host device (2100). For example, the host interface unit (2211) can communicate with the host device (2100) through any one of the following protocols: secure digital, USB (universal serial bus), MMC (multi-media card), eMMC (embedded MMC), PCMCIA (personal computer memory card international association), PATA (parallel advanced technology attachment), SATA (serial advanced technology attachment), SCSI (small computer system interface), SAS (serial attached SCSI), PCI (peripheral component interconnection), PCI-E (PCI Expresss), and UFS (universal flash storage). Additionally, the host interface unit (2211) can perform a disk emulation function that supports the host device (2100) to recognize the SSD (2200) as a general-purpose data storage device, for example, a hard disk drive (HDD).

[0079] The control unit (2212) can analyze and process a signal (SGL) input from the host device (2100). The control unit (2212) can control the operation of internal function blocks according to firmware or software for driving the SSD (2200). Random access memory (2213) can be used as an operating memory for driving such firmware or software.

[0080] The error correction code (ECC) unit (2214) can generate parity data for data to be transmitted to non-volatile memory devices (2231–223n). The generated parity data can be stored in the non-volatile memory devices (2231–223n) along with the data. The error correction code (ECC) unit (2214) can detect errors in the data read from the non-volatile memory devices (2231–223n) based on the parity data. If the detected error is within the correction range, the error correction code (ECC) unit (2214) can correct the detected error.

[0081] The memory interface unit (2215) can provide control signals, such as commands and addresses, to non-volatile memory devices (2231 to 223n) under the control of the control unit (2212). The memory interface unit (2215) can also exchange data with the non-volatile memory devices (2231 to 223n) under the control of the control unit (2212). For example, the memory interface unit (2215) can provide data stored in the buffer memory device (2220) to the non-volatile memory devices (2231 to 223n), or provide data read from the non-volatile memory devices (2231 to 223n) to the buffer memory device (2220).

[0082] FIG. 10 is a diagram illustrating an exemplary data processing system including a storage device according to an embodiment of the present invention. Referring to FIG. 10, the data processing system (3000) may include a host device (3100) and a data storage device (3200).

[0083] The host device (3100) may be configured in the form of a board, such as a printed circuit board. Although not illustrated, the host device (3100) may include internal function blocks to perform the functions of the host device.

[0084] The host device (3100) may include a connection terminal (3110), such as a socket, slot, or connector. A data storage device (3200) may be mounted to the connection terminal (3110).

[0085] The data storage device (3200) may be configured in the form of a substrate such as a printed circuit board. The data storage device (3200) may be referred to as a memory module or a memory card. The data storage device (3200) may include a controller (3210), a buffer memory device (3220), non-volatile memory devices (3231–3232), a power management integrated circuit (PMIC) (3240), and a connection terminal (3250).

[0086] The controller (3210) can control the general operation of the data storage device (3200). The controller (3210) can be configured in the same way as the controller (2210) shown in FIG. 9.

[0087] The buffer memory device (3220) can temporarily store data to be stored in the non-volatile memory devices (3231–3232). Additionally, the buffer memory device (3220) can temporarily store data read from the non-volatile memory devices (3231–3232). Data temporarily stored in the buffer memory device (3220) can be transferred to the host device (3100) or the non-volatile memory devices (3231–3232) under the control of the controller (3210).

[0088] Non-volatile memory devices (3231–3232) can be used as storage media for a data storage device (3200).

[0089] The PMIC (3240) can provide power input through the connection terminal (3250) to the data storage device (3200). The PMIC (3240) can manage the power of the data storage device (3200) under the control of the controller (3210).

[0090] The connection terminal (3250) can be connected to the connection terminal (3110) of the host device. Through the connection terminal (3250), signals such as commands, addresses, data, and power can be transmitted between the host device (3100) and the data storage device (3200). The connection terminal (3250) can be configured in various forms depending on the interface method between the host device (3100) and the data storage device (3200). The connection terminal (3250) can be placed on one side of the data storage device (3200).

[0091] FIG. 11 is a diagram illustrating an exemplary data processing system including a storage device according to an embodiment of the present invention. Referring to FIG. 11, the data processing system (4000) may include a host device (4100) and a data storage device (4200).

[0092] The host device (4100) may be configured in the form of a board, such as a printed circuit board. Although not illustrated, the host device (4100) may include internal function blocks to perform the functions of the host device.

[0093] The data storage device (4200) may be configured in the form of a surface-mount package. The data storage device (4200) may be mounted to a host device (4100) via a solder ball (4250). The data storage device (4200) may include a controller (4210), a buffer memory device (4220), and a non-volatile memory device (4230).

[0094] The controller (4210) can control the general operation of the data storage device (4200). The controller (4210) can be configured in the same way as the controller (2210) shown in FIG. 9.

[0095] The buffer memory device (4220) can temporarily store data to be stored in the non-volatile memory device (4230). Additionally, the buffer memory device (4220) can temporarily store data read from the non-volatile memory devices (4230). Data temporarily stored in the buffer memory device (4220) can be transferred to the host device (4100) or the non-volatile memory device (4230) under the control of the controller (4210).

[0096] The non-volatile memory device (4230) can be used as a storage medium for the data storage device (4200).

[0097] FIG. 12 is a diagram illustrating an exemplary network system (5000) including a storage device according to an embodiment of the present invention. Referring to FIG. 12, the network system (5000) may include a server system (5300) and a plurality of client systems (5410 to 5430) connected through a network (5500).

[0098] The server system (5300) can provide data in response to requests from multiple client systems (5410 to 5430). For example, the server system (5300) can store data provided by multiple client systems (5410 to 5430). As another example, the server system (5300) can provide data to multiple client systems (5410 to 5430).

[0099] The server system (5300) may include a host device (5100) and a data storage device (5200). The data storage device (5200) may be composed of the storage device (200) of FIG. 1, the data storage device (2200) of FIG. 8, the data storage device (3200) of FIG. 10, and the data storage device (4200) of FIG. 11.

[0100] FIG. 13 is a block diagram exemplarily showing a non-volatile memory included in a storage device according to an embodiment of the present invention. Referring to FIG. 13, the non-volatile memory (210) may include a memory cell array (211), a row decoder (212), a column decoder (214), a data read / write block (213), a voltage generator (215), and control logic (216).

[0101] The memory cell array (211) may include memory cells (MC) arranged in areas where word lines (WL1~WLm) and bit lines (BL1~BLn) intersect each other.

[0102] The row decoder (212) can be connected to the memory cell array (211) through the word lines (WL1–WLm). The row decoder (212) can operate under the control of the control logic (216). The row decoder (212) can decode an address provided from an external device (not shown). The row decoder (212) can select and drive the word lines (WL1–WLm) based on the decoding result. For example, the row decoder (212) can provide a word line voltage provided from the voltage generator (215) to the word lines (WL1–WLm).

[0103] The data read / write block (213) can be connected to the memory cell array (211) through bit lines (BL1 to BLn). The data read / write block (213) may include read / write circuits (RW1 to RWn) corresponding to each of the bit lines (BL1 to BLn). The data read / write block (213) can operate under the control of the control logic (216). Depending on the operation mode, the data read / write block (213) can operate as a write driver or as a sense amplifier. For example, the data read / write block (213) can operate as a write driver that stores data provided from an external device in the memory cell array (211) during a write operation. As another example, the data read / write block (213) can operate as a sense amplifier that reads data from the memory cell array (211) during a read operation.

[0104] The column decoder (214) can operate under the control of the control logic (216). The column decoder (214) can decode an address provided from an external device. Based on the decoding result, the column decoder (214) can connect the read / write circuits (RW1~RWn) of the data read / write block (213) corresponding to each of the bit lines (BL1~BLn) with the data input / output line (or data input / output buffer).

[0105] The voltage generator (215) can generate a voltage used for internal operation of the non-volatile memory (210). The voltages generated by the voltage generator (215) can be applied to the memory cells of the memory cell array (211). For example, a program voltage generated during a program operation can be applied to the word lines of the memory cells where the program operation is to be performed. As another example, an erase voltage generated during an erase operation can be applied to the well regions of the memory cells where the erase operation is to be performed. As another example, a read voltage generated during a read operation can be applied to the word lines of the memory cells where the read operation is to be performed.

[0106] The control logic (216) can control the general operations of the non-volatile memory (210) based on a control signal provided from an external device. For example, the control logic (216) can control the operations of the non-volatile memory (210), such as reading, writing, and erasing operations of the non-volatile memory (210).

[0107] A person skilled in the art to which the present invention pertains should understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features, and therefore the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0108] 10: Electronic device 100: Host 110: File system 200: Storage device 210: Non-volatile memory 220: Controller 230: Host interface 240: Processor 250: Volatile memory 260: Memory interface

Claims

Claim 1 A non-volatile memory comprising a plurality of first blocks composed of memory cells storing 1 bit of data and a plurality of second blocks composed of memory cells storing 2 bits or more of data; and a controller comprising determining whether the number of used second blocks having valid pages less than or equal to a first threshold number among the used second blocks is greater than or equal to a second threshold number, and, according to the determination result, selecting a victim block to perform garbage collection among the used first blocks or selecting a victim block to perform garbage collection among the used second blocks having valid pages less than or equal to the first threshold number, wherein the controller selects the victim block to perform garbage collection among the used first blocks if the number of used second blocks having valid pages less than or equal to the first threshold number is less than the second threshold number. Claim 2 A storage device according to claim 1, wherein the plurality of first blocks include SLC (single level cell) blocks, and the plurality of second blocks include XLC (extra level cell) blocks. Claim 3 delete Claim 4 In claim 1, the controller is a storage device that performs garbage collection for the selected sacrifice block by moving the entire data stored in the selected sacrifice block to the second block. Claim 5 In claim 1, the controller is a storage device that selects the victim block to perform garbage collection from among the used second blocks having valid pages less than or equal to the first threshold number, if the number of used second blocks having valid pages less than or equal to the first threshold number is greater than or equal to the second threshold number. Claim 6 In paragraph 5, the controller is a storage device that performs garbage collection for the selected victim block by moving data stored in an effective page within the selected victim block to another second block. Claim 7 In paragraph 6, the other second block is a storage device that is either a second block currently in use or a second block not in use. Claim 8 In claim 1, the controller counts the number of second blocks having valid pages less than or equal to the first threshold number based on the number of valid pages for each of the used second blocks, and compares the counted number of second blocks with the second threshold number. Claim 9 A method of operation of a storage device comprising a plurality of first blocks composed of memory cells storing 1 bit of data and a plurality of second blocks composed of memory cells storing 2 bits or more of data, and a controller for controlling said non-volatile memory, the method comprising: a step of determining whether a garbage collection trigger condition for said non-volatile memory has been reached; a step of checking whether the number of used second blocks among said second blocks that have valid pages less than or equal to a first threshold number is greater than or equal to a second threshold number; and a step of selecting a victim block to perform garbage collection from said used second blocks having valid pages less than or equal to the first threshold number according to the result of checking, or selecting a victim block to perform garbage collection from said used second blocks having valid pages less than or equal to the first threshold number, wherein if, according to the result of checking, the number of used second blocks having valid pages less than or equal to the first threshold number is less than the second threshold number, the method of operation of a storage device comprising selecting the victim block to perform garbage collection from said used first blocks. Claim 10 A method of operation of a storage device according to claim 9, wherein the plurality of first blocks include SLC (single level cell) blocks and the plurality of second blocks include XLC (extra level cell) blocks. Claim 11 delete Claim 12 A method of operation of a storage device according to claim 9, further comprising the step of moving all data stored in the selected sacrifice block to the second block to perform garbage collection on the selected sacrifice block. Claim 13 A method of operation of a storage device for selecting a victim block to perform garbage collection from among the used second blocks having valid pages less than or equal to the first threshold number, wherein, as a result of the above verification, the number of used second blocks having valid pages less than or equal to the first threshold number is greater than or equal to the second threshold number. Claim 14 A method of operation of a storage device according to claim 13, further comprising the step of performing garbage collection for the selected sacrifice block by moving data stored in valid pages within the selected sacrifice block to another second block. Claim 15 In paragraph 14, the above-mentioned other second block is a method of operation of a storage device which is either a second block currently in use or a second block not in use. Claim 16 A method of operation of a storage device according to claim 9, further comprising the step of counting the number of second blocks having valid pages less than or equal to the first threshold number based on the number of valid pages for each of the second blocks that have been used up. Claim 17 In claim 16, the step of determining whether the number of used second blocks having valid pages less than or equal to a first threshold number is greater than or equal to a second threshold number comprises the step of comparing the number of counted second blocks with the second threshold number. Claim 18 A non-volatile memory comprising a plurality of SLC (single level cell) blocks and a plurality of XLC (extra level cell) blocks; and a controller comprising, for each of the plurality of XLC blocks, a sacrifice block to be garbage collected from among the SLC blocks having K (where K is a natural number greater than or equal to 1) or fewer valid pages, a controller comprising, wherein if the number of the XLC blocks having K or fewer valid pages is less than P (where P is a natural number greater than or equal to 1), the controller selects the SLC block among the plurality of SLC blocks as the sacrifice block to perform the garbage collection. Claim 19 delete Claim 20 In claim 18, the controller performs garbage collection by selecting the victim block among the used XLC blocks having K or fewer valid pages when the number of used XLC blocks having K or fewer valid pages is P or more (where P is a natural number greater than or equal to 1).

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