3D random access memory including ovonic threshold switch structure

Abstract

A three-dimensional random access memory having a structure including an OTS is disclosed. According to an embodiment, the three-dimensional random access memory may include: gate electrodes that are formed extending in a horizontal direction and are spaced apart in a vertical direction and stacked; and vertical structures that penetrate the gate electrodes and extend in the vertical direction—each of the vertical structures including a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures.

Description

Technology Field

[0001] The following embodiments relate to three-dimensional random access memory. Background Technology

[0002] A semiconductor device such as a DRAM (Dynamic Random Access Memory) has wiring such as a MOS transistor including a source and a drain, a capacitor electrically connected to the source of the MOS transistor, and a bit line electrically connected to the drain of the MOS transistor.

[0003] These DRAMs began to be implemented in a three-dimensional structure, moving away from the two-dimensional structure, in line with the trend of high integration to secure storage space.

[0004] A 3D DRAM is implemented to support and operate random access based on a vertical conductive pattern that functions as a gate electrode and a vertical electrode within the memory cell string, while including a semiconductor structure comprising interlayer insulating layers and gate electrodes that are stacked alternately in the vertical direction and a memory cell string that is extended and penetrates the semiconductor structure in the vertical direction.

[0005] However, conventional 3D DRAM includes a select transistor placed at a position corresponding to a gate electrode used as a string select line at the top of a memory cell string, and has the disadvantage that the manufacturing process for the select transistor to correspond to the gate electrode used as a string select line is complex.

[0006] Therefore, there is a need to propose a technology to reduce the complexity of the manufacturing process of a component having a string selection function. The problem to be solved

[0008] The embodiments propose a three-dimensional random access memory of a structure comprising at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures to reduce the complexity of the manufacturing process of a component having a string selection function.

[0009] However, the technical problems that the present invention aims to solve are not limited to the above problems and can be expanded in various ways without departing from the technical concept and scope of the present invention. means of solving the problem

[0010] According to an embodiment, a three-dimensional random access memory may include: gate electrodes that are formed extending in a horizontal direction and are spaced apart in a vertical direction and stacked; and vertical structures that penetrate the gate electrodes and extend in the vertical direction—each of the vertical structures comprising a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures.

[0011] According to one aspect, the at least one OTS may be characterized by being positioned at a position corresponding to at least one end of the top or bottom of each of the vertical structures, instead of being positioned at a position corresponding to the gate electrodes.

[0012] According to another aspect, the at least one OTS may be characterized by being selectively turned on or turned off by a voltage applied to a bit line connected to the upper part of each of the vertical structures or a source line connected to the lower part of each of the vertical structures during memory operation, thereby allowing each of the vertical structures to be selected.

[0013] According to another aspect, any one of the vertical structures including a target memory cell that is the target of a memory operation may be characterized in that it is selected in response to at least one OTS being turned on in any one of the vertical structures during the memory operation.

[0014] According to another aspect, at least one vertical structure among the above vertical structures that does not include a target memory cell subject to memory operation may be characterized in that it is not selected in response to the at least one OTS being turned off in the at least one vertical structure during memory operation.

[0015] According to another aspect, the at least one OTS may be characterized by being located at least one portion above or below the data storage pattern and the vertical conductive pattern in each of the vertical structures.

[0016] According to an embodiment, a method of operating a three-dimensional random access memory comprising: gate electrodes formed extending in a horizontal direction and spaced apart in a vertical direction and stacked; and vertical structures formed extending in the vertical direction penetrating the gate electrodes—each of which includes a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures—may include the step of selectively turning on or turning off the at least one OTS included in each of the vertical structures by a voltage applied to a bit line connected to the top of each of the vertical structures or a source line connected to the bottom of each of the vertical structures; and, as the at least one OTS is selectively turned on or turned off, selecting one of the vertical structures including a target memory cell and performing a memory operation for the target memory cell.

[0017] According to one aspect, the step of performing the above may be characterized by not selecting the at least one vertical structure not including the target memory cell in response to the at least one OTS being turned off in the at least one vertical structure not including the target memory cell, and selecting the at least one vertical structure including the target memory cell in response to the at least one OTS being turned on in the at least one vertical structure including the target memory cell.

[0018] According to an embodiment, a method for manufacturing a three-dimensional random access memory may include the step of extending vertical structures that penetrate a semiconductor structure formed by extending horizontally and stacking gate electrodes spaced apart in the vertical direction—each of which includes a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures.

[0019] According to an embodiment, a method for manufacturing a three-dimensional random access memory may include the steps of: forming vertical structures that penetrate the vertical direction of a semiconductor structure including stacked sacrificial layers that are formed extending in a horizontal direction and spaced apart in a vertical direction, wherein each of the vertical structures includes a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures; and removing the sacrificial layers to form gate electrodes in the spaces where the sacrificial layers have been removed.

[0020] According to one aspect, the step of extending and forming the vertical structures may be characterized by including the step of forming the at least one OTS with a semiconductor material that is selectively turned on or turned off by a voltage applied to a bit line connected to the upper part of each of the vertical structures or a source line connected to the lower part of each of the vertical structures during memory operation. Effects of the invention

[0021] The embodiments propose a three-dimensional random access memory structure comprising at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures, thereby achieving the technical effect of reducing the manufacturing process complexity of the component having the function of string selection.

[0022] However, the effects of the present invention are not limited to the above effects and can be extended in various ways without departing from the technical concept and scope of the present invention. Brief explanation of the drawing

[0023] FIG. 1 is a simplified circuit diagram illustrating a three-dimensional random access memory according to embodiments. FIG. 2 is a plan view illustrating a three-dimensional random access memory according to embodiments. FIG. 3 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to the cross-section of FIG. 2 cut along the line A-A'. FIG. 4 is a cross-sectional view illustrating a three-dimensional random access memory according to another embodiment, corresponding to the cross-section of FIG. 2 cut along the line A-A'. FIG. 5 is a flowchart illustrating the operation method of a three-dimensional random access memory according to embodiments. FIGS. 6 and 7 are flowcharts illustrating a method for manufacturing a three-dimensional random access memory according to embodiments. FIGS. 8a to 8g are drawings for explaining a method for manufacturing a three-dimensional random access memory according to one embodiment. FIGS. 9a to 9g are drawings for illustrating a method for manufacturing a three-dimensional random access memory according to another embodiment. FIG. 10 is a schematic perspective view illustrating an electronic system including a three-dimensional random access memory according to embodiments. Specific details for implementing the invention

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or restricted by the embodiments. Also, the same reference numerals in each drawing indicate the same components.

[0025] Furthermore, the terminology used in this specification is used to appropriately describe preferred embodiments of the present invention, and may vary depending on the intent of the viewer or operator, or the conventions of the field to which the present invention belongs. Accordingly, the definitions of these terms should be based on the content throughout this specification. For example, in this specification, the singular form includes the plural form unless specifically stated otherwise in the text. Also, the terms "comprises" and / or "comprising" used in this specification do not exclude the presence or addition of one or more other components, steps, actions, and / or elements to the mentioned components, steps, actions, and / or elements. Additionally, although terms such as "first," "second," etc., are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by such terms. These terms are used merely to distinguish one specific region, direction, or shape from another region, direction, or shape. Accordingly, a part referred to as the first part in one embodiment may be referred to as the second part in another embodiment.

[0026] Furthermore, it should be understood that various embodiments of the present invention are different but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the technical spirit and scope of the present invention in relation to one embodiment. Additionally, it should be understood that the location, arrangement, or configuration of individual components within each presented category of embodiments may be changed without departing from the technical spirit and scope of the present invention.

[0027] Hereinafter, with reference to the drawings, a three-dimensional random access memory structure including at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures will be described in detail.

[0029] FIG. 1 is a simplified circuit diagram illustrating a three-dimensional random access memory according to embodiments.

[0030] Referring to FIG. 1, a three-dimensional random access memory according to one embodiment may include a plurality of bit lines (BL1, BL2), a common source (CS; hereinafter, source), and a plurality of vertical electrodes (VE; hereinafter, vertical conductive patterns) connecting the two. Each of the plurality of vertical electrodes (VE) may constitute a plurality of memory cell strings (CSTR; hereinafter, cell strings).

[0031] Bit lines (BL1, BL2) can be arranged two-dimensionally, spaced apart from each other along the first direction (D1), while extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) can each form a Cartesian coordinate system defined by the X, Y, and Z axes, which are orthogonal to each other.

[0032] A plurality of cell strings (CSTR) can be connected in parallel to each of the bit lines (BL1, BL2). Since a vertical electrode (VE) is included in each of the cell strings (CSTR), a plurality of vertical electrodes (VE) can be connected in parallel to the plurality of bit lines (BL1, BL2).

[0033] Cell strings (CSTR) can be provided between bit lines (BL1, BL2) and a common source (CS) and can be commonly connected to the source (CS).

[0034] At this time, the source (CS) may be implemented in a plate form so as to be shared by cell strings (CSTRs) constituting the array, but is not limited to or restricted thereto and may be implemented in a line form so as to be shared only by cell strings (CSTRs) included in the same row or column. When the source (CS) is implemented in a line form, it may be provided in multiple numbers, and the multiple sources (CS) may be arranged two-dimensionally, spaced apart from each other along the second direction (D2) while extending in the first direction (D1). The same electrical voltage may be applied to the multiple sources (CS), but is not limited to or restricted thereto and may have different voltages applied by each of the multiple sources (CS) being electrically controlled independently.

[0035] Cell strings (CSTRs) may be formed extending in a third direction (D3) and arranged spaced apart from each other along a second direction (D2) by bit line. According to an embodiment, each cell string (CSTR) may include memory cell transistors (MCTs) arranged corresponding to word lines (WL1, WL2, WL3, ..., WLn), and at least one OTS (OTS1-U, OTS1-L, OTS2-U, OTS2-L, OTS3-U, OTS3-L, OTS4-U, OTS4-L) located at at least one end of the top or bottom of each cell string (CSTR). Each memory cell transistor (MCT) may include a data storage element.

[0036] More specifically, a cell string (CSTR) may be composed of an OTS (OTS1-U, OTS2-U, OTS3-U, OTS4-U) located at the top of the string closest to the bit lines (BL1, BL2), a plurality of memory cell transistors (MCTs) at different distances from the bit lines (BL1, BL2), and an OTS (OTS1-L, OTS2-L, OTS3-L, OTS4-L) located at the bottom of the string closest to the source (CS). That is, the memory cell transistors (MCTs) may be serially connected while arranged along a third direction (D3).

[0037] However, without being limited to this, in a single cell string (CSTR), the OTS (OTS1-L, OTS2-L, OTS3-L, OTS4-L) located at the bottom of the string closest to the source (CS) may be omitted.

[0038] Here, the OTS (OTS1-U, OTS2-U, OTS3-U, OTS4-U) located at the top of the string closest to the bit lines (BL1, BL2) can be controlled to be selectively turned on or turned off by the voltage applied to each of the bit lines (BL1, BL2).

[0039] Likewise, the OTS (OTS1-L, OTS2-L, OTS3-L, OTS4-L) located at the bottom of the string closest to the source (CS) can be controlled to be selectively turned on or turned off by the voltage applied to each source (CS).

[0040] Memory cell transistors (MCTs) can be controlled by word lines (WL1, WL2, WL3, ..., WLn). To this end, the gate electrodes (EL) of the memory cell transistors (MCTs) can be connected in common to one of the word lines (WL1, WL2, WL3, ..., WLn) and be in an equipotential state.

[0041] Word lines (WL1, WL2, WL3, ..., WLn) can be implemented in the form of a plate so as to be shared by cell strings (CSTR) that constitute the array.

[0043] FIG. 2 is a plan view illustrating a three-dimensional random access memory according to embodiments, and FIG. 3 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to the cross section cut along line A-A' of FIG. 4 is a cross-sectional view illustrating a three-dimensional random access memory according to another embodiment, corresponding to the cross section cut along line A-A' of FIG. 2.

[0044] Referring to the drawings, the laminated structure (ST) may be formed to extend in a first direction (D1) and a second direction (D2). Although the drawings show a single laminated structure (ST), it is not limited to or restricted thereto, and multiple structures may be provided and arranged two-dimensionally spaced apart from each other along one direction (the first direction (D1) or the second direction (D2)).

[0045] The stacked structure (ST) may include gate electrodes (EL) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., third direction (D3)). The stacked structure (ST) may have a substantially flat top surface. Hereinafter, the vertical direction means the third direction (D3) or the reverse direction of the third direction (D3).

[0046] Although omitted in the drawing, the stacked structure (ST) may exist in a state disposed on the substrate (SUB) prior to the formation of the source (CS). That is, the stacked structure (ST) may be manufactured by alternately stacking gate electrodes (EL) and interlayer insulating layers (ILD) on the substrate (SUB), and then the substrate (SUB) may be removed during the process of forming the source (CS), so that it consequently does not include the substrate (SUB). However, the stacked structure (ST) is not limited to or restricted to this, and may have a structure that includes the substrate (SUB) as the source (CS) is formed through a process such as impurity implantation into the substrate (SUB).

[0047] Such a substrate (SUB) may be a semiconductor substrate, such as a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0048] Referring again to FIG. 1, each of the gate electrodes (EL) is one of the word lines (WL1, WL2, WL3, ..., WLn) stacked in sequence on the substrate (SUB), and may be a component used as a conductor in a three-dimensional random access memory.

[0049] Each of the gate electrodes (EL) is formed in the shape of a plate extending in the first direction (D1) and also extending in the second direction (D2), and can be shared by an array of vertical structures (VS; cell strings in FIG. 1) and can have substantially the same thickness in the third direction (D3). Hereinafter, thickness refers to the thickness in the third direction (D3).

[0050] Each of these gate electrodes (EL) can be formed from a conductive material. For example, each gate electrode (EL) can be formed from at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each gate electrode (EL) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0051] Although not illustrated, either of the upper or lower ends of each of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL) of the stacked structures (ST) may decrease in length in the first direction (D1) as they move from the bottom to the top in the vertical direction. For example, the gate electrode located at the top of the gate electrodes (EL) may have the shortest length in the first direction (D1), and the gate electrode located at the bottom of the gate electrodes (EL) may have the longest length in the first direction (D1).

[0052] However, not limited to or restricted thereto, the end of the laminated structure (ST) may have a stepped structure along the second direction (D2).

[0053] Each interlayer insulating layer (ILD) is depicted as having the same thickness, but is not limited thereto and may have different thicknesses. For example, the bottom and top interlayer insulating layers (ILD) may have a smaller thickness than other interlayer insulating layers (ILD). However, this is exemplary and not limited thereto, and the thickness of each interlayer insulating layer (ILD) may be adaptively set according to the characteristics of the semiconductor device. The interlayer insulating layers (ILD) may be formed of an insulating material for insulation between gate electrodes (EL). For example, the interlayer insulating layers (ILD) may be formed of silicon oxide.

[0054] Additionally, depending on the implementation example, the interlayer insulating layers (ILD) may be omitted. In this case, the gate electrodes (EL) may be spaced apart from each other in the vertical direction (e.g., the third direction (D3)) and stacked, and an air gap may be interposed between the gate electrodes (EL).

[0055] A plurality of vertical holes (H) penetrating a portion of the stacked structures (ST) may be provided. Vertical structures (VS) may be provided within the vertical holes (H). The vertical structures (VS) may be formed as a plurality of cell strings (CSTR) shown in FIG. 1, extending in a third direction (D3) while connected to bit lines (BL1, BL2) and a source (CS).

[0056] The vertical structures (VS) may be connected to the bit lines (BL1, BL2) by the upper surface of each of the vertical structures (VS) indirectly contacting the lower surface of the bit lines (BL1, BL2) through another structure (e.g., a bit line plug (BLPG)). However, without being limited to this, the vertical structures (VS) may also be connected to the bit lines (BL1, BL2) by the upper surface of each of the vertical structures (VS) directly contacting the lower surface of the bit lines (BL1, BL2).

[0057] The vertical structures (VS) may be connected to the source (CS) by the lower surface of each vertical structure (VS) coming into direct contact with the upper surface of the source (CS). However, without being limited to this, the vertical structures (VS) may also be connected to the source (CS) by the lower surface of each vertical structure (VS) coming into indirect contact with the upper surface of the source (CS) through another structure.

[0058] Columns of vertical structures (VS) penetrating any one of the stacked structures (ST) may be provided in multiple numbers. As previously described, since the gate electrodes (EL) are formed in a plate shape, the vertical structures (VS) may form an array consisting of multiple columns and rows on the horizontal plane formed by the gate electrodes (EL). For example, as shown in FIG. 2, eight vertical structures (VS) may penetrate one of the stacked structures (ST) by forming four columns and four rows. However, the number of vertical structures (VS) forming the array is not limited to or restricted therefrom.

[0059] As such, by forming an array consisting of multiple columns and rows on the horizontal plane of the gate electrodes (EL) formed in the shape of a plate, the 3D random access memory can have a structure in which the integration density of the memory cell string is improved.

[0060] At this time, vertical structures (VS) included in an adjacent pair of columns may be shifted to form different rows on a horizontal plane and arranged so as to be offset from each other. For example, vertical structures (VS) included in the first column may be arranged in the first and third rows, and vertical structures (VS) included in the second column may be arranged in the second and fourth rows, and vertical structures (VS) included in the second column may be arranged in a zigzag shape along the first direction (D1). Accordingly, the density of the memory cell string may be further improved compared to the case where vertical structures (VS) included in an adjacent pair of columns are arranged side by side in the same row on a horizontal plane.

[0061] Each of the vertical structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). Although the drawings show each of the vertical structures (VS) as having a column shape with equal widths at the top and bottom, they are not limited to this and may have a shape in which the width increases in the first direction (D1) and the second direction (D2) as they go toward the third direction (D3). The upper surface of each of the vertical structures (VS) may have a circular shape, an elliptical shape, a square shape, or a bar shape.

[0062] These vertical structures (VS) may correspond to the cell strings (CSTR) shown in Fig. 1.

[0063] To this end, each of the vertical structures (VS) may include a data storage pattern (DSP), a vertical conductive pattern (VE), and at least one OTS. In each of the vertical structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with the top and bottom open, and the vertical conductive pattern (VE) may have a shape that fills the space from the top and bottom to a certain depth and height within the inner space of the data storage pattern (DSP) while being wrapped around the outside by the data storage pattern (DSP), and at least one OTS may be located at at least one end of the top or bottom of each of the vertical structures (VS). That is, instead of being placed at a position corresponding to the gate electrodes, at least one OTS may be placed at a position corresponding to at least one end of the top or bottom of each of the vertical structures (VS). Precisely, at least one OTS may be located at at least one part of the top or bottom of the data storage pattern (DSP) and the vertical conductive pattern (VE) in each of the vertical structures (VS).

[0064] For example, referring to Fig. 3 which illustrates a structure in which one OTS is included in a vertical structure (VS), the OTS can be positioned on the top of the vertical structure (VS) by being located above the data storage pattern (DSP) and the vertical conductive pattern (VE) in the vertical structure (VS).

[0065] As another example, referring to FIG. 4 which illustrates a structure in which two OTS (OTS-U, OTS-L) are included in a vertical structure (VS), the upper OTS-U among the OTS (OTS-U, OTS-L) can be positioned at the top of the vertical structure (VS) by being located above the data storage pattern (DSP) and the vertical conductive pattern (VE) in the vertical structure (VS), and the lower OTS-L among the OTS (OTS-U, OTS-L) can be positioned at the bottom of the vertical structure (VS) by being located below the data storage pattern (DSP) and the vertical conductive pattern (VE) in the vertical structure (VS).

[0066] In this way, as at least one OTS is located at at least one end of the top or bottom of the vertical structure (VS) rather than at a position corresponding to the gate electrode (EL), the complexity of the manufacturing process can be reduced.

[0067] The data storage pattern (DSP) surrounds the outer wall of the vertical conductive pattern (VE) and can come into contact with the side walls of the gate electrodes (EL) on the outside. Accordingly, the regions of the data storage pattern (DSP) corresponding to the gate electrodes (EL) can be configured to form memory cells in which memory operations (including write operations, such as program operations and erase operations, and read operations) are performed by the voltage applied through the gate electrodes (EL) and the voltage applied to the vertical conductive pattern (VE). Hereinafter, the statement that a voltage is applied to the vertical conductive pattern (VE) means that as a vertical structure (VS) including the vertical conductive pattern (VE) is selected by at least one OTS, the vertical conductive pattern (VE) is selectively connected to the bit line (BL) and the voltage is transmitted to the vertical conductive pattern (VE).

[0068] The memory cells correspond to the memory cell transistors (MCTs) shown in FIG. 1. For this purpose, the data storage pattern (DSP) may be a polarization generating dielectric pattern, which is a data storage element that generates a polarization phenomenon by a voltage applied through the gate electrodes (EL) and a voltage applied to the vertical conductive pattern (VE) to represent a data value as a voltage, current, or resistance change corresponding to the polarization state of the charges.

[0069] For example, as a data storage pattern (DSP), at least one of HfOx having an orthorhombic crystal structure, HfOx doped with at least one of Al, Zr, or Si, PZT (Pb(Zr, Ti)O3), PTO (PbTiO3), SBT (SrBi2Ti2O3), BLT (Bi(La, Ti)O3), PLZT (Pb(La, Zr)TiO3), BST (Bi(Sr, Ti)O3), barium titanate (BaTiO3), P(VDF-TrFE), PVDF, AlOx, ZnOx, TiOx, TaOx, or InOx may be used.

[0070] As another example, antiferroelectric materials can be used as data storage patterns (DSP), and ZrO₂ is an example of an antiferroelectric material. x , Zr a X b O x (X may include Hf, Si, Al, Ge, or one of the elements of Group 2 of the periodic table) may be used.

[0071] However, the data storage pattern (DSP) may be a data storage element that represents a data value by trapping a charge by an applied voltage, and is not limited to or restricted to this.

[0072] Additionally, although the drawing shows the data storage pattern (DSP) extending in a vertical direction (e.g., a third direction (D3)), it is not limited to or restricted thereto and may have a structure of multiple segments spaced apart and arranged only in regions corresponding to the gate electrodes (EL) on the outer wall of the vertical conductive pattern (VE).

[0073] The vertical conductive pattern (VE) is a component used as a conductor rather than a channel in a three-dimensional random access memory and, like the gate electrodes (EL), can be formed from at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0074] These vertical conductive patterns (VE) can be selectively connected to a bit line (BL) or source (CS) through at least one OTS located in at least one of the upper or lower portions while being included in each of the vertical structures (VS). Hereinafter, the statement that the bit line (BL) or source (CS) is selectively connected to the vertical conductive pattern (VE) does not mean that the bit line (BL) or source (CS) is connected by physical contact with the vertical conductive pattern (VE), but rather that the vertical conductive pattern (VE) is electrically connected to the bit line (BL) or source (CS) to receive the voltage applied to the bit line (BL) or source (CS).

[0075] To this end, at least one OTS can serve as a selector that is selectively turned on or turned off by a voltage applied to the bit line (BL) or source line (CS) during memory operation, thereby selecting each of the vertical structures (VS) (selectively turned on or turned off and serving as a selector that selectively connects the vertical structures (VS) (specifically, the vertical conductive pattern (VE) of each of the vertical structures (VS)) to the bit line (BL) or source (CS)).

[0076] That is, as at least one OTS is optionally turned on or turned off, any one of the vertical structures (VS) containing a target memory cell that is the target of memory operation can be selected.

[0077] For example, any one of the vertical structures (VS) containing a target memory cell may be selected in response to at least one OTS being turned on in any one of the vertical structures during memory operation.

[0078] As another example, at least one vertical structure among the vertical structures (VS) that does not include a target memory cell may not be selected in response to at least one OTS being turned off in at least one vertical structure during memory operation.

[0079] At least one OTS may be formed of a semiconductor material (e.g., polycrystalline silicon, oxide semiconductor material, doped semiconductor material, phase change material, etc.) that is selectively turned on or turned off by a voltage applied to a bit line (BL) or source line (CS) during memory operation to serve as the described selector.

[0080] At least two bit lines (BL1, BL2) are positioned at the same height on the upper part of the vertical structures (VS). The vertical structures (VS) arranged in the same row in the array may further include a bit line plug (BLPG) positioned at a location offset from the center of each of the vertical structures (VS) to be connected to each of the different bit lines (BL1, BL2). That is, the vertical structures (VS) arranged in the same row in the array can be connected to each of the different bit lines (BL1, BL2) through the bit line plug (BLPG) positioned at a location offset from the center of each of the vertical structures (VS).

[0081] A separation trench (BLSLT; not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). Insulating spacers (not shown) may be formed in the separation trench (BLSLT) to separate the adjacent stacked structures (ST). For example, the insulating spacers may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant. The separation trench (BLSLT) may serve to separate the gate electrode (EL-BLSL) as described above.

[0082] A capping insulating film (CAP) may be provided on the stacked structures (ST) and vertical structures (VS). The capping insulating film (CAP) may cover the upper surface of the uppermost of the interlayer insulating layers (ILD). The capping insulating film (CAP) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP). The bit line contact plug (BLPG) may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it moves toward the third direction (D3).

[0083] Bit lines (BL) may be provided on a capping insulating film (CAP) and a bit line contact plug (BLPG). The bit lines (BL) may be formed by extending a conductive material along a second direction (D2) while being spaced apart from each other along a first direction (D2). The conductive material constituting the bit lines (BL) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL).

[0084] As described, the three-dimensional random access memory can perform memory operations by selecting a vertical structure (VS) containing a target memory cell through at least one OTS. This will be described with reference to FIG. 5.

[0086] FIG. 5 is a flowchart illustrating the operation method of a three-dimensional random access memory according to embodiments.

[0087] The operation method described below is based on the premise that it is performed by a three-dimensional random access memory of the structure described with reference to FIGS. 1 to 4, and may mean a memory operation including at least one of a program operation, a read operation, or an erase operation for a target memory cell.

[0088] In step (S510), the three-dimensional random access memory can selectively turn on or turn off at least one OTS included in each of the vertical structures (VS) by a voltage applied to a bit line (BL) connected to the upper part of each of the vertical structures (VS) or a source line (CS) connected to the lower part of each of the vertical structures (VS).

[0089] Accordingly, in step (S520), the three-dimensional random access memory can perform memory operations on the target memory cell by selecting one of the vertical structures (VS) that includes the target memory cell, as at least one OTS is selectively turned on or turned off.

[0090] More specifically, the three-dimensional random access memory may not select at least one vertical structure that does not include a target memory cell in response to at least one OTS being turned off in at least one vertical structure that does not include a target memory cell, and may select at least one vertical structure that includes a target memory cell in response to at least one OTS being turned on in any vertical structure that includes a target memory cell.

[0092] FIGS. 6 and 7 are flowcharts illustrating a method for manufacturing a three-dimensional random access memory according to embodiments. More specifically, FIG. 6 is a flowchart illustrating a manufacturing method based on a gate-first process, and FIG. 7 is a flowchart illustrating a manufacturing method based on a gate replacement process.

[0093] The manufacturing method described below is intended for manufacturing a three-dimensional random access memory of the structure described above with reference to FIGS. 1 to 4, and is based on the premise that it is performed by an automated and mechanized manufacturing system.

[0094] Referring to FIG. 6, in step (S610), the manufacturing system can extend vertical structures (VS) that penetrate vertically through a semiconductor structure (SEMI-STR) that includes stacked gate electrodes (EL) formed while extending horizontally.

[0095] Here, each of the vertical structures (VS) includes a data storage pattern (DSP), a vertical conductive pattern (VE), and at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures (VS), so that as step (S610) is performed, a three-dimensional random access memory of a structure including at least one OTS can be manufactured.

[0096] Referring to FIG. 7, in step (S710), the manufacturing system can extend vertical structures (VS) that penetrate vertically through a semiconductor structure (SEMI-STR) that includes stacked sacrificial layers (SAC) formed while extending horizontally.

[0097] Next, in step (S720), the manufacturing system can remove the sacrificial layers (SAC) to form gate electrodes (EL) in the spaces where the sacrificial layers (SAC) have been removed.

[0098] Each of the vertical structures (VS) includes a data storage pattern (DSP), a vertical conductive pattern (VE), and at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures (VS), and as steps (S710 to S720) are performed, a three-dimensional random access memory of a structure including at least one OTS can be manufactured.

[0099] At this time, in both the gate-first process-based manufacturing method and the gate-replacement process-based manufacturing method, the manufacturing system can form at least one OTS with a semiconductor material that is selectively turned on or turned off by a voltage applied to a bit line (BL) connected to the upper part of each of the vertical structures (VS) or a source line (CS) connected to the lower part of each of the vertical structures (VS) during memory operation.

[0100] Accordingly, when memory operation is performed, at least one OTS is selectively turned on or turned off, so that a vertical structure (VS) containing a target memory cell is selected and memory operation can be performed.

[0101] Below, a detailed process for manufacturing a 3D random access memory using a gate-first process-based manufacturing method is described with reference to the drawings. In the case of a gate replacement process-based manufacturing method, only the step of removing sacrificial layers (SAC) to form gate electrodes (EL) needs to be added to the gate-first process-based manufacturing method, so a detailed description thereof is omitted.

[0103] FIGS. 8a to 8g are drawings for explaining a method for manufacturing a three-dimensional random access memory according to one embodiment.

[0104] First, in the first step, the manufacturing system can prepare a semiconductor structure (SEMI-STR) comprising stacked gate electrodes (EL) that are vertically spaced apart and formed extending horizontally on a source line (CS) and a lower OTS (OTS-L), as illustrated in FIGS. 8a and 8b. Interlayer insulating layers (ILD) may be interposed between the gate electrodes (EL) in the semiconductor structure (SEMI-STR).

[0105] Next, in the second step, the manufacturing system can extend and form vertical holes (H) penetrating in a vertical direction on the semiconductor structure (SEMI-STR) as shown in FIG. 8c.

[0106] Next, in the third step, the manufacturing system can extend and form a data storage pattern (DSP) and a vertical conductive pattern (VE) within each of the vertical holes (H) as shown in FIG. 8d.

[0107] Next, in the fourth step, the manufacturing system can etch the upper region corresponding to the data storage pattern (DSP) and the vertical conductivity pattern (VE) on the semiconductor structure (SEMI-STR) as shown in FIG. 8e.

[0108] Subsequently, in the fifth step, the manufacturing system can form an upper OTS (OTS-U) on an etched upper region as shown in FIG. 8f and form a bit line (BL) thereon. Although the formation of the bit line (BL) has been simplified and illustrated and described as a structure in which the bit line (BL) directly contacts the upper OTS (OTS-U), the case including a bit line plug (BLPG) as shown in FIG. 3 can also be described as forming a bit line plug (BLPG) to contact the upper OTS (OTS-U) and forming a bit line (BL) thereon.

[0109] Additionally, the described manufacturing method is not limited to or restricted thereto, and steps 4 and 5 may be performed differently or omitted. For example, as the previously described step 4 is omitted, the manufacturing system may sequentially form upper OTS and bit lines (BL) directly in the area corresponding to the data storage pattern (DSP) and vertical conductive pattern (VE) on the semiconductor structure (SEMI-STR) in step 5, as illustrated in FIG. 8g.

[0110] Although a method for manufacturing a three-dimensional random access memory structure in which each of the above vertical structures (VS) includes two OTSs (lower OTS, upper OTS) has been described, a three-dimensional random access memory structure in which each of the vertical structures (VS) includes one OTS (upper OTS; OTS-U) can be manufactured in a similar manner.

[0111] For example, instead of preparing a semiconductor structure (SEMI-STR) on a source line (CS) and at least one OTS (lower OTS; OTS-L) in the first step, by preparing a semiconductor structure (SEMI-STR) on the source line (CS) (the remaining steps are performed identically), a three-dimensional random access memory of a structure in which each of the vertical structures (VS) includes one OTS (upper OTS; OTS-U) can be manufactured.

[0113] FIGS. 9a to 9g are drawings for illustrating a method for manufacturing a three-dimensional random access memory according to another embodiment.

[0114] First, the manufacturing system may prepare a semiconductor structure (SEMI-STR) inverted in the first step, comprising stacked gate electrodes (EL) that are vertically spaced apart and formed extending in the horizontal direction as illustrated in FIGS. 9a and 9b, and having vertical structures (VS) formed therein. Interlayer insulating layers (ILD) may be interposed between the gate electrodes (EL) in the semiconductor structure (SEMI-STR).

[0115] At this time, each of the vertical structures (VS) may include a data storage pattern (DSP), a vertical conductive pattern (VE), and an upper OTS (OTS-U), and a bit line (BL) may be formed on the upper OTS (OTS-U).

[0116] Although the semiconductor structure (SEMI-STR) has been simplified and illustrated as a state in which the bit line (BL) is in direct contact with the upper OTS (OTS-U), as shown in FIG. 3, the case including the bit line plug (BLPG) can also be described as a structure in which the bit line plug (BLPG) is positioned to contact the upper OTS (OTS-U) and the bit line (BL) is positioned thereon.

[0117] Next, in the second step, the manufacturing system can etch areas corresponding to the data storage pattern (DSP) and the vertical conductivity pattern (VE) on the inverted semiconductor structure (SEMI-STR) as illustrated in FIG. 9c.

[0118] Next, the manufacturing system can form a lower OTS (OTS-L) in the etched area as shown in FIG. 9d in the third step.

[0119] After that, the manufacturing system can form a source line (CS) on the lower OTS (OTS-L) as shown in FIG. 9e in the fourth step.

[0120] Additionally, the described manufacturing method is not limited to or restricted thereto, and the second, third, and fourth steps may be performed differently or omitted. For example, as the previously described second step is omitted, the manufacturing system may form a lower OTS (OTS-L) directly in the area corresponding to the data storage pattern (DSP) and vertical conductive pattern (VE) on the semiconductor structure (SEMI-STR) as shown in FIG. 9f in the third step, and form a source line (CS) on the lower OTS (OTS-L) as shown in FIG. 9g in the fourth step.

[0121] Although a method for manufacturing a three-dimensional random access memory structure in which each of the above vertical structures (VS) includes two OTSs (lower OTS, upper OTS), a three-dimensional random access memory structure in which each of the vertical structures (VS) includes one OTS (upper OTS; OTS-U) can be manufactured by forming a source line (CS) in an area corresponding to a data storage pattern (DSP) and a vertical conductive pattern (VE) on an inverted semiconductor structure (SEMI-STR) after only the first step is performed.

[0123] FIG. 10 is a schematic perspective view illustrating an electronic system including a three-dimensional random access memory according to embodiments.

[0124] Referring to FIG. 10, an electronic system (1000) including a three-dimensional random access memory according to embodiments may include a main board (1001), a controller (1002) mounted on the main board (1001), one or more semiconductor packages (1003) and a DRAM (1004).

[0125] The semiconductor package (1003) and DRAM (1004) can be connected to the controller (1002) by wiring patterns (1005) provided on the main board (1001).

[0126] The main board (1001) may include a connector (1006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (1006) may vary depending on the communication interface between the electronic system (1000) and the external host.

[0127] The electronic system (1000) can communicate with an external host according to any one of the interfaces, for example, USB (Universal Serial Bus), PCI Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). The electronic system (1000) can operate by power supplied from an external host, for example, through a connector (1006). The electronic system (1000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to a controller (1002) and a semiconductor package (1003).

[0128] The controller (1002) can write data to the semiconductor package (1003) or read data from the semiconductor package (1003), and can improve the operating speed of the electronic system (1000).

[0129] The DRAM (1004) may be a buffer memory to mitigate the speed difference between the semiconductor package (1003), which is a data storage space, and an external host. The DRAM (1004) included in the electronic system (1000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (1003). When the electronic system (1000) includes the DRAM (1004), the controller (1002) may further include a DRAM controller for controlling the DRAM (1004) in addition to the NAND controller for controlling the semiconductor package (1003).

[0130] A semiconductor package (1003) may include first and second semiconductor packages (1003a, 1003b) spaced apart from each other. The first and second semiconductor packages (1003a, 1003b) may each be a semiconductor package including a plurality of semiconductor chips (1020). Each of the first and second semiconductor packages (1003a, 1003b) may include a package substrate (1010), semiconductor chips (1020) on the package substrate (1010), adhesive layers (1030) disposed on the lower surface of each of the semiconductor chips (1020), connection structures (1040) electrically connecting the semiconductor chips (1020) and the package substrate (1010), and a molding layer (1050) covering the semiconductor chips (1020) and the connection structures (1040) on the package substrate (1010).

[0131] The package substrate (1010) may be a printed circuit board including package upper pads (1011). Each semiconductor chip (1020) may include input / output pads (1021). Each semiconductor chip (1020) may include the three-dimensional random access memory described above with reference to FIGS. 1 through 4. More specifically, each semiconductor chip (1020) may include gate stacking structures (1022) and memory structures (1023). The gate stacking structures (1022) may correspond to the stacking structures (ST) described above, and the memory structures (1023) may correspond to the vertical structures (VS) described above.

[0132] The connection structures (1040) may be, for example, bonding wires that electrically connect the input / output pads (1021) and the package upper pads (1011). Accordingly, in each of the first and second semiconductor packages (1003a, 1003b), the semiconductor chips (1020) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pads (1011) of the package substrate (1010). According to embodiments, in each of the first and second semiconductor packages (1003a, 1003b), the semiconductor chips (1020) may be electrically connected to each other by through-silicon vias instead of the bonding wire connection structures (1040).

[0133] Unlike what is described, the controller (1002) and the semiconductor chips (1020) may be included in a single package. The controller (1002) and the semiconductor chips (1020) may be mounted on a separate interposer substrate different from the main substrate (1001), and the controller (1002) and the semiconductor chips (1020) may be connected to each other by wiring provided on the interposer substrate.

[0135] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results can be achieved even if the described techniques are performed in a different order than described, and / or the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

[0136] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.

Claims

Claim 1 A three-dimensional random access memory comprising: gate electrodes formed extending in a horizontal direction and spaced apart in a vertical direction and stacked; and vertical structures formed extending in the vertical direction penetrating the gate electrodes—each of the vertical structures comprising a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures, wherein the vertical conductive pattern is a component in which a voltage for memory operation in regions corresponding to the gate electrodes of the data storage pattern is applied from a bit line connected to the top of each of the vertical structures or a source line connected to the bottom of each of the vertical structures, while not being affected by the voltage applied to the gate electrodes— wherein the at least one OTS is located at at least one portion of the top or bottom of the vertical conductive pattern in each of the vertical structures. Claim 2 A three-dimensional random access memory according to claim 1, wherein the at least one OTS is positioned at a position corresponding to at least one end of the top or bottom of each of the vertical structures, instead of being positioned at a position corresponding to the gate electrodes. Claim 3 A three-dimensional random access memory according to claim 2, wherein at least one OTS is selectively turned on or turned off by a voltage applied to the bit line or the source line during memory operation, so that each of the vertical structures is selected. Claim 4 A three-dimensional random access memory according to claim 3, wherein any one of the vertical structures, which includes a target memory cell that is the target of the memory operation, is selected in response to the at least one OTS being turned on in any one of the vertical structures during the memory operation. Claim 5 A three-dimensional random access memory according to claim 3, wherein at least one vertical structure among the vertical structures that does not include a target memory cell subject to the memory operation is not selected in response to the at least one OTS being turned off in the at least one vertical structure during the memory operation. Claim 6 delete Claim 7 A method of operating a three-dimensional random access memory comprising: gate electrodes formed extending in a horizontal direction and spaced apart in a vertical direction and stacked; and vertical structures formed extending in the vertical direction penetrating the gate electrodes—each of the vertical structures comprising a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) located at at least one end of the upper or lower portion of each of the vertical structures and simultaneously located at at least one portion of the upper or lower portion of the vertical conductive pattern, wherein the vertical conductive pattern is a component in which a voltage for memory operation in regions corresponding to the gate electrodes of the data storage pattern is applied from a bit line connected to the upper portion of each of the vertical structures or a source line connected to the lower portion of each of the vertical structures, while the vertical conductive pattern is not affected by a voltage applied to the gate electrodes, wherein the voltage for memory operation in regions corresponding to the gate electrodes of the data storage pattern is applied from a bit line connected to the upper portion of each of the vertical structures or a source line connected to the lower portion of each of the vertical structures; the method comprising the step of selectively turning on or turning off the at least one OTS included in each of the vertical structures by a voltage applied to the bit line or the source line. A method of operating a three-dimensional random access memory comprising the step of selecting one of the vertical structures including a target memory cell and performing the memory operation on the target memory cell as at least one OTS is selectively turned on or turned off. Claim 8 A method of operation of a three-dimensional random access memory according to claim 7, wherein the step of performing the above includes the step of not selecting the at least one vertical structure not including the target memory cell in response to the at least one OTS being turned off in the at least one vertical structure not including the target memory cell, and selecting the at least one vertical structure including the target memory cell in response to the at least one OTS being turned on in the at least one vertical structure including the target memory cell. Claim 9 A method for manufacturing a three-dimensional random access memory comprising the step of extending vertical structures penetrating a semiconductor structure that includes stacked gate electrodes formed and extended in a horizontal direction, the vertical structures comprising a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures and simultaneously located at at least one portion of the top or bottom of the vertical conductive pattern, wherein the vertical conductive pattern is a component in which a voltage for memory operation in regions corresponding to the gate electrodes of the data storage pattern is applied from a bit line connected to the top of each of the vertical structures or a source line connected to the bottom of each of the vertical structures, while the vertical conductive pattern is not affected by the voltage applied to the gate electrodes. Claim 10 A method for manufacturing a three-dimensional random access memory comprising: a step of extending vertical structures penetrating a semiconductor structure formed by extending horizontally and stacking sacrificial layers spaced apart in the vertical direction, wherein each of the vertical structures includes a data storage pattern, a vertical conductive pattern, and at least one OTS (Ovonic Threshold Switch) located at at least one end of the top or bottom of each of the vertical structures and simultaneously located at at least one portion of the top or bottom of the vertical conductive pattern, wherein the vertical conductive pattern is not affected by a voltage applied to the gate electrodes, and a component in which a voltage for memory operation in regions corresponding to the gate electrodes of the data storage pattern is applied from a bit line connected to the top of each of the vertical structures or a source line connected to the bottom of each of the vertical structures; and a step of removing the sacrificial layers to form the gate electrodes in the spaces where the sacrificial layers have been removed. Claim 11 A method for manufacturing a three-dimensional random access memory, characterized in that, in either claim 9 or 10, the step of extending and forming the vertical structures comprises the step of forming the at least one OTS with a semiconductor material that is selectively turned on or turned off by a voltage applied to the bit line or the source line during memory operation.

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