Semiconductor device

Abstract

The present invention provides a semiconductor device capable of improving device performance and reliability. A semiconductor device according to some embodiments of the present invention comprises a lower insulating layer, a plurality of pin-shaped insulating layers extending in a first direction on the lower insulating layer, a field insulating layer extending in a first direction on the lower insulating layer and disposed between the pin-shaped insulating layers, and a plurality of gate structures including a gate electrode intersecting the pin-shaped insulating layer on the pin-shaped insulating layer, wherein the gate electrode comprises a plurality of gate structures extending in a second direction intersecting the first direction, a source / drain pattern disposed between the gate structures on the pin-shaped insulating layer, and an active pattern on the pin-shaped insulating layer penetrating the gate electrode and connected to the source / drain pattern.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0002] As one of the scaling techniques to increase the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or silicon body) in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the multi-channel active pattern.

[0003] Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale. In addition, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed.

[0004] Meanwhile, as the pitch size of semiconductor devices decreases, research is needed to reduce capacitance and ensure electrical stability between contacts within the semiconductor device. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a semiconductor device capable of improving device performance and reliability.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0007] A semiconductor device according to one aspect of the present invention for achieving the above technical problem comprises: a lower insulating layer; a plurality of pin-shaped insulating layers extending in a first direction on the lower insulating layer; a field insulating layer extending in a first direction on the lower insulating layer and disposed between the pin-shaped insulating layers; a plurality of gate structures including a gate electrode intersecting the pin-shaped insulating layer on the pin-shaped insulating layer, wherein the gate electrode includes a plurality of gate structures extending in a second direction intersecting the first direction; a source / drain pattern disposed between the gate structures on the pin-shaped insulating layer; and an active pattern on the pin-shaped insulating layer penetrating the gate electrode and connected to the source / drain pattern.

[0008] A semiconductor device according to another aspect of the present invention for achieving the above technical problem comprises an insulating layer, a trench disposed within the insulating layer and extending in a first direction, a field insulating layer filling the trench, a gate electrode on the insulating layer extending in a second direction intersecting the first direction, a source / drain pattern disposed between the gate electrodes on the insulating layer, and an active pattern penetrating the gate electrode and connected to the source / drain pattern, wherein the insulating layer comprises a first portion that overlaps with the field insulating layer in a third direction intersecting the first direction and the second direction, and a second portion that does not overlap with the field insulating layer in the third direction, and the bottom surface of the source / drain pattern contacts the second portion of the insulating layer.

[0009] A semiconductor device according to another aspect of the present invention for achieving the above technical problem comprises: a lower insulating layer including a first region and a second region; a plurality of first pin-shaped insulating layers extending in a first direction on the lower insulating layer of the first region; a plurality of second pin-shaped insulating layers extending in a first direction on the lower insulating layer of the second region; and a plurality of gate structures including a gate electrode intersecting the first and second pin-shaped insulating layers on the first and second pin-shaped insulating layers, wherein the gate electrode comprises a plurality of gate structures extending in a second direction intersecting the first direction; a first source / drain pattern disposed between the gate structures on the first pin-shaped insulating layer; a second source / drain pattern disposed between the gate structures on the second pin-shaped insulating layer; a first active pattern penetrating the gate electrode and connected to the first source / drain pattern on the first pin-shaped insulating layer; and a second active pattern penetrating the gate electrode and connected to the second source / drain pattern on the second pin-shaped insulating layer, wherein with respect to the upper surface of the lower insulating layer, the first source / drain pattern The bottom surface is higher than the bottom surface of the second source / drain pattern above.

[0010] Specific details of other embodiments are included in the description of the invention and the drawings. Brief explanation of the drawing

[0011] FIG. 1 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 2 is an exemplary cross-sectional view taken along AA' and B-B' of FIG. 1. FIG. 3 is an exemplary cross-sectional view taken along CC' and D-D' of FIG. 1. FIG. 4 is an exemplary cross-sectional view taken along E-E' of FIG. 1. FIG. 5 is a drawing for explaining a semiconductor device according to some embodiments. FIG. 6 is a drawing for explaining a semiconductor device according to some embodiments. FIG. 7 is a drawing for explaining a semiconductor device according to some embodiments. FIG. 8 is a drawing for explaining a semiconductor device according to some embodiments. FIG. 9 is a drawing for explaining a semiconductor device according to some embodiments. FIG. 10 is a drawing for explaining a semiconductor device according to some embodiments. FIG. 11 is a drawing for illustrating a semiconductor device according to some embodiments. FIG. 12 is a drawing for explaining a semiconductor device according to some embodiments. FIGS. 13a and FIGS. 13b are drawings for illustrating a semiconductor device according to some embodiments. FIG. 14 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 15 is a cross-sectional view taken along FF' and G-G' of FIG. 14. FIG. 16 is a cross-sectional view taken along HH' and I-I' of FIG. 14. Figure 17 is a cross-sectional view taken along J-J' of Figure 14. FIGS. 18 to 35 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. Specific details for implementing the invention

[0012] In the drawings relating to a semiconductor device according to some embodiments, exemplarily, a fin-type transistor (FinFET) including a channel region having a fin-shaped pattern, a transistor including a nanowire or a nanosheet, and an MBCFET TMAlthough a Multi-Bridge Channel Field Effect Transistor has been illustrated, it is not limited thereto. It goes without saying that semiconductor devices according to some embodiments may include tunneling FETs or three-dimensional (3D) transistors. It goes without saying that semiconductor devices according to some embodiments may include planar transistors. Furthermore, the technical concept of the present invention can be applied to transistors based on two-dimensional materials (2D material-based FETs) and heterostructures thereof.

[0013] In addition, semiconductor devices according to some embodiments may include bipolar junction transistors, horizontal dual diffusion transistors (LDMOS), etc.

[0014] Hereinafter, a semiconductor device according to several embodiments will be described with reference to FIGS. 1 to 17.

[0015] FIG. 1 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 2 is an exemplary cross-sectional view cut along AA' and B-B' of FIG. 1. FIG. 3 is an exemplary cross-sectional view cut along CC' and D-D' of FIG. 1. FIG. 4 is an exemplary cross-sectional view cut along E-E' of FIG. 1.

[0016] Referring to FIGS. 1 to 4, a semiconductor device according to some embodiments may include a first insulating layer (110), a second insulating layer (210), a gate electrode (120), a first active contact (CA1), a second active contact (CA2), a first gate contact (160), and a second gate contact (260).

[0017] A first insulating layer (110) may be formed in a first region. A second insulating layer (210) may be formed in a second region. In some embodiments, the first region may be a first active region (RX1) and the second region may be a second active region (RX2), but is not limited thereto.

[0018] The first insulating layer (110) may include a first lower insulating layer (110B) and a first pin-shaped insulating layer (110F). The second insulating layer (210) may include a second lower insulating layer (210B) and a second pin-shaped insulating layer (210F).

[0019] The lower insulating layer (110B, 210B) may include a first active region (RX1), a second active region (RX2), and a field region (FX). The field region (FX) may be formed immediately adjacent to the first active region (RX1) and the second active region (RX2). The field region (FX) may form a boundary with the first active region (RX1) and the second active region (RX2).

[0020] The first active region (RX1) and the second active region (RX2) are spaced apart from each other. The first active region (RX1) and the second active region (RX2) can be separated by a field region (FX).

[0021] Alternatively, a device isolation layer may be disposed around a first active region (RX1) and a second active region (RX2) that are spaced apart from each other. In this case, the portion of the device isolation layer located between the first active region (RX1) and the second active region (RX2) may be a field region (FX). For example, the portion where the channel region of a transistor, which may be an example of a semiconductor device, is formed may be the active region, and the portion separating the channel region of the transistor formed in the active region may be the field region. Alternatively, the active region may be the portion where a fin-shaped pattern or nanosheet used as the channel region of the transistor is formed, and the field region may be the portion where the fin-shaped pattern or nanosheet used as the channel region is not formed.

[0022] In one embodiment, one of the first active region (RX1) and the second active region (RX2) may be a PMOS forming region and the other may be an NMOS forming region. In another embodiment, the first active region (RX1) and the second active region (RX2) may be PMOS forming regions. In yet another embodiment, the first active region (RX1) and the second active region (RX2) may be NMOS forming regions. Hereinafter, the first active region (RX1) is described as an NMOS region and the second active region (RX2) is a PMOS region.

[0023] The first pin-shaped insulating layer (110F) and the second pin-shaped insulating layer (210F) can each be formed on the lower insulating layers (110B, 210B). For example, the first pin-shaped insulating layer (110F) can be formed on the first lower insulating layer (110B). The second pin-shaped insulating layer (210F) can be formed on the second lower insulating layer (210B).

[0024] In some embodiments, a first pin-shaped insulating layer (110F) may be formed in a first active region (RX1). The first pin-shaped insulating layer (110F) may protrude in a third direction (Z) from a first lower insulating layer (110B) of the first active region (RX1). The first pin-shaped insulating layer (110F) may extend along a first direction (X) on the first lower insulating layer (110B). For example, the first pin-shaped insulating layer (110F) may include a long side extending in the first direction (X) and a short side extending in the second direction (Y). Here, the first direction (X) may intersect the second direction (Y) and the third direction (Z). Additionally, the second direction (Y) may intersect the third direction (Z).

[0025] The upper surface (110F_US) of the first fin-shaped insulating layer (110F) may come into contact with the bottom surface (170_BS) of the first source / drain pattern (170). The upper surface (110F_US) of the first fin-shaped insulating layer (110F) may come into contact with the bottom surface (GS_BS) of the gate structure (GS). In a semiconductor device according to some embodiments of the present invention, the first fin-shaped insulating layer (110F) and the first source / drain pattern (170) may come into contact, thereby blocking leakage current occurring between the bottom surface (170_BS) of the first source / drain pattern (170).

[0026] A second pin-shaped insulating layer (210F) may be formed in a second active region (RX2). The second pin-shaped insulating layer (210F) may protrude in a third direction (Z) from a second lower insulating layer (210B) of the second active region (RX2). The upper surface (210F_US) of the second pin-shaped insulating layer (210F) may be in contact with the bottom surface (270_BS) of the second source / drain pattern (270). The upper surface (210F_US) of the second pin-shaped insulating layer (210F) may be in contact with the bottom surface (GS_BS) of the gate structure (GS). Likewise, in a semiconductor device according to some embodiments of the present invention, the second pin-shaped insulating layer (210F) and the second source / drain pattern (270) are in contact so that leakage current occurring between the bottom surface (270_BS) of the second source / drain pattern (270) can be blocked.

[0027] The description of the second pin-shaped insulating layer (210F) may be substantially the same as the description of the first pin-shaped insulating layer (110F).

[0028] In FIG. 2, the first pin-shaped insulating layer (110F) may not overlap with the first source / drain pattern (170) in the first direction (X). The bottom surface (170_BS) of the first source / drain pattern (170) may be located in the same plane as the bottom surface (GS_BS) of the gate structure (GS).

[0029] At least a portion of the second fin-shaped insulating layer (210F) may overlap with the second source / drain pattern (270) in the first direction (X). With respect to the upper surface of the second lower insulating layer (210B), the bottom surface (270_BS) of the second source / drain pattern (270) may be lower than the bottom surface (GS_BS) of the gate structure (GS). With respect to the upper surface of the second lower insulating layer (210B), the bottom surface (270_BS) of the second source / drain pattern (270) may be lower than the bottom surface (170_BS) of the first source / drain pattern (170). That is, the height of the first source / drain pattern (170) in the third direction (Z) may be smaller than the height of the second source / drain pattern (270) in the third direction (Z).

[0030] In FIG. 3, the first insulating layer (110) may include a first portion (110_1) that overlaps with the first field insulating layer (105) in the third direction (Z) and a second portion (110_2) that does not overlap with the first field insulating layer (105) in the third direction (Z). The second portion (110_2) of the first insulating layer (110) may be positioned between the first portion (110_1) of the adjacent first insulating layer (110). The height of the second portion (110_2) of the first insulating layer (110) in the third direction (Z) may be greater than the height of the first portion (110_1) of the first insulating layer (110) in the third direction (Z). The first pin-shaped insulating layer (110F) may be part of the second portion (110_2) of the first insulating layer (110).

[0031] The second insulating layer (210) may include a first portion (210_1) that overlaps with the second field insulating layer (205) in the third direction (Z), and a second portion (210_2) that does not overlap with the second field insulating layer (205) in the third direction (Z). The second portion (210_2) of the second insulating layer (210) may be positioned between the first portion (210_1) of the adjacent second insulating layer (210). The height of the second portion (210_2) of the second insulating layer (210) in the third direction (Z) may be greater than the height of the first portion (210_1) of the second insulating layer (210) in the third direction (Z). The second pin-shaped insulating layer (210F) may be part of the second portion (210_2) of the second insulating layer (210).

[0032] A second portion (110_2) of the first insulating layer (110) may come into contact with the first source / drain pattern (170). The upper surface (110_2_US) of the second portion (110_2) of the first insulating layer (110) may come into contact with the bottom surface (170_BS) of the first source / drain pattern (170). A second portion (210_2) of the second insulating layer (210) may come into contact with the second source / drain pattern (270). The upper surface (210_2_US) of the second portion (210_2) of the second insulating layer (210) may come into contact with the bottom surface (270_BS) of the second source / drain pattern (270).

[0033] In some embodiments, the height of the second portion (110_2) of the first insulating layer (110) in the third direction (Z) may be greater than the height of the second portion (210_2) of the second insulating layer (210) in the third direction (Z). The height of the first source / drain pattern (170) in the third direction (Z) may be smaller than the height of the second source / drain pattern (270) in the third direction (Z).

[0034] In FIG. 4, a second portion (110_2) of the first insulating layer (110) may overlap with the first active pattern (AP1) in a third direction (Z). The first insulating layer (110) may be spaced apart from the first active pattern (AP1) in a third direction (Z). The first insulating layer (110) may not come into contact with the first active pattern (AP1). A gate insulating film (130) may be disposed on the second portion (110_2) of the first insulating layer (110). The gate insulating film (130) may wrap around the first active pattern (AP1).

[0035] Likewise, the first pin-shaped insulating layer (110F) may overlap with the first active pattern (AP1) in the third direction (Z). The first pin-shaped insulating layer (110F) may be spaced apart from the first active pattern (AP1) in the third direction (Z). The first pin-shaped insulating layer (110F) may not come into contact with the first active pattern (AP1).

[0036] The first pin-shaped insulating layer (110F) can completely cover the bottom surface (170_BS) of the first source / drain pattern (170). Accordingly, leakage current between the first source / drain pattern (170) can be blocked. The second pin-shaped insulating layer (210F) can completely cover the bottom surface (270_BS) of the second source / drain pattern (270). Accordingly, leakage current between the second source / drain pattern (270) can be blocked.

[0037] The first and second insulating layers (110, 210) may include an oxide-based insulating material. The first and second insulating layers (110, 210) may include, for example, at least one of silicon oxide, silicon oxynitride, and a low dielectric constant material. Low dielectric constant materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped Silicon Oxide), OSG (Organo Silicate) Glass), SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, It may include mesoporous silica or a combination thereof, but is not limited thereto.

[0038] In FIGS. 3 and 4, a first trench (105t) extending in a first direction (X) may be disposed within the first insulating layer (110).

[0039] The first trench (105t) may be placed on the first lower insulating layer (110B). The first trench (105t) may be placed between the first pin-shaped insulating layer (110F). The first trench (105t) may be placed on both sides of the first pin-shaped insulating layer (110F). The bottom surface of the first trench (105t) may be located in the same plane as the top surface of the first lower insulating layer (110B). The first trench (105t) may overlap with the first part (110_1) of the first insulating layer (110) in the third direction (Z). The first trench (105t) may not overlap with the second part (110_2) of the first insulating layer (110) in the third direction (Z). The first trench (105t) may not overlap with the first part (110_1) in the second direction (Y). The first trench (105t) may overlap with at least a portion of the second part (110_2) of the first insulating layer (110) in the second direction (Y).

[0040] A second trench (205t) extending in a first direction (X) may be disposed within the second insulating layer (210). The second trench (205t) may be disposed on the second lower insulating layer (210B). The second trench (205t) may be disposed between the second pin-shaped insulating layer (210F). The second trench (205t) may be disposed on both sides of the second pin-shaped insulating layer (210F). The bottom surface of the second trench (205t) may be located in the same plane as the top surface of the second lower insulating layer (210B). The second trench (205t) may overlap with the first portion (210_1) of the second insulating layer (210) in a third direction (Z). The second trench (205t) may not overlap with the second portion (210_2) of the second insulating layer (210) in the third direction (Z). The second trench (205t) may not overlap with the first portion (210_1) in the second direction (Y). The second trench (205t) may overlap with at least a portion of the second portion (210_2) of the second insulating layer (210) in the second direction (Y).

[0041] The first field insulation layer (105) can fill the first trench (105t). The first field insulation layer (105) can be placed within the first trench (105t). The second field insulation layer (205) can fill the second trench (205t). The second field insulation layer (205) can be placed within the second trench (205t).

[0042] In some embodiments, the first field insulating layer (105) may include a first field liner film (105L) and a first field filling film (105F).

[0043] The first field liner membrane (105L) may be placed along the side walls and bottom surface of the first trench (105t). The first field filling membrane (105F) may be formed on the first field liner membrane (105L). The first field filling membrane (105F) may fill the first trench (105t) remaining after filling the first field liner membrane (105L).

[0044] In some embodiments, the first field liner membrane (105L) may define the first field recess (105R). The first field filling membrane (105F) may fill the first field recess (105R).

[0045] The first field liner membrane (105L) may include a horizontal section positioned along the bottom surface of the first trench (105t) and a vertical section positioned along the side wall of the first trench (105t). The horizontal section of the first field liner membrane (105L) may define the bottom surface of the first field recess (105R). The vertical section of the first field liner membrane (105L) may define the side wall of the first field recess (105R).

[0046] The horizontal portion of the first field liner membrane (105L) may come into contact with the first lower insulation layer (110B). The vertical portion of the first field liner membrane (105L) may come into contact with the first pin-shaped insulation layer (110F). The horizontal portion of the first field liner membrane (105L) may come into contact with the upper surface of the first lower insulation layer (110B). The vertical portion of the first field liner membrane (105L) may come into contact with the side wall of the first pin-shaped insulation layer (110F).

[0047] The horizontal portion of the first field liner membrane (105L) may come into contact with the first portion (110_1) of the first insulating layer (110). The horizontal portion of the first field liner membrane (105L) may come into contact with the upper surface of the first portion (110_1) of the first insulating layer (110). The vertical portion of the first field liner membrane (105L) may come into contact with the second portion (110_2) of the first insulating layer (110). The vertical portion of the first field liner membrane (105L) may come into contact with the side wall of the second portion (110_2) of the first insulating layer (110).

[0048] The upper surface (105_US) of the first field insulation layer (105) may have a convex shape with respect to the first lower insulation layer (110B). That is, with respect to the upper surface of the first lower insulation layer (110B), the upper surface (105_US) of the first field insulation layer (105) may gradually become lower as it moves away from the side wall of the first pin-shaped insulation layer (110F). However, the technical concept of the present invention is not limited thereto.

[0049] In some embodiments, the second field insulation layer (205) may include a second field liner (205L) and a second field filling film (205F). The second field liner (205L) may be positioned along the bottom surface and sidewall of the second trench (205t). The second field filling film (205F) may fill the second trench (205t) remaining after filling the second field liner (205L) on the second field liner (205L). The second field liner (205L) may define a second field recess (205R). The second field filling film (205F) may fill the second field recess (205R).

[0050] The description of the second field insulation layer (205) may be substantially the same as the description of the first field insulation layer (105).

[0051] In FIG. 3, the upper surface (105_US) of the first field insulation layer (105) may be formed higher than the upper surface (205_US) of the second field insulation layer (205). That is, with respect to the upper surface of the lower insulation layer (110B, 210B), the upper surface (105_US) of the first field insulation layer (105) may be higher than the upper surface (205_US) of the second field insulation layer (205).

[0052] In FIGS. 3 and 4, the upper surface (105_US) of the first field insulation layer (105) may be formed lower than the upper surface (110F_US) of the first pin-shaped insulation layer (110F). That is, with respect to the upper surface of the first lower insulation layer (110B), the upper surface (105_US) of the first field insulation layer (105) may be lower than the upper surface (110F_US) of the first pin-shaped insulation layer (110F).

[0053] In some embodiments, the upper surface (105_US) of the first field insulation layer (105) may be in contact with the sidewall of the first pin-shaped insulation layer (110F). The upper surface (205_US) of the second field insulation layer (205) may be in contact with the sidewall of the second pin-shaped insulation layer (210F). However, the technical concept of the present invention is not limited thereto.

[0054] Each of the first field liner film (105L) and the second field liner film (205L) may include, for example, silicon nitride. Each of the first field filling film (105F) and the second field filling film (205F) may include, for example, silicon oxide. However, the technical concept of the present invention is not limited thereto.

[0055] At least one first active pattern (AP1) may be formed in the first active region (RX1). The first active pattern (AP1) may be placed on the first pin-shaped insulating layer (110F). The first active pattern (AP1) may be placed on the first pin-shaped insulating layer (110F) and penetrate the gate electrode (120). The first active pattern (AP1) may be spaced apart from the first pin-shaped insulating layer (110F) in a third direction (Z). The first active pattern (AP1) may not be in contact with the first pin-shaped insulating layer (110F). A plurality of first active patterns (AP1) may be spaced apart from each other in a third direction (Z).

[0056] At least one second active pattern (AP2) may be formed in the first active region (RX1). The description of the second active pattern (AP2) may be substantially the same as the description of the first active pattern (AP1).

[0057] The first active pattern (AP1) and the second active pattern (AP2) may each be a multichannel active pattern. In a semiconductor device according to some embodiments, each of the first active pattern (AP1) and the second active pattern (AP2) may be, for example, a sheet pattern.

[0058] Although the first active pattern (AP1) and the second active pattern (AP2) are each depicted as having three, this is for convenience of explanation only and is not limited thereto.

[0059] The first active pattern (AP1) can be connected to the first source / drain pattern (170) by penetrating the gate electrode (120). The second active pattern (AP2) can be connected to the second source / drain pattern (270) by penetrating the gate electrode (120).

[0060] The first active pattern (AP1) and the second active pattern (AP2) may include, for example, elemental semiconductor materials such as silicon or germanium. Additionally, the first active pattern (AP1) and the second active pattern (AP2) may include compound semiconductors, for example, group IV-IV compound semiconductors or group III-V compound semiconductors.

[0061] Group IV-IV compound semiconductors may be, for example, binary compounds, ternary compounds containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds doped with a Group IV element.

[0062] A III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimonium (Sb).

[0063] In some embodiments, the first active pattern (AP1) and the second active pattern (AP2) may contain the same material. In other embodiments, the first active pattern (AP1) and the second active pattern (AP2) may contain different materials.

[0064] A plurality of gate structures (GS) may be disposed on the first and second insulating layers (110, 210). A plurality of gate structures (GS) may be disposed on the first and second lower insulating layers (110B, 210B). A plurality of gate structures (GS) may be disposed on the first pin-shaped insulating layer (110F) and the second pin-shaped insulating layer (210F). At least one gate structure (GS) may extend in the second direction (Y). A plurality of gate structures (GS) may be disposed on the first and second field insulating layers (105, 205). Each of the gate structures (GS) may be spaced apart from each other in the first direction (X).

[0065] The gate structure (GS) can intersect with the first pin-shaped insulating layer (110F) and the second pin-shaped insulating layer (210F).

[0066] Although the gate structure (GS) is depicted as being positioned across the first active region (RX1) and the second active region (RX2), this is for convenience of explanation only and is not limited thereto. That is, some of the gate structure (GS) may be separated into two parts by a gate isolation structure positioned on the first and second field insulation layers (105, 205) and positioned on the first active region (RX1) and the second active region (RX2).

[0067] The gate structure (GS) may include, for example, a gate electrode (120), a gate insulating film (130), a gate spacer (140), and a gate capping pattern (150).

[0068] A gate electrode (120) may be formed on a first pin-shaped insulating layer (110F) and a second pin-shaped insulating layer (210F). The gate electrode (120) may intersect the first pin-shaped insulating layer (110F) and the second pin-shaped insulating layer (210F). The gate electrode (120) may include a long side extended in a second direction (Y) and a short side extended in a first direction (X).

[0069] The upper surface of the gate electrode (120) may be a concave curved surface recessed toward the upper surface of the first and second insulating layers (110, 210), but is not limited thereto. That is, unlike what is illustrated, the upper surface of the gate electrode (120) may be a flat plane.

[0070] The gate electrode (120) is, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum It may include at least one of nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof.

[0071] The gate electrode (120) may include a conductive metal oxide, a conductive metal oxynitride, etc., and may include an oxidized form of the above-described material.

[0072] The gate spacer (140) may be placed on the side wall of the gate electrode (120). The gate spacer (140) may extend in a second direction (Y).

[0073] The gate spacer (140) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0074] The gate insulating film (130) may extend along the sidewalls and bottom surfaces of the gate electrode (120). The gate insulating film (130) may be formed between the gate electrode (120) and the gate spacer (140).

[0075] The gate insulating film (130) may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. High dielectric constant materials may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0076] A semiconductor device according to some embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating film (130) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0077] Ferroelectric film materials can have negative capacitance, while paraelectric film materials can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be smaller than the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance will have a positive value and may be greater than the absolute value of each individual capacitance.

[0078] When a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0079] Ferroelectric material films may have ferroelectric properties. Ferroelectric material films may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0080] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0081] When the ferroelectric material film contains hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0082] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0083] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0084] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0085] Ferroelectric and paraelectric film layers may contain the same material. Ferroelectric film layers possess ferroelectric properties, whereas paraelectric film layers may not. For example, if both ferroelectric and paraelectric film layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film layer is different from the crystal structure of the hafnium oxide contained in the paraelectric film layer.

[0086] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0087] In some embodiments, the gate insulating film (130) may include a single ferroelectric material film. In other embodiments, the gate insulating film (130) may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film (130) may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0088] A gate capping pattern (150) may be disposed on the upper surface of the gate electrode (120) and the upper surface of the gate spacer (140). The gate capping pattern (150) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), and combinations thereof.

[0089] Unlike what is illustrated, the gate capping pattern (150) may be placed between the gate spacers (140). In this case, the upper surface of the gate capping pattern (150) may be placed in the same plane as the upper surface of the gate spacer (140). The upper surface of the gate capping pattern (150) may be the upper surface of the gate structure (GS).

[0090] A first source / drain pattern (170) may be formed on a first fin-shaped insulating layer (110F). The first source / drain pattern (170) may be placed between gate structures (GS). The first source / drain pattern (170) may be placed on the side of a gate structure (GS). The first source / drain pattern (170) may be placed between adjacent gate structures (GS).

[0091] In some embodiments, the first source / drain pattern (170) may be placed on both sides of the gate structure (GS). Unlike what is illustrated, the first source / drain pattern (170) may be placed on one side of the gate structure (GS) and not on the other side of the gate structure (GS).

[0092] A second source / drain pattern (270) may be formed on a second pin-shaped insulating layer (210F). The second source / drain pattern (270) may be placed between gate structures (GS). The second source / drain pattern (270) may be placed on the side of a gate structure (GS). The second source / drain pattern (270) may be placed between adjacent gate structures (GS).

[0093] In some embodiments, the second source / drain pattern (270) may be placed on both sides of the gate structure (GS). Unlike what is illustrated, the second source / drain pattern (270) may be placed on one side of the gate structure (GS) and not on the other side of the gate structure (GS).

[0094] The bottom surface (170_BS) of the first source / drain pattern (170) may be located in the same plane as the bottom surface (GS_BS) of the gate structure (GS). The bottom surface (270_BS) of the second source / drain pattern (270) may protrude from the bottom surface (GS_BS) of the gate structure (GS) toward the second lower insulating layer (210B). That is, the bottom surface (270_BS) of the second source / drain pattern (270) may be a convex curved surface with respect to the second lower insulating layer (210B). However, the technical concept of the present invention is not limited thereto.

[0095] With respect to the upper surface of the lower insulating layer (110B, 210B), the bottom surface of the first source / drain pattern (170) is higher than the bottom surface of the second source / drain pattern (270). The height of the first source / drain pattern (170) in the third direction (Z) is greater than the height of the second source / drain pattern (270) in the third direction (Z). However, the technical concept of the present invention is not limited thereto.

[0096] The first source / drain pattern (170) and the second source / drain pattern (270) may include an epitaxial pattern. That is, the first source / drain pattern (170) may be included in the source / drain region of a transistor using the first active pattern (AP1) as the channel region. The second source / drain pattern (270) may be included in the source / drain region of a transistor using the second active pattern (AP2) as the channel region.

[0097] In some embodiments, the first source / drain pattern (170) and the second source / drain pattern (270) may contain different materials. For example, the first source / drain pattern (170) may contain silicon (Si), and the second source / drain pattern (270) may contain silicon-germanium (SiGe). However, the technical concept of the present invention is not limited thereto.

[0098] In some embodiments, the first protective layer (176) may be disposed on the upper surface (105_US) of the first field insulating layer (105), the sidewall of the gate structure (GS), and the sidewall of the first source / drain pattern (170). The first protective layer (176) may extend to the upper surface of the gate capping pattern (150). The second protective layer (276) may be disposed on the upper surface (205_US) of the second field insulating layer (205), the sidewall of the gate structure (GS), and the sidewall of the second source / drain pattern (270). In other embodiments, although not illustrated, the first protective layer (176) and the second protective layer (276) may not be formed.

[0099] The first protective layer (176) and the second protective layer (276) may include, for example, a material having an etching selectivity with respect to the first interlayer insulating layer (190). The first protective layer (176) and the second protective layer (276) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0100] The first active contact (CA1) may be placed on the first active region (RX1). The second active contact (CA2) may be placed on the second active region (RX2).

[0101] The first active contact (CA1) can be connected to the first source / drain pattern (170) formed in the first active region (RX1). The second active contact (CA2) can be connected to the second source / drain pattern (270) formed in the second active region (RX2).

[0102] In some embodiments, the first active contact (CA1) may include a first lower active contact (180) and a first upper active contact (185).

[0103] The first lower active contact (180) may be formed on the first source / drain pattern (170). The first lower active contact (180) may be connected to the first source / drain pattern (170). Although the upper surface of the first lower active contact (180) is shown as being formed higher than the upper surface of the gate electrode (120), this is for convenience of explanation only and is not limited thereto. Of course, the upper surface of the first lower active contact (180) may be formed lower than the upper surface of the gate electrode (120).

[0104] A first silicide film (175) may be formed between the first lower active contact (180) and the first source / drain pattern (170). Although the first silicide film (175) is illustrated as being formed along the profile of the interface between the first source / drain pattern (170) and the first lower active contact (180), it is not limited thereto. The first silicide film (175) may include, for example, a metal silicide material.

[0105] The first lower active contact (180) may be formed as a multilayer film. The first lower active contact (180) may include, for example, a first lower active contact barrier film (180a) and a first lower active contact filling film (180b). The first lower active contact filling film (180b) may be disposed on the first lower active contact barrier film (180a). The first lower active contact barrier film (180a) may extend along the sidewalls and bottom surfaces of the first lower active contact filling film (180b).

[0106] The first lower active contact barrier film (180a) may comprise, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional (2D) material. In semiconductor devices according to some embodiments, the two-dimensional material may be a metallic material and / or a semiconductor material. The two-dimensional material may include a two-dimensional allotrope or a two-dimensional compound, and may include, for example, at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2), but is not limited thereto. That is, the above-described two-dimensional materials are listed merely as examples, so the two-dimensional material that may be included in the semiconductor device of the present invention is not limited by the above-described material.

[0107] The first lower active contact filling film (160b) may include, for example, at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn) and molybdenum (Mo).

[0108] The first upper active contact (185) may be placed on the first lower active contact (180). The first upper active contact (185) may be connected to the first lower active contact (180). That is, the first upper active contact (185) may be connected to the first source / drain pattern (170).

[0109] The first upper active contact (185) may be formed as a multilayer. The first upper active contact (185) may include, for example, a first upper active contact barrier film (185a) and a first upper active contact filling film (185b). The first upper active contact filling film (185b) may be disposed on the first upper active contact barrier film (185a). The first upper active contact barrier film (185a) may be disposed along the sidewalls and bottom surfaces of the first upper active contact filling film (185b).

[0110] The description of the material included in the first upper active contact barrier film (185a) and the first upper active contact filling film (185b) may be the same as the description of the material included in the first lower active contact barrier film (180a) and the first lower active contact filling film (180b).

[0111] The second active contact (CA2) may include a second lower active contact (280) and a second upper active contact (285). The description of the second lower active contact (280) may be the same as the description of the first lower active contact (180). The description of the second upper active contact (285) may be the same as the description of the first upper active contact (185).

[0112] A second silicide film (275) may be formed between the second lower active contact (280) and the second source / drain pattern (270). Although the second silicide film (275) is illustrated as being formed along the profile of the interface between the second source / drain pattern (270) and the second lower active contact (280), it is not limited thereto. The second silicide film (275) may include, for example, a metal silicide material.

[0113] The second lower active contact (280) may be formed as a multilayer film. The second lower active contact (280) may include, for example, a second lower active contact barrier film (280a) and a second lower active contact filling film (280b). The second lower active contact filling film (280b) may be disposed on the second lower active contact barrier film (280a). The second lower active contact barrier film (280a) may be disposed along the sidewalls and bottom surfaces of the second lower active contact filling film (280b).

[0114] The description of the material included in the second lower active contact barrier film (280a) and the second lower active contact filling film (280b) may be the same as the description of the material included in the first lower active contact barrier film (180a) and the first lower active contact filling film (180b).

[0115] The second upper active contact (285) may be placed on the second lower active contact (280). The second upper active contact (285) may be connected to the second lower active contact (280). That is, the second upper active contact (285) may be connected to the second source / drain pattern (270).

[0116] The second upper active contact (285) may be formed as a multilayer. The second upper active contact (285) may include, for example, a second upper active contact barrier film (285a) and a second upper active contact filling film (285b). The second upper active contact filling film (285b) may be disposed on the second upper active contact barrier film (285a). The second upper active contact barrier film (285a) may be disposed along the sidewalls and bottom surfaces of the second upper active contact filling film (285b).

[0117] The description of the material included in the second upper active contact barrier film (285a) and the second upper active contact filling film (285b) may be the same as the description of the material included in the first lower active contact barrier film (180a) and the first lower active contact filling film (180b).

[0118] The first gate contact (160) may be placed on the first active region (RX1). The second gate contact (260) may be placed on the second active region (RX2). Since the first gate contact (160) and the second gate contact (260) may be substantially the same, only the first gate contact (160) will be described below.

[0119] The first gate contact (160) may be disposed within the gate structure (GS). The first gate contact (160) may be connected to the gate electrode (120) included in the gate structure (GS). The first gate contact (160) may be formed by penetrating the gate capping pattern (150) in a third direction (Z).

[0120] The first gate contact (160) may be positioned in a location overlapping with the gate structure (GS). In some embodiments, at least a portion of the first gate contact (160) may be positioned in a location overlapping with the first active pattern (AP1).

[0121] The upper surface of the first gate contact (160) may be placed in the same plane as the upper surface of the gate capping pattern (150). The upper surface of the first gate contact (160) may be located in the same plane as the upper surface of the second upper active contact (285).

[0122] The first gate contact (160) may be formed as a multilayer film. The first gate contact (160) may include, for example, a gate contact barrier film (160a) and a gate contact filling film (160b). The gate contact filling film (160b) may be disposed on the gate contact barrier film (160a). The gate contact barrier film (160a) may be disposed along the sidewalls and bottom surfaces of the gate contact filling film (160b).

[0123] The description of the material included in the gate contact barrier film (160a) and the gate contact filling film (160b) may be the same as the description of the material included in the first lower active contact barrier film (180a) and the first lower active contact filling film (180b), respectively.

[0124] The first interlayer insulating layer (190) may be formed on the first source / drain pattern (170), the second source / drain pattern (270), the first field insulating layer (105), and the second field insulating layer (205). The first interlayer insulating layer (190) may cover the sidewalls of the first lower active contact (180), the sidewalls of the first upper active contact (185), the sidewalls of the second lower active contact (280), and the sidewalls of the second upper active contact (285).

[0125] The first interlayer insulating layer (190) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Low dielectric constant materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped Silicon Oxide), OSG (Organo Silicate) Glass), SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, It may include mesoporous silica or a combination thereof, but is not limited thereto.

[0126] In some embodiments, a second interlayer insulating layer (390) and a third interlayer insulating layer (490) may be formed on the first interlayer insulating layer (190).

[0127] Each of the second interlayer insulating layer (390) and the third interlayer insulating layer (490) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0128] In some embodiments, the wiring etch stop layer (195) may extend along the upper surface of the gate capping pattern (150) and the upper surface of the first interlayer insulating layer (190). A second interlayer insulating layer (390) may be disposed on the wiring etch stop layer (195). The wiring etch stop layer (195) may comprise a material having an etch selectivity ratio with respect to the second interlayer insulating layer (390). The wiring etch stop layer (195) may comprise, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), aluminum nitride (AlN) and aluminum carbonitride (AlOC) and combinations thereof.

[0129] A first wiring pattern (310) may be placed on a first gate contact (160) and a second upper active contact (285). The first wiring pattern (310) may be connected to the first gate contact (160). The first wiring pattern (310) may be connected to the second upper active contact (285). The first wiring pattern (310) may be formed by penetrating a wiring etch stop layer (195).

[0130] The first wiring pattern (310) may be placed within the second interlayer insulation layer (390). The first wiring pattern (310) may include a portion that is in direct contact with the gate capping pattern (150).

[0131] The first wiring pattern (310) may have a multi-conductive film structure. The first wiring pattern (310) may include, for example, a first wiring barrier film (310a) and a first wiring filling film (310b). The first wiring filling film (310b) may be disposed on the first wiring barrier film (310a). The first wiring barrier film (310a) may be disposed along the sidewalls and bottom surfaces of the first wiring filling film (310b).

[0132] The first wiring barrier film (310a) may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), nickel (Ni), nickel boron (NiB), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional (2D) material.

[0133] The first wiring filling film (310b) may include, for example, at least one of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn) and molybdenum (Mo).

[0134] In some embodiments, a via structure (410) and a second wiring pattern (420) may be included on the first wiring pattern (310). The via structure (410) and the second wiring pattern (420) may be disposed within a third interlayer insulating layer (490).

[0135] A via structure (410) may be formed on a first wiring pattern (310). The via structure (410) may be connected to the first wiring pattern (310). The via structure (410) may be a multilayer film comprising a via barrier film (410a) and a via filling film (410b). The via filling film (410b) may be disposed on the via barrier film (410a). The via barrier film (410a) may be disposed along the sidewalls and bottom surfaces of the via filling film (410b).

[0136] The via barrier film (410a) may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional (2D) material.

[0137] The via filling film (410b) may include, for example, at least one of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn) and molybdenum (Mo).

[0138] The second wiring pattern (420) may be placed on the via structure (410). The second wiring pattern (420) may be a multilayer film comprising a second wiring barrier film (420a) and a second wiring filling film (420b).

[0139] The second wiring filling film (420b) may be placed on the second wiring barrier film (420a). The second wiring barrier film (420a) may be placed along the side walls and bottom surface of the second wiring filling film (420b). The description of the material contained in the second wiring barrier film (420a) and the second wiring filling film (420b) may be the same as the description of the material contained in the first wiring barrier film (310a) and the first wiring filling film (310b).

[0140] FIG. 5 is a drawing for explaining a semiconductor device according to some embodiments. For convenience of explanation, the explanation will focus on the differences from the explanation using FIG. 1 to 4. For reference, FIG. 5 may be a cross-sectional view taken along AA' and B-B' of FIG. 1.

[0141] Referring to FIG. 5, the bottom surface (170_BS) of the first source / drain pattern (170) can be superimposed with the gate structure (GS) in the first direction (X).

[0142] In some embodiments, the bottom surface (170_BS) of the first source / drain pattern (170) may be formed higher than the bottom surface (GS_BS) of the gate structure (GS). That is, with respect to the upper surface of the lower insulating layer (110B, 210B), the bottom surface (170_BS) of the first source / drain pattern (170) may be higher than the bottom surface (GS_BS) of the gate structure (GS). The bottom surface (170_BS) of the first source / drain pattern (170) may overlap with the gate electrode (120) in the first direction (X). Although not illustrated, the bottom surface (170_BS) of the first source / drain pattern (170) may overlap with the gate insulating film (130) in the first direction (X).

[0143] In some embodiments, at least a portion of the first fin-shaped insulating layer (110F) may overlap with the gate structure (GS) in the first direction (X). At least a portion of the first fin-shaped insulating layer (110F) may overlap with the gate electrode (120) in the first direction (X). At least a portion of the first fin-shaped insulating layer (110F) may overlap with the gate insulating film (130) in the first direction (X). During the process of removing the silicon substrate, the first source / drain pattern (170) may be excessively recessed so that the bottom surface (170_BS) of the first source / drain pattern (170) is formed higher than the bottom surface (GS_BS) of the gate structure (GS).

[0144] FIG. 6 is a drawing for explaining a semiconductor device according to some embodiments. For convenience of explanation, the explanation will focus on the differences from the explanation using FIG. 1 to 4. For reference, FIG. 6 may be a cross-sectional view taken along AA' and B-B' of FIG. 1.

[0145] Referring to FIG. 6, the bottom surface (170_BS) of the first source / drain pattern (170) may be located in the same plane as the bottom surface of the first active pattern (AP1).

[0146] The upper surface (110F_US) of the first fin-shaped insulating layer (110F) may be located in the same plane as the bottom surface of the first active pattern (AP1). The first fin-shaped insulating layer (110F) does not overlap with the first active pattern (AP1) in the first direction (X). At least a portion of the first fin-shaped insulating layer (110F) may overlap with the gate electrode (120) and the gate insulating film (130) in the first direction (X). The first active pattern (AP1) may completely overlap with the first source / drain pattern (170) in the first direction (X).

[0147] FIG. 7 is a drawing for explaining a semiconductor device according to some embodiments. For convenience of explanation, the explanation will focus on the differences from the explanation using FIG. 1 to 4. For reference, FIG. 7 may be a cross-sectional view taken along AA' and B-B' of FIG. 1.

[0148] Referring to FIGS. 1 and 7, the gate spacer (140) of the first active region (RX1) may include an outer spacer (141) and an inner spacer (142). The gate spacer (140) of the second active region (RX2) may not include an inner spacer.

[0149] In some embodiments, the transistor formed in the first active region (RX1) may be an NMOS. The transistor formed in the second active region (RX2) may be a PMOS. In the case of an NMOS, the gate spacer (140) may include an inner spacer (142). In the case of a PMOS, the gate spacer (140) may not include an inner spacer.

[0150] FIG. 8 is a drawing for explaining a semiconductor device according to some embodiments. For convenience of explanation, the explanation will focus on the differences from the explanation using FIG. 1 to 4. For reference, FIG. 8 may be a cross-sectional view taken along AA' and B-B' of FIG. 1.

[0151] Referring to FIG. 8, the bottom surface (170_BS) of the first source / drain pattern (170) can be formed lower than the bottom surface (GS_BS) of the gate structure (GS).

[0152] For example, with respect to the upper surface of the lower insulating layer (110B, 210B), the bottom surface (170_BS) of the first source / drain pattern (170) may be lower than the bottom surface (GS_BS) of the gate structure (GS).

[0153] At least a portion of the first source / drain pattern (170) may overlap with the first pin-shaped insulating layer (110F) in the first direction (X). The first pin-shaped insulating layer (110F) may not overlap with the gate structure (GS) in the first direction (X).

[0154] The bottom surface (170_BS) of the first source / drain pattern (170) is depicted as convex with respect to the first lower insulating layer (110B), but this is for convenience of explanation only and is not limited thereto.

[0155] In some embodiments, the bottom surface (170_BS) of the first source / drain pattern (170) may be higher than the bottom surface (270_BS) of the second source / drain pattern (270). That is, with respect to the upper surface of the lower insulating layer (110B, 210B), the bottom surface (170_BS) of the first source / drain pattern (170) may be higher than the bottom surface (270_BS) of the second source / drain pattern (270). The height of the first source / drain pattern (170) in the third direction (Z) may be smaller than the height of the second source / drain pattern (270) in the third direction (Z).

[0156] FIG. 9 is a drawing for explaining a semiconductor device according to some embodiments. FIG. 10 is a drawing for explaining a semiconductor device according to some embodiments. For convenience of explanation, the explanation will focus on the differences from the explanation using FIG. 1 to 4. For reference, FIG. 9 may be a cross-sectional view taken along AA' and B-B' of FIG. 1. FIG. 10 may be a cross-sectional view taken along CC' and D-D' of FIG. 1.

[0157] Referring to FIGS. 9 and 10, the bottom surface (270_BS) of the second source / drain pattern (270) may be located in the same plane as the bottom surface (GS_BS) of the gate structure (GS).

[0158] For example, the bottom surface (170_BS) of the first source / drain pattern (170), the bottom surface (GS_BS) of the gate structure (GS), and the bottom surface (270_BS) of the second source / drain pattern (270) may be located on the same plane. The bottom surface (270_BS) of the second source / drain pattern (270) may be a flat plane with respect to the upper surface of the second lower insulating layer (210B).

[0159] The height of the first source / drain pattern (170) in the third direction (Z) may be the same as the height of the second source / drain pattern (270) in the third direction (Z).

[0160] FIG. 11 is a drawing for explaining a semiconductor device according to some embodiments. FIG. 12 is a drawing for explaining a semiconductor device according to some embodiments. For convenience of explanation, the explanation will focus on the differences from the explanation using FIG. 1 to 4. For reference, FIG. 11 may be a cross-sectional view taken along CC' and D-D' of FIG. 1. FIG. 12 may be a cross-sectional view taken along E-E' of FIG. 1.

[0161] Referring to FIGS. 11 and 12, the first field insulating layer (105) and the second field insulating layer (205) may not each include the first field liner film (105L) and the second field liner film (205L).

[0162] That is, the first field insulation layer (105) and the second field insulation layer (205) may be a single layer. The upper surface (105_US) of the first field insulation layer (105) may be a convex curved surface with respect to the first lower insulation layer (110B). Accordingly, a person skilled in the art can distinguish between the first pin-shaped insulation layer (110F) and the first field insulation layer (105).

[0163] The upper surface (205_US) of the second field insulation layer (205) may be a convex curved surface with respect to the second lower insulation layer (110B). Likewise, a person skilled in the art can distinguish between the second pin-shaped insulation layer (210F) and the second field insulation layer (205).

[0164] The first field insulating layer (105) and the second field insulating layer (205) may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

[0165] FIGS. 13a and FIGS. 13b are drawings for illustrating a semiconductor device according to some embodiments. For convenience of explanation, the description will focus on the differences from the description using FIGS. 1 to 4. For reference, FIG. 13a may be a cross-sectional view taken along AA' and B-B' of FIG. 1. FIG. 13b may be a cross-sectional view taken along CC' and D-D' of FIG. 1.

[0166] Referring to FIGS. 13a and 13b, the first upper active contact (185) and the second upper active contact (285) can be formed as a single film.

[0167] The first lower active contact liner (180a) may extend to the upper surface of the gate capping pattern (150) and the upper surface of the first interlayer insulating layer (190). The second lower active contact liner (280a) may extend to the upper surface of the gate capping pattern (150) and the upper surface of the first interlayer insulating layer (190).

[0168] In some embodiments, the semiconductor device of the present invention may further include a via contact (305). The via contact (305) may connect the first gate contact (160) and the first wiring pattern (310) in the first active region (RX1). The via contact (305) may connect the second active contact (CA2) and the first wiring pattern (310) in the second active region (RX2).

[0169] The via contact (305) may be a multilayer film comprising a via contact barrier film (305a) and a via contact filling film (305b). The via contact filling film (305b) may be disposed on the via contact barrier film (305a). The via contact barrier film (305a) may be disposed along the sidewalls and bottom surfaces of the via contact filling film (305b).

[0170] The via contact barrier film (305a) may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and a two-dimensional (2D) material.

[0171] The via contact filling film (305b) may include, for example, at least one of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn) and molybdenum (Mo).

[0172] FIG. 14 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 15 is a cross-sectional view taken along FF' and G-G' of FIG. 14. FIG. 16 is a cross-sectional view taken along HH' and I-I' of FIG. 14. FIG. 17 is a cross-sectional view taken along J-J' of FIG. 14. For convenience of explanation, the description will focus on the differences from the description using FIG. 1 to 4.

[0173] Referring to FIGS. 14 to 17, in a semiconductor device according to some embodiments, the first active pattern (AP1) and the second active pattern (AP2) may include a pin-shaped pattern.

[0174] In FIGS. 14 and 16, the first active pattern (AP1) and the second active pattern (AP2) are each depicted as having three, but this is for convenience of explanation only and is not limited thereto. The first active pattern (AP1) and the second active pattern (AP2) may each have one or more.

[0175] As illustrated in FIGS. 14 and 16, the field region (FX) may be defined by a deep trench (DT), but is not limited thereto. Additionally, it is obvious that a person skilled in the art to which the present invention pertains can distinguish which part is the field region and which part is the active region.

[0176] A first field insulation layer (105) may be formed on a first lower insulation layer (110B). A second field insulation layer (205) may be formed on a second lower insulation layer (210B). The first and second field insulation layers (105, 205) may be formed across a first active region (RX1), a second active region (RX2), and a field region (FX). The first and second field insulation layers (105, 205) may fill a deep trench (DT).

[0177] In FIG. 15, the first pin-shaped insulating layer (110F) may be in contact with the first active pattern (AP1). The first active pattern (AP1) may be positioned between the bottom surface (GS_BS) of the gate structure (GS) and the top surface (110F_US) of the first pin-shaped insulating layer (110F). The top surface (110F_US) of the first pin-shaped pattern (110F) may be located in the same plane as the bottom surface of the first active pattern (AP1) and the bottom surface (170_BS) of the first source / drain pattern (170). However, the technical concept of the present invention is not limited thereto.

[0178] Although not illustrated, at least a portion of the first pin-shaped insulating layer (110F) may overlap with the first source / drain pattern (170) in the first direction (X).

[0179] The second pin-shaped insulating layer (210F) may be in contact with the second active pattern (AP2). The second active pattern (AP2) may be positioned between the bottom surface (GS_BS) of the gate structure (GS) and the top surface (210F_US) of the second pin-shaped insulating layer (210F). The top surface (210F_US) of the second pin-shaped insulating layer (210F) may be formed higher than the bottom surface (270_BS) of the second source / drain pattern (270). With respect to the top surface of the second lower insulating layer (210B), the top surface (210F_US) of the second pin-shaped insulating layer (210F) may be higher than the bottom surface (270_BS) of the second source / drain pattern (270). However, the technical concept of the present invention is not limited thereto.

[0180] The first source / drain pattern (170) and the second source / drain pattern (270) are illustrated as being formed by merging three epitaxial patterns formed on each of the first active pattern (AP1) and the second active pattern (AP2), but this is for convenience of explanation only and is not limited thereto. That is, the epitaxial patterns formed on each of the first active pattern (AP1) and the second active pattern (AP2) may be separated from each other.

[0181] In some embodiments, an air gap may be placed in the space between the first source / drain pattern (170) combined with the first field insulation layer (105). An air gap may be placed in the space between the second source / drain pattern (270) combined with the second field insulation layer (205). As another example, an insulating material may be filled in the space between the first source / drain pattern (170) combined with the first field insulation layer (105). An insulating material may be filled in the space between the second source / drain pattern (270) combined with the second field insulation layer (205).

[0182] In some embodiments, the first field liner membrane (105L) may not be placed on the sidewalls and bottom surface of the deep trench (DT). The second field liner membrane (205L) may not be placed on the sidewalls and bottom surface of the deep trench (DT). However, the technical concept of the present invention is not limited thereto.

[0183] FIGS. 18 to 35 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. A method of manufacturing a semiconductor device according to some embodiments is explained using FIGS. 18 to 35.

[0184] Referring to FIGS. 18 to 20, a gate structure (GS), a first source / drain pattern (170), a first active pattern (AP1), a first active contact (CA1), and a first gate contact (160) may be formed on a first substrate (100).

[0185] On the second substrate (200), a gate structure (GS), a second source / drain pattern (270), a second active pattern (AP2), and a second active contact (CA2) may be formed.

[0186] The first substrate (100) may include a first lower substrate (100B) and a first pin-shaped substrate (100F). The second substrate (200) may include a second lower substrate (200B) and a second pin-shaped substrate (200F).

[0187] The first pin-shaped substrate (100F) may extend in a first direction (X) on the first lower substrate (100B). The second pin-shaped substrate (200F) may extend in a first direction (X) on the second lower substrate (200B). For example, the first pin-shaped substrate (100F) and the second pin-shaped substrate (200F) may include a long side extending in the first direction (X) and a short side extending in the second direction (Y).

[0188] The first lower substrate (100B) and the second lower substrate (200B) may be, for example, a silicon substrate or a silicon-on-insulator (SOI). Alternatively, the first lower substrate (100B) and the second lower substrate (200B) may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but are not limited thereto.

[0189] The first pin-shaped substrate (100F) and the second pin-shaped substrate (200F) may each be part of the first lower substrate (100B) and the second lower substrate (200B), and may include an epitaxial layer grown from the first lower substrate (100B) and the second lower substrate (200B).

[0190] The first pin-shaped substrate (100F) and the second pin-shaped substrate (200F) may include, for example, silicon or germanium, which are elemental semiconductor materials. Additionally, the first pin-shaped substrate (100F) and the second pin-shaped substrate (200F) may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0191] Group IV-IV compound semiconductors may be, for example, binary compounds, ternary compounds containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds doped with a Group IV element.

[0192] A III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimonium (Sb).

[0193] At least one gate structure (GS) may be formed on a first pin-shaped substrate (100F) and a second pin-shaped substrate (200F). At least one gate structure (GS) may intersect the first pin-shaped substrate (100F) and the second pin-shaped substrate (200F). At least one gate structure (GS) may extend in a second direction (Y) that intersects the first pin-shaped substrate (100F) and the second pin-shaped substrate (200F). The gate structure (GS) may include a long side extending in the second direction (Y) and a short side extending in the first direction (X).

[0194] The first source / drain pattern (170) and the second source / drain pattern (270) can be formed between the gate structure (GS) on the first substrate (100) and the second substrate (200).

[0195] Referring to FIGS. 21 to 23, a support substrate (10, 20) may be formed on the third interlayer insulating layer (490). The support substrate (10, 20) may serve to support the semiconductor device of the present invention during the process of forming the first and second insulating layers (110, 210).

[0196] The first support substrate (10) may be formed on the third interlayer insulating layer (490) of the first active region (RX1). The second support substrate (20) may be formed on the third interlayer insulating layer (490) of the second active region (RX2).

[0197] The first support substrate (10) and the second support substrate (20) may include, for example, silicon. However, the technical concept of the present invention is not limited thereto.

[0198] Referring to FIGS. 24 to 26, the first lower substrate (100B) and the second lower substrate (200B) can be removed.

[0199] The first lower substrate (100B) may be removed to expose the first pin-shaped substrate (100F). The second lower substrate (200B) may be removed to expose the second pin-shaped substrate (100F). The first lower substrate (100B) may be removed to expose the first field insulation layer (105). The second lower substrate (200B) may be removed to expose the second field insulation layer (205).

[0200] The first lower substrate (100B) and the second lower substrate (200B) may be removed, for example, using a chemical mechanical polishing (CMP) process. However, the technical concept of the present invention is not limited thereto.

[0201] Referring to FIGS. 27 to 29, the first pin-shaped substrate (100F) and the second pin-shaped substrate (200F) can be removed.

[0202] The first pin-shaped substrate (100F) and the second pin-shaped substrate (200F) can be removed to expose the first source / drain pattern (170), the second source / drain pattern (270), and the gate insulating film (130).

[0203] The first pin-shaped substrate (100F) and the second pin-shaped substrate (200F) can be removed using a dry etching process. Due to the difference in etching selectivity between the first pin-shaped substrate (100F) and the first field insulating layer (105), the first field insulating layer (105) may not be removed when the first pin-shaped substrate (100F) is removed. Similarly, due to the difference in etching selectivity between the second pin-shaped substrate (200F) and the second field insulating layer (205), the second field insulating layer (205) may not be removed when the second pin-shaped substrate (200F) is removed.

[0204] In some embodiments, during the process of removing the first pin-shaped substrate (100F), a portion of the first source / drain pattern (170) may be removed. On the other hand, during the process of removing the second pin-shaped substrate (200F), the second source / drain pattern (270) may not be removed.

[0205] Due to the difference in properties between the material included in the first source / drain pattern (170) and the material included in the second source / drain pattern (270), the second source / drain pattern (270) may not be selectively removed. However, the technical concept of the present invention is not limited thereto.

[0206] Unlike what is described, the first lower substrate (100B) and the first pin-shaped substrate (100F) may not be removed using a separate process. The first lower substrate (100B) and the first pin-shaped substrate (100F) may be removed simultaneously. In this case, the first substrate (100) may be removed using a dry etching process.

[0207] Likewise, the second lower substrate (200B) and the second pin-shaped substrate (200F) may not be removed using a separate process. The second lower substrate (200B) and the second pin-shaped substrate (200F) may be removed simultaneously. In this case, the second substrate (200) may be removed using a dry etching process.

[0208] Referring to FIGS. 30 to 32, a first insulating layer (110) may be formed on a first source / drain pattern (170) and a first field insulating layer (105).

[0209] A second insulating layer (210) may be formed on the second source / drain pattern (270) and the second field insulating layer (205).

[0210] The first insulating layer (110) may include a first pin-shaped insulating layer (110F) and a first lower insulating layer (110B). The first pin-shaped insulating layer (110F) may be a portion that overlaps with the first field insulating layer (105) in the second direction (Y). The first lower insulating layer (110B) may be a portion that does not overlap with the first field insulating layer (105) in the second direction (Y).

[0211] The second insulating layer (210) may include a second pin-shaped insulating layer (210F) and a second lower insulating layer (210B). The second pin-shaped insulating layer (210F) may be a portion that overlaps with the second field insulating layer (205) in the second direction (Y). The second lower insulating layer (210B) may be a portion that does not overlap with the second field insulating layer (205) in the second direction (Y).

[0212] Referring to FIGS. 33 to 35, the first support substrate (10) and the second support substrate (20) can be removed.

[0213] Although not illustrated, after removing the first support substrate (10) and the second support substrate (20), a semiconductor device according to some embodiments of the present invention can be manufactured by rotating 180°.

[0214] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0215] 105: First field insulation layer 205: Second field insulation layer 110: First insulating layer 210: Second insulating layer 110B: First lower insulating layer 210B: Second lower insulating layer 110F: First pin-shaped insulating layer 210F: Second pin-shaped insulating layer 170: 1st Source / Drain Pattern 270: 2nd Source / Drain Pattern 120: Gate electrode

Claims

Claim 1 A semiconductor device comprising: a lower insulating layer; a fin-shaped insulating layer extending in a first direction on the lower insulating layer, wherein the fin-shaped insulating layer protrudes above the upper surface of the lower insulating layer; a field insulating layer extending in the first direction on the lower insulating layer and disposed between the fin-shaped insulating layers; a plurality of gate structures on the fin-shaped insulating layer, each gate structure including a gate electrode intersecting the fin-shaped insulating layer, wherein the gate electrode extends in a second direction intersecting the first direction; a source / drain pattern disposed between the gate structures on the fin-shaped insulating layer; and an active pattern on the fin-shaped insulating layer penetrating the gate electrode and connected to the source / drain pattern, wherein at least a portion of the source / drain pattern overlaps with the fin-shaped insulating layer in the first direction. Claim 2 In claim 1, the field insulating layer comprises a field liner film defining a field recess and a field filling film on the field liner film, and the field filling film fills the field recess. Claim 3 A semiconductor device according to claim 2, wherein the field liner film comprises a horizontal portion defining the bottom surface of the field recess and a vertical portion defining the side wall of the field recess, wherein the horizontal portion of the field liner film contacts the lower insulating layer and the vertical portion of the field liner film contacts the fin-shaped insulating layer. Claim 4 A semiconductor device according to claim 1, wherein the upper surface of the field insulating layer is convex with respect to the upper surface of the lower insulating layer. Claim 5 A semiconductor device according to claim 1, wherein at least a portion of the fin-shaped insulating layer overlaps with the gate structure in the first direction. Claim 6 In claim 1, the active pattern is a semiconductor device that is not in contact with the fin-shaped insulating layer. Claim 7 A semiconductor device comprising: an insulating layer; a trench disposed within the insulating layer and extending in a first direction; a field insulating layer filling the trench; a gate electrode on the insulating layer extending in a second direction intersecting the first direction; a source / drain pattern disposed between the gate electrodes on the insulating layer; and an active pattern penetrating the gate electrode and connected to the source / drain pattern, wherein the insulating layer comprises a first portion overlapping the field insulating layer in a third direction intersecting the first direction and the second direction, and a second portion not overlapping the field insulating layer in the third direction, and the bottom surface of the source / drain pattern contacting the second portion of the insulating layer. Claim 8 In claim 7, the field insulating layer comprises a field liner film disposed along the sidewall and bottom surface of the trench and a field filling film on the field liner film, and the field filling film fills the trench remaining after filling the field liner film. Claim 9 A lower insulating layer comprising a first region and a second region; a plurality of first pin-shaped insulating layers extending in a first direction on the lower insulating layer of the first region; a plurality of second pin-shaped insulating layers extending in the first direction on the lower insulating layer of the second region; a plurality of gate structures comprising gate electrodes intersecting the first and second pin-shaped insulating layers on the first and second pin-shaped insulating layers, wherein the gate electrodes are a plurality of gate structures extending in a second direction intersecting the first direction; a first source / drain pattern disposed between the gate structures on the first pin-shaped insulating layer; a second source / drain pattern disposed between the gate structures on the second pin-shaped insulating layer; a first active pattern on the first pin-shaped insulating layer penetrating the gate electrode and connected to the first source / drain pattern; A semiconductor device comprising a second active pattern that penetrates the gate electrode and is connected to the second source / drain pattern on the second pin-shaped insulating layer, wherein, with respect to the upper surface of the lower insulating layer, the bottom surface of the first source / drain pattern is higher than the bottom surface of the second source / drain pattern. Claim 10 A semiconductor device according to claim 9, wherein the first source / drain pattern is non-overlapping with the first fin-shaped insulating layer in the first direction, and at least a portion of the second source / drain pattern overlaps with the second fin-shaped insulating layer in the first direction.

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