Semiconductor device and method of fabricating the same

Abstract

A semiconductor device is provided comprising a semiconductor substrate including a device region and an edge region, a semiconductor device provided in the device region of the semiconductor substrate, a metal structure provided in the edge region of the semiconductor substrate, an insulating film covering the semiconductor device and the metal structure on the semiconductor substrate, and a pad disposed on the semiconductor device in the device region, wherein the metal structure may be embedded by the insulating film and not exposed on the side of the insulating film, and the metal structure may be electrically insulated from the semiconductor device.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including a test pattern on a scribe lane area and a method for manufacturing the same. Background Technology

[0002] Generally, a wafer on which semiconductor devices are formed is divided into a chip area where multiple cells are formed and a scribe lane to separate the chips. Multiple semiconductor devices, such as transistors, resistors, and capacitors, are formed on the chip area, while semiconductor devices are not formed on the scribe lane; instead, they are sawed along the scribe lane to be completed as individual chips. Test patterns or alignment keys for the photolithography process may be placed in the scribe lane to monitor whether the process has proceeded normally by monitoring the electrical characteristics and the presence of defective patterns of the semiconductor devices provided in the chip area. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor device with improved structural stability and a method for manufacturing the same.

[0004] Another problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor device with a low occurrence of defects and a semiconductor device manufactured thereby.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A semiconductor device according to embodiments of the present invention for solving the aforementioned technical problems may include a semiconductor substrate comprising a device region and an edge region, a semiconductor device provided in the device region of the semiconductor substrate, a metal structure provided in the edge region of the semiconductor substrate, an insulating film covering the semiconductor device and the metal structure on the semiconductor substrate, and a pad disposed on the semiconductor device in the device region. The metal structure may be embedded by the insulating film and may not be exposed on the side of the insulating film. The metal structure may be electrically insulated from the semiconductor device.

[0007] A semiconductor device according to embodiments of the present invention for solving the aforementioned technical problems may include a semiconductor substrate comprising a device region and an edge region surrounding the device region, a semiconductor device provided on the upper surface of the semiconductor substrate on the device region, a metal structure provided on the upper surface of the semiconductor substrate on the edge region, a wiring layer on the semiconductor device and the metal structure, and a pad disposed on the wiring layer on the device region and electrically connected to the wiring layer. The metal structure may be spaced apart from the side of the semiconductor substrate in a direction facing the interior of the semiconductor substrate.

[0008] A method for manufacturing a semiconductor device according to embodiments of the present invention for solving the aforementioned technical problems may include providing a semiconductor substrate having a first element region, a second element region, and a scribe lane between the first and second element regions; forming semiconductor elements on the first and second element regions of the semiconductor substrate; forming metal structures on the scribe lane of the semiconductor substrate; the metal structures being spaced apart from each other in a first direction toward the first element region toward the second element region; forming an insulating film covering the semiconductor elements and the metal structures on the semiconductor substrate; forming a wiring layer electrically connected to the semiconductor elements on the insulating film; and cutting the semiconductor substrate and the insulating film on the scribe lane to separate the semiconductor elements. When separating the semiconductor elements, the metal structures may not be cut. Effects of the invention

[0009] In a semiconductor device according to embodiments of the present invention, when shock or stress is applied from one side of the semiconductor device toward a semiconductor element, a metal structure can act as a barrier to mitigate said shock or stress and can protect the semiconductor element from said shock or stress. Additionally, the metal structure can absorb a large amount of said shock or stress even if it is damaged. Therefore, the semiconductor element can be more robustly protected from said shock or stress, and a semiconductor device with improved structural stability can be provided.

[0010] In the method for manufacturing a semiconductor device according to embodiments of the present invention, since the metal structures are spaced apart from the laser cutting line by a certain distance or more, the metal structures may not be cut by the laser. Therefore, fracture may not occur at the interface between the semiconductor substrate and the metal structures, or at the interface between the metal structures and the insulating film between the device layers. That is, the metal structures may not be impacted by the laser, and the metal structures may not peel off from the semiconductor substrate during the sawing process, nor may bonding defects occur at the bonding surface between the metal structures or the insulating film between the device layers and the semiconductor substrate. Accordingly, defects may not occur during the manufacturing process of the semiconductor device. Brief explanation of the drawing

[0011] FIG. 1 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. FIGS. 2 and FIGS. 3 are cross-sectional views for illustrating a semiconductor device according to embodiments of the present invention. FIG. 4 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. Figure 5 is a plan view of a wafer. FIGS. 6a to 10a are plan views for illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 6b to 10b are cross-sectional views illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention. FIG. 7c is a plan view illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 11a and FIGS. 12a are plan views for comparing and explaining the manufacturing method of a semiconductor device. FIGS. 11b and FIGS. 12b are cross-sectional views for comparing and explaining the manufacturing method of a semiconductor device. Specific details for implementing the invention

[0012] A semiconductor device according to the concept of the present invention is described with reference to the drawings.

[0013] FIG. 1 is a plan view for explaining a semiconductor device according to embodiments of the present invention, and for convenience of explanation, the configuration of the wiring layer and the protective film among the components of the semiconductor device is omitted. FIG. 2 is a cross-sectional view for explaining a semiconductor device according to embodiments of the present invention, and FIG. 2 corresponds to a cross-section cut along line I-I' of FIG. 1.

[0014] Referring to FIGS. 1 and FIGS. 2, the semiconductor device (1) may include a semiconductor substrate (10) and a circuit structure (CS) disposed on the semiconductor substrate (10).

[0015] A semiconductor substrate (10) may be provided. The semiconductor substrate (10) may include a semiconductor material. For example, the semiconductor substrate (10) may be a silicon (Si) single-crystal substrate.

[0016] A semiconductor substrate (10) may have a device region (DR) and an edge region (ER). In a planar view, the device region (DR) may be located at the center of the semiconductor substrate (10), and the edge region (ER) may surround the device region (DR). The semiconductor substrate (10) may have a first surface (10a) and a second surface (10b) facing each other. The first surface (10a) of the semiconductor substrate (10) may be the front surface of the semiconductor substrate (10), and the second surface (10b) may be the rear surface of the semiconductor substrate (10). Here, the front surface (10a) of the semiconductor substrate (10) is defined as one side of the semiconductor substrate (10) on which semiconductor devices are mounted or wiring, pads, etc. are formed, and the rear surface (10b) of the semiconductor substrate (10) may be defined as the opposite side facing the front surface.

[0017] A circuit structure (CS) may be disposed on a semiconductor substrate (10). The circuit structure (CS) may include a device layer (DL), a wiring layer (IL), and a protective film (PL) that are sequentially stacked on a first surface (10a) of the semiconductor substrate (10).

[0018] The device layer (DL) may include a semiconductor device (20) and a metal structure (30).

[0019] A semiconductor device (20) may include transistors (TR) provided on a first surface (10a) in a device region (DR) of a semiconductor substrate (10). For example, the transistors (TR) may include a source and a drain formed on the upper surface of the semiconductor substrate (10), a gate electrode disposed on the first surface (10a) of the semiconductor substrate (10), and a gate insulating film interposed between the semiconductor substrate (10) and the gate electrode. Although FIG. 2 illustrates the provision of a single transistor (TR), the present invention is not limited thereto. The semiconductor device (20) may include a plurality of transistors (TR). As an example, although not illustrated, the semiconductor device (20) may be composed of a shallow device isolation pattern, a logic cell, or a plurality of memory cells on the first surface (10a) in the device region (DR). Alternatively, the semiconductor device (20) may include passive components such as a capacitor. The semiconductor device (20) may not be placed on the edge region (ER) of the semiconductor substrate (10).

[0020] A metal structure (30) may be provided on a first surface (10a) at an edge region (ER) of a semiconductor substrate (10). The metal structure (30) may be in contact with the first surface (10a) of the semiconductor substrate (10). The metal structure (30) may be a test pattern for testing the semiconductor device (1) during the manufacturing process of the semiconductor device (1). For example, the metal structure (30) may include a test capacitor. In the embodiments of the present invention, the metal structure (30) is referred to as a metal structure for convenience of explanation, but the present invention is not limited thereto. The metal structure (30) may not necessarily include only metal and may include various elements or structures for testing the semiconductor device (1).

[0021] A metal structure (30) may be disposed on one side of a semiconductor device (20). A plurality of metal structures (30) may be provided, and each of the metal structures (30) may be located on one of the sides of the semiconductor device (20). Hereinafter, the metal structures (30) will be described based on one of the metal structures (30).

[0022] The metal structure (30) may be positioned on the edge region (ER) between the semiconductor device (20) and the side (10c) of the semiconductor substrate (10). The metal structure (30) may be positioned in a direction toward the inside of the semiconductor substrate (10) from the side (10c) of the semiconductor substrate (10). That is, the metal structure (30) may be spaced apart from the side (10c) of the semiconductor substrate (10). For example, the gap (gap1) between the metal structure (30) and the side (10c) of the semiconductor substrate (10) may be 2.5 μm to 20 μm. The metal structure (30) may be spaced apart from the semiconductor device (20), more preferably from the device region (DR).

[0023] The metal structure (30) may be electrically insulated from the semiconductor device (20). Additionally, the metal structure (30) may be electrically insulated from other devices, wiring, etc. within the semiconductor device (1). That is, the metal structure (30) may be floating within the semiconductor device (1). However, the present invention is not limited thereto. The metal structure (30) may not be placed on the device region (DR) of the semiconductor substrate (10).

[0024] A first surface (10a) of a semiconductor substrate (10) may be covered with an interlayer insulating film (40). The interlayer insulating film (40) may embed a semiconductor device (20) in a device region (DR). The interlayer insulating film (40) may embed a metal structure (30) in an edge region (ER). At this time, the interlayer insulating film (40) may cover the semiconductor device (20) and the metal structure (30) from above. That is, the semiconductor device (20) and the metal structure (30) may not be exposed by the interlayer insulating film (40). A side surface (40a) of the interlayer insulating film (40) may be aligned with a side surface (10c) of the semiconductor substrate (10). For example, a side surface (40a) of the interlayer insulating film (40) may be coplanar with a side surface (10c) of the semiconductor substrate (10). As the metal structure (30) is spaced apart from the side (10c) of the semiconductor substrate (10), the metal structure (30) may also be spaced apart from the side (40a) of the interlayer insulating film (40). For example, the gap (gap1) between the metal structure (30) and the side (40a) of the interlayer insulating film (40) may be 2.5 µm to 20 µm. The interlayer insulating film (40) may include, for example, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). The interlayer insulating film (40) may have a mono-layer or multi-layer structure.

[0025] According to embodiments of the present invention, a metal structure (30) may be provided in the edge region (ER) of a semiconductor substrate (10). When an impact or stress is applied from one side of the semiconductor device (1) toward the semiconductor element (20), the metal structure (30) may act as a barrier to mitigate the impact or stress and may protect the semiconductor element (20) from the impact or stress. Additionally, the metal structure (30) is a configuration provided for testing during the manufacturing process of the semiconductor device (1) and may not be used during the operation of the finished semiconductor device (1). That is, the metal structure (30) may be damaged and may absorb a large amount of the impact or stress. Therefore, the semiconductor element (20) may be more robustly protected from the impact or stress, and a semiconductor device (1) with improved structural stability may be provided.

[0026] Contact plugs (22) connected to transistors (TR) may be disposed within the interlayer insulating film (40) on the device region (DR). The contact plugs (22) may penetrate vertically through the interlayer insulating film (40) and be connected to any one of the source electrode, drain electrode, or gate electrode of the transistors (TR). Alternatively, the contact plugs (22) may be connected to various components of the semiconductor device (20). The contact plugs (22) may penetrate vertically through the interlayer insulating film (40) and be exposed on the upper surface of the interlayer insulating film (40). The contact plugs (22) may include, for example, tungsten (W).

[0027] Although not illustrated, the side and bottom surfaces of the contact plugs (22) may be covered with a seed film or a barrier film. The seed film or the barrier film may be interposed between the contact plugs (22) and the interlayer insulating film (40). The seed film may include, for example, gold (Au). The barrier film may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN).

[0028] The semiconductor device (20), the transistors (TR) of the semiconductor device (20), the insulating film (40) between the device layers, and the contact plugs (22) can form a device layer (DL).

[0029] A wiring layer (IL) may be disposed on the interlayer insulating film (40). The wiring layer (IL) may cover the device region (DR) and edge region (ER) of the semiconductor substrate (10). That is, when viewed from above, the metal structure (30) may be obscured by the wiring layer (IL).

[0030] The wiring layer (IL) may include an insulating stack (51). The insulating stack (51) may include multiple lower inter-metallic dielectric layers (52). The lower inter-metallic dielectric layers (52) may have a low-k dielectric material. More preferably, the dielectric constant of the lower inter-metallic dielectric layers (52) may be smaller than the dielectric constant of the material constituting the device inter-layer dielectric layer (40), for example, silicon oxide (SiO). For example, the lower inter-metallic dielectric layers (52) may be porous dielectric layers. The mechanical strength of each lower inter-metallic dielectric layer (52) may be smaller than the mechanical strength of the device inter-layer dielectric layer (40).

[0031] Although not illustrated, an etch stop layer may be interposed between the lower intermetallic insulating films (52). For example, the etch stop layer may be provided on the lower surface of the lower intermetallic insulating films (52). The etch stop layer may comprise, for example, one of silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide nitride (SiCN).

[0032] The wiring layer (IL) may include a plurality of lower wiring patterns (53) disposed within an insulating stack (51) and lower via patterns (54) connecting them. The lower wiring patterns (53) and the lower via patterns (54) may be located on a device region (DR) of a semiconductor substrate (10). However, the present invention is not limited thereto, and the lower wiring patterns (53) may extend from the device region (DR) of the semiconductor substrate (10) onto an edge region (ER), and a portion of the lower via patterns (54) may be located on the edge region (ER).

[0033] The lower wiring patterns (53) may correspond to horizontal wiring that provides rewiring of electrical connections within the wiring layer (IL). The lower wiring patterns (53) may extend horizontally within one of the lower metal-to-metal insulating films (52). The lower wiring patterns (53) placed at the bottom may each be connected to contact plugs (22) on the device area (DR). The lower wiring patterns (53) may be electrically connected to the semiconductor device (20) through the contact plugs (22).

[0034] The lower via patterns (54) may correspond to vertical wiring that vertically connects the lower wiring patterns (53). The lower via patterns (54) may vertically penetrate one of the lower metal-to-metal insulating films (52) to connect adjacent lower wiring patterns (53).

[0035] The lower wiring patterns (53) and lower via patterns (54) may be provided as separate configurations, as shown in FIG. 2. Alternatively, unlike as shown in FIG. 2, the lower wiring patterns (53) and lower via patterns (54) may comprise the same material and may be provided integrally. The lower wiring patterns (53) and lower via patterns (54) may comprise a conductive material. For example, the lower wiring patterns (53) and lower via patterns (54) may comprise copper (Cu).

[0036] Although not illustrated, the sides and bottom surfaces of the lower wiring patterns (53) and lower via patterns (54) may be covered with a seed film or a barrier film. The seed film or the barrier film may be interposed between the lower wiring patterns (53) and the lower intermetallic insulating films (52) and between the lower via patterns (54) and the lower intermetallic insulating films (52). The seed film may, for example, comprise gold (Au). The barrier film may, for example, comprise at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN).

[0037] Lower intermetallic insulating films (52), lower wiring patterns (53), and lower via patterns (54) can form a wiring layer (IL). Sides of the wiring layer (IL) (i.e., sides of the lower intermetallic insulating films (52)) can be aligned with sides (10c) of the semiconductor substrate (10) and sides (40a) of the interlayer insulating film (40). For example, the sides of the wiring layer (IL) can be coplanar with sides (10c) of the semiconductor substrate (10) and sides (40a) of the interlayer insulating film (40).

[0038] An upper intermetallic insulating film (55) may be disposed on the wiring layer (IL). The upper intermetallic insulating film (55) may include an insulating material. In this case, the dielectric constant of the upper intermetallic insulating film (55) may be greater than that of the lower intermetallic insulating films (52). The mechanical strength of the upper intermetallic insulating film (55) may be greater than that of the lower intermetallic insulating films (52). Although FIG. 2 illustrates the provision of a single upper intermetallic insulating film (55), the present invention is not limited thereto. According to other embodiments, the upper intermetallic insulating films (55) may be provided in multiple numbers. In this case, the upper intermetallic insulating films (55) may be stacked sequentially on the wiring layer (IL). The upper intermetallic insulating film (55) may include, for example, silicon oxide (SiO), tetraethyl orthosilicate (TEOS), or HDP (High Density Plasma) oxide. Alternatively, the upper intermetallic insulating film (55) may include silicon nitride (SiN), in which case the upper intermetallic insulating film (55) may function as an etching stop layer. Alternatively, the upper intermetallic insulating film (55) may include a material with low hydrogen permeability, in which case the upper intermetallic insulating film (55) may function as a hydrogen blocking layer. For example, the material with low hydrogen permeability may include at least one of aluminum oxide (AlO), tungsten oxide (WO), and silicon nitride (SiN). The upper intermetallic insulating film (55) may have a mono-layer or multi-layer structure.

[0039] Sub-pads (56) may be disposed on the upper intermetallic insulating film (55). The sub-pads (56) may be disposed on the upper surface of the upper intermetallic insulating film (55). The sub-pads (56) may be located on the device region (DR) of the semiconductor substrate (10).

[0040] The upper via patterns (57) can penetrate the upper intermetallic insulating film (55). The upper via patterns (57) can connect one of the lower wiring patterns (53) and one of the sub-pads (56). The sub-pads (56) can be electrically connected to the semiconductor device (20) through the upper via patterns (57) and the wiring layer (IL). The upper via patterns (57) and the sub-pads (56) may include a conductive material. For example, the upper via patterns (57) and the sub-pads (56) may include copper (Cu).

[0041] Although not illustrated, upper wiring may be additionally provided on the upper intermetallic insulating film (55) of the device region (DR). The upper wiring may be spaced apart from the sub-pads (56) on the upper surface of the upper intermetallic insulating film (55). Alternatively, the upper wiring may be provided within the upper intermetallic insulating film (55). For example, if the upper intermetallic insulating film (55) is provided as a multi-layer, the upper wiring may be placed within the layers of the upper intermetallic insulating film (55).

[0042] A protective film (PL) may be disposed on the upper intermetallic insulating film (55). The protective film (PL) may cover sub-pads (56) on the upper surface of the upper intermetallic insulating film (55). The protective film (PL) may conformally cover the upper surface of the upper intermetallic insulating film (55) and the sub-pads. For example, on the device region (DR) where sub-pads (56) are provided on the upper surface of the upper intermetallic insulating film (55), the first thickness (TK1) of the protective film (PL) may be thick. On the edge region (ER) where sub-pads (56) are not provided on the upper surface of the upper intermetallic insulating film (55), the second thickness (TK2) of the protective film (PL) may be thin. The first thickness (TK1) may be thicker than the second thickness (TK2). In other words, the distance from the first surface (10a) of the semiconductor substrate (10) to the upper surface of the protective film (PL) on the device region (DR) may be greater than the distance from the first surface (10a) of the semiconductor substrate (10) to the upper surface of the protective film (PL) on the edge region (ER). The protective film (PL) may include one of High Density Plasma (HDP) oxide, Undoped Silicate Glass (USG), Tetraethyl Orthosilicate (TEOS), Silicon Nitride (SiN), Silicon Oxide (SiO), Silicon Oxide Carbide (SiOC), Silicon Oxide Nitride (SiON), and Silicon Carbide Nitride (SiCN). The protective film (PL) may have a mono-layer or multi-layer structure.

[0043] Bonding pads (65) may be disposed on a protective film (PL). Although FIG. 2 illustrates the bonding pads (65) being located on the upper surface of the protective film (PL), the present invention is not limited thereto. The protective film (PL) may extend over the upper surface of the bonding pads (65). The bonding pads (65) may be electrically connected to the sub-pads (56). The bonding pads (65) may include a conductive material. For example, the bonding pads (65) may include a metal such as copper (Cu).

[0045] FIG. 3 is a cross-sectional view for illustrating a semiconductor device according to embodiments of the present invention, and FIG. 3 may correspond to a cross-section cut along line A-A' of FIG. 1. In the following embodiments, for convenience of explanation, detailed descriptions of technical features that overlap with those previously described with reference to FIG. 1 and FIG. 2 are omitted, and differences are described in detail. The same reference numerals may be provided for configurations identical or similar to the semiconductor package according to the embodiments of the present invention described above.

[0046] Referring to FIG. 1 and FIG. 3 together, the semiconductor device (2) may be a die of a stacked semiconductor package. For example, the semiconductor device (2) may include a semiconductor substrate (10), a circuit structure (CS) disposed on the front side of the semiconductor substrate (10), i.e., a first surface (10a), and a lower bonding pad (14) disposed on the rear side of the semiconductor substrate (10), i.e., a second surface (10b).

[0047] A circuit structure (CS) may be disposed on a first surface (10a) of a semiconductor substrate (10). The circuit structure (CS) may include a device layer (DL), a wiring layer (IL), and a protective film (PL) that are stacked sequentially on the first surface (10a) of the semiconductor substrate (10).

[0048] The device layer (DL) may include a semiconductor device (20), a metal structure (30), and an interlayer insulating film (40). The semiconductor device (20) may include transistors (TR) provided on a first surface (10a) in a device region (DR) of a semiconductor substrate (10). The metal structure (30) may be provided on a first surface (10a) in an edge region (ER) of a semiconductor substrate (10). The interlayer insulating film (40) may embed the semiconductor device (20) in the device region (DR). The interlayer insulating film (40) may embed the metal structure (30) in the edge region (ER).

[0049] A wiring layer (IL) may be disposed on the interlayer insulating film (40). The wiring layer (IL) may include multiple layers of lower intermetallic insulating films (52), a plurality of lower wiring patterns (53) disposed within the lower intermetallic insulating films (52), and lower via patterns (54) connecting them.

[0050] The second surface (10b) of the semiconductor substrate (10) may be covered with a lower protective film (12). The lower protective film (12) may include, for example, one of silicon oxide (SiO), silicon nitride (SiN), or silicon carbide nitride (SiCN). The protective film (60) may have a mono-layer or multi-layer structure.

[0051] In the device region (DR), the device interlayer insulating film (40), the semiconductor substrate (10), and the lower protective film (12) can be penetrated by a through electrode (TSV). The through electrode (TSV) can be in contact with one of the lower wiring patterns (53). The through electrode (TSV) may include a metal such as, for example, tungsten (W) or copper (Cu). A through insulating film (TL) may be interposed between the through electrode (TSV) and the semiconductor substrate (10). The through insulating film (TL) may be, for example, silicon oxide (SiO).

[0052] A lower bonding pad (14) may be placed below the lower protective film (12). The lower bonding pad (14) may come into contact with a through electrode (TSV) on the lower surface of the lower protective film (12). The lower bonding pad (14) may include a metal such as copper (Cu), gold (Au), nickel (Ni), or aluminum (Al).

[0053] An upper intermetallic insulating film (55) may be disposed on the wiring layer (IL). Sub-pads (56) may be disposed on the upper intermetallic insulating film (55). Upper via patterns (57) may penetrate the upper intermetallic insulating film (55) to connect one of the lower wiring patterns (53) with one of the sub-pads (56).

[0054] A protective film (PL) may be placed on the upper intermetallic insulating film (55). Bonding pads (65) may be placed on the protective film (60). The bonding pads (65) may be under bump pads.

[0055] A sub-protective layer (62) may be provided on the protective layer (PL). The sub-protective layer (62) may have a flat top surface. That is, the sub-protective layer (62) may function as a flattening layer. The sub-protective layer (62) may have a recess that exposes at least a portion of the top surface of the bonding pads (65). The mechanical strength of the sub-protective layer (62) may be greater than the mechanical strength of the protective layer (PL). The sub-protective layer (62) may comprise one of High Density Plasma (HDP) oxide, Undoped Silicate Glass (USG), Tetraethyl Orthosilicate (TEOS), Silicon Nitride (SiN), Silicon Oxide (SiO), Silicon Oxide Carbide (SiOC), Silicon Oxide Nitride (SiON), and Silicon Carbide Nitride (SiCN). The sub-protective layer (62) may have a mono-layer or multi-layer structure.

[0056] Conductive bumps (67) can penetrate the sub-protective layer (62) and come into contact with bonding pads (65). The conductive bumps (67) can be placed within the recess formed in the sub-protective layer (62). A portion of the conductive bumps (67) may protrude over the sub-protective layer (62). The conductive bumps (67) may comprise a metal. For example, the conductive bumps (67) may comprise copper (Cu). Solder films (69) may be bonded to the conductive bumps (67). The solder films (69) may comprise, for example, at least one of tin (Sn), lead (Pb), or silver (Ag).

[0058] FIG. 4 is a plan view for illustrating a semiconductor device according to embodiments of the present invention.

[0059] In the embodiments of FIGS. 1 to 3, a metal structure (30) is shown provided on one of the sides of the semiconductor device (20), but the present invention is not limited thereto.

[0060] Referring to FIGS. 1 and 4, the metal structures (30) may be provided in plurality and may be arranged in a row along the edge of the semiconductor device (20). At this time, the plurality of metal structures (30) may be located on one side of the semiconductor device (20). More specifically, each of the metal structures (30) may be provided on a first surface (10a) in the edge region (ER) of the semiconductor substrate (10). The metal structures (30) may be located between the semiconductor device (20) and the side (10c) of the semiconductor substrate (10) in the edge region (ER). Each of the metal structures (30) may be located in a direction toward the inside of the semiconductor substrate (10) from the side (10c) of the semiconductor substrate (10). The metal structures (30) may be spaced apart from the side (10c) of the semiconductor substrate (10). For example, the distance between each metal structure (30) and the side (10c) of the semiconductor substrate (10) may be 2.5 μm to 20 μm. On the one side of the semiconductor device (20), the metal structures (30) may be arranged in a direction parallel to the one side. The metal structures (30) may be provided as different devices or structures as needed. Each metal structure (30) may be floating within the semiconductor device (3). Alternatively, the metal structures (30) may be electrically insulated from the semiconductor device (20), but some of the metal structures (30) may be electrically connected to each other.

[0061] According to embodiments of the present invention, elements and wiring for driving a semiconductor device (3) are provided in an element region (DR), and an edge region (ER) may be a remaining region where the elements and wiring are not provided. By providing a plurality of metal structures (30) in the edge region (ER), it may be easier to perform a test process during the manufacturing process of the semiconductor device (3). Additionally, as the metal structures (30) are provided in a plurality between the semiconductor element (20) and the side (40a) of the interlayer insulating film (40), the metal structures (30) can more easily absorb external stress and shock. Accordingly, the semiconductor element (20) can be more robustly protected from the shock or stress, and a semiconductor device (3) with improved structural stability can be provided.

[0063] FIG. 5 is a plan view of a wafer. FIG. 6a to 10a are plan views for illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention. FIG. 6b to 10b are cross-sectional views for illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention. FIG. 7c is a plan view for illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention. FIG. 6a to 10a and FIG. 7c correspond to enlarged views of region A of FIG. 5. FIG. 6b to 10b correspond to cross-sections cut along line II-II' of FIG. 5.

[0064] With reference to FIGS. 5, FIGS. 6a, and FIGS. 6b, a wafer (W) may be provided. The wafer (W) may correspond to the semiconductor substrate (10) of FIG. 6b. A plurality of device regions (DR) may be arranged on the wafer (W). Each of the device regions (DR) may also be referred to as a 'chip region'. A scribe lane region (SR) may be placed between the device regions (DR). A cutting line (SL) may be set on the scribe lane region (SR). The cutting line (SL) may extend in a direction traversing between the device regions (DR). The cutting line (SL) may be located in the middle of the scribe lane region (SR). For example, the distances from each of the device regions (DR) to the cutting line (SL) may be substantially the same or similar.

[0065] Semiconductor devices (20) can be formed on a first surface (10a) of a semiconductor substrate (10) through a conventional process. For example, on device regions (DR), a source and a drain can be formed on the upper surface of the semiconductor substrate (10), and a gate insulating film and a gate electrode can be formed between the source and the drain to form transistors (TR).

[0066] Referring to FIGS. 5, 7a, and 7b, metal structures (30) may be formed on a first surface (10a) of a semiconductor substrate (10). For example, test capacitors may be formed on the scribe lane region (SR). The metal structures (30) may be formed simultaneously during the process of forming semiconductor devices (20), or may be formed through a separate process after the semiconductor devices (20) have been formed. The metal structures (30) may be formed spaced apart from each other on the scribe lane region (SR). More specifically, the metal structures (30) may be spaced apart from each other with a cutting line (SL) between them. Between adjacent device regions (DR), the metal structures (30) may be formed one by one between the device regions (DR) and the cutting line (SL). At this time, the metal structures (30) may be spaced apart from the cutting line (SL). The gap (gap2) between the metal structures (30) can be 5 µm to 100 µm.

[0067] FIG. 7a illustrates that metal structures (30) are formed one by one adjacent to the device regions (DR) between adjacent device regions (DR), but the present invention is not limited thereto. According to other embodiments, as illustrated in FIG. 7c, a plurality of metal structures (30) are provided between adjacent device regions (DR), and a plurality of metal structures (30) may be formed between one device region (DR) and a cutting line (SL). For example, the metal structures (30) may include first metal structures (30-1) and second metal structures (30-2). The first metal structures (30-1) may be formed between one of the device regions (DR) and the cutting line (SL), and the second metal structures (30-2) may be formed between the other of the device regions (DR) and the cutting line (SL). The first metal structures (30-1) and the second metal structures (30-2) may be spaced apart from each other with a cutting line (SL) in between. The first metal structures (30-1) may be arranged along the side of the semiconductor device (20) adjacent to them or in a direction along the cutting line (SL). The second metal structures (30-2) may be arranged along the side of the semiconductor device (20) adjacent to them or in a direction along the cutting line (SL). In this case, the semiconductor device (3) described with reference to FIG. 4 may be manufactured. Hereinafter, the description will continue based on the embodiment of FIG. 7a.

[0068] Referring to FIGS. 5, FIGS. 8a, and FIGS. 8b, an interlayer insulating film (40) can be formed on a semiconductor substrate (10). For example, the interlayer insulating film (40) can be formed by depositing an insulating material on a first surface (10a) of the semiconductor substrate (10). The interlayer insulating film (40) can cover semiconductor devices (20) on device regions (DR) and can cover metal structures (30) on scribe lane regions (SR).

[0069] Contact plugs (22) can be formed on the interlayer insulating film (40). For example, the interlayer insulating film (40) on the device regions (DR) can be etched to form a hole that exposes the semiconductor device (20), and then a conductive material can be filled into the hole to form the contact plugs (22).

[0070] The device layer (DL) can be formed as described above.

[0071] According to other embodiments, the device layer (DL) and the semiconductor substrate (10) may be etched to form holes for through-electrodes, and through-electrodes (TSV) and through-insulating film (TL) may be formed therein. In this case, the semiconductor device (2) described with reference to FIG. 3 may be manufactured. The following description will continue based on the embodiment of FIG. 8b.

[0072] A wiring layer (IL) can be formed on a device layer (DL) through conventional processes. The wiring layer (IL) may include an insulating stack (51) comprising the multilayer lower intermetallic insulating films (52) of FIG. 2. Lower wiring patterns (53) and lower via patterns (54) may be formed within the insulating stack (51). The lower wiring patterns (53) and lower via patterns (54) may be formed on device regions (DR).

[0073] An upper intermetallic insulating film (55) may be formed on the wiring layer (IL). Upper via patterns (57) penetrating the upper intermetallic insulating film (55) may be formed. Sub-pads (56) may be formed on the upper intermetallic insulating film (55). The sub-pads (56) may be formed on the device regions (DR).

[0074] Referring to FIGS. 5, 9a, and 9b, a protective film (PL) may be formed on an upper intermetallic insulating film (55). The protective film (PL) may be formed conformally on the upper intermetallic insulating film (55). At this time, sub-pads (56) may be formed on the device regions (DR), and the protective film (PL) may cover the sub-pads (56). Accordingly, the upper surface of the protective film (PL) on the device regions (DR) may be located at a level higher than the upper surface of the protective film (PL) on the scribe lane region (SR).

[0075] Although not shown, wiring patterns connected to sub-pads (56) may be provided within the protective film (PL).

[0076] Bonding pads (65) may be formed on a protective film (PL). For example, bonding pads (65) may be formed by forming a metal-containing film on the protective film (PL) and then patterning the metal-containing film. The metal-containing film may include, for example, aluminum (Al). Alternatively, bonding pads (65) may be formed by forming a mask pattern on the protective film (PL) and then filling a conductive material into the pattern holes of the mask pattern. Bonding pads (65) may be formed on device regions (DR).

[0077] In FIG. 10a, the configuration of the protective film (PL) and the wiring layer (IL) is omitted for convenience of explanation. Referring to FIG. 5, FIG. 10a, and FIG. 10b, a sawing process can be performed using a laser to remove the breaking region (BR) and separate individual semiconductor devices (1). More specifically, the laser can be irradiated along the cutting line (SL), and the semiconductor substrate (10), the interlayer insulating film (40), the wiring layer (IL), and the protective film (PL) on the breaking region (BR) can be removed by the laser. After the sawing process, the remaining area excluding the breaking region (BR) in the scribe lane area (SR) can become the edge region (ER) of the semiconductor devices (1).

[0078] Since the metal structures (30) are spaced apart from the cutting line (SL) by a certain distance or more, the laser may pass through the semiconductor substrate (10), the interlayer insulating film, the wiring layer (IL), and the protective film (PL) in sequence, but may not pass through the metal structures (30). Therefore, after the sawing process, the metal structures (30) of the semiconductor devices (1) may not be exposed to the outside. More specifically, the metal structures (30) may be located on the first surface (10a) of the semiconductor substrate (10) and may be covered by the interlayer insulating film (40). At this time, the metal structures (30) may be spaced apart from the cutting surface (40a) of the interlayer insulating film (40) and the cutting surface (10c) of the semiconductor substrate (10). That is, the metal structures (30) may be buried by the semiconductor substrate (10) and the interlayer insulating film (40) and may not be exposed to the outside. The cut surface (10c) of the semiconductor substrate (10) and the cut surface (40a) of the interlayer insulating film (40) can be coplanar with each other.

[0079] FIGS. 11a and FIGS. 12a are plan views for comparing and explaining a method of manufacturing a semiconductor device. FIGS. 11b and FIGS. 12b are cross-sectional views for comparing and explaining a method of manufacturing a semiconductor device.

[0080] Referring to FIGS. 11a and FIGS. 11b, a metal structure (30') may be formed on a first surface (10a) of a semiconductor substrate (10) on the result of FIGS. 6a and FIGS. 6b. A metal structure (30') may be formed between adjacent device regions (DR). At this time, the metal structure (30') may be located on a cutting line (SL) between adjacent device regions (DR).

[0081] Subsequently, the process described with reference to FIGS. 7a to 9a and FIGS. 7b to 9b may be performed. For example, an interlayer insulating film (40), a wiring layer (IL), and a protective film (PL) may be formed on a semiconductor substrate (10).

[0082] Referring to FIGS. 12a and 12b, a sawing process can be performed using a laser to remove the breaking region (BR) and separate individual semiconductor devices (1). More specifically, the laser can be irradiated along a cutting line (SL), and the semiconductor substrate (10), metal structure (30'), interlayer insulating film (40), wiring layer (IL), and protective film (PL) on the breaking region (BR) can be removed by the laser. After the sawing process, the remaining area of ​​the scribe lane region (SR), excluding the breaking region (BR), can become the edge region (ER) of the semiconductor devices (1).

[0083] Since the metal structure (30') is positioned on the cutting line (SL), the laser can sequentially cut the semiconductor substrate (10), the metal structure (30'), and the interlayer insulating film (40). At this time, because there is a large difference in hardness between the semiconductor substrate (10), the interlayer insulating film (40), and the metal structure (30'), fracture may occur at the interface between the semiconductor substrate (10) and the metal structure (30') and at the interface between the metal structure (30') and the interlayer insulating film (40), or the metal structure (30') may be peeled off from the semiconductor substrate (10). More specifically, when the laser reaches the lower surface of the metal structure (30') after cutting the semiconductor substrate (10), a fracture may occur at the interface between the semiconductor substrate (10) and the metal structure (30'), and a bonding defect (BK) may be created along the interface between the semiconductor substrate (10) and the metal structure (30'). In this specification, a bonding defect (BK) may refer to a defect such as delamination of two bonded components or the formation of a gap or void between the two components. The bonding defect (BK) may extend along the interface between the semiconductor substrate (10) and the metal structure (30') or the interface between the semiconductor substrate (10) and the interlayer insulating film (40), and may damage the semiconductor device (20) on the device region (DR). Alternatively, the cut surface (10c) of the semiconductor substrate (10) and the cut surface of the metal structure (30') may be horizontally shifted by the bonding defect (BK), and a step may be formed on the side of the semiconductor device (5).

[0084] On the other hand, according to embodiments of the present invention, since the metal structures (30) are spaced apart from the cutting line (SL) by a certain distance or more, the metal structures (30) may not be cut by the laser. Therefore, fracture may not occur at the interface between the semiconductor substrate (10) and the metal structures (30), and at the interface between the metal structures (30) and the interlayer insulating film (40). That is, the metal structures (30) may not be impacted by the laser, and the metal structures (30) may not be peeled off from the semiconductor substrate (10) during the sawing process, nor may bonding defects occur at the bonding surface between the metal structures (30) or the interlayer insulating film (40) and the semiconductor substrate (10). Accordingly, defects may not occur during the manufacturing process of the semiconductor device.

[0086] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A semiconductor substrate comprising a device region and an edge region; a semiconductor device provided on the upper surface of the semiconductor substrate on the device region; a metal structure disposed on the semiconductor substrate in the edge region, wherein the metal structure is in contact with the upper surface of the semiconductor substrate; an insulating film covering the semiconductor device and the metal structure on the semiconductor substrate; and a pad disposed on the semiconductor device in the device region, wherein the metal structure is embedded by the insulating film and is not exposed on the side surface of the insulating film, the metal structure is located between the semiconductor device and the side surface of the semiconductor substrate on the edge region, the metal structure is electrically insulated from the semiconductor device, the metal structure includes a test pattern, and the test pattern includes a capacitor. Claim 2 delete Claim 3 delete Claim 4 A semiconductor device according to claim 1, wherein the side surface of the semiconductor substrate and the side surface of the insulating film form a coplanar plane. Claim 5 A semiconductor device according to claim 1, further comprising a wiring layer disposed on the insulating film, wherein the pad is disposed on the wiring layer and electrically connected to the wiring layer. Claim 6 A semiconductor device according to claim 5, further comprising a protective film disposed on the wiring layer, wherein the distance from the upper surface of the semiconductor substrate to the upper surface of the protective film on the device region is greater than the distance from the upper surface of the semiconductor substrate to the upper surface of the protective film on the edge region. Claim 7 delete Claim 8 A semiconductor device according to claim 1, wherein the metal structures are provided in plurality, and the metal structures are arranged in a direction parallel to the side of the insulating film on the edge region. Claim 9 A semiconductor substrate comprising a device region and an edge region surrounding the device region; a semiconductor device provided on the upper surface of the semiconductor substrate on the device region; a metal structure disposed on the semiconductor substrate on the edge region, wherein the metal structure is in contact with the upper surface of the semiconductor substrate; a wiring layer on the semiconductor device and the metal structure; and a pad disposed on the wiring layer on the device region and electrically connected to the wiring layer, wherein the metal structure is located between the semiconductor device and the side of the semiconductor substrate on the edge region, and the metal structure is spaced apart from the side of the semiconductor substrate in a direction toward the interior of the semiconductor substrate, and the metal structure includes a test pattern, and the test pattern includes a capacitor. Claim 10 A semiconductor device according to claim 9, further comprising an insulating film covering the semiconductor element and the metal structure on the semiconductor substrate, wherein the wiring layer is disposed on the insulating film. Claim 11 A semiconductor device according to claim 10, wherein the side of the insulating film and the side of the metal structure are horizontally spaced apart from each other. Claim 12 In claim 10, the semiconductor device wherein the metal structure is embedded by the insulating film and is not exposed on the side of the insulating film. Claim 13 A semiconductor device according to claim 10, wherein the side of the semiconductor substrate and the side of the insulating film form a coplanar plane. Claim 14 In claim 9, the metal structure is a semiconductor device electrically insulated from the semiconductor element. Claim 15 delete Claim 16 delete Claim 17 A semiconductor device according to claim 9, further comprising a protective film disposed on the wiring layer, wherein the distance from the upper surface of the semiconductor substrate to the upper surface of the protective film on the device region is greater than the distance from the upper surface of the semiconductor substrate to the upper surface of the protective film on the edge region. Claim 18 delete Claim 19 Providing a semiconductor substrate having a first element region, a second element region, and a scribe lane between the first and second element regions; forming semiconductor elements on the upper surface of the semiconductor substrate on the first and second element regions; forming metal structures on the upper surface of the semiconductor substrate on the scribe lane, wherein the metal structures are spaced apart from each other in a first direction toward the second element region from the first element region, and the metal structures are located between the semiconductor element of the first element region and the semiconductor element of the second element region on the scribe lane, and the metal structures are in contact with the upper surface of the semiconductor substrate; forming an insulating film covering the semiconductor elements and the metal structures on the semiconductor substrate; and forming a wiring layer electrically connected to the semiconductor elements on the insulating film. A method for manufacturing a semiconductor device comprising cutting a semiconductor substrate on the scribe lane and an insulating film to separate them into semiconductor devices, wherein when separating the semiconductor devices, the metal structures are not cut, the metal structures include a test pattern, and the test pattern includes a capacitor. Claim 20 A method for manufacturing a semiconductor device according to claim 19, wherein the scribe lane includes a cutting line extending in a second direction that intersects the first direction and crosses between the first and second element regions, and separating the semiconductor elements by means of irradiating a laser along the cutting line, and the metal structures are spaced apart from each other with the cutting line in between.

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