Wafer structure and Semiconductor device

Abstract

According to embodiments of the present invention, a semiconductor device comprises a substrate having a device region and a dummy region surrounding the device region in a planar view; and a cell array structure provided on the substrate and comprising first insulating layers, gate structures, a vertical channel structure, and a dummy pattern, wherein the vertical channel structure overlaps with the device region of the substrate and penetrates the gate structures and the first insulating layer, the outer wall of the cell array structure is exposed by the substrate, and a recessed portion is provided on the outer wall of the cell array structure, the dummy pattern covers the side wall and bottom surface of the recessed portion, and the dummy pattern may comprise the same material as the vertical channel structure.

Description

Technology Field

[0001] The present invention relates to a wafer structure and a semiconductor device manufactured using the same. Background Technology

[0002] With the advancement of the electronics industry, lightweight, miniaturized, high-speed, and high-performance electronic products can be provided at low prices. In the manufacturing of semiconductor devices, wafer structures may be used. A wafer structure may include multiple device regions. A wafer structure can be diced to separate semiconductor devices from one another. During the substrate dicing process, problems are being raised regarding defective dicing of the wafer structure or damage to the semiconductor devices. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a dicing process for a wafer structure that effectively separates semiconductor devices.

[0004] The problem that the present invention aims to solve is to provide a semiconductor device with improved reliability and a method for manufacturing the same. means of solving the problem

[0005] According to embodiments of the present invention, a semiconductor device comprises a substrate having a device region and a dummy region surrounding the device region in a planar view; and a cell array structure provided on the substrate and comprising first insulating layers, gate structures, a vertical channel structure, and a dummy pattern, wherein the vertical channel structure overlaps with the device region of the substrate and penetrates the gate structures and the first insulating layer, the outer wall of the cell array structure is exposed by the substrate, and a recessed portion is provided on the outer wall of the cell array structure, the dummy pattern covers the side wall and bottom surface of the recessed portion, and the dummy pattern may comprise the same material as the vertical channel structure.

[0006] According to embodiments of the present invention, a semiconductor device comprises: a semiconductor substrate having a device region and a dummy region surrounding the device region in a planar view; a logic structure provided on the semiconductor substrate and including peripheral circuits; a cell array structure on the logic structure; a wiring layer provided on the cell array structure; a chip pad on the wiring layer; and a protective layer provided on the wiring layer and exposing the chip pad, wherein a recessed portion is provided on the outer wall of the cell array structure, and the outer wall of the cell array structure is exposed by the semiconductor substrate and the logic structure, and the cell array structure comprises: first insulating layers that overlap with the device region and the dummy region of the semiconductor substrate and are vertically spaced from each other; gate structures that overlap with the device region of the semiconductor substrate and are interposed between the first insulating layers; second insulating layers that overlap with the dummy region of the semiconductor substrate and are interposed between the first insulating layers; and a vertical channel structure disposed on the device region of the semiconductor substrate and penetrating the first insulating layers and the gate structures. The apparatus comprises a conductive pad provided on the vertical channel structure; a dummy pattern provided on the dummy region of the semiconductor substrate and spaced laterally from the vertical channel structure; and a capping film provided on the upper surface of the vertical channel structure and extending onto the dummy region of the semiconductor substrate, wherein the dummy pattern covers the bottom surface and side wall of the recessed portion, and the height of the dummy pattern may be substantially equal to the sum of the height of the vertical channel structure and the height of the conductive pad.

[0007] According to embodiments of the present invention, a wafer structure comprises: a substrate having a device region and a scribe lane region in a planar view; and a cell array structure provided on the substrate, comprising first insulating layers, a vertical channel structure, and a dummy pattern, wherein the first insulating layers are spaced perpendicularly apart from each other, and the cell array structure comprises: a first trench provided on the scribe lane region of the substrate and penetrating the first insulating layers; and a first trench provided on the scribe lane region of the substrate and penetrating the first insulating layers, wherein a void is provided within the first trench, and the dummy pattern may cover the sidewalls and bottom surface of the first trench. Effects of the invention

[0008] According to the present invention, a wafer structure may include voids. The voids may be provided on the scribe lane region of a semiconductor substrate and may be provided within a cell array structure. The wafer structure may be diced more effectively by means of the voids. Accordingly, damage to components on the device regions of a semiconductor chip may be prevented. The manufacturing process yield of the semiconductor device is improved, and the semiconductor device may exhibit improved reliability. Brief explanation of the drawing

[0009] FIG. 1 is a plan view illustrating a wafer structure according to embodiments. FIG. 2a is an enlarged view of area I of FIG. 1. Figure 2b is a cross-section taken along the line II-II' of Figure 2a. FIG. 2c is an enlarged view of region III of FIG. 2b. FIG. 2d is an enlarged view of region IV of FIG. 2c. FIG. 2e is a drawing for explaining a void according to embodiments. FIG. 3a is a plan view illustrating a wafer structure according to embodiments. Figure 3b is a cross-section taken along the line II-II' of Figure 3a. FIGS. 4a to 4j are drawings for explaining a method of manufacturing a wafer structure according to embodiments. FIGS. 5a and FIG. 6a are drawings for explaining a dicing process according to embodiments. Figures 5b and 6b are enlarged drawings of area III of Figure 5a and area III of Figure 6a, respectively. FIG. 7a is a cross-sectional view illustrating a semiconductor device according to embodiments. Figure 7b is an enlarged view of area V of Figure 7a. FIG. 7c is a drawing for illustrating a recessed portion and a first capping membrane according to embodiments. FIG. 7d is a drawing for illustrating a recessed portion and a first capping membrane according to embodiments. FIG. 8a is a drawing for explaining a semiconductor device according to embodiments. Figure 8b is an enlarged view of area V of Figure 8a. FIG. 9 is a drawing for illustrating a semiconductor package according to embodiments. Specific details for implementing the invention

[0010] In this specification, the same reference numerals throughout the text may refer to the same components. A wafer structure, a semiconductor device, a semiconductor package, and a method for manufacturing the same are described according to the concept of the present invention.

[0012] FIG. 1 is a plan view illustrating a wafer structure according to embodiments. FIG. 2a is an enlarged view of region I of FIG. 1. FIG. 2b is a cross-section cut along the line II-II' of FIG. 2a. FIG. 2c is an enlarged view of region III of FIG. 2b. FIG. 2d is an enlarged view of region IV of FIG. 2c.

[0013] Referring to FIGS. 1, 2a through 2d, the wafer structure (1000) may include a substrate (100), a logic structure (200), a cell array structure (300), a wiring layer (400), chip pads (550), and a protection layer (PL). The logic structure (200) may be disposed between the substrate (100) and the cell array structure (300).

[0014] The substrate (100) may have device regions (DR) and scribe lane regions (SLR) in a planar view. Each of the device regions (DR) may be a region used as a substrate for a semiconductor device (10 in FIG. 7a and 7b). The device regions (DR) of the substrate (100) may be spaced apart from each other by scribe lane regions (SLR). The device regions (DR) may be spaced apart from each other in a first direction (D1) or a second direction (D2). For example, the device regions (DR) may be arranged along rows parallel to the first direction (D1) and columns parallel to the second direction (D2).

[0015] The first direction (D1) may be parallel to the lower surface of the substrate (100). The second direction (D2) may be parallel to the lower surface of the substrate (100) but substantially perpendicular to the first direction (D1). The third direction (D3) may be substantially perpendicular to the lower surface of the substrate (100) and may intersect the first direction (D1) and the second direction (D2).

[0016] A scribe lane region (SLR) of the substrate (100) may be positioned between device regions (DR). The device regions (DR) may be surrounded by the scribe lane region (SLR). The scribe lane region (SLR) may be a virtual region. The scribe lane region (SLR) may include first regions and second regions. In a planar view, each of the first regions of the scribe lane region (SLR) may extend in a direction parallel to the first direction (D1), and each of the second regions may extend in a direction parallel to the second direction (D2). The first regions of the scribe lane region (SLR) may be connected to the second regions.

[0017] As shown in FIG. 2c, the scribe lane region (SLR) may include a dicing region (R1) and a dummy region (R2). The dicing region (R1) of the scribe lane region (SLR) may be a region that is removed during the dicing process described later in FIG. 5a to 6b. The dummy region (R2) may be provided between the dicing region (R1) and the device regions (DR). Since the dummy region (R2) is provided, damage to the components of the device region (DR) can be prevented during the dicing process.

[0018] The substrate (100) may be a semiconductor substrate. The substrate (100) may be a crystalline semiconductor substrate. For example, the substrate (100) may have a single-crystal structure, but is not limited thereto. The substrate (100) may include silicon, germanium, and / or silicon-germanium.

[0019] A logic structure (200) may be disposed on the upper surface of a substrate (100). The logic structure (200) may include a device isolation layer (210), peripheral circuits (250), well regions (215), conductive plugs (220), lower wiring (230), and a lower buried insulating layer (240). The logic structure (200) may further include a resistor and a capacitor.

[0020] Peripheral circuits (250) may be provided on the upper surface of the substrate (100). The upper surface of the substrate (100) may be the front surface. Peripheral circuits (250) may include transistors. Each of the peripheral circuits (250) may include a gate electrode (253) and source / drain regions (251) on both sides of the gate electrode (253). The gate electrode (253) may include a conductive material. Each of the peripheral circuits (250) may further include a gate insulating film, and the gate insulating film may be disposed between the substrate (100) and the gate electrode (253).

[0021] Device isolation films (210) and well regions (215) may be provided on the substrate (100). The well regions (215) may be doped regions of the substrate (100), but are not limited thereto. Device isolation films (210) may be provided between the well regions (215). Active regions within the well regions (215) may be defined by the device isolation films (210). Transistors may be provided on each of the well regions (215). Source / drain regions (251) are provided within the well regions (215) and may have a different type of conductivity than the corresponding well regions (215).

[0022] Conductive plugs (220) are placed on source / drain regions (251) or a gate electrode (253) and can be connected to the source / drain regions (251) or the gate electrode (253). The conductive plugs (220) may include a conductive material such as metal.

[0023] Lower wiring (230) and lower buried insulating film (240) may be provided on the device isolation film (210) and well regions (215). Lower wiring (230) may be provided within the lower buried insulating film (240). Lower wiring (230) may be electrically connected to peripheral circuits (250) through conductive plugs (220). Lower wiring (230) may include a conductive material such as metal. The lower buried insulating film (240) may be a single film or a multilayer. The lower buried insulating film (240) may include a silicon-based insulating material. The silicon-based insulating material may include, for example, silicon oxide, silicon nitride, and / or silicon oxide nitride.

[0024] Peripheral circuits (250), conductive plugs (220), and lower wiring (230) are provided on the device regions (DR) of the substrate (100) but may not be provided on the scribe lane region (SLR). For example, the peripheral circuits (250), conductive plugs (220), and lower wiring (230) may be spaced apart from the scribe lane region (SLR) of the substrate (100) in a planar view. The lower buried insulating film (240) may be provided on the device regions (DR) and the scribe lane region (SLR) of the substrate (100).

[0025] A cell array structure (300) may be placed on a logic structure (200). For example, the cell array structure (300) may be placed on a lower embedded insulating film (240). The cell array structure (300) may overlap with the device regions (DR) and scribe lane regions (SLR) of the substrate (100). As shown in FIGS. 2c and 2d, the cell array structure (300) may include a semiconductor layer (310), gate structures (320), vertical channel structures (330X), a capping film, contact plugs (340), spacers (343), and a dummy pattern (330Y). The cell array structure (300) may have a first trench (TR1) and a second trench (TR2).

[0026] A semiconductor layer (310) may be disposed on a logic structure (200) to cover an underlying embedded insulating film (240). The semiconductor layer (310) may include a semiconductor material such as silicon (Si), germanium (Ge), and / or silicon germanium (SiGe). The semiconductor layer (310) may include a semiconductor doped with an impurity of the first conductivity type and / or an intrinsic semiconductor in an undoped state. The semiconductor layer (310) may have a single crystal or polycrystalline structure. For example, the impurity of the first conductivity type may include a group 3 element such as boron. The first conductivity type may be p-type.

[0027] The semiconductor layer (310) may have common source regions (314). For example, the common source regions (314) may be provided within the semiconductor layer (310) and on the upper surface of the semiconductor layer (310). The common source regions (314) may be regions doped with impurities of a second conductivity type. The impurities of the second conductivity type may include group 5 elements such as arsenic or phosphorus. The second conductivity type may be n-type. The common source regions (314) may be provided on the device regions (DR) of the substrate (100), but may not be provided on the scribe lane region (SLR).

[0028] A stacked structure is provided on a semiconductor layer (310) and may extend in a direction parallel to a first direction (D1). The stacked structure may include gate structures (320), first insulating films (321), and second insulating films (324). The stacked structure may include a plurality of stacked structures. The stacked structure of FIG. 2c may be any one of a plurality of stacked structures. The stacked structures may be spaced apart from each other in a second direction (D2). Hereinafter, for simplification, a single stacked structure is described.

[0029] The first insulating films (321) may be stacked perpendicularly to each other on the semiconductor layer (310). The first insulating films (321) may overlap with the device regions (DR) and scribe lane regions (SLR) of the substrate (100). The bottom first insulating film (321) may have a smaller thickness than the other first insulating films (321). The thicknesses of the other first insulating films (321) may be the same or different from each other. The first insulating films (321) may include a silicon-containing insulating material. The silicon-containing insulating material may include, for example, silicon oxide, silicon nitride, and / or silicon oxide nitride. The first insulating films (321) may include a low dielectric material. The low dielectric material may have a lower dielectric constant than the silicon oxide film.

[0030] Gate structures (320) are provided on device regions (DR) of the substrate (100) and may not be provided on the scribe lane region (SLR). Gate structures (320) may be stacked perpendicularly to each other on the semiconductor layer (310). In this specification, "perpendicular" may mean parallel to the third direction (D3). Gate structures (320) may be interposed between the first insulating films (321). Gate structures (320) may be used as string select lines, ground select lines, and word lines. For example, the top and bottom of the stacked gate structures (320) may be used as string select lines and ground select lines, respectively. The gate structures (320) between the top and bottom gate structures (320) may be used as word lines. Gate structures (320) may include a conductive material such as metal. For example, the gate structures (320) may include tungsten. The gate structures (320) may have major axes parallel to the second direction (D2) in a planar view. The gate structures (320) may be spaced apart from each other in the first direction (D1).

[0031] Vertical channel structures (330X) are provided within a stacked structure and may be spaced apart from each other laterally. Some components spaced apart laterally may include being spaced apart horizontally. Horizontal may mean parallel to the lower surface of the substrate (100). For example, the vertical channel structures (330X) may be provided within a second trench (TR2), and the second trench (TR2) may penetrate the vertical channel structures (330X). For example, the second trench (TR2) may penetrate the first insulating films (321) and the gate structures (320). The bottom surface of the second trench (TR2) may be provided within the semiconductor layer (310). Accordingly, the bottom surfaces of the vertical channel structures (330X) may be located at a level lower than the upper surface of the semiconductor layer (310) and higher than the lower surface of the semiconductor layer (310). The level of a component may refer to a vertical level, and the level difference between two components may be measured in a third direction (D3).

[0032] The first lower dielectric pattern (331Y), the first semiconductor pattern (332Y), and the first upper dielectric pattern (333Y) will be described later in the example of the dummy pattern (330Y).

[0033] The vertical channel structures (330X) and the second trench (TR2) may overlap with the device regions (DR) of the substrate (100). The vertical channel structures (330X) and the second trench (TR2) may not be provided on the scribe lane region (SLR) of the substrate (100). The vertical channel structures (330X) and the second trench (TR2) may be spaced apart from the scribe lane region (SLR) of the substrate (100) in a planar view. Each of the vertical channel structures (330X) may include a second lower dielectric pattern (331X), a second semiconductor pattern (332X), and a second upper dielectric pattern (333X). The second lower dielectric pattern (331X) may cover the sidewalls of the second trench (TR2). The sidewalls of the second trench (TR2) may include the inner walls of the first insulating films (321). The second lower dielectric pattern (331X) may be provided on the inner walls of the first insulating films (321) and the inner walls of the gate structures (320). The second lower dielectric pattern (331X) may expose the upper surface of the semiconductor layer (310). The second lower dielectric pattern (331X) may include a single insulating layer or multiple insulating layers. The second lower dielectric pattern (331X) may function as part of the data storage film of a charge trap type flash memory transistor. For example, the second lower dielectric pattern (331X) may include a silicon-based insulating material or a high dielectric material.

[0034] A second semiconductor pattern (332X) is provided on the sidewalls of the second trench (TR2) and may cover the first lower dielectric pattern (331Y). The second semiconductor pattern (332X) extends onto the semiconductor layer (310) and may come into contact with a portion of the upper surface of the semiconductor layer (310) exposed by the second trench (TR2). The second semiconductor pattern (332X) may have a pipe-shaped, hollow cylindrical shape, or cup shape within the second trench (TR2). The second semiconductor pattern (332X) may define an empty region in the central part of the second trench (TR2).

[0035] The second semiconductor pattern (332X) may include, for example, silicon (Si), germanium (Ge), or a mixture thereof. The second semiconductor pattern (332X) may have a crystalline structure including at least one of single crystal, amorphous, and polycrystalline. The second semiconductor pattern (332X) may further include doped impurities. As another example, the second semiconductor pattern (332X) may be an intrinsic semiconductor in an undoped state.

[0036] A second upper dielectric pattern (333X) may be provided within the second trench (TR2) to cover the second semiconductor pattern (332X). The second upper dielectric pattern (333X) may fill the second trench (TR2). For example, the second upper dielectric pattern (333X) may fill the remainder within the second trench (TR2). The second upper dielectric pattern (333X) may include a silicon-containing insulating material. The second upper dielectric pattern (333X) may be formed from an insulating material with excellent gap-fill properties. The second upper dielectric pattern (333X) may be formed, for example, from a high-density plasma oxide film, a SOG film (Spin On Glass layer), and / or a CVD oxide film.

[0037] The cell array structure (300) may further include gate dielectric patterns (323). The gate dielectric patterns (323) may be interposed between the gate structures (320) and the first insulating films (321), and between the gate structures (320) and the vertical channel structures (330X). For example, each of the gate dielectric patterns (323) may be interposed between the corresponding gate structure (320) and the corresponding vertical channel structure (330X), and may extend over the upper and lower surfaces of the corresponding gate structure (320). The gate dielectric pattern (323) may include a high dielectric material. A high dielectric material refers to an insulating material having a dielectric constant higher than that of silicon oxide and may include zirconium oxide, aluminum oxide, and / or hafnium oxide, etc.

[0038] Conductive pads (335) may be disposed on each of the vertical channel structures (330X). The lower surfaces of the conductive pads (335) may be disposed at a level higher than the upper surface of the top gate structure (320). The conductive pads (335) may comprise an impurity-doped semiconductor material or a metal. Each of the conductive pads (335) may be provided within the upper portion of the second trench (TR2). The depth of the second trench (TR2) (A2 in FIG. 2d) may be substantially equal to the sum of the height of the corresponding vertical channel structure (330X) and the height of the corresponding conductive pad (335).

[0039] A capping film may be provided on the vertical channel structures (330X) and the stacked structure. The upper surface of the stacked structure may be the upper surface of the uppermost first insulating film (321). The capping film may include a first capping film (360) and a second capping film (370). The first capping film (360) may cover the upper surfaces of the vertical channel structures (330X) and the upper surface of the uppermost first insulating film (321). For example, the first capping film (360) may include a silicon-containing insulating material.

[0040] Contact plugs (340) may be provided penetrating the first insulating films (321), gate structures (320), and first capping film (360). The contact plugs (340) may be spaced apart from the vertical channel structures (330X). The contact plugs (340) may be provided between the vertical channel structures (330X). The contact plugs (340) may be disposed on the common source regions (314) and may be connected to the common source regions (314). The contact plugs (340) may include a barrier film and a metal film. The barrier film may cover the sidewalls of the metal film. The barrier film may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), and combinations thereof. The metal film may include tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), cobalt (Co), or copper (Cu). The contact plugs (340) may be common source plugs. In a planar view, the major axes of the contact plugs (340) may extend parallel to the second direction (D2).

[0041] Spacers (343) may cover the sidewalls of the contact plugs (340). Each of the spacers (343) may be provided between the first insulating films (321) and the corresponding contact plug (340) and between the gate structures (320) and the corresponding contact plug (340). The spacers (343) may comprise an insulating material. The spacers (343) may comprise a silicon-containing insulating material, for example, silicon oxide, silicon nitride, and / or silicon oxide nitride. As another example, the spacers (343) may comprise a low dielectric material, and the low dielectric material may have a lower dielectric constant than silicon oxide.

[0042] A second capping film (370) may be disposed on the first capping film (360) to cover the upper surfaces of the contact plugs (340). The second capping film (370) may include an insulating material. For example, the second capping film (370) may include a silicon-containing insulating material.

[0043] Upper conductive plugs (350) may be formed within the first capping membrane (360) and the second capping membrane (370). For example, each of the upper conductive plugs (350) may penetrate the second capping membrane (370) and the first capping membrane (360). The upper conductive plugs (350) may be provided on the conductive pads (335) to be connected to the conductive pads (335). The upper conductive plugs (350) may be electrically connected to the vertical channel structures (330X) through the conductive pads (335). The upper conductive plugs (350) may be bitline contact plugs.

[0044] A conductive line (390) is provided on the second capping membrane (370) and the upper conductive plugs (350) so as to be connected to the upper conductive plugs (350). The conductive line (390) may extend in a first direction (D1) in a planar view. The upper conductive plugs (350) and the conductive lines (390) may include a conductive material such as metal. The conductive lines (390) may be bit lines. The conductive line (390) of FIGS. 2c and FIGS. 2d may be any one of a plurality of conductive lines (390), and the plurality of conductive lines (390) may be spaced apart from each other in a second direction (D2) in a planar view.

[0045] Vertical channel structures (330X), contact plugs (340), conductive pads (335), upper conductive plugs (350), and conductive lines (390) may be provided on the device regions (DR) of the substrate (100) but may not be provided on the scribe lane region (SLR). For example, the vertical channel structures (330X), contact plugs (340), conductive pads (335), upper conductive plugs (350), and conductive lines (390) may be spaced apart from the scribe lane region (SLR) of the substrate (100) in a planar view.

[0046] A cell array structure (300) on a scribe lane region (SLR) of a substrate (100) according to the following embodiments will be described in more detail.

[0047] The semiconductor layer (310), first insulating films (321), first capping film (360), and first and second capping films (360, 370) may be provided on the device regions (DR) and scribe lane regions (SLR) of the substrate (100). Second insulating films (324) and a dummy pattern (330Y) may be further provided on the scribe lane regions (SLR) of the substrate (100).

[0048] The second insulating films (324) may be interposed between the first insulating films (321) on the scribe lane region (SLR) of the substrate (100). The second insulating films (324) may not be provided on the device region (DR) of the substrate (100), but are not limited thereto. The second insulating films (324) may be spaced horizontally apart from the gate structures (320). For example, in one device region (DR), the second insulating films (324) may be disposed on the first side of the outermost vertical channel structure (330X) among the vertical channel structures (330X), and the gate structures (320) may be disposed on the second side of the outermost vertical channel structure (330X). The second side of the outermost vertical channel structure (330X) may be opposite to the first side. The second insulating films (324) may include a material different from the first insulating films (321). For example, the first insulating films (321) may include silicon oxide, and the second insulating films (324) may include silicon nitrides.

[0049] The first trench (TR1) is provided on the scribe lane region (SLR) of the substrate (100), but may not be provided on the device regions (DR) of the substrate (100). As shown in FIG. 2a, the first trench (TR1) may have a grid shape in a planar view. For example, in a planar view, the first trench (TR1) may include first sub-trenches and second sub-trenches. The first sub-trenches extend parallel to the first direction (D1) and may be spaced apart from each other in a second direction (D2). The second sub-trenches extend parallel to the second direction (D2) and may be spaced apart from each other in a first direction (D1). The second sub-trenches may be connected to the first sub-trenches. The first trench (TR1) may surround the device regions (DR) of the substrate (100) in a planar view.

[0050] As shown in FIGS. 2c and 2d, a first trench (TR1) may be provided on the dicing region (R1) and dummy region (R2) of the substrate (100). The first trench (TR1) may penetrate the first insulating films (321) and the second insulating films (324). The first trench (TR1) may expose the sidewalls of the first insulating films (321), the sidewalls of the second insulating films (324), and the substrate (100). For example, the bottom surface of the first trench (TR1) may be provided within the semiconductor layer (310). For example, the bottom surface of the first trench (TR1) may be located at a level lower than the upper surface of the semiconductor layer (310) and higher than the lower surface of the semiconductor layer (310). However, the level of the bottom surface of the first trench (TR1) may be varied. The first trench (TR1) may be spaced apart from the vertical channel structures (330X). The bottom surface of the first trench (TR1) may be the recessed inner surface of the semiconductor layer (310).

[0051] The bottom surface of the first trench (TR1) may be provided at substantially the same level as the bottom surface of the second trench (TR2). As shown in FIG. 2d, the depth (A1) of the first trench (TR1) may be substantially the same as the depth (A2) of the second trench (TR2). The fact that the widths, depths, heights, and levels of certain components are identical to one another may mean that the range of error that may occur during the process is identical. The depth (A1) of the first trench (TR1) may be, for example, 8 μm to 20 μm. The depth (A2) of the second trench (TR2) may be, for example, 8 μm to 20 μm.

[0052] The width (W1) of the first trench (TR1) may be larger than the width of the second trench (TR2). The width (W1) of the first trench (TR1) may be, for example, 10 nm to 100 nm. Since the width (W1) of the first trench (TR1) is 10 nm or more, a void (VO) to be described later may be provided within the first trench (TR1).

[0053] A dummy pattern (330Y) may be provided on the bottom surface and sidewall of the first trench (TR1). The dummy pattern (330Y) may have a “U” shaped cross-section. The dummy pattern (330Y) may conformally cover the bottom surface and sidewall of the first trench (TR1). For example, the thickness of the dummy pattern (330Y) on the bottom surface of the first trench (TR1) may be the same as or similar to the thickness of the dummy pattern (330Y) on the sidewall of the first trench (TR1). The dummy pattern (330Y) may not be provided on the device regions (DR) of the substrate (100). The dummy pattern (330Y) may be spaced apart from the vertical channel structures (330X). The dummy pattern (330Y) may contain the same material as the vertical channel structures (330X). The height of the dummy pattern (330Y) may be substantially equal to the depth (A1) of the first trench (TR1). The height of the dummy pattern (330Y) may be substantially equal to the sum of the height of any one of the vertical channel structures (330X) and the height of the corresponding conductive pad (335). The sum of the height of any one of the vertical channel structures (330X) and the height of the corresponding conductive pad (335) may be substantially equal to the depth (A2) of the corresponding second trench (TR2).

[0054] As shown in FIG. 2d, the bottom surface (330Yb) of the dummy pattern (330Y) may be placed at substantially the same level as the bottom surfaces (330Xb) of the vertical channel structures (330X). The bottom surface (330Yb) of the dummy pattern (330Y) may correspond to the bottom surface of the first trench (TR1), and the bottom surfaces (330Xb) of the vertical channel structures (330X) may correspond to the bottom surface of the second trench (TR2).

[0055] The dummy pattern (330Y) may include a first lower dielectric pattern (331Y), a first semiconductor pattern (332Y), and a first upper dielectric pattern (333Y). The first lower dielectric pattern (331Y) may cover the bottom surface and sidewalls of the first trench (TR1). The first lower dielectric pattern (331Y) may include a silicon-based insulating material or a high dielectric material. The first lower dielectric pattern (331Y) may include the same material as the second lower dielectric pattern (331X). The thickness of the first lower dielectric pattern (331Y) may be substantially the same as the thickness of the second lower dielectric pattern (331X).

[0056] The first semiconductor pattern (332Y) is provided on the bottom surface and sidewall of the first trench (TR1) and may cover the first lower dielectric pattern (331Y). The first semiconductor pattern (332Y) may include any one of the materials described in the example of the second semiconductor pattern (332X). For example, the first semiconductor pattern (332Y) may include a material identical to that of the second semiconductor pattern (332X). The thickness of the first semiconductor pattern (332Y) may be substantially the same as the thickness of the second semiconductor pattern (332X).

[0057] The first upper dielectric pattern (333Y) is provided on the bottom surface and sidewall of the first trench (TR1) and may cover the first semiconductor pattern (332Y). The first upper dielectric pattern (333Y) may include a silicon-containing insulating material. The first upper dielectric pattern (333Y) may include the same material as the second upper dielectric pattern (333X). The thickness of the first upper dielectric pattern (333Y) may be substantially the same as the thickness of the second upper dielectric pattern (333X).

[0058] The first capping membrane (360) can block the entrance of the first trench (TR1). The bottom surface of the first capping membrane (360) may be vertically spaced from the upper surface (330Ya) of the dummy pattern (330Y) on the bottom surface of the first trench (TR1). The bottom surface of the first capping membrane (360) may be spaced from the side wall of the dummy pattern (330Y) on the side wall of the first trench (TR1). Accordingly, a void (VO) may be provided within the first trench (TR1). The void (VO) may be a space enclosed by the dummy pattern (330Y) and the first capping membrane (360). Specifically, it may be the space between the upper surface (330Ya) of the dummy pattern (330Y) on the bottom surface of the first trench (TR1) of the void (VO), the side wall of the dummy pattern (330Y) on the side wall of the first trench (TR1), and the lower surface of the first capping membrane (360). The void (VO) may be a vacuum-state empty space or an empty space occupied by air.

[0059] As shown in FIG. 2d, the width (W10) and height of the void (VO) may be smaller than the width (W1) and depth (A1) of the first trench (TR1), respectively. The void (VO) may surround the device regions (DR) of the substrate (100) in a planar view.

[0060] A void (VO) is provided on the scribe lane region (SLR) of the substrate (100) and may not be provided on the device regions (DR). For example, the void (VO) may be provided on the dicing region (R1 in FIG. 2c and 2d) and dummy region (R2 in FIG. 2c and 2d) of the substrate (100) in a planar view.

[0061] As shown in FIG. 2a, the shape and arrangement of the void (VO) in a planar view may be similar to the first trench (TR1). For example, the void (VO) may have the shape of a grid in a planar view. For example, the void (VO) may have parts extended in a first direction (D1) and parts extended in a second direction (D2) in a planar view.

[0062] Although not illustrated, the wafer structure (1000) may further include a connecting conductive structure. The connecting conductive structure may be connected to any one of the conductive lines (390) and any one of the lower wirings (230). Accordingly, the cell array structure (300) may be electrically connected to the logic structure (200). Being electrically connected to the logic structure (200) may mean being electrically connected to peripheral circuits (250). Being electrically connected to the cell array structure (300) may mean being electrically connected to at least one of the gate structures (320) or the conductive lines (390). Electrical connection may include direct connection and indirect connection through other components.

[0063] A wiring layer (400) may be disposed on a conductive line (390). The wiring layer (400) may include a front-end layer (FEOL) and a back-end layer (BEOL). The wiring layer (400) may include upper insulating layers (410) and conductive patterns (450). The upper insulating layers (410) may be laminated on the conductive line (390). The upper insulating layers (410) may include a silicon-containing insulating material.

[0064] The conductive patterns (450) may include wiring patterns and via patterns. The wiring patterns may be interposed between the upper insulating layers (410). Each of the via patterns may penetrate a corresponding one of the upper insulating layers (410). The via patterns are interposed between the wiring patterns and may be electrically connected to the wiring patterns. The conductive patterns (450) may include a metal such as copper or tungsten. The conductive patterns (450) may be electrically connected to corresponding conductive lines (390). The conductive patterns (450) may be provided on the device regions (DR) of the substrate (100).

[0065] Chip pads (550) may be disposed on the upper surface of the wiring layer (400). The chip pads (550) may be electrically connected to the conductive patterns (450). The chip pads (550) may be spaced apart from each other and may be electrically isolated from each other. The chip pads (550) may include, for example, aluminum. As another example, the chip pads (550) may include metals such as nickel, gold, copper, and tungsten. The chip pads (550) may be provided on the device regions (DR) of the substrate (100) but may not be provided on the scribe lane region (SLR).

[0066] The wafer structure (1000) may further include solder balls (500). The solder balls (500) may each be provided on the chip pads (550). The solder balls (500) may include solder materials such as tin, lead, silver, and alloys thereof.

[0067] A protective layer (PL) may be disposed on the upper surface of the wiring layer (400). The protective layer (PL) covers the upper surface of the wiring layer (400) and may expose the chip pads (550). The protective layer (PL) may comprise a material different from the upper insulating layers (410). For example, the protective layer (PL) may comprise an insulating polymer such as polyimide or photosensitive polyimide (PSPI).

[0068] An opening (510) may be provided on the scribe lane region (SLR) of the substrate (100). The protective layer (PL) may have an opening (510). The opening (510) may penetrate the protective layer (PL). The opening (510) may expose the upper surface of the wiring layer (400). For example, the opening (510) may expose the upper surface of the uppermost of the upper insulating layers (410). For example, the opening (510) may expose the upper surface of the wiring layer (400) on the scribe lane region (SLR) of the substrate (100). The opening (510) may define the scribe lane region (SLR) of the substrate (100). For example, the opening (510) may be provided on the dicing region (R1) of the substrate (100). The opening (510) may be extended further onto the dummy area (R2) of the substrate (100). The width (W3) of the opening (510) may be greater than the width (W1) of the first trench (TR1) and greater than the width (W10) of the void (VO).

[0069] The opening (510) may have a grid shape in a planar view. For example, the opening (510) may include first openings and second openings. The first openings may extend parallel to the first direction (D1) and may be spaced apart from each other in the second direction (D2). The second openings may extend parallel to the second direction (D2) and may be spaced apart from each other in the first direction (D1). The second openings may be connected to the first openings.

[0071] FIG. 2e is a drawing for explaining voids according to embodiments. Below, descriptions that overlap with those previously described are omitted.

[0072] Referring to FIG. 2e, the first capping film (360) blocks the entrance of the first trench (TR1), and a void (VO) can be provided within the first trench (TR1). At this time, the first capping film (360) may extend further into the upper part of the first trench (TR1). For example, the first capping film (360) may include a protrusion, and the protrusion may extend into the upper part of the first trench (TR1). The first capping film (360) may have a first lower surface (360b1) and a second lower surface (360b2). The first lower surface (360b1) of the first capping film (360) may be placed on the uppermost first insulating film (321). The second lower surface (360b2) of the first capping membrane (360) is connected to the first lower surface (360b1) and may be provided on or within the first trench (TR1). For example, the second lower surface (360b2) of the first capping membrane (360) may overlap with the void (VO). The second lower surface (360b2) of the first capping membrane (360) may be provided at a lower level than the first lower surface (360b1). The second lower surface (360b2) of the first capping membrane (360) may be the lower surface of the protrusion.

[0074] FIG. 3a is a plan view illustrating a wafer structure according to embodiments, and is an enlarged view of region I of FIG. 1. FIG. 3b is a cross-section taken along the line II-II' of FIG. 3a.

[0075] Referring to FIGS. 3a and 3b, the wafer structure (1000) may include a substrate (100), a logic structure (200), a cell array structure (300), a wiring layer (400), chip pads (550), and a protection layer (PL).

[0076] The cell array structure (300) may have a plurality of first trenches (TR1). Each of the first trenches (TR1) may be provided on the scribe lane region (SLR) of the substrate (100) described in the examples of FIGS. 2a through 2d. A first capping film (360) may block the entrance of the first trenches (TR1), so that voids (VO) may be provided within each of the first trenches (TR1). The cell array structure (300) may include a plurality of dummy patterns (330Y). The dummy patterns (330Y) may cover the bottom surfaces and side walls of the first trenches (TR1). The dummy patterns (330Y) may be spaced laterally from each other, but are not limited thereto. At least one of the first trenches (TR1), at least one of the voids (VO), and at least one of the dummy patterns (330Y) may overlap vertically with the dicing area (R1) described in the example of FIG. 2c.

[0077] Hereinafter, for the sake of simplification, a single first trench (TR1), a single void (VO), and a single dummy pattern (330Y) are described, but the present invention is not limited thereto.

[0079] Hereinafter, a method for manufacturing a wafer structure according to the embodiments is described.

[0080] FIGS. 4a to 4j are drawings for explaining a method of manufacturing a wafer structure according to embodiments, and correspond to drawings showing an enlarged view of region III of FIG. 2a. Hereinafter, content that overlaps with what has been previously described is omitted.

[0081] Referring to FIG. 4a, a logic structure (200) may be formed on a substrate (100). The logic structure (200) may be substantially the same as described in the examples of FIG. 2b through 2d.

[0082] A semiconductor layer (310) may be formed on a logic structure (200). A first insulating layer may be formed on the semiconductor layer (310), and a second insulating layer (324) may be formed on the first insulating layer (321). The first insulating layer (321) and the second insulating layer (324) may be formed repeatedly to form alternately stacked first insulating layers (321) and second insulating layers (324). A lower first insulating layer (321) may be provided between the semiconductor layer (310) and the lower second insulating layer (324). An upper first insulating layer (321) may be provided on the upper second insulating layer (324). A portion of each of the second insulating layers (324) may function as sacrificial layers.

[0083] Referring to FIG. 4b, a first trench (TR1) and a second trench (TR2) may be formed. The first trench (TR1) is formed on the scribe lane region (SLR) of the substrate (100) and may penetrate the first insulating films (321) and the second insulating films (324). The second trench (TR2) may include a plurality of second trenches (TR2) spaced apart from each other. The second trenches (TR2) are formed on the device regions (DR) of the substrate (100) and may penetrate the first insulating films (321) and the second insulating films (324). Each of the first trench (TR1) and the second trenches (TR2) may expose the substrate (100). The first trench (TR1) and the second trenches (TR2) may be formed by a single process. For example, the first trench (TR1) can be formed by a single etching process with the second trenches (TR2). Accordingly, the depth (A1) of the first trench (TR1) may be substantially the same as the depths (A2) of the second trenches (TR2). However, the width (W1) of the first trench (TR1) may be greater than the width (W2) of the second trench (TR2).

[0084] Referring to FIG. 4c, a lower dielectric layer (331), a semiconductor pattern (332), and an upper dielectric layer (333) are formed on the uppermost first insulating film (321) and can extend into the first trench (TR1) and the second trenches (TR2).

[0085] According to the embodiments, a lower dielectric layer (331) is formed on the uppermost first insulating film (321) and may cover the bottom surface and side walls of the first trench (TR1) and the bottom surface and side walls of the second trenches (TR2). The lower dielectric layer (331) may be formed by a deposition process. The lower dielectric layer (331) may include, for example, a silicon-based insulating material or a high dielectric material.

[0086] A semiconductor pattern (332) is formed on the uppermost first insulating film (321) and can cover the lower dielectric layer (331). The semiconductor pattern (332) extends over the bottom surface and sidewalls of the first trench (TR1) and the bottom surface and sidewalls of the second trenches (TR2) to conformally cover the lower dielectric layer (331). The semiconductor pattern (332) can be formed by a deposition process such as thermal chemical vapor deposition (Thermal CVD), plasma enhanced CVD, physical chemical vapor deposition (physical CVD), or atomic layer deposition (ALD) technology.

[0087] An upper dielectric layer (333) is formed on the uppermost first insulating film (321) and can cover the semiconductor pattern (332). The upper dielectric layer (333) can extend into the first trench (TR1) and the second trenches (TR2). The second trenches (TR2) have a relatively small width (W2) so that the upper dielectric layer (333) can fill the remainder of the second trenches (TR2).

[0088] The upper dielectric layer (333) may extend over the sidewalls and bottom surface of the first trench (TR1). The width (W1) of the first trench (TR1) may be relatively large. For example, the width (W1) of the first trench (TR1) may be larger than the width (W2) of the second trenches (TR2). Accordingly, the upper dielectric layer (333) may not fill the first trench (TR1). The upper dielectric layer (333) may have a “U” shaped cross-section within the first trench (TR1). For example, the upper dielectric layer (333) may conformally cover the semiconductor pattern (332) on the bottom surface and sidewalls of the first trench (TR1). After the upper dielectric layer (333) is formed, an empty space may be provided within the first trench (TR1).

[0089] Referring to FIG. 4d, the upper dielectric layer (333) can be patterned to form a first upper dielectric pattern (333Y) and a second upper dielectric pattern (333X). The first upper dielectric pattern (333Y) and the second upper dielectric pattern (333X) can be separated from each other.

[0090] The semiconductor layer (310) can be patterned to form a first semiconductor pattern (332Y) and a second semiconductor pattern (332X). The first semiconductor pattern (332Y) and the second semiconductor pattern (332X) can be separated from each other.

[0091] The lower dielectric layer (331) can be patterned to form a first lower dielectric pattern (331Y) and a second lower dielectric pattern (331X). By patterning the lower dielectric layer (331), the upper surface of the uppermost first insulating film (321) can be exposed. Accordingly, vertical channel structures (330X) and a dummy pattern (330Y) can be formed. The dummy pattern (330Y) may include a first lower dielectric pattern (331Y), a first semiconductor pattern (332Y), and a first upper dielectric pattern (333Y). The first lower dielectric pattern (331Y), the first semiconductor pattern (332Y), and the first upper dielectric pattern (333Y) may be provided within a corresponding first trench (TR1).

[0092] Each of the vertical channel structures (330X) may include a second lower dielectric pattern (331X), a second semiconductor pattern (332X), and a first upper dielectric pattern (333Y). The second lower dielectric pattern (331X), the second semiconductor pattern (332X), and the second upper dielectric pattern (333X) may be provided within a corresponding second trench (TR2). The second lower dielectric pattern (331X), the second semiconductor pattern (332X), and the second upper dielectric pattern (333X) may not be provided on the upper portion of the corresponding second trench (TR2).

[0093] Conductive pads (335) are formed on the upper surface of the second trenches (TR2) and can cover the upper surfaces of the vertical channel structures (330X).

[0094] Referring to FIG. 4e, a first capping film (360) is formed on the uppermost first insulating film (321) to cover the upper surfaces of the conductive pads (335). The formation of the first capping film (360) can be performed by a deposition process. The deposition process can be performed on the device regions (DR) and scribe lane regions (SRL) of the substrate (100). The first capping film (360) has low step coverage characteristics so as to block the entrance of the first trench (TR1). The lower surface of the first capping film (360) can be vertically spaced from the upper surface of the dummy pattern (330Y) on the bottom surface of the first trench (TR1). Accordingly, a void (VO) can be formed within the first trench (TR1). The void (VO) may be surrounded by a dummy pattern (330Y) and a first capping membrane (360). Unlike what is shown, a portion of the first capping membrane (360) may extend further into the upper part of the first trench (TR1). In this case, a void (VO) as described in the example of FIG. 2e may be formed.

[0095] Referring to FIG. 4f, third trenches (TR3) may be formed within the first capping film (360), the first insulating films (321), and the second insulating films (324). Each of the third trenches (TR3) may expose the semiconductor layer (310) by penetrating the first capping film (360), the first insulating films (321), and the second insulating films (324). The bottom surfaces of the third trenches (TR3) may be provided at the same or different level as the first trench (TR1). The side walls of the third trenches (TR3) may expose the first insulating films (321) and the second insulating films (324). The third trenches (TR3) may be formed between adjacent second trenches (TR2). The third trenches (TR3) may not be formed on the scribe lane region (SLR) of the substrate (100). The third trenches (TR3) may be formed by an anisotropic etching process.

[0096] Referring to FIG. 4g, the second insulating films (324) may be removed to form gate regions (329). The gate regions (329) may be voids. The gate regions (329) are formed between the first insulating films (321) and may be connected to the third trenches (TR3). The gate regions (329) may expose portions of the sidewalls of the vertical channel structures (330X). The thicknesses of the gate regions (329) may be substantially the same as the thicknesses of the removed second insulating films (324). The removal of the second insulating films (324) may be performed by an etching process. The etching process may be a wet etching process.

[0097] Referring to FIG. 4h, gate dielectric patterns (323) and gate structures (320) can each be formed within gate regions (329).

[0098] According to the embodiments, a preliminary dielectric film (not shown) may be formed within the third trenches (TR3) and gate regions (329). The preliminary dielectric film may be formed by depositing a material with good step coverage.

[0099] Forming gate structures (320) may include forming a gate conductive film and patterning the gate conductive film. The gate conductive film may be formed on a pre-dielectric film. The gate conductive film may fill at least a portion of each of the third trenches (TR3) and the gate regions (329). By patterning the gate conductive film, the gate structures (320) may be localized within the gate regions (329). Patterning the gate conductive film may be performed by an etching process.

[0100] Subsequently, the preliminary dielectric film can be patterned to form gate dielectric patterns (323). The patterning of the preliminary dielectric film can be performed by an etching process. The gate dielectric pattern (323) can be localized to gate regions (329). The arrangement of the gate dielectric patterns (323) and the gate structures (320) is as described in the examples of FIGS. 2b through 2d.

[0101] Common source regions (314) may be formed within the semiconductor layer (310) exposed to the third trenches (TR3). The common source regions (314) may be formed through an ion implantation process. The common source regions (314) may overlap with at least one portion of the first insulating films (321) in a planar view by the diffusion of impurities. The common source regions (314) may have a conductivity type different from that of the semiconductor layer (310). The formation of the common source regions (314) may be performed before or after the formation of the gate structures (320).

[0102] Referring to FIG. 4i, spacers (343) and contact plugs (340) may each be formed within the third trenches (TR3). The spacers (343) may cover the sidewalls of the gate structures (320). Contact plugs (340) may be formed on the inner sidewalls of the spacers (343) to fill the third trenches (TR3). The contact plugs (340) may each be connected to the common source regions (314). Forming the contact plugs (340) may include depositing a barrier film covering the sidewalls of the spacers (343) and depositing a metal film on the barrier film.

[0103] A second capping film (370) is formed on the first capping film (360) to cover the upper surfaces of the contact plugs (340).

[0104] Referring to FIG. 4j, upper conductive plugs (350) may be formed within the second capping film (370) and the first capping film (360). The upper conductive plugs (350) may penetrate the second capping film (370) and the first capping film (360) and be connected to the conductive pads (335), respectively.

[0105] Conductive patterns (450) are formed on the second capping membrane (370) and can be connected to the upper conductive plugs (350).

[0106] Referring again to FIG. 2b, a wiring layer (400) can be formed on conductive patterns (450). Chip pads (550) and a protective layer (PL) can be formed on the wiring layer (400). Solder balls (500) can be formed on the chip pads (550). Accordingly, the manufacturing of the wafer structure (1000) can be completed.

[0108] Hereinafter, a dicing process of a wafer structure and a semiconductor device according to the embodiments are described.

[0109] FIGS. 5a and FIGS. 6a are drawings for explaining a dicing process according to embodiments. FIG. 5b is an enlarged view of region III of FIG. 5a. FIG. 6b is an enlarged view of region III of FIG. 6a.

[0110] Referring to FIGS. 5a and 5b, a wafer structure (1000) may be prepared. The wafer structure (1000) may include a substrate (100), a logic structure (200), a cell array structure (300), a wiring layer (400), chip pads (550), and a protection layer (PL) as previously described. The cell array structure (300) has a first trench (TR1), and a void (VO) may be provided within the first trench (TR1). The void (VO) may be surrounded by a dummy pattern (330Y) and a first capping film (360).

[0111] A laser device (900) may be disposed on the lower surface of a substrate (100). A laser from the laser device (900) may be irradiated into the substrate (100), so that the substrate (100) may be locally heated. The crystal structure of the heated region of the substrate (100) may be deformed. Accordingly, amorphous portions (190) may be formed within the substrate (100). The laser may be irradiated along the scribe lane region (SLR) of the substrate (100), so that the amorphous portions (190) may overlap with the scribe lane region (SLR) in a planar view. Specifically, as shown in FIG. 5b, the amorphous portions (190) may be formed within the dicing region (R1) of the substrate (100). The amorphous portions (190) may be formed at different depths within the substrate (100). For example, amorphous portions (190) may be provided at different distances from the lower surface of the substrate (100). The amorphous portions (190) may be spaced vertically apart from each other within the substrate (100).

[0112] Referring to FIGS. 6a and 6b, a grinding process is performed on the lower surface of the substrate (100) so that a portion of the substrate (100) can be removed as shown by the dotted line. The substrate (100) can be thinned by the grinding process. The grinding process of the substrate (100) may include a back lap process or a chemical mechanical polishing process. In the grinding process of the substrate (100), the amorphous portions (190) of the substrate (100) can act as crack seeds. For example, cracks can be formed from the amorphous portions (190) of the substrate (100). The cracks can propagate vertically from the amorphous portions (190) toward the lower surface of the substrate (100) and the upper surface of the wiring layer (400). The wafer structure (1000) can be diced by the propagation of the cracks.

[0113] If the void (VO) is omitted, the crack may propagate along the interface between the first insulating films (321) and the second insulating films (324) as it crosses the first insulating films (321) and the second insulating films (324) of the substrate (100). Since the crack propagates horizontally, the wafer structure (1000) may be difficult to dice. Additionally, the vertical channel structures (330X) or gate structures (320) within the device regions (DR) of the substrate (100) may be damaged by the horizontal propagation of the crack. According to the embodiments, since the void (VO) is provided on the dicing region (R1) of the substrate (100), the interface between the first insulating films (321) and the second insulating films (324) may not be provided on the dicing region (R1) of the substrate (100). Accordingly, the horizontal propagation of the crack may be prevented. Cracks can easily pass through the cell array structure (300) through the void (VO). In addition, the wafer structure (1000) can be diced well.

[0114] A dicing region (R1) of a substrate (100) can be removed by a dicing process of a wafer structure (1000). Additionally, a portion of a logic structure (200), a portion of a cell array structure (300), and a portion of a wiring layer (400) on the dicing region (R1) of the substrate (100) can be removed.

[0115] At least a portion of the dummy region (R2) of the substrate (100) may not be removed during the dicing process. Since the dummy region (R2) of the substrate (100) is provided, damage to the logic structure (200), cell array structure (300), and wiring layer (400) on the device regions (DR) of the substrate (100) can be prevented during the dicing process. For example, damage to peripheral circuits (250), lower wiring (230), vertical channel structures (330X), gate structures (320), conductive lines (390), and conductive patterns (450) can be prevented.

[0116] As a result of the above dicing process, semiconductor devices (10) separated from each other may be formed. Each of the semiconductor devices (10) may include any one of the device regions (DR) of the substrate (100). Each of the semiconductor devices (10) may include a logic structure (200), a cell array structure (300), and a wiring layer (400) corresponding to the device region (DR). In addition, each of the semiconductor devices (10) may include a corresponding dummy region (R2) of the substrate (100), and a logic structure (200), a wiring structure, a wiring layer (400), a protection layer (PL), chip pads (550), and solder balls (500) on the dummy region (R2). A plurality of dummy patterns (330Y') separated from each other may be formed by the dicing process. A first trench (TR1) may be diced to form a recessed portion (RP).

[0117] Some amorphous portions (190) may remain within the dummy region (R2) of the substrate (100). As another example, the amorphous portions (190) may be removed along with the dicing region (R1) of the substrate (100) so that they do not remain in the semiconductor device (10).

[0118] The manufacturing of semiconductor devices (10) can be completed by the examples described so far. Each of the semiconductor devices (10) may be a semiconductor chip.

[0119] Below, semiconductor devices (10) will be described in more detail. For simplification, a single semiconductor device (10) will be described.

[0121] FIG. 7a is a cross-sectional view illustrating a semiconductor device according to embodiments. FIG. 7b is an enlarged view of region V of FIG. 7a.

[0122] Referring to FIGS. 7a and 7b, the semiconductor device (10) may include a substrate (100), a logic structure (200), a cell array structure (300), a wiring layer (400), a protective layer (PL), chip pads (550), and solder balls (500). The semiconductor device (10) may be any one of the semiconductor devices (10) formed by the dicing process of the wafer structure (1000) described in the examples of FIGS. 5a to 6b. The outer wall of the semiconductor device (10) may be a cut surface. The outer wall of the semiconductor device (10) may include the outer wall (100c) of the substrate (100), the outer wall of the logic structure (200), the outer wall (300c) of the cell array structure (300), and the outer wall of the wiring layer (400). The outer wall of the semiconductor device (10) may be exposed to the outside.

[0123] The substrate (100) may include a device region (DR) and a dummy region (R2). The dummy region (R2) of the substrate (100) may be an edge region. For example, the dummy region (R2) of the substrate (100) may surround the device region (DR) in a planar view. An amorphous portion (190) may remain on the outer wall (100c) of the substrate (100). The amorphous portion (190) may be exposed to the outside.

[0124] A logic structure (200) may be provided on a substrate (100). The logic structure (200) may be vertically aligned with the outer wall (100c) of the substrate (100).

[0125] A cell array structure (300) may be provided on a logic structure (200). The cell array structure (300) may include a dummy pattern (330Y'), first insulating layers (321), second insulating layers (324), gate structures (320), vertical channel structures (330X), contact plugs (340), spacers (343), a first capping layer (360), a second capping layer (370), and a conductive line (390).

[0126] The outer wall (300c) of the cell array structure (300) may be exposed by the substrate (100) and the logic structure (200). The cell array structure (300) may have a recessed portion (RP) on its outer wall (300c). The recessed portion (RP) may be provided on the outer walls of the first insulating films (321) and the outer walls of the second insulating layer. As a result of performing a dicing process on the first trench (TR1) and void (VO) described in the examples of FIGS. 2a through 2d, the recessed portion (RP) may be formed. For example, the recessed portion (RP) may be a portion of the first trench (TR1) remaining as a result of the dicing process. The width (W11) of the recessed portion (RP) may be approximately 3 nm to 50 nm. In detail, the width (W11) of the recessed portion (RP) may be approximately 5 nm to 50 nm. The width (W11) of the recessed portion (RP) may be substantially equal to the horizontal gap between the outer surface of the semiconductor layer (310) and the outer surfaces of the first insulating films (321). The outer surface of the semiconductor layer (310) may correspond to the outer wall (300c) of the cell array structure (300). The width (W11) of the recessed portion (RP) may be equal to or greater than the width (W2) of the second trench (TR2).

[0127] A dummy pattern (330Y') is provided on a recessed portion (RP) to cover the bottom surface and side walls of the recessed portion (RP). For example, the dummy pattern (330Y') can conformally cover the top surface of the substrate (100), the outer surfaces of the first insulating films (321), and the outer surfaces of the second insulating films (322). The dummy pattern (330Y') may have an “L” shape or a shape symmetrical to an “L”. The dummy pattern (330Y') may include a first lower dielectric pattern (331Y'), a first semiconductor pattern (332Y'), and a first upper dielectric pattern (333Y'). The first lower dielectric pattern (331Y'), the first semiconductor pattern (332Y'), and the first upper dielectric pattern (333Y') may be substantially the same as described in the example of the first lower dielectric pattern (331Y), the first semiconductor pattern (332Y), and the first upper dielectric pattern (333Y) of FIGS. 2a to 2d or the example of the first lower dielectric pattern (331Y), the first semiconductor pattern (332Y), and the first upper dielectric pattern (333Y) of FIG. 2e. However, the shape of the first lower dielectric pattern (331Y'), the first semiconductor pattern (332Y'), and the first upper dielectric pattern (333Y') may differ from the shape of the first lower dielectric pattern (331Y), the first semiconductor pattern (332Y), and the first upper dielectric pattern (333Y) of FIG. 2a to 2d or FIG. 2e. Each of the first lower dielectric pattern (331Y'), the first semiconductor pattern (332Y'), and the first upper dielectric pattern (333Y') may have an “L” shape or a shape that is symmetrical to an “L”.

[0128] The outer wall of the dummy pattern (330Y') on the side wall of the recessed portion (RP) may not be vertically aligned with the outer wall (100c) of the substrate (100) and the outer wall of the logic structure (200). The outer wall of the dummy pattern (330Y') on the side wall of the recessed portion (RP) may be more recessed than the outer wall (100c) of the substrate (100).

[0129] The first capping film (360) may extend further over the dummy area (R2) of the substrate (100). The outer wall of the first capping film (360) may protrude horizontally further than the outer wall of the dummy pattern (330Y') on the side of the recessed portion (RP). The lower surface of the first capping film (360) on the dummy area (R2) of the substrate (100) may overlap vertically with the upper surface of the recessed portion (RP). The lower surface of the first capping film (360) on the dummy area (R2) of the substrate (100) may be spaced vertically apart from the upper surface of the dummy pattern (330Y') on the upper surface of the recessed portion (RP). A gap area may be provided between the lower surface of the first capping film (360) on the dummy area (R2) of the substrate (100) and the upper surface of the dummy pattern (330Y') on the upper surface of the recessed portion (RP). The outer wall of the first capping film (360) may be vertically aligned with the outer wall (100c) of the substrate (100), but is not limited thereto.

[0130] The second capping film (370) and the wiring layer (400) can be placed on the first capping film (360).

[0131] A protective layer (PL) may be placed on a wiring layer (400). A diced opening (510) of the protective layer (PL) may overlap with a dummy area (R2) of the substrate (100). The outer wall of the protective layer (PL) may not be vertically aligned with the outer wall of the wiring layer (400). The gap (W31) between the outer wall of the protective layer (PL) and the outer wall of the wiring layer (400) may be larger than the width (W11) of the recessed portion (RP). The gap (W31) between the outer wall of the protective layer (PL) and the outer wall of the wiring layer (400) may be smaller than the width (W3) of the opening (510) of FIG. 2C. Each of the semiconductor devices (10) may include a memory device such as a NAND flash. Each of the semiconductor devices (10) may further include a logic device such as a digital signal processor or a controller.

[0133] FIG. 7c is a drawing for explaining the recessed portion and the first capping membrane according to the embodiments, and corresponds to an enlarged view of region V of FIG. 7a.

[0134] Referring to FIG. 7c, the outer wall of the first capping film (360) may not be vertically aligned with the outer wall (100c) of the substrate (100). The outer wall of the first capping film (360) may not protrude further than the outer wall of the dummy pattern (330Y') on the side of the recessed portion (RP). For example, the outer wall of the first capping film (360) may be vertically aligned with the outer wall of the dummy pattern (330Y') on the side of the recessed portion (RP). Alternatively, the outer wall of the first capping film (360) may be horizontally more recessed than the outer wall of the dummy pattern (330Y') on the side of the recessed portion (RP).

[0136] FIG. 7d is a drawing for explaining the recessed portion and the first capping membrane according to the embodiments, and corresponds to an enlarged view of region V of FIG. 7a.

[0137] Referring to FIG. 7d, the outer wall of the first capping film (360) may protrude horizontally further than the outer wall of the dummy pattern (330Y') on the side of the recessed portion (RP). The outer wall of the first capping film (360) may protrude further than the outer wall (100c) of the substrate (100) in a planar view.

[0139] FIG. 8a is a diagram illustrating a semiconductor device according to embodiments. FIG. 8b is an enlarged view of region V of FIG. 8a.

[0140] Referring to FIGS. 8a and 8b, the semiconductor device (10A) may include a substrate (100), a logic structure (200), a cell array structure (300), a wiring layer (400), a protection layer (PL), chip pads (550), and solder balls (500). The semiconductor device (10A) may be formed by dicing the wafer structure described in the example of FIGS. 3a and 3b.

[0141] The cell array structure (300) may have a recessed portion (RP) and a first trench (TR1). The recessed portion (RP) may be substantially the same as described in the examples of FIGS. 7a through 7d. The cell array structure (300) includes a dummy pattern (330Y'), and the dummy pattern (330Y') may be provided on the sidewalls and bottom surfaces of the recessed portion (RP).

[0142] A void (VO) may be provided within the first trench (TR1). The first trench (TR1) and the void (VO) may be provided on a dummy region (R2) of the substrate (100). The first trench (TR1) and the void (VO) may be provided between the recessed portion (RP) of the substrate (100) and the device region (DR) of the substrate (100), as shown in FIG. 8B. For example, the first trench (TR1) may be interposed between a dummy pattern (330Y') and an outermost vertical channel structure (330X). The cell array structure (300) may include a dummy pattern (330Y'). The dummy pattern (330Y') may be provided on the bottom surface and sidewall of the first trench (TR1). The void (VO), dummy pattern (330Y'), and first trench (TR1) may be substantially the same as described in the examples of the void (VO), dummy pattern (330Y), and first trench (TR1) of FIGS. 2a to 2d or the examples of the void (VO), dummy pattern (330Y), and first trench (TR1) of FIGS. 3a and 3b.

[0144] FIG. 9 is a drawing for illustrating a semiconductor package according to embodiments.

[0145] Referring to FIG. 9, the semiconductor package (1) may further include a package substrate (20) and a semiconductor device (10). The package substrate (20) may be, for example, a printed circuit board (PCB) or a redistribution layer. The package substrate (20) may include lower substrate pads (22), upper substrate pads (21), and substrate wiring (23). The lower substrate pads (22) and the upper substrate pads (21) may be disposed on the lower surface and the upper surface of the package substrate (20), respectively. The substrate wiring (23) may be provided within the package substrate (20). The upper substrate pads (21) may be electrically connected to the lower substrate pads (22). The lower substrate pads (22), the upper substrate pads (21), and the substrate wiring (23) may include a conductive material such as metal.

[0146] The semiconductor package (1) may further include solder terminals (50). The solder terminals (50) may each be disposed on the lower substrate pads (22). The solder terminals (50) may include a solder material.

[0147] A semiconductor device (10) may be mounted on a substrate (100). Mounting the semiconductor device (10) may include connecting solder balls (500) to upper substrate pads (21). Accordingly, the semiconductor device (10) may be electrically and physically connected to the package substrate (20). The semiconductor device (10) may be the same as the semiconductor device (10) described in the example of FIGS. 7a and 7b. As another example, the semiconductor device (10) may be the semiconductor device (10A) described in the example of FIGS. 8a and 8b mounted on the package substrate (20).

[0148] The semiconductor package (1) may further include a molding film. The molding film may be placed on the upper surface of the package substrate (20) to cover the semiconductor device (10). The molding film may include an insulating polymer such as an epoxy-based molding compound.

[0150] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments and may be used in various other combinations, modifications, and environments without departing from the essence of the invention.

Claims

Claim 1 A semiconductor device comprising: a substrate having a device region and a dummy region surrounding the device region in a planar view; and a cell array structure provided on the substrate and comprising first insulating layers, gate structures, a vertical channel structure, and a dummy pattern, wherein the vertical channel structure overlaps with the device region of the substrate and penetrates the gate structures and the first insulating layers, the outer wall of the cell array structure is exposed by the substrate, and a recessed portion is provided on the outer wall of the cell array structure, wherein the dummy pattern covers the sidewall and bottom surface of the recessed portion, and the dummy pattern comprises the same material as the vertical channel structure. Claim 2 A semiconductor device according to claim 1, wherein the dummy pattern is spaced apart from the vertical channel structure, and the dummy pattern includes a first semiconductor pattern and a first upper dielectric pattern stacked on a first lower dielectric pattern. Claim 3 In claim 2, the vertical channel structure comprises: a second lower dielectric pattern having the same material as the first lower dielectric pattern; a second semiconductor pattern provided on the second lower dielectric pattern and having the same material as the first semiconductor pattern; and a second upper dielectric pattern provided on the second semiconductor pattern and having the same material as the first upper dielectric pattern. Claim 4 A semiconductor device according to claim 1, further comprising a conductive pad provided on the vertical channel structure, wherein the height of the dummy pattern is substantially the same as the sum of the height of the vertical channel structure and the height of the conductive pad. Claim 5 In claim 1, the cell array structure further comprises a capping film provided on the vertical channel structure, wherein the capping film is a semiconductor device vertically spaced from the dummy pattern on the upper surface of the recessed portion. Claim 6 A semiconductor device according to claim 1, wherein the cell array structure further comprises second insulating layers interposed between the first insulating layers and overlapping with the dummy region of the substrate, wherein the second insulating layers are horizontally spaced apart from the gate structures, and the recessed portion is provided on the outer walls of the first insulating layers and the outer walls of the second insulating layers. Claim 7 In claim 6, the first insulating layer is provided on the device region and the dummy region of the substrate and is spaced perpendicularly apart from each other, and the gate structures are interposed between the first insulating layers on the device region of the substrate, and the gate structures are a semiconductor device spaced apart from the dummy pattern. Claim 8 A semiconductor device according to claim 1, wherein the substrate comprises a crystalline semiconductor material, and the substrate further comprises an amorphous portion exposed on its outer wall. Claim 9 A semiconductor device according to claim 1, comprising: a wiring layer on the cell array structure; chip pads on the wiring layer; and a protective layer provided on the wiring layer and exposing the chip pads, wherein the protective layer does not vertically overlap with the dummy pattern. Claim 10 A semiconductor device according to claim 1, wherein the width of the recessed portion is 3 nm to 50 nm. Claim 11 A semiconductor substrate having a device region and a dummy region surrounding the device region in a planar view; a logic structure provided on the semiconductor substrate and including peripheral circuits; a cell array structure on the logic structure; a wiring layer provided on the cell array structure; a chip pad on the wiring layer; and a protective layer provided on the wiring layer and exposing the chip pad, wherein a recessed portion is provided on the outer wall of the cell array structure, and the outer wall of the cell array structure is exposed by the semiconductor substrate and the logic structure, and the cell array structure comprises: first insulating layers that overlap the device region and the dummy region of the semiconductor substrate and are vertically spaced from each other; gate structures that overlap the device region of the semiconductor substrate and are interposed between the first insulating layers; second insulating layers that overlap the dummy region of the semiconductor substrate and are interposed between the first insulating layers; a vertical channel structure disposed on the device region of the semiconductor substrate and penetrating the first insulating layers and the gate structures; and a conductive pad provided on the vertical channel structure. A semiconductor device comprising: a dummy pattern provided on the dummy region of the semiconductor substrate and laterally spaced from the vertical channel structure; and a capping film provided on the upper surface of the vertical channel structure and extending onto the dummy region of the semiconductor substrate, wherein the dummy pattern covers the bottom surface and side wall of the recessed portion and the height of the dummy pattern is substantially equal to the sum of the height of the vertical channel structure and the height of the conductive pad. Claim 12 In claim 11, the dummy pattern is a semiconductor device comprising the same material as the vertical channel structure. Claim 13 In claim 11, the dummy pattern comprises: a first lower dielectric pattern covering the bottom surface and the side wall of the recessed portion; a first semiconductor pattern on the first lower dielectric pattern; and a first upper dielectric pattern on the first semiconductor pattern. Claim 14 In claim 13, the vertical channel structure comprises: a second lower dielectric pattern having the same material as the first lower dielectric pattern; a second semiconductor pattern provided on the second lower dielectric pattern and having the same material as the first semiconductor pattern; and a second upper dielectric pattern provided on the second semiconductor pattern and having the same material as the first upper dielectric pattern. Claim 15 A substrate having a device region and a scribe lane region in a planar view; and a cell array structure provided on the substrate and comprising first insulating layers, a vertical channel structure, and a dummy pattern, wherein the first insulating layers are spaced vertically apart from each other, and the cell array structure comprises: a wafer structure provided on the scribe lane region of the substrate and having a first trench penetrating the first insulating layers, a void provided within the first trench, and the dummy pattern covering the sidewall and bottom surface of the first trench. Claim 16 In claim 15, the cell array structure further has a second trench that overlaps with the element region of the substrate and penetrates the first insulating layers, the vertical channel structure is provided within the second trench and spaced apart from the dummy pattern, and the dummy pattern comprises the same material as the vertical channel structure. Claim 17 In claim 16, the cell array structure further comprises a capping film that blocks the entrance of the first trench, wherein the capping film extends over the upper surface of the channel structure, and the void is a wafer structure surrounded by the dummy pattern and the capping film. Claim 18 In claim 16, the cell array structure comprises: gate structures interposed between the first insulating layers and overlapping with the device region of the substrate; second insulating layers overlapping with the scribe lane region of the substrate and described between the first insulating layers; and a wafer structure in which the first trench further penetrates the second insulating layers and the second trench further penetrates the gate structures. Claim 19 A wafer structure according to claim 16, wherein the depth of the first trench is substantially the same as the depth of the second trench, and the width of the first trench is greater than the width of the second trench. Claim 20 A wafer structure according to claim 15, further comprising: a wiring layer on the cell array structure; chip pads on the wiring layer; and a protective layer provided on the wiring layer and exposing the chip pads, wherein the protective layer has an opening that overlaps vertically with a scribe lane area of ​​the substrate, and the width of the opening is greater than the width of the first trench.

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