Semiconductor packages

Abstract

A semiconductor package comprises a lower semiconductor chip, a plurality of semiconductor chips stacked on the lower semiconductor chip in a first direction perpendicular to the upper surface of the lower semiconductor chip, a plurality of connecting bumps disposed between the lowest semiconductor chip among the plurality of semiconductor chips and the lower semiconductor chip, and between the plurality of semiconductor chips, a protective film covering each side of the plurality of connecting bumps, and a mold film covering the sides of the plurality of semiconductor chips on the lower semiconductor chip. The mold film extends between the lowest semiconductor chip and the lower semiconductor chip, and between the plurality of semiconductor chips, and the protective film is interposed between each side of the plurality of connecting bumps and the mold film.

Description

Technology Field

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same, and more specifically, to a semiconductor package having a plurality of semiconductor chips mounted thereon and a method for manufacturing the same. Background Technology

[0002] A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting semiconductor chips on a printed circuit board (PCB) and electrically connecting them using bonding wires or bumps. With the development of the electronics industry, there is a demand for miniaturization, lightweighting, and multifunctionality in electronic devices. Accordingly, multi-chip packages, in which multiple chips are stacked within a single semiconductor package, and system-in-packages, in which heterogeneous chips are mounted within a single package to operate as a single system, are being proposed. The problem to be solved

[0003] The technical problem that the present invention aims to solve is to provide a semiconductor package with improved electrical characteristics and a method for manufacturing the same.

[0004] Another technical objective of the present invention is to provide a semiconductor package with a simplified manufacturing process and improved heat dissipation characteristics, and a method for manufacturing the same. means of solving the problem

[0005] A semiconductor package according to the present invention may include: a lower semiconductor chip; a plurality of semiconductor chips stacked on the lower semiconductor chip in a first direction perpendicular to the upper surface of the lower semiconductor chip; a plurality of connecting bumps disposed between the lowest semiconductor chip among the plurality of semiconductor chips and the lower semiconductor chip, and between the plurality of semiconductor chips; a protective film covering each side of the plurality of connecting bumps; and a mold film covering the sides of the plurality of semiconductor chips on the lower semiconductor chip. The mold film may extend between the lowest semiconductor chip and the lower semiconductor chip, and between the plurality of semiconductor chips, and the protective film may be interposed between each side of the plurality of connecting bumps and the mold film.

[0006] A semiconductor package according to the present invention may comprise: a lower semiconductor chip; a plurality of semiconductor chips stacked on the lower semiconductor chip in a first direction perpendicular to the upper surface of the lower semiconductor chip; a plurality of connecting bumps disposed between the lowest semiconductor chip among the plurality of semiconductor chips and the lower semiconductor chip, and between the plurality of semiconductor chips; a protective film covering each side of the plurality of connecting bumps; a molding film covering the sides of the plurality of semiconductor chips and extending between the lowest semiconductor chip and the lower semiconductor chip, and between the plurality of semiconductor chips; and at least one void provided within the molding film between the lowest semiconductor chip and the lower semiconductor chip, or between the plurality of semiconductor chips. The at least one void may expose at least a portion of the protective film.

[0007] A semiconductor package according to the present invention may include: a lower semiconductor chip (100); a plurality of semiconductor chips stacked on the lower semiconductor chip in a first direction perpendicular to the upper surface of the lower semiconductor chip, wherein each of the plurality of semiconductor chips includes chip penetration electrodes penetrating the interior thereof; a plurality of connection bumps disposed between the plurality of semiconductor chips; a protective film covering each side of the plurality of connection bumps; and a mold film covering the sides of the plurality of semiconductor chips and extending between the plurality of semiconductor chips. The chip penetration electrodes may each be connected to corresponding connection bumps among the plurality of connection bumps. The protective film may be interposed between each side of the plurality of connection bumps and the mold film. Effects of the invention

[0008] According to the concept of the present invention, when at least one void is formed within the mold film between a pair of adjacent connecting bumps, a protective film may be interposed between each of the pair of connecting bumps and the mold film and may extend between each of the pair of connecting bumps and the at least one void. Each of the pair of connecting bumps may be spaced apart from the at least one void with the protective film in between. Accordingly, in a subsequent process, the solder bumps of the pair of connecting bumps may be prevented from being extruded through the at least one void, and as a result, an electrical short circuit between the pair of connecting bumps may be prevented.

[0009] In addition, the mold film may include a Molded Underfill (MUF) material, and accordingly, the mold film can function as an underfill between vertically stacked semiconductor chips and simultaneously as a molding compound covering the sides of the semiconductor chips. Accordingly, the manufacturing process of the semiconductor package can be simplified. Furthermore, since the mold film includes a Molded Underfill (MUF) material, it may be easy to increase the content of the heat dissipation material within the mold film. Accordingly, the heat dissipation characteristics of the semiconductor package can be improved.

[0010] Accordingly, a semiconductor package with improved electrical and heat dissipation characteristics and a simplified manufacturing process and a method for manufacturing the same can be provided. Brief explanation of the drawing

[0011] FIG. 1 is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. Figure 2 is an enlarged view of part P of Figure 1. Figures 3 and 4 are conceptual diagrams to exemplarily explain the self-assembled monolayer within the protective film of Figure 1. FIG. 5 is a drawing showing a modified example of a semiconductor package according to some embodiments of the present invention, and is an enlarged view corresponding to part P of FIG. 1. FIG. 6 is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. Figure 7 is an enlarged view of section P of Figure 6. FIG. 8 is a drawing showing a modified example of a semiconductor package according to some embodiments of the present invention, and is an enlarged view corresponding to part P of FIG. 6. FIGS. 9 to 11 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to some embodiments of the present invention. FIG. 12 is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. FIG. 13 is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. Specific details for implementing the invention

[0012] The present invention will be described in detail below by explaining embodiments of the present invention with reference to the attached drawings.

[0013] FIG. 1 is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. FIG. 2 is an enlarged view of portion P of FIG. 1. FIG. 3 and FIG. 4 are conceptual diagrams for exemplarily illustrating a self-assembled monolayer within the protective film of FIG. 1.

[0014] Referring to FIG. 1, a semiconductor package (1000) may include a lower semiconductor chip (100) and a plurality of semiconductor chips (200) stacked vertically on the lower semiconductor chip (100). The lower semiconductor chip (100) may have an upper surface (100a) and a lower surface (100b) facing each other. The plurality of semiconductor chips (200) may be disposed on the upper surface (100a) of the lower semiconductor chip (100) and may be stacked on the lower semiconductor chip (100) along a first direction (D1) perpendicular to the upper surface (100a) of the lower semiconductor chip (100). In FIG. 1, a structure in which eight semiconductor chips (200) are stacked on the lower semiconductor chip (100) is illustrated as an example, but the concept of the present invention is not limited thereto.

[0015] The lower semiconductor chip (100) may include a lower semiconductor substrate (110), a lower circuit layer (120), lower through-electrodes (130), lower chip pads (140), and lower bumps (150). The lower semiconductor substrate (110) may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The lower circuit layer (120) may include integrated circuits formed on the lower semiconductor substrate (110). For example, the lower circuit layer (120) may be adjacent to the lower surface (100b) of the lower semiconductor chip (100).

[0016] The lower penetrating electrodes (130) may penetrate the lower semiconductor substrate (110) and may be horizontally spaced apart from each other within the lower semiconductor substrate (110). The lower penetrating electrodes (130) may be spaced apart from each other along a second direction (D2) parallel to the upper surface (100a) of the lower semiconductor chip (100). The lower penetrating electrodes (130) may be electrically connected to the lower circuit layer (120). The lower penetrating electrodes (130) may include a metal (e.g., copper, tungsten, titanium, tantalum, etc.).

[0017] The lower chip pads (140) may be disposed on the lower surface (100b) of the lower semiconductor chip (100) and may be spaced apart from each other in the second direction (D2). The lower chip pads (140) may be electrically connected to the lower circuit layer (120). The lower bumps (150) may be disposed on the lower chip pads (140) and connected to the lower chip pads (140). The lower bumps (150) may be connected to external terminals. The lower chip pads (140) may include a metal (e.g., copper). The lower bumps (150) may include a conductive material and may have at least one form of a solder ball, a bump, and a pillar.

[0018] Each of the plurality of semiconductor chips (200) may include a semiconductor substrate (210), a circuit layer (220), and chip through-electrodes (230). According to some embodiments, the uppermost semiconductor chip (200U) among the plurality of semiconductor chips (200) may not include the chip through-electrodes (230). The semiconductor substrate (210) may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The circuit layer (220) may include integrated circuits formed on the semiconductor substrate (210). Each of the plurality of semiconductor chips (200) may have an upper surface (200a) and a lower surface (200b) facing each other, and the circuit layer (220) may be adjacent to each lower surface (200b) of the plurality of semiconductor chips (200). The chip penetrating electrodes (230) can penetrate the semiconductor substrate (210) and can be horizontally spaced apart from each other within the semiconductor substrate (210). The chip penetrating electrodes (230) can be spaced apart from each other in the second direction (D2) and can be electrically connected to the circuit layer (220). The chip penetrating electrodes (230) may include a metal (e.g., copper, tungsten, titanium, tantalum, etc.).

[0019] The semiconductor package (1000) may further include a plurality of connection bumps (CB) disposed between the bottom semiconductor chip (200L) among the plurality of semiconductor chips (200) and the lower semiconductor chip (100), and between the plurality of semiconductor chips (200). Among the plurality of connection bumps (CB), the first connection bumps (CB1) may be disposed on the lower surface (200b) of the bottom semiconductor chip (200L) and may be spaced apart from each other in the second direction (D2). The first connection bumps (CB1) may be electrically connected to the circuit layer (220) of the bottom semiconductor chip (200L) and may be connected to the lower through electrodes (130) of the lower semiconductor chip (100), respectively. The bottom semiconductor chip (200L) may be electrically connected to the lower semiconductor chip (100) through the first connection bumps (CB1). Among the plurality of connection bumps (CB), the second connection bumps (CB2) may be placed on the lower surface (200b) of each of the remaining semiconductor chips (200) among the plurality of semiconductor chips (200) and may be spaced apart from each other in the second direction (D2). The second connection bumps (CB2) may be electrically connected to each of the circuit layers (220) of the remaining semiconductor chips (200). The second connection bumps (CB2) may be connected to the chip penetration electrodes (230) of the corresponding semiconductor chip (200) among the plurality of semiconductor chips (200). The plurality of semiconductor chips (200) may be electrically connected to each other through the second connection bumps (CB2). The lower semiconductor chip (100) and the plurality of semiconductor chips (200) may be electrically connected to each other through the plurality of connection bumps (CB).

[0020] The lower semiconductor chip (100) may be a memory chip, a logic chip, an application processor (AP) chip, or a system-on-chip (SOC). The plurality of semiconductor chips (200) may be memory chips. The plurality of semiconductor chips (200) may be identical semiconductor chips, for example, identical memory chips. The plurality of semiconductor chips (200) and the lower semiconductor chip (100) may be electrically connected to each other and may form a High Bandwidth Memory (HBM) chip. Each of the plurality of semiconductor chips (200) and the lower semiconductor chip (100) may have a width according to the second direction (D2). According to some embodiments, the width (100WD) of the lower semiconductor chip (100) may be greater than the width (200WD) of each of the plurality of semiconductor chips (200).

[0021] Referring to FIGS. 1 and 2, each of the plurality of connection bumps (CB) may include a conductive pillar (240), a solder bump (250), and a conductive pad (260). The conductive pillar (240) may be adjacent to the lower surface (200b) of each of the plurality of semiconductor chips (200) and may be electrically connected to the circuit layer (220) of each of the plurality of semiconductor chips (200). The solder bump (250) may be placed on the conductive pillar (240) and may be connected to the conductive pillar (240). The conductive pillar (240) may be interposed between the lower surface (200b) of each of the plurality of semiconductor chips (200) and the solder bump (250). The conductive pad (260) may be placed on the solder bump (250) and may be connected to the solder bump (250). The conductive pillar (240) and the solder bump (250) may be interposed between the lower surface (200b) of each of the plurality of semiconductor chips (200) and the conductive pad (260). The conductive pad (260) may be adjacent to the upper surface (200a) of the corresponding semiconductor chip (200) among the plurality of semiconductor chips (200), or the upper surface (100a) of the lower semiconductor chip (100), and may be connected to one of the chip penetration electrodes (230) of the corresponding semiconductor chip (200) or one of the lower penetration electrodes (130) of the lower semiconductor chip (100).

[0022] The conductive pillar (240) and the conductive pad (260) may comprise a metal (e.g., copper). The conductive pillar (240) and the conductive pad (260) may have a thickness along the first direction (D1), and the thickness (240T) of the conductive pillar (240) may be greater than the thickness (260T) of the conductive pad (260). The solder bump (250) may comprise a conductive material and may have at least one of the forms of a solder ball, a bump, and a pillar.

[0023] The semiconductor package (1000) may further include a protective film (300) covering each side (CB_S) of the plurality of connection bumps (CB), and a mold film (400) disposed on the upper surface (100a) of the lower semiconductor chip (100) and covering the sides (200s) of the plurality of semiconductor chips (200). The mold film (400) may extend between the bottom semiconductor chip (200L) and the lower semiconductor chip (100) and may fill the space between the first connection bumps (CB1). The mold film (400) may extend between the plurality of semiconductor chips (200) and may fill the space between the second connection bumps (CB2). The above mold film (400) can be extended without an interface from the sides (200s) of the plurality of semiconductor chips (200) to the bottom layer semiconductor chip (200L) and the lower semiconductor chip (100), and between the plurality of semiconductor chips (200).

[0024] The protective film (300) may be interposed between each of the respective sides (CB_S) of the plurality of connection bumps (CB) and the mold film (400). The protective film (300) may cover the sides of the solder bump (250) and may extend over the sides of the conductive pillar (240) and the conductive pad (260). The protective film (300) may be interposed between the sides of the solder bump (250) and the mold film (400), and may extend between the sides of the conductive pillar (240) and the mold film (400), and between the sides of the conductive pad (260) and the mold film (400).

[0025] The protective film (300) may come into contact with each of the sides (CB_S) of the plurality of connection bumps (CB). The protective film (300) may come into contact with the sides of the solder bump (250), the conductive pillar (240), and the conductive pad (260). The protective film (300) may come into contact with the mold film (400). The mold film (400) may include a Molded Underfill (MUF) material, and, for example, may include an epoxy molding compound (EMC). The mold film (400) may further include a heat dissipation material, and the heat dissipation material may include, for example, at least one of Al2O3, BeO, AlN, SiC, and BN.

[0026] According to some embodiments, the protective film (300) may extend over each lower surface (200b) and upper surface (200a) of the plurality of semiconductor chips (200), and may extend over each side surface (200s) of the plurality of semiconductor chips (200). The protective film (300) may extend over the upper surface (100a) of the lower semiconductor chip (100). The protective film (300) may extend between each lower surface (200b) of the plurality of semiconductor chips (200) and the mold film (400), and between each upper surface (200a) of the plurality of semiconductor chips (200) and the mold film (400). The protective film (300) may further extend between each side surface (200s) of the plurality of semiconductor chips (200) and the mold film (400). The protective film (300) can be extended between the upper surface (100a) of the lower semiconductor chip (100) and the mold film (400).

[0027] According to some embodiments, the protective film (300) may comprise a self-assembled monolayer. The self-assembled monolayer may comprise a hydrocarbon chain, a first reactor connected to one end of the hydrocarbon chain, and a second reactor connected to the other end of the hydrocarbon chain. The self-assembled monolayer may be represented, for example, by the following chemical formula.

[0028] [Chemical Formula]

[0029] R1-C n H 2n -R2

[0030] Here, n is an integer greater than or equal to 1. R1 represents the first reactor and is a reactor that reacts with the plurality of connecting bumps (CB). R1 ​​is, for example, any one of -SH, -COOH, -SiH3, etc. R2 represents the second reactor and is a reactor that reacts with the mold film (400). For example, R2 is any one of OH, -NH2, imidazole group, epoxy group, etc.

[0031] The self-assembled monolayer can be chemically adsorbed to each of the sides (CB_S) of the plurality of connecting bumps (CB) by the first reactor and can be chemically adsorbed to the surface of the mold film (400) by the second reactor. According to some embodiments, the self-assembled monolayer may comprise at least one of a thiol, a carboxylic acid, an aminosilane, and an epoxysilane.

[0032] Referring to FIGS. 2 to 4, when the first reactor (R1) of the self-assembled monolayer is -SH and the second reactor (R2) is -NH2, the first reactor (R1) can react with the metal inside each of the plurality of connecting bumps (CB), and accordingly, the self-assembled monolayer can be chemically adsorbed on each of the sides (CB_S) of the plurality of connecting bumps (CB). The second reactor (R2) of the self-assembled monolayer can react with the epoxy inside the mold film (400), and accordingly, the self-assembled monolayer can be chemically adsorbed on the surface of the mold film (400).

[0033] Referring again to FIGS. 1 and FIGS. 2, according to other embodiments, the protective film (300) may include an inorganic insulating material. For example, the protective film (300) may include at least one of SiO2, Si3N4, PSG (phosphosilicate glass, SiO2 / P2O5), and BPSG (Borophosphosilicate glass, SiO2 / P2O5 / B2O3).

[0034] The semiconductor package (1000) may further include at least one void (400V) formed within the mold film (400). The at least one void (400V) may be formed within the mold film (400) between the bottom semiconductor chip (200L) and the lower semiconductor chip (100), and / or between the plurality of semiconductor chips (200). The at least one void (400V) may be positioned between the first connection bumps (CB1) and / or between the second connection bumps (CB2), and may expose at least a portion of the protective film (300).

[0035] The plurality of connection bumps (CB) may include a pair of connection bumps (CB) adjacent to each other with the at least one void (400V) in between. The protective film (300) may be interposed between each of the pair of connection bumps (CB) and the at least one void (400V). According to some embodiments, the protective film (300) may extend between the lower semiconductor chip (100) and the at least one void (400V) or between each of the plurality of semiconductor chips (200) and the at least one void (400V). Each of the pair of connection bumps (CB) may be spaced apart from the mold film (400) and the at least one void (400V) with the protective film (300) in between.

[0036] As the mold film (400) contains a Molded Underfill (MUF) material, at least one void (400V) may be formed within the mold film (400) between the bottom layer semiconductor chip (200L) and the lower semiconductor chip (100), and / or between the plurality of semiconductor chips (200). If the at least one void (400V) is formed between a pair of adjacent connection bumps (CB), in a subsequent process, at least one solder bump (250) of the pair of connection bumps (CB) may be extruded through the at least one void (400V), and as a result, the pair of connection bumps (CB) may be electrically short-circuited to each other.

[0037] According to the concept of the present invention, the protective film (300) may be formed to cover each of the respective sides (CB_S) of the plurality of connecting bumps (CB) and may be interposed between each of the respective sides (CB_S) of the plurality of connecting bumps (CB) and the mold film (400). When the at least one void (400V) is formed within the mold film (400) between a pair of adjacent connecting bumps (CB), the protective film (300) may be interposed between each of the pair of connecting bumps (CB) and the mold film (400) and may extend between each of the pair of connecting bumps (CB) and the at least one void (400V). Each of the pair of connecting bumps (CB) may be spaced apart from the at least one void (400V) with the protective film (300) in between. Accordingly, in a subsequent process, at least one of the solder bumps (250) of the pair of connection bumps (CB) can be prevented from being extruded through the at least one void (400V), and as a result, an electrical short circuit between the pair of connection bumps (CB) can be prevented.

[0038] Additionally, as the mold film (400) includes a Molded Underfill (MUF) material, the mold film (400) can cover the sides (200s) of the plurality of semiconductor chips (200) and can extend without an interface from the sides (200s) of the plurality of semiconductor chips (200) to the bottom layer semiconductor chip (200L) and the bottom semiconductor chip (100), and between the plurality of semiconductor chips (200). That is, the mold film (400) can function as an underfill between the bottom semiconductor chip (100) and the plurality of semiconductor chips (200), and simultaneously as a molding compound covering the sides (200s) of the plurality of semiconductor chips (200). Accordingly, the manufacturing process of the semiconductor package (1000) can be simplified. In addition, as the mold film (400) includes a Molded Underfill (MUF) material, it may be easy to increase the content of the heat dissipation material within the mold film (400). Accordingly, the heat dissipation characteristics of the semiconductor package (1000) may be improved.

[0039] Accordingly, a semiconductor package with improved electrical and heat dissipation characteristics and a simplified manufacturing process and a method for manufacturing the same can be provided.

[0040] FIG. 5 is a drawing showing a modified example of a semiconductor package according to some embodiments of the present invention, and is an enlarged view corresponding to part P of FIG. 1. For the sake of simplicity, the differences from the semiconductor package described with reference to FIGS. 1 to 4 will be mainly explained.

[0041] Referring to FIGS. 1 and 5, according to some embodiments, the protective film (300) may be a double film comprising a self-assembled monolayer (300a) and an organic insulating film (300b). The self-assembled monolayer (300a) is substantially the same as the self-assembled monolayer described with reference to FIGS. 1 through 4. The self-assembled monolayer (300a) may be chemically adsorbed to each of the sides (CB_S) of the plurality of connecting bumps (CB) by the first reactor. The organic insulating film (300b) may be interposed between the self-assembled monolayer (300a) and the mold film (400). The self-assembled monolayer (300a) may be chemically adsorbed to the surface of the organic insulating film (300b) by the second reactor. The above organic insulating film (300b) may include, for example, an epoxy resin.

[0042] Referring to FIGS. 3 to 5, when the first reactor (R1) of the self-assembled monolayer (300a) is -SH and the second reactor (R2) is -NH2, the first reactor (R1) can react with the metal inside each of the plurality of connecting bumps (CB), and accordingly, the self-assembled monolayer (300a) can be chemically adsorbed on each of the sides (CB_S) of the plurality of connecting bumps (CB). The second reactor (R2) of the self-assembled monolayer (300a) can react with the epoxy inside the organic insulating film (300b), and accordingly, the self-assembled monolayer (300a) can be chemically adsorbed on the surface of the organic insulating film (300b).

[0043] Referring again to FIGS. 1 and FIGS. 5, the at least one void (400V) may be provided between a pair of adjacent connection bumps (CB). The at least one void (400V) may expose at least a portion of the organic insulating film (300b).

[0044] FIG. 6 is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. FIG. 7 is an enlarged view of portion P of FIG. 6.For the sake of simplicity, the differences from the semiconductor package described with reference to FIGS. 1 to 4 will be mainly explained.

[0045] Referring to FIGS. 6 and 7, the protective film (300) may be interposed between each of the sides (CB_S) of the plurality of connection bumps (CB) and the mold film (400). The protective film (300) may cover the sides of the solder bump (250) and may extend over the sides of the conductive pillar (240) and the conductive pad (260). The protective film (300) may be interposed between the sides of the solder bump (250) and the mold film (400), and may extend between the sides of the conductive pillar (240) and the mold film (400), and between the sides of the conductive pad (260) and the mold film (400). The protective film (300) may be in contact with each of the sides (CB_S) of the plurality of connection bumps (CB). The protective film (300) may come into contact with the sides of the solder bump (250), the conductive pillar (240), and the conductive pad (260). The protective film (300) may come into contact with the mold film (400).

[0046] According to some embodiments, the protective film (300) may be provided locally on each of the sides (CB_S) of the plurality of connection bumps (CB). The mold film (400) may be in contact with each of the lower surface (200b) and upper surface (200a) of the plurality of semiconductor chips (200), and may be in contact with each of the sides (200s) of the plurality of semiconductor chips (200). The mold film (400) may be in contact with the upper surface (100a) of the lower semiconductor chip (100).

[0047] According to some embodiments, the protective film (300) may comprise the self-assembled monolayer. The self-assembled monolayer may be chemically adsorbed to each of the sides (CB_S) of the plurality of connecting bumps (CB) by the first reactor and may be chemically adsorbed to the surface of the mold film (400) by the second reactor. According to other embodiments, the protective film (300) may comprise an inorganic insulating material. For example, the protective film (300) may comprise at least one of SiO2, Si3N4, PSG (phosphosilicate glass, SiO2 / P2O5), and BPSG (Borophosphosilicate glass, SiO2 / P2O5 / B2O3).

[0048] The above at least one void (400V) may be formed between a pair of adjacent connecting bumps (CB). The protective film (300) may be interposed between each of the pair of connecting bumps (CB) and the at least one void (400V). The at least one void (400V) may expose the upper surface (100a) of the lower semiconductor chip (100) between the pair of connecting bumps (CB), or the upper surface (200a, or lower surface (200b)) of each of the plurality of semiconductor chips (200) between the pair of connecting bumps (CB). Each of the pair of connecting bumps (CB) may be spaced apart from the mold film (400) and the at least one void (400V) with the protective film (300) in between.

[0049] Except for the differences described above, the semiconductor package (1000) according to the embodiments is substantially the same as the semiconductor package (1000) described with reference to FIGS. 1 to 4.

[0050] FIG. 8 is a drawing showing a modified example of a semiconductor package according to some embodiments of the present invention, and is an enlarged view corresponding to part P of FIG. 6. For the sake of simplicity, the differences from the semiconductor package described with reference to FIGS. 6 and FIGS. 7 will be mainly explained.

[0051] Referring to FIGS. 6 and FIGS. 8, according to some embodiments, the protective film (300) may be a double film comprising a self-assembled monolayer (300a) and an organic insulating film (300b). The self-assembled monolayer (300a) is substantially the same as the self-assembled monolayer described with reference to FIGS. 1 through 4. The self-assembled monolayer (300a) may be chemically adsorbed to each of the sides (CB_S) of the plurality of connecting bumps (CB) by the first reactor. The organic insulating film (300b) may be interposed between the self-assembled monolayer (300a) and the mold film (400). The self-assembled monolayer (300a) may be chemically adsorbed to the surface of the organic insulating film (300b) by the second reactor. The above organic insulating film (300b) may include, for example, an epoxy resin.

[0052] Referring to FIGS. 3, 4 and 8, when the first reactor (R1) of the self-assembled monolayer (300a) is -SH and the second reactor (R2) is -NH2, the first reactor (R1) can react with the metal inside each of the plurality of connecting bumps (CB), and accordingly, the self-assembled monolayer (300a) can be chemically adsorbed on each of the sides (CB_S) of the plurality of connecting bumps (CB). The second reactor (R2) of the self-assembled monolayer (300a) can react with the epoxy inside the organic insulating film (300b), and accordingly, the self-assembled monolayer (300a) can be chemically adsorbed on the surface of the organic insulating film (300b).

[0053] Referring again to FIGS. 6 and FIGS. 8, the at least one void (400V) may be provided between a pair of adjacent connection bumps (CB). The at least one void (400V) may expose at least a portion of the organic insulating film (300b) and may expose the upper surface (100a) of the lower semiconductor chip (100) between the pair of connection bumps (CB), or the upper surface (200a, or lower surface (200b)) of each of the plurality of semiconductor chips (200) between the pair of connection bumps (CB).

[0054] FIGS. 9 to 11 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to some embodiments of the present invention. For the sake of simplicity, descriptions that overlap with the semiconductor package described with reference to FIGS. 1 to 8 are omitted.

[0055] Referring to FIG. 9, a lower substrate (100W) comprising a plurality of lower semiconductor chips (100) may be provided. The lower substrate (100W) may have an upper surface (100Wa) and a lower surface (100Wb) facing each other. The upper surface (100Wa) of the lower substrate (100W) may correspond to the upper surfaces (100a) of the plurality of lower semiconductor chips (100), and the lower surface (100Wb) of the lower substrate (100W) may correspond to the lower surfaces (100b) of the plurality of lower semiconductor chips (100). The plurality of lower semiconductor chips (100) may be arranged in a direction parallel to the upper surface (100Wa) of the lower substrate (100W) (for example, the second direction (D2)). Each of the plurality of lower semiconductor chips (100) described with reference to FIG. 1 may include the lower semiconductor substrate (110), the lower circuit layer (120), the lower through electrodes (130), the lower chip pads (140), and the lower bumps (150).

[0056] A plurality of chip stacks (CS) may be provided on the upper surface (100Wa) of the lower substrate (100W) and may each be provided on the plurality of lower semiconductor chips (100). Each of the plurality of chip stacks (CS) may include a plurality of semiconductor chips (200) stacked vertically in the first direction (D1), and a plurality of connection bumps (CB) disposed on the lower surface (200b) of each of the plurality of semiconductor chips (200). Each of the plurality of semiconductor chips (200) may include the semiconductor substrate (210), the circuit layer (220), and the chip through-electrodes (230) as described with reference to FIG. 1. According to some embodiments, the uppermost semiconductor chip (200U) among the plurality of semiconductor chips (200) may not include the chip through-electrodes (230). Each of the plurality of connection bumps (CB) may include the conductive pillar (240), the solder bump (250), and the conductive pad (260) as described with reference to FIGS. 1 and 2.

[0057] Among the plurality of connection bumps (CB), the first connection bumps (CB1) may be positioned between the bottom layer semiconductor chip (200L) and the corresponding lower semiconductor chip (100) among the plurality of semiconductor chips (200), and the second connection bumps (CB2) among the plurality of connection bumps (CB) may be positioned between the plurality of semiconductor chips (200). The plurality of semiconductor chips (200) may be electrically connected to each other through the second connection bumps (CB2), and the bottom layer semiconductor chip (200L) may be electrically connected to the corresponding lower semiconductor chip (100) through the first connection bumps (CB1). Accordingly, each of the chip stacks (CS) may be electrically connected to the corresponding lower semiconductor chip (100).

[0058] Referring to FIG. 10, a protective film (300) may be formed to cover the plurality of chip stacks (CS) on the lower substrate (100W). According to some embodiments, the protective film (300) may be formed to cover the upper surfaces (200a), side surfaces (200s), and lower surfaces (200b) of the plurality of semiconductor chips (200), and may be formed to cover each side surface (CB_S) of the plurality of connection bumps (CB). The protective film (300) may be formed to cover the upper surface (100Wa) of the lower substrate (100W). According to other embodiments, the protective film (300) may be formed locally on each side surface (CB_S) of the plurality of connection bumps (CB), as described with reference to FIG. 6 through 8.

[0059] According to some embodiments, the protective film (300) may be formed as a single film comprising the self-assembled monolayer or a single film comprising an inorganic insulating material, as described with reference to FIGS. 1 to 4, FIGS. 6 and FIGS. 7. According to other embodiments, the protective film (300) may be formed as a double film comprising the self-assembled monolayer (300a) and the organic insulating film (300b), as described with reference to FIGS. 5 and FIGS. 8.

[0060] The above protective film (300) can be formed, for example, using at least one of a spray coating process, a dipping coating process, a spin coating process, a sputtering deposition process, an electrodeposition process, and a chemical vapor deposition process.

[0061] Referring to FIG. 11, a mold film (400) may be formed on the lower substrate (100W) to cover the plurality of chip stacks (CS) and the protective film (300). The mold film (400) may be formed to cover the sides (200s) of the plurality of semiconductor chips (200) and extend between the plurality of semiconductor chips (200). The mold film (400) may be formed to extend between each of the plurality of chip stacks (CS) and the lower substrate (100W). The mold film (400) may extend between the plurality of semiconductor chips (200) to fill the space between the second connection bumps (CB2), and may extend between each of the plurality of chip stacks (CS) and the lower substrate (100W) to fill the space between the first connection bumps (CB1).

[0062] The protective film (300) may be interposed between each of the respective sides (CB_S) of the plurality of connection bumps (CB) and the mold film (400). According to some embodiments, the protective film (300) may extend between each lower surface (200b) of the plurality of semiconductor chips (200) and the mold film (400), and between each upper surface (200a) of the plurality of semiconductor chips (200) and the mold film (400). The protective film (300) may further extend between each of the respective sides (200s) of the plurality of semiconductor chips (200) and the mold film (400). The protective film (300) may extend between each upper surface (100a) of the lower semiconductor chips (100) and the mold film (400).

[0063] The above mold film (400) may include a Molded Underfill (MUF) material, and, for example, may include an epoxy molding compound (EMC). The above mold film (400) may further include a heat dissipation material. The above mold film (400) may be formed using at least one of a compression molding process and a transfer molding process, for example.

[0064] After the mold film (400) is formed, a cutting process (CP) may be performed on the lower substrate (100W). The cutting process (CP) may, for example, include cutting the mold film (400) between the plurality of chip stacks (CS) using a blade, and cutting the lower substrate (100W) between the plurality of lower semiconductor chips (100). Each of the plurality of lower semiconductor chips (100) and each of the plurality of chip stacks (CS) may constitute the semiconductor package (1000) described with reference to FIGS. 1 to 8.

[0065] FIG. 12 is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. For the sake of simplicity, the differences from the semiconductor package described with reference to FIGS. 1 to 8 will be mainly explained.

[0066] Referring to FIG. 12, the semiconductor package (1100) may include a first substrate (500), a unit chip package (1000) mounted on the first substrate (500), and an additional semiconductor chip (600).

[0067] The first substrate (500) may be an interposer substrate. The first substrate (500) may include a base substrate (510), a plurality of through electrodes (530) penetrating the base substrate (510), and a wiring layer (520) on the base substrate (510). The base substrate (510) may be, for example, a silicon substrate. The plurality of through electrodes (530) may be horizontally spaced apart from each other within the base substrate (510), and each of the plurality of through electrodes (530) may penetrate the base substrate (510). The plurality of through electrodes (530) may include a metal (for example, copper (Cu)). The wiring layer (520) may include metal patterns electrically connected to the plurality of through electrodes (530).

[0068] The first substrate (500) may have a first surface (500a) and a second surface (500b) facing each other, and the wiring layer (520) may be adjacent to the first surface (500a). The second surface (500b) of the first substrate (500) may correspond to one surface of the base substrate (510). Each of the plurality of through electrodes (530) may extend from the wiring layer (520) toward the second surface (500b).

[0069] First substrate pads (560) may be disposed adjacent to the first surface (500a) of the first substrate (500). The first substrate pads (560) may be spaced apart from each other along a direction parallel to the first surface (500a) of the first substrate (500) (e.g., the second direction (D2)). The first substrate pads (560) may be connected to the metal patterns within the wiring layer (520) and may be electrically connected to the plurality of through electrodes (530) through the metal patterns. The first substrate pads (560) may include a conductive material (e.g., metal).

[0070] Second substrate pads (540) may be disposed on the second surface (500b) of the first substrate (500). The second substrate pads (540) may be spaced apart from each other along a direction parallel to the second surface (500b) of the first substrate (500) (e.g., the second direction (D2)). Each of the plurality of through electrodes (530) may be connected to a corresponding second substrate pad (540) among the second substrate pads (540). The second substrate pads (540) may include a conductive material (e.g., a metal).

[0071] The first bumps (550) may be disposed on the second surface (500b) of the first substrate (500) and may be connected to the second substrate pads (540) respectively. The first bumps (550) may be disposed on the second substrate pads (540) respectively. The first bumps (550) may include a conductive material and may have at least one of a solder ball, a bump, and a pillar.

[0072] The unit chip package (1000) and the additional semiconductor chip (600) may be mounted on the first surface (500a) of the first substrate (500). The unit chip package (1000) and the additional semiconductor chip (600) may be spaced apart from each other in a direction parallel to the first surface (500a) of the first substrate (500) (e.g., in the second direction (D2)). According to some embodiments, the unit chip package (1000) may be the semiconductor package (1000) described with reference to FIGS. 1 through 8. In this case, the lower semiconductor chip (100) of the unit chip package (1000) may be disposed on the first surface (500a) of the first substrate (500), and the lower bumps (150) of the lower semiconductor chip (100) may be connected to the corresponding first substrate pads (560) among the first substrate pads (560) of the first substrate (500). The unit chip package (1000) may be electrically connected to the wiring layer (520) of the first substrate (500) through the lower bumps (150) and the corresponding first substrate pads (560).

[0073] A first underfill film (650) may be interposed between the lower semiconductor chip (100) of the unit chip package (1000) and the first substrate (500), and may cover the lower bumps (150) of the lower semiconductor chip (100). The first underfill film (650) may include an insulating polymer material such as epoxy resin.

[0074] The additional semiconductor chip (600) may be horizontally spaced apart from the unit chip package (1000). The additional semiconductor chip (600) may be mounted so as to be horizontally spaced apart from the lower semiconductor chip (100) of the unit chip package (1000). The additional semiconductor chip (600) may include additional chip pads (610) disposed on one side of the additional semiconductor chip (600), and additional bumps (620) each connected to the additional chip pads (610). The additional bumps (620) may be connected to corresponding first substrate pads (560) among the first substrate pads (560) of the first substrate (500). The additional semiconductor chip (600) can be electrically connected to the wiring layer (520) of the first substrate (500) through the additional chip pads (610), the additional bumps (620), and the corresponding first substrate pads (560).

[0075] A second underfill film (660) may be interposed between the additional semiconductor chip (600) and the first substrate (500) and may cover the additional bumps (620) of the additional semiconductor chip (600). The second underfill film (660) may include an insulating polymer material such as epoxy resin.

[0076] The unit chip package (1000) and the additional semiconductor chip (600) may be electrically connected to each other through the metal patterns within the wiring layer (520) of the first substrate (500). For example, the unit chip package (1000) may be a High Bandwidth Memory (HBM) chip, and the additional semiconductor chip (600) may be a memory chip, a logic chip, an application processor (AP) chip, or a system-on-chip (SOC).

[0077] FIG. 13 is a cross-sectional view of a semiconductor package according to some embodiments of the present invention.For the sake of simplicity, the differences from the semiconductor package described with reference to FIGS. 1 to 8 and FIG. 12 will be mainly explained.

[0078] Referring to FIG. 13, the semiconductor package (1200) may further include a second substrate (700) and a heat dissipation structure (800) on the second substrate (700). The configurations of the semiconductor package described with reference to FIG. 1 through 8 and FIG. 12 may be disposed on the second substrate (700) and inside the heat dissipation structure (800).

[0079] The second substrate (700) may include first lower substrate pads (710) adjacent to a first surface (700a) of the second substrate (700), and second lower substrate pads (720) adjacent to a second surface (700b) of the second substrate (700). The first lower substrate pads (710) may be electrically connected to the second lower substrate pads (720) through internal wiring within the second substrate (700). The first and second lower substrate pads (710, 720) may include a conductive material (e.g., metal). Second bumps (730) may be disposed on the second surface (700b) of the second substrate (700) and connected to the second lower substrate pads (720), respectively. The second bumps (730) may include a conductive material and may have at least one form of a solder ball, a bump, and a pillar. The second substrate (900) may be, for example, a printed circuit board, a semiconductor chip, or a semiconductor package.

[0080] The first substrate (500) may be mounted on the first surface (700a) of the second substrate (700). The first bumps (550) of the first substrate (500) may be connected to the corresponding first lower substrate pads (710) among the first lower substrate pads (710) of the second substrate (700). The first substrate (500) may be electrically connected to the second substrate (700) through the first bumps (550) and the first lower substrate pads (710).

[0081] A lower underfill film (740) may be disposed between the first substrate (500) and the second substrate (700) and may cover the first bumps (550). The lower underfill film (740) may include an insulating polymer material such as epoxy resin.

[0082] The heat dissipation structure (800) may be disposed on the first surface (700a) of the second substrate (700) and may cover the components of the semiconductor package (1000 / 1100) described with reference to FIGS. 1 through 8 and FIG. 12. The heat dissipation structure (800) may include a thermally conductive material. The thermally conductive material may include a metal (e.g., copper and / or aluminum, etc.) or a carbon-containing material (e.g., graphene, graphite, and / or carbon nanotubes, etc.). As an example, the heat dissipation structure (800) may include a single metal layer or a plurality of stacked metal layers. As another example, the heat dissipation structure (800) may include a heat sink or a heat pipe. As yet another example, the heat dissipation structure (800) may utilize a water cooling method.

[0083] The semiconductor package (1200) may further include a thermal conductive layer (810) interposed between the unit chip package (1000) and the heat dissipation structure (800). The thermal conductive layer (810) may include a thermal interface material (TIM). The thermal interface material may, for example, include a polymer and thermally conductive particles. The thermally conductive particles may be dispersed within the polymer. Heat generated from the unit chip package (1000) may be transferred to the heat dissipation structure (800) through the thermal conductive layer (810).

[0084] The above description of the embodiments of the present invention provides examples for explaining the present invention. Accordingly, the present invention is not limited to the above embodiments, and it is evident that many modifications and changes are possible within the technical scope of the present invention, such as combining the above embodiments by those skilled in the art.

Claims

Claim 1 A lower semiconductor chip; a plurality of semiconductor chips stacked on the lower semiconductor chip in a first direction perpendicular to the upper surface of the lower semiconductor chip; a plurality of connecting bumps disposed between the semiconductor chip of the lowest layer among the plurality of semiconductor chips and the lower semiconductor chip, and between the plurality of semiconductor chips; a protective film covering each side of the plurality of connecting bumps; A semiconductor package comprising a mold film covering the sides of the plurality of semiconductor chips on the lower semiconductor chip, wherein the mold film extends between the bottom semiconductor chip and the lower semiconductor chip and between the plurality of semiconductor chips and is interposed between the plurality of connecting bumps, and each of the plurality of semiconductor chips has an upper surface and a lower surface facing each other in the first direction, and the protective film is interposed between the side of each of the plurality of connecting bumps and the mold film, extends between the upper surface of each of the plurality of semiconductor chips and the mold film, and between the lower surface of each of the plurality of semiconductor chips and the mold film, and the mold film is spaced apart from each of the plurality of connecting bumps, each of the upper surface of each of the plurality of semiconductor chips, and each of the lower surface of the plurality of semiconductor chips with the protective film in between. Claim 2 In claim 1, the protective film is a semiconductor package in contact with each of the sides of the plurality of connection bumps. Claim 3 In claim 2, the protective film is a semiconductor package in contact with the mold film. Claim 4 A semiconductor package according to claim 1, wherein the mold film extends without an interface from the sides of the plurality of semiconductor chips to the bottom layer semiconductor chip and the lower semiconductor chip, and between the plurality of semiconductor chips. Claim 5 delete Claim 6 A semiconductor package according to claim 1, wherein the protective film extends between the sides of the plurality of semiconductor chips and the mold film, and the mold film is spaced apart from the sides of the plurality of semiconductor chips with the protective film in between. Claim 7 A semiconductor package according to claim 1, further comprising at least one void provided within the mold film between the bottom layer semiconductor chip and the lower semiconductor chip, or between the plurality of semiconductor chips. Claim 8 In claim 7, the semiconductor package wherein the at least one void exposes at least a portion of the protective film. Claim 9 A semiconductor package according to claim 1, wherein the protective film comprises a self-assembled monolayer, the self-assembled monolayer comprises a hydrocarbon chain, a first reactor connected to one end of the hydrocarbon chain, and a second reactor connected to the other end of the hydrocarbon chain, and the self-assembled monolayer is chemically adsorbed to each of the respective sides of the plurality of connecting bumps by the first reactor. Claim 10 A semiconductor package according to claim 9, wherein the self-assembled monolayer is chemically adsorbed onto the surface of the mold film by the second reactor. Claim 11 A semiconductor package according to claim 9, wherein the protective film further comprises an organic insulating film between the self-assembled monolayer and the mold film. Claim 12 A semiconductor package according to claim 11, wherein the self-assembled monolayer is chemically adsorbed onto the surface of the organic insulating film by the second reactor. Claim 13 In claim 1, the protective film comprises a semiconductor package including an inorganic insulating material. Claim 14 A semiconductor package comprising: a lower semiconductor chip; a plurality of semiconductor chips stacked on the lower semiconductor chip in a first direction perpendicular to the upper surface of the lower semiconductor chip; a plurality of connecting bumps disposed between the lower semiconductor chip and the lower semiconductor chip among the plurality of semiconductor chips, and between the plurality of semiconductor chips; a protective film covering each side of the plurality of connecting bumps; a mold film covering the sides of the plurality of semiconductor chips and extending between the lower semiconductor chip and the lower semiconductor chip and between the plurality of semiconductor chips, and interposed between the plurality of connecting bumps; and at least one void provided within the mold film between the lower semiconductor chip and the lower semiconductor chip, or between the plurality of semiconductor chips, wherein the at least one void exposes at least a portion of the protective film, and the at least one void is spaced apart from adjacent connecting bumps among the plurality of connecting bumps with the protective film in between. Claim 15 A semiconductor package according to claim 14, wherein the plurality of connecting bumps comprises a pair of connecting bumps spaced apart from each other with at least one void in between, the protective film is interposed between each of the pair of connecting bumps and the at least one void, and each of the pair of connecting bumps is spaced apart from the at least one void with the protective film in between. Claim 16 A semiconductor package according to claim 15, wherein the at least one void is provided within the mold film between the pair of connecting bumps, the protective film extends between each of the pair of connecting bumps and the mold film, and each of the pair of connecting bumps is spaced apart from the mold film with the protective film in between. Claim 17 In claim 14, each of the plurality of semiconductor chips has an upper surface and a lower surface facing each other in the first direction, and each of the plurality of connecting bumps includes a conductive pillar, a solder bump, and a conductive pad stacked in sequence on the lower surface of each of the plurality of semiconductor chips, and the protective film covers the side of the solder bump and extends over the sides of the conductive pillar and the conductive pad. Claim 18 A semiconductor package according to claim 17, wherein the conductive pillar is adjacent to the lower surface of each of the plurality of semiconductor chips, the conductive pad is adjacent to the upper surface of a corresponding semiconductor chip among the plurality of semiconductor chips or the upper surface of the lower semiconductor chip, and the solder bump is interposed between the conductive pillar and the conductive pad. Claim 19 In claim 14, each of the plurality of semiconductor chips has an upper surface and a lower surface facing each other in the first direction, and the protective film extends between the lower surface of each of the plurality of semiconductor chips and the mold film, and between the upper surface of each of the plurality of semiconductor chips and the mold film, forming a semiconductor package. Claim 20 A semiconductor package comprising: a lower semiconductor chip; a plurality of semiconductor chips stacked on the lower semiconductor chip in a first direction perpendicular to the upper surface of the lower semiconductor chip; a plurality of connecting bumps disposed between the plurality of semiconductor chips; a protective film covering each side of the plurality of connecting bumps; and a mold film covering the sides of the plurality of semiconductor chips and extending between the plurality of semiconductor chips and interposed between the plurality of connecting bumps, wherein the plurality of semiconductor chips include a pair of semiconductor chips spaced apart from each other in the first direction, and the plurality of connecting bumps include a pair of connecting bumps spaced apart from each other in a second direction parallel to the upper surface of the lower semiconductor chip and disposed between the pair of semiconductor chips, and the protective film is interposed between each side of the pair of connecting bumps and the mold film, extending between the pair of semiconductor chips and the mold film, and the mold film is spaced apart from the pair of connecting bumps and the pair of semiconductor chips with the protective film in between.

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