Integrated circuit device

Abstract

An integrated circuit element according to the technical concept of the present invention comprises a substrate having an active region, a plurality of bit line structures formed on the substrate and each having an insulating spacer on its respective sidewall, a buried contact formed between the plurality of bit line structures and connected to the active region, an insulating capping pattern formed on the upper side of each of the plurality of bit line structures, a barrier conductive film disposed to cover the side of the insulating capping pattern and the upper and side surfaces of the insulating spacers, and a landing pad electrically connected to the buried contact and disposed to overlap vertically with one of the plurality of bit line structures on the insulating capping pattern and the barrier conductive film.

Description

Technology Field

[0001] The technical field of the present invention relates to integrated circuit devices, and more specifically, to an integrated circuit device including a landing pad. Background Technology

[0002] Due to the rapid development of the electronics industry and user demands, electronic devices are becoming smaller and lighter. Consequently, there is a demand for integrated circuit devices with high integration density used in electronic devices, and design rules for the configurations of integrated circuit devices are decreasing. As a result, the difficulty of the manufacturing process for forming regular conductive patterns and insulating patterns around them that constitute integrated circuit devices is gradually increasing. The background technology of the present invention is disclosed in Korean Published Patent Application No. 10-2017-0008925 (January 25, 2017). The problem to be solved

[0003] The problem that the technical concept of the present invention aims to solve is to provide an integrated circuit device capable of securing production efficiency and stable operation performance by forming a plurality of landing pads with a regular conduction pattern with improved step height.

[0004] The problems that the technical concept of the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] An integrated circuit element according to the technical concept of the present invention comprises: a substrate having an active region; a plurality of bit line structures formed on the substrate and each having an insulating spacer on a sidewall; a buried contact formed between the plurality of bit line structures and connected to the active region; an insulating capping pattern formed on the upper surface of each of the plurality of bit line structures; a barrier conductive film disposed to cover the side surface of the insulating capping pattern and the upper surface and side surface of the insulating spacer; and a landing pad electrically connected to the buried contact and disposed to overlap vertically with one of the plurality of bit line structures on the insulating capping pattern and the barrier conductive film.

[0006] An integrated circuit element according to the technical concept of the present invention comprises: a substrate having a cell region and a core / periphery region; a plurality of bit line structures formed on the cell region and each having an insulating spacer on a sidewall; a buried contact formed between the plurality of bit line structures; an insulating capping pattern formed on the upper portion of each of the plurality of bit line structures; a barrier conductive film disposed to cover the side of the insulating capping pattern and the upper and side surfaces of the insulating spacers; a landing pad electrically connected to the buried contact and disposed to overlap vertically with one of the plurality of bit line structures on the insulating capping pattern and the barrier conductive film; and a core structure formed on the core / periphery region and having a barrier metal film on a sidewall; wherein the vertical level of the uppermost surface of the insulating capping pattern and the vertical level of the uppermost surface of the barrier conductive film are substantially the same, and the vertical level of the uppermost surface of the core structure and the vertical level of the uppermost surface of the barrier metal film are substantially the same.

[0007] An integrated circuit device according to the technical concept of the present invention comprises: a substrate having an active region defined by a device isolation region; a pair of bit line structures formed on the substrate and each having an insulating spacer on its respective sidewall; a buried contact formed between the pair of bit line structures and connected to the active region; an insulating capping pattern formed on the upper portion of each of the pair of bit line structures; a barrier conductive film disposed to cover the side of the insulating capping pattern and the upper surface and side of the insulating spacer; a landing pad electrically connected to the buried contact and disposed to overlap vertically with one of the pair of bit line structures on the insulating capping pattern and the barrier conductive film; and a node isolation pattern that contacts one side of the insulating capping pattern of the remaining of the pair of bit line structures and contacts the upper surface of the insulating spacer disposed on the same side as the one side of the insulating capping pattern. and a capacitor structure including a capacitor lower electrode formed on the upper surface of the landing pad and electrically connected to the landing pad. Effects of the invention

[0008] An integrated circuit device according to the technical concept of the present invention is flattened so that the uppermost surface of an insulating capping pattern and the uppermost surface of a barrier conductive film are of the same plane on the upper part of a bit line structure, thereby enabling the formation of multiple landing pads with a regular conductive pattern with improved step height, thus having the effect of securing production efficiency and stable operation performance. Brief explanation of the drawing

[0009] FIG. 1 is a plan view showing the schematic configuration of an integrated circuit element according to an embodiment of the technical concept of the present invention. FIG. 2 is a planar layout showing the main configurations of the cell region of an integrated circuit element according to an embodiment of the technical concept of the present invention. FIGS. 3a to 3d are cross-sectional views showing the main configurations of an integrated circuit element according to an embodiment of the technical concept of the present invention. FIG. 4 is a flowchart illustrating a method for manufacturing an integrated circuit element according to an embodiment of the technical concept of the present invention. FIGS. 5a to 13a are cross-sectional views cut along the position corresponding to line AA' of FIG. 2, and FIGS. 5b to 13b are cross-sectional views cut along the position corresponding to line BB' of FIG. 2, and are cross-sectional views shown in the order of process to explain a method for manufacturing an integrated circuit element according to an embodiment of the technical concept of the present invention. FIG. 14 is a configuration diagram showing a system including an integrated circuit element according to an embodiment of the technical concept of the present invention. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings.

[0011] FIG. 1 is a plan view showing the schematic configuration of an integrated circuit element according to an embodiment of the technical concept of the present invention.

[0012] Referring to FIG. 1, the integrated circuit element (10) has a substrate (110) comprising a cell region (CA), a core / periphery region (PA) surrounding the cell region (CA), and an interface region (IA) interposed between the cell region (CA) and the core / periphery region (PA).

[0013] The substrate (110) may be a wafer containing silicon (Si). Alternatively, the substrate (110) may be a wafer containing a semiconductor element such as germanium (Ge), or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), or InP (indium phosphide). Meanwhile, the substrate (110) may have a silicon-on-insulator (SOI) structure. Additionally, the substrate (110) may include a conductive region, for example, an impurity-doped well or an impurity-doped structure.

[0014] In some embodiments, the cell region (CA) may be a memory cell region of an integrated circuit element (10). The cell region (CA) may constitute a memory cell region of a volatile memory element or a memory cell region of a non-volatile memory element. The memory cell region may be a memory cell region such as a DRAM (dynamic random access memory), MRAM (magnetic RAM), SRAM (static RAM), PRAM (phase change RAM), RRAM (resistance RAM), or FRAM (ferroelectric RAM). The cell region (CA) may include a unit memory cell having a transistor and a capacitor, or a unit memory cell having a switching element and a variable resistor.

[0015] Core circuits and peripheral circuits necessary to drive memory cells located in the cell area (CA) may be placed in the core / periphery area (PA).

[0016] In the interface area (IA), a plurality of wiring lines installed to enable electrical connection between the cell area (CA) and the core / periphery area (PA), and a structure for insulation between the cell area (CA) and the core / periphery area (PA) may be arranged.

[0017] FIG. 2 is a planar layout showing the main configurations of the cell region of an integrated circuit element according to an embodiment of the technical concept of the present invention.

[0018] Referring to FIG. 2, the integrated circuit element (10) may include a plurality of active regions (ACTs) arranged to have long axes in a diagonal direction with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0019] A plurality of word lines (WL) may be extended in mutually parallel along a first horizontal direction (X direction) across a plurality of active regions (ACT). A plurality of bit lines (BL) may be extended in mutually parallel along a second horizontal direction (Y direction) that intersects the first horizontal direction (X direction) on the plurality of word lines (WL).

[0020] Multiple bit lines (BL) may be connected to multiple active regions (ACT) through direct contacts (DC). In some embodiments, multiple berid contacts (BC) may be formed between two mutually adjacent bit lines (BL). Each of the multiple berid contacts (BC) may extend to the top of either of the two mutually adjacent bit lines (BL). In some embodiments, the multiple berid contacts (BC) may be arranged in a line along a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0021] A plurality of landing pads (LP) may be formed on a plurality of buried contacts (BC). The plurality of buried contacts (BC) and the plurality of landing pads (LP) may serve to connect the lower electrode (not shown) of a capacitor formed on the upper part of a plurality of bit lines (BL) to a plurality of active regions (ACT). Each of the plurality of landing pads (LP) may be positioned to partially overlap with the plurality of buried contacts (BC). This will be examined in detail below.

[0022] FIGS. 3a to 3d are cross-sectional views showing the main configurations of an integrated circuit element according to an embodiment of the technical concept of the present invention.

[0023] Specifically, FIG. 3a is a cross-sectional view cut along the position corresponding to the line AA' in FIG. 1 and FIG. 2, FIG. 3b is a cross-sectional view cut along the position corresponding to the line BB' in FIG. 1 and FIG. 2, FIG. 3c is a cross-sectional view cut along the position corresponding to the line CC' in FIG. 1, and FIG. 3d is an enlarged cross-sectional view of the DD portion of FIG. 3a.

[0024] Referring together to FIGS. 3a to 3d, the integrated circuit element (10) has a plurality of memory cell structures formed on a substrate (110) including a cell region (CA) and a core / periphery region (PA).

[0025] The important components constituting the integrated circuit element (10) according to the technical concept of the present invention are as follows.

[0026] An integrated circuit element (10) may include a substrate (110) having a plurality of active regions (118), a plurality of gate dielectric films (122) sequentially formed within a plurality of word line trenches (120T) crossing the plurality of active regions (118) within the substrate (110), a plurality of word lines (120), and a plurality of berid insulating films (124).

[0027] Additionally, the integrated circuit element (10) may include an insulating film pattern (112, 114) covering an element isolation film (116), a plurality of active regions (118), and a plurality of buried insulating films (124), a plurality of bit line structures (140) on the insulating film pattern (112, 114), and a plurality of insulating spacers (150) covering both side walls of the plurality of bit line structures (140).

[0028] Additionally, the integrated circuit element (10) may include a plurality of buried contacts (170) that fill the lower part of the space defined by a plurality of insulating fences (180) and a plurality of insulating spacers (150) and are connected to a plurality of active regions (118), and a plurality of landing pads (194) that fill the upper part and extend to the upper part of the bit line structure (140) and are spaced apart from each other with a node separation pattern (196) in between.

[0029] Additionally, the integrated circuit element (10) may include a plurality of capacitor structures (200) comprising a plurality of lower electrodes (210) connected to a plurality of landing pads (194), a capacitor dielectric film (220), and an upper electrode (230).

[0030] In the integrated circuit element (10) of the present invention, the upper sidewall of the insulating capping pattern (148) formed on the upper portion of each of the plurality of bit line structures (140) may not be covered by the insulating spacer (150). In other words, the vertical level of the uppermost surface (148T) of the insulating capping pattern (148) may be located higher than the vertical level of the uppermost surface (150T) of the insulating spacer (150). Here, the vertical level of the uppermost surface (148T) of the insulating capping pattern (148) is referred to as the first level (LV1).

[0031] Accordingly, the width along the first horizontal direction (X direction) of the part of the landing pad (194) located at the first level (LV1), generally referred to as the neck of the landing pad (194), is increased, while the spacing between two adjacent landing pads (194) can be sufficiently secured.

[0032] In the integrated circuit element (10) of the present invention, a barrier conductive film (192) may be disposed to cover the side of the insulating capping pattern (148) and the upper and side surfaces of the insulating spacer (150). Here, the vertical level of the uppermost surface (148T) of the insulating capping pattern (148) and the vertical level of the uppermost surface (192T) of the barrier conductive film (192) may be the same as the first level (LV1). In other words, the uppermost surface (148T) of the insulating capping pattern (148) and the uppermost surface (192T) of the barrier conductive film (192) may be formed as flat surfaces on the same plane. As will be described later, this feature may be the result of performing a flattening process on the insulating capping pattern (148) and the barrier conductive film (192).

[0033] In the integrated circuit element (10) of the present invention, the landing pad (194) fills the interior of the barrier conductive film (192) and contacts the uppermost surface (148T) of the insulating capping pattern (148), but may not contact the insulating spacer (150). In other words, the upper surface of the insulating spacer (150), which is positioned to overlap the landing pad (194) in a vertical direction (Z direction), may be surrounded by the barrier conductive film (192).

[0034] Therefore, since the outer wall of the insulating spacer (150) is not exposed, the insulating spacer (150) may not be damaged by a wet etching solution (e.g., LAL solution) in a subsequent process for manufacturing an integrated circuit element (10). Accordingly, the insulating performance of the insulating spacer (150) may be further improved. Here, the LAL solution refers to a hydrofluoric acid (HF) solution containing ammonium fluoride (NH4F) and can be used for etching silicon oxide films.

[0035] In the integrated circuit element (10) of the present invention, the node separation pattern (196) may be positioned to contact one side of the insulating capping pattern (148) and to contact the upper surface of the insulating spacer (150) positioned on the same side as said one side of the insulating capping pattern (148). In other words, the vertical level of the lowest side of the node separation pattern (196) may be positioned lower than the vertical level of the upper surface of the insulating spacer (150). The node separation pattern (196) may be positioned to extend along the space between the landing pad (194) and the preliminary insulating spacer (150P) as it goes from the upper side to the lower side. For example, the node separation pattern (196) may be rounded so as to extend with an incline from the landing pad (194) toward the insulating capping pattern (148), which is the upper part of the bit line structure (140). The center of the lower part of the node separation pattern (196) can be aligned along the vertical direction (Z direction) with the center of the upper part of the barrier conductive film (192).

[0036] In the integrated circuit element (10) of the present invention, a core structure (140D) may be formed on a core / periphery region (PA) and may include a barrier metal film (192D) on a sidewall. The vertical level of the uppermost surface of the core structure (140D) and the vertical level of the uppermost surface of the barrier metal film (192D) are substantially the same and may be the same as a first level (LV1).

[0037] Here, the core structure (140D) and the conductive material layer (194D) in the core / periphery region (PA) are shown to be covered with an insulating layer such as the first insulating layer (175) and the second insulating layer (250), but are not limited thereto. That is, a number of conductive wirings and other components electrically connected to the active region (118) and / or the core structure (140D) may be formed in the core / periphery region (PA).

[0038] In the integrated circuit element (10) of the present invention, at the boundary between the cell region (CA) and the core / periphery region (PA), the vertical level of the top surface (148T) of the insulating capping pattern (148) and the vertical level of the top surface of the core structure (140D) are substantially the same, and this may be the same as the first level (LV1). In addition, the vertical level of the top surface of the landing pad (194) in the cell region (CA) and the vertical level of the top surface of the conductive material layer (194D) composed of the same material as the landing pad (194) in the core / periphery region (PA) may be substantially the same. These features may be the result of performing a planarization process on the insulating capping pattern (148) and the barrier conductive film (192).

[0039] Ultimately, the integrated circuit element (10) according to the technical concept of the present invention can be flattened so that the uppermost surface of the insulating capping pattern (148) and the uppermost surface of the barrier conductive film (192) are on the same plane at the top of the bit line structure (140), thereby forming a plurality of landing pads (194) with a regular conductive pattern with improved step height, thus having the effect of securing production efficiency and stable operation performance.

[0040] FIG. 4 is a flowchart illustrating a method for manufacturing an integrated circuit element according to an embodiment of the technical concept of the present invention.

[0041] Referring to FIG. 4, a method for manufacturing an integrated circuit element (S10) according to the technical concept of the present invention may include a process sequence of steps 1 to 8 (S110 to S180).

[0042] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described in succession may be performed substantially simultaneously or in the reverse order of the description.

[0043] A method for manufacturing an integrated circuit device (S10) according to the technical concept of the present invention comprises: a first step (S110) of forming a plurality of bit line structures on the upper surface of a substrate; a second step (S120) of forming a preliminary insulating spacer covering both side walls of each of the plurality of bit line structures; a third step (S130) of etching the upper surface of the preliminary insulating spacer so that the upper surface of the insulating capping pattern is exposed; a fourth step (S140) of forming a barrier conductive film conformally covering the plurality of bit line structures and the insulating spacer; a fifth step (S150) of forming a first landing pad layer covering the barrier conductive film; a sixth step (S160) of polishing the first landing pad layer and the barrier conductive film so that the upper surface of the insulating capping pattern is exposed; a seventh step (S170) of forming a second landing pad layer on the upper surface of the insulating capping pattern, the upper surface of the barrier conductive film, and the upper surface of the first landing pad layer; and a method for forming a landing pad by node separating the first landing pad layer and the second landing pad layer. It may include the eighth step (S180) of forming.

[0044] The technical features for each of the above-mentioned first to eighth steps (S110 to S180) will be explained in detail through FIGS. 5a to 13a and FIGS. 5b to 13b described later.

[0045] FIGS. 5a to 13a are cross-sectional views cut along the position corresponding to line AA' of FIG. 2, and FIGS. 5b to 13b are cross-sectional views cut along the position corresponding to line BB' of FIG. 2, and are cross-sectional views shown in the order of process to explain a method for manufacturing an integrated circuit element according to an embodiment of the technical concept of the present invention.

[0046] Referring to FIG. 5a and FIG. 5b together, a device isolation trench (116T) can be formed in a substrate (110), and a device isolation film (116) that fills the device isolation trench (116T) can be formed.

[0047] The device isolation film (116) may be made of a material comprising, for example, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The device isolation film (116) may be composed of a single layer made of one type of insulating film, a double layer made of two types of insulating films, or a multilayer made of a combination of at least three types of insulating films. For example, the device isolation film (116) may be composed of a double layer or a multilayer made of a silicon oxide film and a silicon nitride film, but is not limited thereto.

[0048] A plurality of active regions (118) can be defined on the substrate (110) by means of a device isolation layer (116). The active regions (118) may each have a relatively long island shape having a short axis and a long axis in a planar manner, such as the active region (ACT) illustrated in FIG. 2.

[0049] A plurality of word line trenches (120T) can be formed on the substrate (110). The plurality of word line trenches (120T) may have a line shape that extends in a first horizontal direction (X direction) parallel to each other and is arranged at equal intervals along a second horizontal direction (Y direction) across an active area (118). In some embodiments, a step may be formed on the bottom surface of the plurality of word line trenches (120T).

[0050] In some embodiments, a plurality of word line trenches (120T) can etch the device isolation film (116) and the substrate (110) separately using a separate etching process, so that the etching depth of the device isolation film (116) and the etching depth of the substrate (110) are different from each other. In other embodiments, a plurality of word line trenches (120T) can etch the device isolation film (116) and the substrate (110) together, but the etching depth of the device isolation film (116) and the etching depth of the substrate (110) are different from each other due to the difference in etching rates between the device isolation film (116) and the substrate (110).

[0051] After cleaning the result in which a plurality of word line trenches (120T) are formed, a plurality of gate dielectric films (122), a plurality of word lines (120), and a plurality of buried insulating films (124) can be formed sequentially inside the plurality of word line trenches (120T). The plurality of word lines (120) can be configured as a plurality of word lines (WL) as illustrated in FIG. 2. The plurality of word lines (120) may have a line shape that extends parallelly in a first horizontal direction (X direction) and is arranged at equal intervals along a second horizontal direction (Y direction) while crossing an active region (118). The upper surface of each of the plurality of word lines (120) may be located at a vertical level lower than the upper surface of the substrate (110). Additionally, the bottom surface of the plurality of word lines (120) may have an uneven shape, and a saddle fin structure transistor (saddle FinFET) may be formed in the plurality of active regions (118).

[0052] In some embodiments, each of the plurality of word lines (120) may be a stacked structure of a lower word line layer (120a) and an upper word line layer (120b). For example, the lower word line layer (120a) may be made of a metallic material, a conductive metal nitride, or a combination thereof. In some embodiments, the lower word line layer (120a) may be made of Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. For example, the upper word line layer (120b) may be made of doped polysilicon.

[0053] In some embodiments, before or after forming a plurality of word lines (120), impurity ions may be injected into the active regions (118) on both sides of the plurality of word lines (120) to form source / drain regions inside the substrate (110).

[0054] The gate dielectric film (122) may be composed of at least one selected from silicon oxide, silicon nitride, silicon oxynitride, ONO (oxide / nitride / oxide), and a high-k dielectric film having a dielectric constant higher than that of silicon oxide. In some embodiments, the gate dielectric film (122) may be made of at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxide nitride (HfON), hafnium silicon oxide nitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxide nitride (ZrON), zirconium silicon oxide nitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the gate dielectric film (122) can be made of HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2.

[0055] The upper surface of a plurality of berid insulating films (124) may be located at a vertical level substantially identical to the upper surface of the substrate (110). The berid insulating film (124) may be made of at least one material film selected from silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0056] Referring to FIG. 6a and FIG. 6b together, an insulating film pattern (112, 114) covering a device isolation film (116), a plurality of active regions (118), and a plurality of buried insulating films (124) is formed.

[0057] The insulating film pattern (112, 114) may be made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal-based dielectric film, or a combination thereof. In some embodiments, the insulating film pattern (112, 114) may be formed by stacking a plurality of insulating films including a first insulating film pattern (112) and a second insulating film pattern (114). In some embodiments, the first insulating film pattern (112) may be made of a silicon oxide film and the second insulating film pattern (114) may be made of a silicon oxynitride film. In other embodiments, the first insulating film pattern (112) may be made of a non-metal-based dielectric film and the second insulating film pattern (114) may be made of a metal-based dielectric film.

[0058] After forming a conductive semiconductor layer (132P) on an insulating film pattern (112, 114), a direct contact hole (134H) is formed that penetrates the conductive semiconductor layer (132P) and the insulating film pattern (112, 114) to expose a source / drain region within an active region (118), and a conductive layer (134P) for direct contact is formed to fill the direct contact hole (134H). The direct contact hole (134H) may extend from the active region (118) into the interior of the source / drain region.

[0059] The conductive semiconductor layer (132P) may be made of, for example, doped polysilicon. The conductive layer (134P) for direct contact may be made of, for example, doped polysilicon, tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or a combination thereof.

[0060] In other embodiments, a direct contact hole (134H) that penetrates the insulating film pattern (112, 114) to expose the source / drain region within the active region (118) may be formed first, and then a conductive semiconductor layer (132P) that fills the direct contact hole (134H) and covers the insulating film pattern (112, 114) and a conductive layer (134P) for direct contact may be formed together.

[0061] Referring to FIG. 7a and FIG. 7b together, a metal-based conductive layer and an insulating capping layer are sequentially formed to cover a conductive semiconductor layer (132P) and a conductive layer (134P) for direct contact, and to form a bit line structure (140).

[0062] In some embodiments, the metallic conductive layer may be a stacked structure of a first metallic conductive layer and a second metallic conductive layer. The metallic conductive layer may have a double-layered conductive layer stacked structure, but is not limited thereto. For example, the metallic conductive layer may be formed as a single layer or a plurality of stacked structures of three or more layers.

[0063] In some embodiments, the insulating capping layer may have a laminated structure of a first insulating capping layer, a second insulating capping layer, and a third insulating capping layer. The insulating capping layer may have a triple-layer insulating layer laminated structure, but is not limited thereto. For example, the insulating capping layer may be formed as a single layer, a double layer, or a plurality of laminated structures of four or more layers.

[0064] The first metal-based conductive layer, the second metal-based conductive layer, and the insulating capping layer are etched to form a plurality of bit lines (147) and a plurality of insulating capping patterns (148) having a stacked structure of a first metal-based pattern (145) and a second metal-based pattern (146) in the shape of a line.

[0065] In some embodiments, the first metal-based pattern (145) may be made of titanium nitride (TiN) or TSN (Ti-Si-N), and the second metal-based pattern (146) may be made of tungsten (W) or tungsten silicide (WSi x It can be composed of ).

[0066] In some embodiments, a plurality of insulating capping patterns (148) may be formed as a stacked structure of a first insulating capping pattern (148a), a second insulating capping pattern (148b), and a third insulating capping pattern (148c). In some embodiments, each of the first insulating capping pattern (148a), the second insulating capping pattern (148b), and the third insulating capping pattern (148c) may be made of a silicon-based insulating film, for example, the third insulating capping pattern (148c) may be made of a silicon nitride film.

[0067] A single bit line (147) and a single insulating capping pattern (148) covering it may form a single bit line structure (140). Each of the multiple bit line structures (140) composed of multiple bit lines (147) and multiple insulating capping patterns (148) may extend in a second horizontal direction (Y direction) with respect to the main surface of the substrate (110) in mutually parallel. The multiple bit lines (147) may form multiple bit lines (BL) as illustrated in FIG. 2. In some embodiments, the bit line structure (140) may further include a conductive semiconductor pattern (132) which is part of a conductive semiconductor layer (132P, see FIG. 6a) disposed between the insulating film patterns (112, 114) and the first metal-based pattern (145).

[0068] In an etching process for forming multiple bit lines (147), a portion of the conductive layer (134P, see FIG. 6a) for direct contact that does not vertically overlap with the bit lines (147) may be removed together in the etching process to form multiple direct contact patterns (134). In this case, the insulating film patterns (112, 114) may function as an etch stop layer in the etching process for forming multiple bit lines (147) and multiple direct contact patterns (134). The multiple direct contact patterns (134) may constitute multiple direct contacts (DC) as exemplified in FIG. 2. The multiple bit lines (147) may be electrically connected to multiple active regions (118) through the multiple direct contact patterns (134).

[0069] After forming the bit line structure (140), during the process of forming the direct contact pattern (134), a buried insulation pattern (136) may be formed to fill the portion of the direct contact hole (134H) from which a portion of the direct contact conductive layer (134P, see FIG. 6a) has been removed. The buried insulation pattern (136) may be made of, for example, a silicon nitride film.

[0070] Each of the multiple bit line structures (140) may have both side walls covered with a preliminary insulation spacer (150P). Each of the multiple preliminary insulation spacers (150P) may include a first insulation spacer (152), a second insulation spacer (154), a third insulation spacer (156), and a fourth insulation spacer (158). In some embodiments, each of the multiple preliminary insulation spacers (150P) may not include either the third insulation spacer (156) or the fourth insulation spacer (158). That is, each of the multiple preliminary insulation spacers (150P) may consist of a first insulation spacer (152), a second insulation spacer (154), and a third insulation spacer (156). Alternatively, a plurality of preliminary insulation spacers (150P) may each include a first insulation spacer (152), a second insulation spacer (154), and a fourth insulation spacer (158).

[0071] A plurality of buried contact holes (170H) may be formed between a plurality of bit lines (147). The internal space of the plurality of buried contact holes (170H) may be limited by a preliminary insulating spacer (150P) and an active region (118) that cover the sidewalls of each of the two adjacent bit lines (147) among the plurality of bit lines (147).

[0072] A plurality of buried contact holes (170H) can be formed by removing a portion of the insulating film patterns (112, 114) and the active region (118) using a plurality of insulating capping patterns (148) and a preliminary insulating spacer (150P) as an etching mask. In some embodiments, the plurality of buried contact holes (170H) can be formed by first performing an anisotropic etching process to remove a portion of the insulating film patterns (112, 114) and the active region (118), and then further performing an isotropic etching process to remove another portion of the active region (118), so that the space defined by the active region (118) is expanded.

[0073] Referring to FIG. 8a and FIG. 8b together, a plurality of buried contacts (170) and a plurality of insulating fences (180) are formed in the space between a plurality of preliminary insulating spacers (150P, see FIG. 7a) covering both side walls of each of a plurality of bit line structures (140), and an insulating spacer (150) is formed by etching the upper part of the preliminary insulating spacer (150P, see FIG. 7a).

[0074] A plurality of buried contacts (170) and a plurality of insulating fences (180) may be alternately arranged along a pair of mutually facing preliminary insulating spacers (150P, see FIG. 7a) among a plurality of preliminary insulating spacers (150P, see FIG. 7a) covering both side walls of a plurality of bit line structures (140). For example, the plurality of buried contacts (170) may be made of doped polysilicon, and the plurality of insulating fences (180) may be made of silicon nitride films.

[0075] A plurality of buried contacts (170) may extend from the active region (118) in a vertical direction (Z direction) perpendicular to the substrate (110). A plurality of buried contacts (170) may constitute a plurality of buried contacts (BC) as illustrated in FIG. 2. A plurality of buried contacts (170) may be placed in a space defined by a plurality of insulating fences (180) and a plurality of pre-insulating spacers (150P, see FIG. 7a). Additionally, a plurality of buried contacts (170) may fill a lower portion of the space between the plurality of pre-insulating spacers (150P, see FIG. 7a).

[0076] The upper surface of the plurality of buried contacts (170) may be located at a lower vertical level than the upper surface of the plurality of insulating capping patterns (148). Additionally, the upper surface of the plurality of insulating fences (180) and the upper surface of the plurality of insulating capping patterns (148) may be located at substantially the same vertical level.

[0077] A plurality of landing pad holes (190H) may be defined by a plurality of pre-insulating spacers (150P, see FIG. 7a) and a plurality of insulating fences (180). A plurality of buried contacts (170) may be exposed on the bottom surface of the plurality of landing pad holes (190H).

[0078] In the process of forming a plurality of buried contacts (170) and / or a plurality of insulating fences (180), an upper portion of a preliminary insulating spacer (150P, see FIG. 7a) may be removed to form an insulating spacer (150), and a portion of the upper and side surfaces of the insulating capping pattern (148) may be exposed to the outside. Alternatively, the upper portion of the preliminary insulating spacer (150P, see FIG. 7a) may be etched by an additional etching process to expose the upper portion of the insulating capping pattern (148), thereby forming an insulating spacer (150).

[0079] Referring to FIG. 9a and FIG. 9b together, a barrier conductive film (192) is formed to conformally cover a plurality of bit line structures (140) along a plurality of landing pad holes (190H).

[0080] For example, the barrier conductive film (192) may be made of a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the barrier conductive film (192) may be made of a Ti / TiN stacked structure or TiN.

[0081] In some embodiments, a metal silicide film may be formed on a plurality of buried contacts (170) before forming the barrier conductive film (192). The metal silicide film may be disposed between the plurality of buried contacts (170) and the barrier conductive film (192). The metal silicide film is cobalt silicide (CoSi x ), nickel silicide (NiSi x ), or manganese silicide (MnSi x It can be composed of ), but is not limited to this.

[0082] The barrier conductive film (192) can cover both the upper surface of the insulating capping pattern (148) and the upper surface of the insulating spacer (150). Additionally, the barrier conductive film (192) can cover both the upper surface of the blocked contact (170) and the upper surface of the insulating fence (180).

[0083] Referring to FIG. 10a and FIG. 10b together, a first landing pad layer (194A) is formed by filling a plurality of landing pad holes (190H) and covering a barrier conductive film (192).

[0084] The first landing pad layer (194A) may include tungsten (W). In some embodiments, the first landing pad layer (194A) is formed by filling a plurality of landing pad holes (190H) on a barrier conductive film (192), so the lower and upper surfaces of the first landing pad layer (194A) may be formed as uneven surfaces. In some embodiments, the first landing pad layer (194A) may constitute a lower region of the landing pad (194, see FIG. 13a).

[0085] Referring to FIG. 11a and FIG. 11b together, the first landing pad layer (194A) and the barrier conductive film (192) are polished so that the upper surface of the insulating capping pattern (148) is exposed.

[0086] A grinding and flattening process is performed using a grinder. The grinding and flattening process may be a chemical mechanical grinding process. The grinder can remove a portion of the first landing pad layer (194A) and a portion of the barrier conductive film (192) through the grinding and flattening process to form a flat surface in which the uppermost surface of a plurality of insulating capping patterns (148) is exposed.

[0087] After the above polishing and flattening process is completed, the top surface of the insulating capping pattern (148), the top surface of the barrier conductive film (192), and the top surface of the first landing pad layer (194A) can form a coplanar.

[0088] In addition, the step difference between the cell region (CA, see FIG. 1) and the core / periphery region (PA, see FIG. 1) can be eliminated through the chemical mechanical polishing process. As a result, the step difference caused by the difference in the substructure between the cell region (CA, see FIG. 1) and the core / periphery region (PA, see FIG. 1) is eliminated, thereby preventing patterning defects in subsequent processes caused by the step difference.

[0089] Referring to FIG. 12a and FIG. 12b together, a second landing pad layer (194B) is formed on the upper surface of a plurality of insulating capping patterns (148) after the polishing process is completed, the upper surface of a barrier conductive film (192), and the upper surface of a first landing pad layer (194A).

[0090] The second landing pad layer (194B) may include tungsten (W). That is, since the first landing pad layer (194A) and the second landing pad layer (194B) may be composed of substantially the same material, the boundary between them may be ambiguous. In some embodiments, the first landing pad layer (194A) is formed on the upper surface of a plurality of flattened insulating capping patterns (148), the upper surface of a barrier conductive film (192), and the upper surface of the first landing pad layer (194A), so the lower and upper surfaces of the second landing pad layer (194B) may be formed as flat surfaces. In some embodiments, the second landing pad layer (194B) may constitute the upper region of the landing pad (194, see FIG. 13a).

[0091] A plurality of hard mask patterns (HMK) are formed on the second landing pad layer (194B). In some embodiments, the plurality of hard mask patterns (HMK) may be formed through an ArF lithography process or an EUV lithography process.

[0092] Referring to FIG. 13a and FIG. 13b together, a recess (190) is formed by performing an etching process that removes a portion of the first landing pad layer (194A) and the second landing pad layer (194B) using a plurality of hard mask patterns (HMK, see FIG. 12a) as an etching mask.

[0093] In the etching process for forming the recess (190), the upper portion of the plurality of insulating spacers (150), the upper portion of the plurality of insulating capping patterns (148), the upper portion of the barrier conductive film (192), and the upper portion of the plurality of insulating fences (180) may be removed.

[0094] The first landing pad layer (194A) and the second landing pad layer (194B) can be formed into a plurality of landing pads (194) by a process in which they are separated into multiple parts by a recess (190), a process generally referred to as a node separation process. The plurality of landing pads (194) can be spaced apart from each other with the recess (190) in between.

[0095] A plurality of landing pads (194) are disposed on a plurality of buried contacts (170) and may extend onto a plurality of bit line structures (140). In some embodiments, a plurality of landing pads (194) may extend onto a plurality of bit lines (147). A plurality of landing pads (194) are disposed on a plurality of buried contacts (170) so that a plurality of corresponding buried contacts (170) and a plurality of landing pads (194) may be electrically connected. A plurality of landing pads (194) may be electrically connected to an active region (118) through a plurality of buried contacts (170).

[0096] A plurality of landing pads (194) may comprise a plurality of landing pads (LP) as illustrated in FIG. 2. Each of the plurality of landing pads (194) may be formed on a barrier conductive film (192). In some embodiments, the plurality of landing pads (194) may be made of tungsten (W).

[0097] A buried contact (170) can be placed between two adjacent bit line structures (140), and a landing pad (194) can be extended from between two adjacent bit line structures (140) with the buried contact (170) in between onto one bit line structure (140).

[0098] Again, referring to FIG. 3a and FIG. 3b together, after forming a node separation pattern (196) that fills the recess (190), a plurality of lower electrodes (210), a capacitor dielectric film (220), and an upper electrode (230) are sequentially formed on a plurality of landing pads (194) to form an integrated circuit element (10) including a plurality of capacitor structures (200).

[0099] In some embodiments, the node separation pattern (196) may consist of an interlayer insulating layer and an etch stop layer. For example, the interlayer insulating layer may be made of a silicon oxide film, and the etch stop layer may be made of a silicon nitride film.

[0100] Each of the plurality of lower electrodes (210) may be electrically connected to each of the plurality of landing pads (194). A capacitor dielectric film (220) may conformally cover the plurality of lower electrodes (210). An upper electrode (230) may cover the capacitor dielectric film (220). The upper electrode (230) may face the lower electrode (210) with the capacitor dielectric film (220) in between. Each of the capacitor dielectric film (220) and the upper electrode (230) may be integrally formed to cover the plurality of lower electrodes (210) together within a certain area.

[0101] In some embodiments, each of the plurality of lower electrodes (210) may be in the shape of a pillar, which is a filled column shape having a circular horizontal cross-section, but is not limited thereto. In other embodiments, each of the plurality of lower electrodes (210) may be in the shape of a cylinder with a closed bottom. Additionally, the plurality of lower electrodes (210) may be arranged in a honeycomb shape arranged in a zigzag pattern with respect to a first horizontal direction (X direction) or a second horizontal direction (Y direction). Alternatively, the plurality of lower electrodes (210) may be arranged in a matrix shape arranged in a line along the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. The plurality of lower electrodes (210) may be made of, for example, a metal such as silicon, tungsten, or copper doped with impurities, or a conductive metal compound such as titanium nitride. Although not illustrated, at least one support pattern may be further included in contact with the side walls of the plurality of lower electrodes (210).

[0102] The capacitor dielectric film (220) may be made of, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST((Ba,Sr)TiO), STO(SrTiO), BTO(BaTiO), PZT(Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or a combination thereof.

[0103] The upper electrode (230) may be made of, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof.

[0104] Through such a manufacturing method, an integrated circuit element (10) according to the technical concept of the present invention can be manufactured. Ultimately, the integrated circuit element (10) according to the technical concept of the present invention can be flattened so that the uppermost surface of the insulating capping pattern (148) and the uppermost surface of the barrier conductive film (192) on the upper part of the bit line structure (140) are of the same plane, thereby forming a plurality of landing pads (194) with a regular conductive pattern with improved step height, thus having the effect of securing production efficiency and stable operation performance.

[0105] FIG. 14 is a configuration diagram showing a system including an integrated circuit element according to an embodiment of the technical concept of the present invention.

[0106] Referring to FIG. 14, the system (1000) includes a controller (1010), an input / output device (1020), a memory device (1030), an interface (1040), and a bus (1050).

[0107] The system (1000) may be a mobile system or a system that transmits or receives information. In some embodiments, the mobile system may be a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card.

[0108] The controller (1010) is for controlling an execution program in the system (1000) and may be composed of a microprocessor, a digital signal processor, a microcontroller, or a similar device.

[0109] The input / output device (1020) can be used to input or output data of the system (1000). The system (1000) can be connected to an external device, for example, a personal computer or a network, using the input / output device (1020), and can exchange data with the external device. The input / output device (1020) may be, for example, a touch screen, a touchpad, a keyboard, or a display.

[0110] The memory device (1030) can store data for the operation of the controller (1010) or data processed by the controller (1010). The memory device (1030) may include an integrated circuit element (10) according to the technical concept of the present invention described above.

[0111] The interface (1040) may be a data transmission channel between the system (1000) and an external device. The controller (1010), input / output device (1020), memory device (1030), and interface (1040) may communicate with each other via a bus (1050).

[0112] Although embodiments of the technical concept of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0113] 10: Integrated circuit components 110: Substrate 118: Active region 120: Word line 140: Bit line structure 148: Insulation capping pattern 150: Insulation spacer 170: Buried contact 180: Insulated fence 192: Barrier Challenge Membrane 194: Landing Pad 196: Node separation pattern 200: Capacitor structure

Claims

Claim 1 An integrated circuit device comprising: a substrate having an active region; a plurality of bit line structures formed on the substrate and each having an insulating spacer on a sidewall; a buried contact formed between the plurality of bit line structures and connected to the active region; an insulating capping pattern formed on the upper portion of each of the plurality of bit line structures; a barrier conductive film disposed to cover the side of the insulating capping pattern and the upper and side surfaces of the insulating spacers; and a landing pad electrically connected to the buried contact and disposed to overlap vertically with one of the plurality of bit line structures on the insulating capping pattern and the barrier conductive film. Claim 2 An integrated circuit device according to claim 1, characterized in that the vertical level of the uppermost surface of the insulating capping pattern and the vertical level of the uppermost surface of the barrier conductive film are substantially the same. Claim 3 An integrated circuit device according to claim 2, characterized in that the uppermost surface of the insulating capping pattern and the uppermost surface of the barrier conductive film are formed as flat surfaces on the same plane. Claim 4 An integrated circuit element according to claim 1, characterized in that the vertical level of the uppermost surface of the insulating capping pattern is higher than the vertical level of the uppermost surface of the insulating spacer. Claim 5 An integrated circuit element according to claim 4, wherein the landing pad fills the interior of the barrier conductive film, contacts the uppermost surface of the insulating capping pattern, and does not contact the insulating spacer. Claim 6 An integrated circuit device according to claim 5, characterized in that the upper surface of the insulating spacer, which is positioned to overlap vertically with the landing pad, is surrounded by the barrier conductive film. Claim 7 An integrated circuit element according to claim 1, further comprising a node separation pattern that contacts one side of the insulating capping pattern and contacts the upper surface of the insulating spacer disposed on the same side as the one side of the insulating capping pattern. Claim 8 An integrated circuit device according to claim 7, wherein the node separation pattern is in contact with the landing pad and the barrier conductive film. Claim 9 An integrated circuit device according to claim 7, characterized in that the vertical level of the lowest surface of the node separation pattern is lower than the vertical level of the uppermost surface of the insulating spacer. Claim 10 An integrated circuit device according to claim 1, wherein the insulating spacer comprises an inner spacer in contact with each of the plurality of bit line structures; and an outer spacer interposed between the inner spacer and the barrier conductive film.

Images