Semiconductor devices and manufacturing methods for the same

Abstract

A method for manufacturing a semiconductor device comprises: forming a plurality of reference patterns and peripheral patterns connected to the ends of the plurality of reference patterns using a first material on a feature layer; forming a plurality of first spacers using a second material on both sidewalls of each of the plurality of reference patterns; removing the plurality of reference patterns; forming a plurality of second spacers using the first material on both sidewalls of each of the plurality of first spacers; removing the plurality of first spacers so as to leave only the plurality of second spacers and the peripheral patterns on the feature layer; and patterning the feature layer using the plurality of second spacers and the peripheral patterns as an etching mask.

Description

Technology Field

[0001] The technical concept of the present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a method for manufacturing a semiconductor device using quadruple patterning technology and a semiconductor device formed by the same. Background Technology

[0002] With the downscaling of semiconductor devices, the size of individual fine circuit patterns for implementing semiconductor devices is being further reduced. However, due to the resolution limit in the photolithography process, there is a limit to the reduction in pitch of fine patterns. To form fine patterns that are further reduced within the resolution limit of the photolithography process, patterning technologies such as double patterning technology (DPT) or quadruple patterning technology (QPT) are being developed. The problem to be solved

[0003] The technical problem that the technical concept of the present invention aims to solve is to provide a method for manufacturing a semiconductor device capable of forming a fine pattern having a reduced width. means of solving the problem

[0004] A method for manufacturing a semiconductor device according to exemplary embodiments for achieving the above technical problem comprises: forming a plurality of reference patterns and peripheral patterns connected to the ends of the plurality of reference patterns using a first material on a feature layer; forming a plurality of first spacers using a second material on both sidewalls of each of the plurality of reference patterns; removing the plurality of reference patterns; forming a plurality of second spacers using the first material on both sidewalls of each of the plurality of first spacers; removing the plurality of first spacers so as to leave only the plurality of second spacers and the peripheral patterns on the feature layer; and patterning the feature layer using the plurality of second spacers and the peripheral patterns as an etching mask.

[0005] A method for manufacturing a semiconductor device according to exemplary embodiments for achieving the above technical problem comprises: forming a plurality of reference patterns and peripheral patterns connected to the ends of the plurality of reference patterns on a feature layer; forming a plurality of first spacers on both side walls of each of the plurality of reference patterns; removing the plurality of reference patterns; forming a plurality of second spacers on both side walls of each of the plurality of first spacers; forming a gap-fill insulating layer on the feature layer that fills the space between the plurality of second spacers; removing the gap-fill insulating layer and the plurality of first spacers to leave only the plurality of second spacers and the peripheral patterns on the feature layer; and patterning the feature layer using the plurality of second spacers and the peripheral patterns as an etching mask.

[0006] A method for manufacturing a semiconductor device according to exemplary embodiments for achieving the above technical problem comprises: providing a substrate including a cell array region and a boundary region; forming a feature layer on the substrate; forming a plurality of reference patterns and a peripheral pattern on the feature layer using a first material, wherein the plurality of reference patterns are disposed on the cell array region and the peripheral pattern is connected to the ends of the plurality of reference patterns and disposed on the boundary region; forming a plurality of first spacers using a second material on both sidewalls of each of the plurality of reference patterns; removing the plurality of reference patterns; forming a plurality of second spacers using the first material on both sidewalls of each of the plurality of first spacers; removing the plurality of first spacers so as to leave only the plurality of second spacers and the peripheral pattern on the feature layer; and patterning the feature layer using the plurality of second spacers and the peripheral pattern as an etching mask. and a step of forming a device isolation trench by removing a portion of the substrate using the feature layer as an etching mask;

[0007] A semiconductor device according to exemplary embodiments for achieving the above technical problem comprises: a substrate including a cell array region and a boundary region; a device isolation trench having a first portion extending in a first direction in the cell array region of the substrate and a second portion connected to the first portion in the boundary region; and a device isolation film filling the device isolation trench and defining an active region in the substrate, wherein the first portion of the device isolation trench includes a set of a first trench, a second trench, a third trench, and a fourth trench arranged in order along a second direction, and the length of the first trench is greater than the length of the second trench, and the length of the third trench is greater than the length of the fourth trench.

[0008] A semiconductor device according to exemplary embodiments for achieving the above technical problem comprises: a substrate including a cell array region and a boundary region; a plurality of line patterns disposed on the cell array region of the substrate and extending in parallel; and an alignment key pattern disposed on the boundary region of the substrate, comprising a main pattern having a first height and an edge pattern disposed spaced apart from the main pattern and surrounding the main pattern, and having a second height equal to the first height. Effects of the invention

[0009] According to the technical concept of the present invention, a first spacer is formed on both side walls of a plurality of reference patterns, and then the plurality of reference patterns are removed. A second spacer is formed on both side walls of the first spacer using the same material as the reference pattern or a material of the same type having similar etching characteristics, and then the first spacer is removed. A feature layer is patterned using the second spacer. Since the plurality of reference patterns and the second spacer contain the same material, only the pattern formation area can be patterned with a fine pitch while the surrounding area of ​​the plurality of reference patterns is covered. Accordingly, a plurality of intermediate sacrificial layers can be omitted to use the conventional quadruple patterning technique, thereby allowing the patterning process to be precisely controlled. Brief explanation of the drawing

[0010] FIGS. 1a to 10b are schematic diagrams illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. Specifically, FIGS. 1a, 2a, 3a, 4a, 5a, 6a, 7a, and 9a are horizontal cross-sectional views taken at the first vertical level (LV1) of FIG. 1b according to the process sequence, FIG. 10a is a horizontal cross-sectional view taken at the second vertical level (LV2) of FIG. 10b, and FIGS. 1b, 2b, 3b, 4b, 5b, 6b, 7b, 8, 9b, and 10b are cross-sectional views along the line AA' of FIG. 1a. FIGS. 11a to 13 are schematic diagrams illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 11a, 12a, and 13 are plan views illustrating a method for manufacturing a semiconductor device in the order of process, and FIGS. 11b and 12b are cross-sectional views along the line BB' of FIGS. 11a and 12a. FIGS. 14a through 19b are schematic diagrams illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 14a and 19a are plan views shown in the process sequence, and FIGS. 14b, 15 through 18, and 19b are cross-sectional views along the CC' line of FIG. 14a. Specific details for implementing the invention

[0011] Hereinafter, exemplary embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings.

[0012] FIGS. 1a to 10b are schematic diagrams illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. Specifically, FIGS. 1a, 2a, 3a, 4a, 5a, 6a, 7a, and 9a are horizontal cross-sectional views taken at the first vertical level (LV1) of FIG. 1b according to the process sequence, FIG. 10a is a horizontal cross-sectional view taken at the second vertical level (LV2) of FIG. 10b, and FIGS. 1b, 2b, 3b, 4b, 5b, 6b, 7b, 8, 9b, and 10b are cross-sectional views along the line AA' of FIG. 1a.

[0013] Referring to FIG. 1a and FIG. 1b, a feature layer (120) and a reference pattern layer (130L) can be formed on a substrate (110).

[0014] The substrate (110) may comprise silicon, for example, single-crystal silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the substrate (110) may comprise at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate (110) may comprise a conductive region, for example, an impurity-doped well, or an impurity-doped structure.

[0015] The feature layer (120) may be an etchable layer required to form a plurality of feature patterns (122) (see FIG. 10b) by patterning the feature layer (120). The feature layer (120) may include silicon oxide, silicon nitride, or polysilicon, etc. The reference pattern layer (130L) may be formed using a first material, for example, the first material may include polysilicon or amorphous silicon.

[0016] Subsequently, a first mask pattern (M10) may be formed on the reference pattern layer (130L). The first mask pattern (M10) may include a plurality of openings (M10H) extending in a second direction (Y). The first mask pattern (M10) may include a plurality of line patterns (M12) extending in the second direction (Y) and a surrounding pattern (M14) connected to both ends of the plurality of line patterns (M12) and surrounding the periphery of the plurality of line patterns (M12).

[0017] Referring to FIGS. 2a and 2b, a reference pattern layer (130L) can be patterned using a first mask pattern (M10) as an etching mask to form a reference pattern structure (130) including a plurality of reference patterns (132) and surrounding patterns (134).

[0018] A plurality of reference patterns (132) may be formed at positions corresponding to a plurality of line patterns (M12) of a first mask pattern (M10), each having a first width (W11) in a first direction (X) and arranged spaced apart from each other by a first interval (D11) in a first direction (X). For example, a plurality of reference patterns (132) may be arranged with a first pitch (P11), and when a plurality of feature patterns (122) are to be formed with a width of 1F and a pitch of 2F (i.e., when the target feature size of the plurality of feature patterns (122) is 1F), the first pitch (P11) may correspond to 8F. In exemplary embodiments, the first width (W11) of each of the plurality of reference patterns (132) may correspond to 3F, and the first interval (D11) may correspond to 5F.

[0019] A reference pattern trench (132T) may be placed between two adjacent reference patterns (132). The upper surface of the feature layer (120) may be exposed at the bottom of the reference pattern trench (132T).

[0020] The surrounding pattern (134) is connected to both ends of a plurality of reference patterns (132) and can surround the plurality of reference patterns (132) in a plan view. The surrounding pattern (134) can be formed at a position corresponding to the surrounding pattern (M14) of the first mask pattern (M10).

[0021] In exemplary embodiments, a plurality of reference patterns (132) may be formed in a pattern forming region where the formation of a pattern having a fine pitch is required, and a peripheral pattern (134) may be formed in a peripheral circuit region surrounding the pattern forming region or in a region where the formation of a pattern having a relatively large size is required. In some examples, a plurality of reference patterns (132) may be formed in a memory cell array region, and a peripheral pattern (134) may be formed in a boundary region or a peripheral circuit region surrounding the memory cell array region. In other examples, a plurality of reference patterns (132) may be formed in a logic cell placement region, and a peripheral pattern (134) may be formed in an input / output element placement region.

[0022] Referring to FIGS. 3a and 3b, a first spacer layer (140L) can be formed on a feature layer (120) to cover a plurality of reference patterns (132) and surrounding patterns (134).

[0023] A first portion (140P1) of the first spacer layer (140L) may be conformally disposed on both side walls and the top surface of each of the plurality of reference patterns (132), and on the top surface of the feature layer (120) exposed at the bottom of the reference pattern trench (132T). A second portion (140P2) of the first spacer layer (140L) may be conformally disposed on the side walls and the top surface of the surrounding pattern (134).

[0024] In exemplary embodiments, the first spacer layer (140L) may be formed using a second material different from the first material included in a plurality of reference patterns (132) and surrounding patterns (134), for example, the second material may include silicon oxide, silicon nitride, or silicon oxynitride. In exemplary embodiments, the first spacer layer (140L) may be formed by an atomic layer stacking process, a chemical vapor deposition process, etc. In some examples, the feature layer (120) and the first spacer layer (140L) may include silicon oxide.

[0025] Subsequently, a second mask pattern (M20) can be formed on the first spacer layer (140L). The second mask pattern (M20) includes an opening (M20H), and the opening (M20H) can be positioned so as to be vertically overlapped with a plurality of reference patterns (132) and not vertically overlapped with a surrounding pattern (134). Accordingly, a first portion (140P1) of the first spacer layer (140L) positioned on the plurality of reference patterns (132) can be exposed without being covered by the second mask pattern (M20), and a second portion (140P2) of the first spacer layer (140L) positioned on the surrounding pattern (134) can be covered by the second mask pattern (M20).

[0026] Referring to FIGS. 4a and 4b, an etch-back process can be performed on a first portion (140P1) of a first spacer layer (140L) that is not covered by a second mask pattern (M20) to form a plurality of first spacers (142) on both side walls of each of a plurality of reference patterns (132).

[0027] During the above etch-back process, a portion of the first part (140P1) of the first spacer layer (140L) disposed on the upper surface of a plurality of reference patterns (132) and a portion of the first part (140P1) of the first spacer layer (140L) disposed on the upper surface of the feature layer (120) at the bottom of the reference pattern trench (132T) may be removed, and the first spacer (142) may be left on both side walls of the plurality of reference patterns (132). Additionally, during the above etch-back process, the second part (140P2) of the first spacer layer (140L), whose upper surface is covered by the second mask pattern (M20), may remain without being removed.

[0028] In exemplary embodiments, as observed in the vertical cross-section in FIG. 4b, the number of multiple first spacers (142) may be twice the number of multiple reference patterns (132). For example, one first spacer (142) may be placed on a first side wall of one reference pattern (132), one first spacer (142) may be placed on a second side wall opposite to the first side wall of the one reference pattern (132), and two first spacers (142) may be placed spaced apart from each other within one reference pattern trench (132T).

[0029] Subsequently, the second mask pattern (M20) can be removed.

[0030] Referring to FIGS. 5a and 5b, a plurality of reference patterns (132) are removed, and a plurality of first spacers (142) may remain on the upper surface of the feature layer (120).

[0031] In exemplary embodiments, the process for removing a plurality of reference patterns (132) may be an etching process using an etching selectivity. For example, when a plurality of reference patterns (132) are removed, a plurality of first spacers (142) may remain without being removed. Additionally, a second portion (140P2) of the first spacer layer (140L) disposed on the surrounding pattern (134) during the etching process may remain without being removed, and the surrounding pattern (134) may remain covered by the second portion (140P2) without being exposed to the etching atmosphere.

[0032] A plurality of first spacers (142) each have a second width (W12) in the first direction (X) and can be spaced apart from each other by a second spacing (D12) in the first direction (X). For example, a plurality of first spacers (142) can be arranged with a second pitch (P12), and when the target feature size of a plurality of feature patterns (122) is 1F, the second pitch (P12) can correspond to 4F. In exemplary embodiments, the second width (W12) of each of the plurality of first spacers (142) can correspond to 1F, and the second spacing (D12) can correspond to 3F.

[0033] The space between each of the plurality of first spacers (142) can be referred to as the first spacer trench (142T), and the upper surface of the feature layer (120) can be exposed at the bottom of the first spacer trench (142T).

[0034] Meanwhile, although the process of etching back the first spacer layer (140L) and the process of removing a plurality of reference patterns (132) are described as being performed sequentially in FIGS. 4a to 5b as an example, the technical concept of the present invention is not limited thereto. In other embodiments, the process of etching back the first spacer layer (140L) and the process of removing a plurality of reference patterns (132) may be performed simultaneously.

[0035] Referring to FIGS. 6a and 6b, a second spacer layer (150L) can be formed on a feature layer (120) to conformally cover a plurality of first spacers (142).

[0036] The second spacer layer (150L) may include a first portion (150P1) disposed on both side walls of the first spacer (142) and a second portion (150P2) disposed on a second portion (140P2) on the surrounding pattern (134).

[0037] The second spacer layer (150L) can be formed using the first material, for example, the first material may include polysilicon or amorphous silicon. For example, the second spacer layer (150L) may be formed using the same material as the first material or a material having similar etching characteristics as the material included in the plurality of reference patterns (132) (see FIG. 4b) and surrounding patterns (134). In some embodiments, the plurality of reference patterns (132) and surrounding patterns (134) may include polysilicon and the second spacer layer (150L) may include polysilicon. In some other embodiments, the plurality of reference patterns (132) and surrounding patterns (134) may include polysilicon and the second spacer layer (150L) may include amorphous silicon.

[0038] Referring to FIGS. 7a and 7b, a plurality of second spacers (152) can be formed on both side walls of each of the plurality of first spacers (142) by performing an etch-back process on the second spacer layer (150L).

[0039] During the above etch-back process, a portion of the first part (150P1) of the second spacer layer (150L) disposed on the upper surface of a plurality of first spacers (142) and a portion of the first part (150P1) of the second spacer layer (150L) disposed on the upper surface of the feature layer (120) at the bottom of the first spacer trench (142T) may be removed, and the second spacers (152) may be left on both side walls of the plurality of first spacers (142).

[0040] In exemplary embodiments, during the etch-back process, a portion of the second part (150P2) of the second spacer layer (150L) placed on the upper surface of the surrounding pattern (134) may be removed together, and the second part (140P2) of the first spacer layer (140L) placed on the upper surface of the surrounding pattern (134) may be exposed.

[0041] In the above etch-back process, a second portion (140P2) of the first spacer layer (140L) is placed on the side wall of the surrounding pattern (134), and a portion of the second portion (150P2) of the second spacer layer (150L) may remain on the side wall of the second portion (140P2). Here, the portion of the second portion (150P2) of the second spacer layer (150L) placed on the side wall of the surrounding pattern (134) is referred to as the edge spacer pattern (154).

[0042] In exemplary embodiments, as shown in FIG. 7b, the upper surface of the edge spacer pattern (154) may be positioned at a higher level than the upper surface of the plurality of second spacers (152), but is not limited thereto. Additionally, the upper surface of the plurality of second spacers (152) may be positioned at a lower level than the upper surface of the plurality of first spacers (142).

[0043] In exemplary embodiments, as observed in the vertical cross-section in FIG. 7b, the number of multiple second spacers (152) may be twice the number of multiple first spacers (142). For example, one second spacer (152) may be placed on a first side wall of one first spacer (142), and one second spacer (152) may be placed on a second side wall opposite to the first side wall of the one first spacer (142), and two second spacers (152) may be placed spaced apart from each other within one first spacer trench (142T).

[0044] A plurality of second spacers (152) each have a third width (W13) in the first direction (X) and can be spaced apart from each other by a third spacing (D13) in the first direction (X). For example, a plurality of second spacers (152) can be arranged with a third pitch (P13), and when the target feature size of a plurality of feature patterns (122) is 1F, the third pitch (P13) can correspond to 2F. In exemplary embodiments, the third width (W13) of each of the plurality of second spacers (152) can correspond to 1F, and the third spacing (D13) can correspond to 1F.

[0045] Afterwards, a gap-fill insulating layer (160) can be formed that covers the feature layer (120), a plurality of first spacers (142), and a plurality of second spacers (152) and fills the first spacer trench (142T).

[0046] The gap-fill insulating layer (160) may be formed using a second material, and the second material may include silicon oxide, silicon nitride, silicon oxynitride, or spin-on hardmask (SOH). For example, the gap-fill insulating layer (160) may be formed using the same material as the material included in the plurality of first spacers (142), or a material of the same type having similar etching characteristics. In some embodiments, the plurality of first spacers (142) may include silicon oxide and the gap-fill insulating layer (160) may include silicon oxide. In some other embodiments, the plurality of first spacers (142) may include silicon oxide and the gap-fill insulating layer (160) may include SOH.

[0047] In exemplary embodiments, the gap-fill insulating layer (160) may be formed such that the upper surface level of the portion of the gap-fill insulating layer (160) disposed on the peripheral pattern (134) and the second portion (140P2) of the first spacer layer (140L) is higher than the upper surface level of the portion of the gap-fill insulating layer (160) disposed on the upper surfaces of the plurality of first spacers (142) and the plurality of second spacers (152).

[0048] Referring to FIG. 8, a flattening process can be performed on the upper side of the gap-fill insulating layer (160). By the flattening process, the difference between the upper surface level of the gap-fill insulating layer (160) placed on the second part (140P2) of the first spacer layer (140L) and the upper surface level of the gap-fill insulating layer (160) placed on a plurality of second spacers (152) can be reduced.

[0049] In some embodiments, as illustrated in FIG. 8, the flattening process may be performed until the gap-fill insulating layer (160) remains on the second portion (140P2) of the first spacer layer (140L) with a predetermined thickness. In other embodiments, unlike illustrated in FIG. 8, the flattening process may be performed until the entire portion of the gap-fill insulating layer (160) disposed on the second portion (140P2) of the first spacer layer (140L) is removed and the upper surface of the second portion (140P2) of the first spacer layer (140L) is exposed. In this case, the gap-fill insulating layer (160) may only fill the space between the plurality of second spacers (152).

[0050] Referring to FIGS. 9a and 9b, a plurality of first spacers (142) and a gap-fill insulating layer (160) can be removed to leave a plurality of second spacers (152) and a surrounding pattern (134) on the feature layer (120).

[0051] In exemplary embodiments, a plurality of first spacers (142) and a gap-fill insulating layer (160) may be formed using the same second material or a homogeneous material having similar etching characteristics, and accordingly, the process of removing the plurality of first spacers (142) and the gap-fill insulating layer (160) may be performed in an etching step using the same etching recipe.

[0052] In exemplary embodiments, a process for removing a plurality of first spacers (142) and a gap-fill insulating layer (160) may be performed in an etching atmosphere having an etching selectivity ratio for a plurality of second spacers (152) and a surrounding pattern (134). In the etching process for removing a plurality of first spacers (142) and a gap-fill insulating layer (160), a plurality of second spacers (152) and a surrounding pattern (134) may remain without being removed. Additionally, a second portion (140P2) of the first spacer layer (140L) disposed on the sidewall of the surrounding pattern (134) may be removed, and only the second portion (140P2) of the first spacer layer (140L) disposed below the edge spacer pattern (154) may remain.

[0053] Afterwards, a plurality of second spacers (152) and a surrounding pattern (134) can be used as etching masks to etch the feature layer (120) and form a plurality of feature patterns (122) and a bulk pattern (124).

[0054] A plurality of feature patterns (122) may be formed at positions corresponding to a plurality of second spacers (152), and a bulk pattern (124) may be formed at positions corresponding to a surrounding pattern (134). An edge pattern (122E) may be formed at a position corresponding to an edge spacer pattern (154).

[0055] For example, a plurality of feature patterns (122) may each have a fourth width (W2) in the first direction (X) and may be spaced apart from each other by a fourth interval (D2) in the first direction (X). For example, a plurality of feature patterns (122) may be arranged by a fourth pitch (P2), and when the target feature size of the plurality of feature patterns (122) is 1F, the fourth pitch (P2) may correspond to 2F. In exemplary embodiments, the fourth width (W2) of each of the plurality of feature patterns (122) may correspond to 1F, and the fourth interval (D2) may correspond to 1F.

[0056] Referring to FIG. 10a and FIG. 10b, if necessary, a plurality of second spacers (152), peripheral patterns (134), and edge spacer patterns (154) can be removed and a plurality of feature patterns (122) and bulk patterns (124) can be left.

[0057] According to the method for manufacturing a semiconductor device according to exemplary embodiments, a plurality of feature patterns (122) having a fine pitch can be formed by a quadruple patterning technique using a simple stack configuration.

[0058] Generally, in quadruple patterning technology, a double patterning process is performed twice using a stack configuration having a relatively large height that includes multiple sacrificial layers for pattern transfer. Specifically, a first spacer having a pitch of 4F is formed on the sidewall of a reference pattern having a pitch of 8F, a first sacrificial pattern is formed on a first sacrificial layer disposed below the first spacer, a second spacer having a pitch of 2F is formed on the sidewall of the first sacrificial pattern, a second sacrificial pattern is formed on a second sacrificial layer disposed below the second spacer, and multiple feature patterns are formed using the second sacrificial pattern. However, in the process of etching the carbon-based material used as the first sacrificial layer, a tail portion or a slope portion is prone to be formed on the sidewall of the first sacrificial pattern, and also, in the process of etching the polysilicon-based material used as the second sacrificial layer, process defects are prone to occur.

[0059] However, according to the technical concept of the present invention, a first spacer (142) is formed on both side walls of a plurality of reference patterns (132), and then the plurality of reference patterns (132) are removed. A second spacer (152) is formed on both side walls of the first spacer (142) using a material identical or of the same type as the reference pattern (132), and then the first spacer (142) is removed. A feature layer (120) is patterned using the second spacer (152). Since the plurality of reference patterns (132) and the second spacer (152) contain the same material, only the pattern formation area can be patterned with a fine pitch while the surrounding area of ​​the plurality of reference patterns (132) (e.g., surrounding pattern (134)) is covered. Therefore, pattern transfer processes using the first sacrificial layer and the second sacrificial layer can be omitted, and process defects caused by these first and second sacrificial layers can be prevented. Therefore, according to the manufacturing method of the semiconductor device above, the patterning process of a fine pattern can be precisely controlled.

[0060] FIGS. 11a to 13 are schematic diagrams illustrating a method for manufacturing a semiconductor device (200) according to exemplary embodiments. FIGS. 11a, 12a, and 13 are plan views illustrating the method for manufacturing a semiconductor device (200) in the order of process, and FIGS. 11b and 12b are cross-sectional views along the line BB' of FIGS. 11a and 12a.

[0061] Referring to FIGS. 11a and FIGS. 11b, a plurality of feature patterns (222) and bulk patterns (224) are formed on a substrate (210) by performing the process described with reference to FIGS. 1a to FIGS. 10.

[0062] The substrate (210) may include a cell array region (MCA) and a boundary region (BA), and a plurality of feature patterns (222) are extended along a first diagonal direction (D1) in the cell array region (MCA), and a bulk pattern (224) may be disposed in the boundary region (BA).

[0063] In exemplary embodiments, the cell array region (MCA) is a region where unit memory cells of a DRAM device are formed, and the boundary region (BA) may be a region where peripheral circuits for driving unit memory cells formed in the cell array region (MCA) are formed.

[0064] In exemplary embodiments, a plurality of feature patterns (222) may be formed using silicon oxide. A plurality of feature patterns (222) may include a plurality of line patterns extending along a first diagonal direction (D1), and a bulk pattern (224) may be connected to the ends of the plurality of feature patterns (222) and surround the plurality of feature patterns (222) in a plan view.

[0065] A plurality of feature patterns (222) may include a plurality of sets of line patterns, and one set of the line patterns may consist of a first line pattern (LP1), a second line pattern (LP2), a third line pattern (LP3), and a fourth line pattern (LP4) arranged in succession.

[0066] For example, the extension of the second line pattern (LP2) extending to the boundary region (BA) and the extension of the third line pattern (LP3) can be connected to each other, and the part where the extension of the second line pattern (LP2) and the extension of the third line pattern (LP3) are connected can be referred to as the extension edge pattern (LPE). The extension edge pattern (LPE) can correspond to an edge pattern (122E) formed using the edge spacer pattern (154) described with reference to FIGS. 9a and 9b as an etching mask.

[0067] In addition, the length of the extension of the second line pattern (LP2) and the length of the extension of the third line pattern (LP3) may be greater than the length of the extension of the fourth line pattern (LP4) and the length of the extension of the first line pattern (LP1).

[0068] Multiple sets of trenches may be placed between each of the line patterns of multiple sets of multiple feature patterns (222). One set of trenches may include a first trench (FT1), a second trench (FT2), a third trench (FT3), and a fourth trench (FT4) that are placed consecutively. For example, the first trench (FT1) may be placed between the first line pattern (LP1) and the second line pattern (LP2), the second trench (FT2) may be placed between the second line pattern (LP2) and the third line pattern (LP3), the third trench (FT3) may be placed between the third line pattern (LP3) and the fourth line pattern (LP4), and the fourth trench (FT4) may be placed between the fourth line pattern (LP4) and the first line pattern (LP1).

[0069] For example, the extension of the first trench (FT1) extending into the boundary area (BA) and the extension of the third trench (FT3) can be connected to each other. For example, the extension of the first trench (FT1) and the extension of the third trench (FT3) can be connected to each other in a planar manner, surrounding the extension of the second trench (FT2). The extension of the fourth trench (FT4) is surrounded by a bulk pattern (224) and is not connected to other trenches.

[0070] Referring to FIGS. 12a and 12b, a mask pattern (not shown) is formed on a plurality of feature patterns (222) and a bulk pattern (224), and a portion of the plurality of feature patterns (222) is removed to form a plurality of active area patterns (ACP). The plurality of active area patterns (ACP) may have a plurality of island shapes having a major axis in the first diagonal direction (D1).

[0071] Subsequently, a portion of the substrate (210) is removed using a plurality of active region patterns (ACP) and a bulk pattern (224) as an etching mask to form a device isolation trench (230T), and a device isolation film (230) can be formed using an insulating material within the device isolation trench (230T). A plurality of active regions (AC) can be defined by the device isolation film (230).

[0072] A portion of the device isolation trench (230T) in the boundary region (BA) may have a shape in which a first extension (TE1), a second extension (TE2), a third extension (TE3), and a fourth extension (TE4) are repeatedly arranged. For example, the first extension (TE1) and the third extension (TE3) may be connected to each other. Additionally, the connecting portion of the first extension (TE1) and the third extension (TE3) may planarly surround the second extension (TE2). The first extension (TE1) and the third extension (TE3) may have a longer length than the second extension (TE2). The first extension (TE1) and the third extension (TE3) may have a longer length than the fourth extension (TE4).

[0073] Meanwhile, a portion of the substrate (210) corresponding to the extension edge pattern (LPE) may be referred to as a boundary edge pattern (210E). The boundary edge pattern (210E) is surrounded by a device isolation film (230) and may have a U-shaped horizontal cross-section in a plan view.

[0074] Referring to FIG. 13, a word line trench (not shown) extending in a first direction (X) can be formed inside a substrate (210), and a word line (WL) including a plurality of gate dielectric films (not shown) and a plurality of gate electrodes (not shown) can be formed within the word line trench.

[0075] Subsequently, a direct contact (not shown) connected to an active region (AC) on the substrate (210) and a bit line (BL) connected to the direct contact and extending in a second direction (Y) can be formed. Between each bit line (BL), a contact (not shown) connected to an active region (AC) can be formed, and a storage node (not shown) can be formed on the contact.

[0076] According to exemplary embodiments, an active region (AC) having a fine pitch can be formed using the method described with reference to FIGS. 1a through 10b, and thus the patterning process of the active region (AC) can be precisely controlled. The semiconductor device (200) can have excellent electrical characteristics.

[0077] Meanwhile, FIGS. 11a to 13 describe, by way of example, a method for manufacturing a DRAM device using the method described with reference to FIGS. 1a to 10b, but the technical concept of the present invention is not limited thereto. In addition to the method for manufacturing a DRAM device, the method for manufacturing a semiconductor device according to the present invention may include a method for manufacturing various devices such as a logic device, a flash memory device, a vertical NAND memory device, a phase change memory device, a magnetic memory device, and a CMOS image sensor using the method described with reference to FIGS. 1a to 10b.

[0078] FIGS. 14a to 19b are schematic diagrams illustrating a method of manufacturing a semiconductor device (300) according to exemplary embodiments. FIGS. 14a and FIGS. 19a are plan views shown in the order of process, and FIGS. 14b, 15 to 18, and 19b are cross-sectional views along the CC' line of FIG. 14a.

[0079] Referring to FIGS. 14a and FIGS. 14b, a feature layer (320) is formed on a substrate (310) including a cell array region (MCA) and a boundary region (BA).

[0080] A reference pattern layer (not shown) may be formed on a feature layer (320), and the reference pattern layer may be patterned to form a plurality of reference patterns (332) in a cell array region (MCA) and an alignment key reference pattern (334) in a boundary region (BA). The plurality of reference patterns (332) and the alignment key reference pattern (334) may be formed using a first material, and the first material may include polysilicon or amorphous silicon.

[0081] Referring to FIG. 15, a first spacer layer (340L) covering a plurality of reference patterns (332) and an alignment key reference pattern (334) is formed on a feature layer (320), and a mask pattern (not shown) covering the alignment key reference pattern (334) is formed on the first spacer layer (340L).

[0082] Subsequently, an etch-back process may be performed on the upper part of the first spacer layer (340L) that is not covered by the mask pattern to form a plurality of first spacers (342) on both side walls of a plurality of reference patterns (332). The plurality of first spacers (342) may be formed using a second material, and the second material may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0083] Meanwhile, the first spacer layer (340L) covering the upper surface and side wall of the alignment key reference pattern (334) may remain without being removed during the etch-back process.

[0084] Referring to FIG. 16, a plurality of reference patterns (332) are removed, and a plurality of first spacers (342) are left on the cell array area (MCA).

[0085] In exemplary embodiments, the process of removing a plurality of reference patterns (332) is an etching process using an etching selectivity, wherein the first spacer layer (340L) in the boundary region (BA) may be etched in a small amount or remain almost unetched, and the upper surface of the alignment key reference pattern (334) may not be exposed.

[0086] Referring to FIG. 17, a plurality of first spacers (342) and a second spacer layer (not shown) covering the first spacer layer (340L) are formed on the feature layer (320), and an etch-back process is performed on the second spacer layer to form a plurality of second spacers (352) on both side walls of the plurality of first spacers (342).

[0087] At this time, a portion of the second spacer layer may remain on the side wall of the alignment key reference pattern (334), and said portion is referred to as the edge spacer pattern (354).

[0088] In exemplary embodiments, the second spacer (352) may be formed using the first material, and the first material may include polysilicon or amorphous silicon. For example, the second spacer (352) may be formed using the same material as the first material included in the plurality of reference patterns (332) and the alignment key reference pattern (334), or a material of the same type having similar etching characteristics.

[0089] Subsequently, a gap-fill insulating layer (360) can be formed on the feature layer (320) to fill the space between a plurality of second spacers (352). The gap-fill insulating layer (360) may be formed using a second material, and the second material may include silicon oxide, silicon nitride, silicon oxynitride, or spin-on hardmask (SOH). For example, the gap-fill insulating layer (360) may be formed using the same material as the material included in the plurality of first spacers (342), or a material of the same type having similar etching characteristics. In some embodiments, the plurality of first spacers (342) may include silicon oxide and the gap-fill insulating layer (360) may include silicon oxide. In other embodiments, the plurality of first spacers (342) may include silicon oxide and the gap-fill insulating layer (360) may include SOH.

[0090] Optionally, a flattening process may be performed on the upper side of the gap-fill insulation layer (360).

[0091] Referring to FIG. 18, a plurality of first spacers (342) and a gap-fill insulating layer (360) can be removed to leave a plurality of second spacers (352), an edge spacer pattern (354), and an alignment key reference pattern (334) on the feature layer (320).

[0092] In exemplary embodiments, a plurality of first spacers (342) and a gap-fill insulating layer (360) may be formed using the same second material or a homogeneous material having similar etching characteristics, and accordingly, the process of removing the plurality of first spacers (342) and the gap-fill insulating layer (360) may be performed in an etching step using the same etching recipe. The process for removing the plurality of first spacers (342) and the gap-fill insulating layer (360) may be performed in an etching atmosphere having an etching selectivity ratio for a plurality of second spacers (352) and an alignment key reference pattern (334).

[0093] Referring to FIGS. 19a and 19b, a plurality of second spacers (352), edge spacer patterns (354), and alignment key reference patterns (334) can be used as etching masks to etch a feature layer (320) and form a plurality of feature patterns (322) and an alignment key pattern (AK).

[0094] A plurality of feature patterns (322) may be formed at positions corresponding to a plurality of second spacers (352), and an alignment key pattern (AK) may be formed at positions corresponding to an edge spacer pattern (354) and an alignment key reference pattern (334).

[0095] For example, a plurality of feature patterns (322) may each have a first width (W31) in a first direction (X) and may be spaced apart from each other by a first distance (D31) in a first direction (X). For example, a plurality of feature patterns (322) may be arranged by a first pitch (P3), and when the target feature size of the plurality of feature patterns (322) is 1F, the first pitch (P3) may correspond to 2F. In exemplary embodiments, the first width (W31) of each of the plurality of feature patterns (322) may correspond to 1F, and the first distance (D31) may correspond to 1F.

[0096] In exemplary embodiments, the alignment key pattern (AK) may include a main pattern (AKM) and an edge pattern (AKE). The main pattern (AKM) has a second width (W32), and the second width (W32) may be larger than the first width (W31) of a plurality of feature patterns (322).

[0097] In exemplary embodiments, the edge pattern (AKE) is positioned to surround the main pattern (AKM) in a plan view and may be positioned spaced apart from the main pattern (AKM) with a second distance (D32). For example, the second distance (D32) may be equal to the first distance (D31). The second distance (D32) may correspond to 1F. The edge pattern (AKE) has a third width (W33), the third width (W33) may be smaller than the second width (W32) and equal to the first width (W31). For example, the third width (W33) may correspond to 1F.

[0098] The edge pattern (AKE) can be formed around the main pattern (AKM) at the same height as the main pattern (AKM). For example, the main pattern (AKM) may have a first height (H31), and the edge pattern (AKE) may have a second height (H32) equal to the first height (H31).

[0099] According to exemplary embodiments, an aligned key pattern (AK) can be formed with a plurality of feature patterns (322) having fine pitch, and the patterning process of the plurality of feature patterns (322) having fine pitch can be precisely controlled.

[0100] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims. Explanation of the symbols

[0101] 120: Feature layer 132: Reference pattern 142: 1st Spacer 152: 2nd Spacer 160: Gap-fill insulation layer

Claims

Claim 1 A method for manufacturing a semiconductor device comprising: forming a plurality of reference patterns and peripheral patterns connected to the ends of the plurality of reference patterns using a first material on a feature layer; forming a plurality of first spacers using a second material on both side walls of each of the plurality of reference patterns; removing the plurality of reference patterns; forming a plurality of second spacers using the first material on both side walls of each of the plurality of first spacers; forming a gap-fill insulating layer on the feature layer that fills the space between the plurality of second spacers and contacts the feature layer; removing the plurality of first spacers and the gap-fill insulating layer so as to leave only the plurality of second spacers and the peripheral patterns on the feature layer; and patterning the feature layer using the plurality of second spacers and the peripheral patterns as an etching mask. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein the first material comprises polysilicon or amorphous silicon, and the second material comprises silicon oxide, silicon nitride, or silicon oxynitride. Claim 3 A method for manufacturing a semiconductor device according to claim 1, wherein, in a plan view, the surrounding pattern surrounds the plurality of reference patterns. Claim 4 A method for manufacturing a semiconductor device according to claim 1, wherein F is a target feature size, the plurality of reference patterns are arranged at a pitch of 8F, the plurality of first spacers are arranged at a pitch of 4F, and the plurality of second spacers are arranged at a pitch of 2F. Claim 5 A method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the plurality of first spacers comprises: forming a first spacer layer on the feature layer to cover the plurality of reference patterns and the surrounding pattern; forming a mask pattern on the first spacer layer to cover a second portion of the first spacer layer placed on the surrounding pattern without covering a first portion of the first spacer layer placed on the plurality of reference patterns; and removing portions of the first portion of the first spacer layer placed on the upper surface of the plurality of reference patterns to leave the plurality of first spacers on both side walls of the plurality of reference patterns. Claim 6 A method for manufacturing a semiconductor device according to claim 5, wherein, in the step of removing the plurality of reference patterns, the second portion of the first spacer layer remains to cover the upper surface of the surrounding pattern. Claim 7 delete Claim 8 A method for manufacturing a semiconductor device according to claim 5, further comprising the step of performing a planarization process on the upper surface of the gap-fill insulating layer after the step of forming the gap-fill insulating layer, such that the difference between the upper surface level of the gap-fill insulating layer disposed on the second portion of the first spacer layer and the upper surface level of the gap-fill insulating layer disposed on the plurality of second spacers is reduced. Claim 9 A method for manufacturing a semiconductor device according to claim 5, wherein the gap-fill insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, or spin-on hard mask (SOH). Claim 10 A method for manufacturing a semiconductor device comprising: forming a plurality of reference patterns and peripheral patterns connected to the ends of the plurality of reference patterns on a feature layer; forming a plurality of first spacers on both side walls of each of the plurality of reference patterns; removing the plurality of reference patterns; forming a plurality of second spacers on both side walls of each of the plurality of first spacers; forming a gap-fill insulating layer on the feature layer that fills the space between the plurality of second spacers and contacts the feature layer; removing the gap-fill insulating layer and the plurality of first spacers to leave only the plurality of second spacers and the peripheral patterns on the feature layer; and patterning the feature layer using the plurality of second spacers and the peripheral patterns as an etching mask. Claim 11 A method for manufacturing a semiconductor device according to claim 10, wherein the plurality of reference patterns, the surrounding patterns, and the plurality of second spacers comprise polysilicon or amorphous silicon, and the plurality of first spacers and the gap-fill insulating layer comprise silicon oxide, silicon nitride, or silicon oxynitride. Claim 12 A method for manufacturing a semiconductor device according to claim 10, wherein the step of forming the plurality of first spacers comprises: forming a first spacer layer on the feature layer to cover the plurality of reference patterns and the surrounding pattern; forming a mask pattern on the first spacer layer to cover a second portion of the first spacer layer placed on the surrounding pattern without covering a first portion of the first spacer layer placed on the plurality of reference patterns; and removing portions of the first portion of the first spacer layer placed on the upper surface of the plurality of reference patterns to leave the plurality of first spacers on both side walls of the plurality of reference patterns. Claim 13 A method for manufacturing a semiconductor device according to claim 12, wherein, in the step of removing the plurality of reference patterns, the second portion of the first spacer layer remains to cover the upper surface of the surrounding pattern. Claim 14 A method for manufacturing a semiconductor device according to claim 12, further comprising the step of performing a planarization process on the upper surface of the gap-fill insulating layer after the step of forming the gap-fill insulating layer, such that the difference between the upper surface level of the gap-fill insulating layer disposed on the second portion of the first spacer layer and the upper surface level of the gap-fill insulating layer disposed on the plurality of second spacers is reduced. Claim 15 A method for manufacturing a semiconductor device according to claim 10, wherein, in a plan view, the surrounding pattern surrounds the plurality of reference patterns. Claim 16 A method for manufacturing a semiconductor device according to claim 10, wherein F is a target feature size, the plurality of reference patterns are arranged at a pitch of 8F, the plurality of first spacers are arranged at a pitch of 4F, and the plurality of second spacers are arranged at a pitch of 2F. Claim 17 A step of providing a substrate including a cell array region and a boundary region; a step of forming a feature layer on the substrate; a step of forming a plurality of reference patterns and a peripheral pattern on the feature layer using a first material, wherein the plurality of reference patterns are disposed on the cell array region and the peripheral pattern is connected to the ends of the plurality of reference patterns and disposed on the boundary region; a step of forming a plurality of first spacers using a second material on both sidewalls of each of the plurality of reference patterns; a step of removing the plurality of reference patterns; a step of forming a plurality of second spacers using the first material on both sidewalls of each of the plurality of first spacers; a step of forming a gap-fill insulating layer on the feature layer that fills the space between the plurality of second spacers and contacts the feature layer; a step of removing the plurality of first spacers and the gap-fill insulating layer so as to leave only the plurality of second spacers and the peripheral pattern on the feature layer; a step of patterning the feature layer using the plurality of second spacers and the peripheral pattern as an etching mask. A method for manufacturing a semiconductor device comprising the step of removing a portion of the substrate using the feature layer as an etching mask to form a device isolation trench. Claim 18 A method for manufacturing a semiconductor device according to claim 17, wherein the step of forming the plurality of first spacers comprises: forming a first spacer layer on the feature layer to cover the plurality of reference patterns and the surrounding pattern; forming a mask pattern on the first spacer layer to cover a second portion of the first spacer layer placed on the surrounding pattern without covering a first portion of the first spacer layer placed on the plurality of reference patterns; and removing portions of the first portion of the first spacer layer placed on the upper surface of the plurality of reference patterns to leave the plurality of first spacers on both side walls of the plurality of reference patterns, wherein in the step of removing the plurality of reference patterns, the second portion of the first spacer layer remains to cover the upper surface of the surrounding pattern. Claim 19 delete Claim 20 A method for manufacturing a semiconductor device according to claim 18, further comprising the step of performing a planarization process on the upper surface of the gap-fill insulating layer after the step of forming the gap-fill insulating layer, such that the difference between the upper surface level of the gap-fill insulating layer disposed on the second portion of the first spacer layer and the upper surface level of the gap-fill insulating layer disposed on the plurality of second spacers is reduced.

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