Semiconductor memory device and method of manufacturing the same

Abstract

According to exemplary embodiments, a semiconductor memory device is provided. The semiconductor memory device comprises a plurality of contact electrodes disposed on a contact region and extending in a first direction parallel to the upper surface of the substrate, wherein each of the plurality of contact electrodes comprises a connecting portion having a first thickness and a landing portion having a second thickness.

Description

Technology Field

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing the same, and specifically to a three-dimensional semiconductor memory device. Background Technology

[0002] As electronic products are required to be miniaturized, multifunctional, and high-performance, high-capacity semiconductor memory devices are needed. Since the integration density of conventional 2D semiconductor memory devices is primarily determined by the reduction in the area occupied by a unit memory cell, the improvement of the integration density of 2D semiconductor memory devices is limited by the physical limitations of the ultra-high-density semiconductor manufacturing process. Accordingly, 3D semiconductor memory devices that stack multiple memory cells vertically are attracting attention as a solution to increase integration density. The problem to be solved

[0003] The technical problem of the present invention is to provide a semiconductor memory device with improved reliability and integration density and a method for manufacturing the same. means of solving the problem

[0004] According to exemplary embodiments for achieving the above technical problem, a semiconductor memory device is provided. The semiconductor memory device comprises: a substrate including a cell array region and a contact region; a plurality of contact electrodes disposed on the contact region and extending in a first direction parallel to the upper surface of the substrate; transistor body portions disposed on the cell array region and extending along a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, wherein each of the transistor body portions includes a first source-drain region, a single crystal channel layer, and a second source-drain region disposed sequentially along the second direction; a lower electrode layer disposed on the cell array region and connected to the second source-drain region; and a capacitor dielectric film disposed on the cell array region, covering the lower electrode layer and having a uniform thickness. and includes an upper electrode layer disposed on the cell array region and spaced apart from the lower electrode layer with the capacitor dielectric film in between, wherein the single crystal channel layer of each of the transistor body portions is connected to a corresponding one of the plurality of contact electrodes, and each of the plurality of contact electrodes is longer in the first direction than those disposed above among the plurality of contact electrodes to form a step structure; and each of the plurality of contact electrodes includes a connecting portion having a first thickness and a landing portion having a second thickness.

[0005] According to exemplary embodiments, a semiconductor memory device is provided. The semiconductor memory device comprises: a substrate including a cell array region and a contact region; a plurality of memory cells disposed on the cell array region, each comprising a cell transistor and a cell capacitor, wherein the plurality of memory cells are disposed along a third direction perpendicular to the substrate; a first step structure disposed on the contact region and extending in a first direction parallel to the upper surface of the substrate; and a second step structure disposed on the contact region and extending in the first direction, and extending in a second direction perpendicular to the first direction and parallel to the upper surface of the substrate. The invention includes an interlayer insulating layer interposed between the first step structure and the second step structure, wherein each of the first step structure and the second step structure comprises a plurality of contact electrodes stacked along the third direction on the substrate and an uppermost contact electrode disposed on the plurality of contact electrodes, wherein the uppermost contact electrode comprises a first connecting portion having a first thickness and a first landing portion having a second thickness, and each of the plurality of contact electrodes comprises a second connecting portion having the first thickness and a second landing portion having the second thickness, and the first direction length of the first landing portion is different from the first direction length of the second landing portion.

[0006] According to exemplary embodiments, a method for manufacturing a semiconductor memory is provided. The method comprises the steps of: forming a plurality of compound semiconductor layers and a plurality of single crystal semiconductor layers on a substrate, wherein the plurality of compound semiconductor layers and the plurality of single crystal semiconductor layers are alternately stacked; forming a plurality of compound semiconductor patterns extending in a first direction parallel to the upper surface of the substrate by etching the plurality of compound semiconductor layers and forming a plurality of single crystal semiconductor patterns extending in the first direction by etching the plurality of single crystal semiconductor layers, wherein the plurality of single crystal semiconductor patterns constitute a first and a second mold, and the first mold and the second mold are spaced apart from each other along a second direction parallel to the upper surface of the substrate and perpendicular to the first direction; removing the plurality of compound semiconductor patterns; isotropically etching the plurality of single crystal semiconductor patterns; forming an interlayer insulating layer that fills the space between the first mold and the second mold and surrounds the plurality of single crystal semiconductor patterns; and etching the interlayer insulating layer with a high etch selectivity for the plurality of single crystal semiconductor patterns. and includes the step of etching at least one of the single-crystal semiconductor patterns. Effects of the invention

[0007] When forming contact electrodes of the semiconductor memory device of the present invention, the silicon single crystal pattern and the oxide layer can be etched by different etching processes. Accordingly, profile deformation occurring during the etching process of different materials can be prevented.

[0008] Furthermore, by increasing the thickness of the landing portion of the contact electrodes, device defects caused by punch-through can be prevented.

[0009] The effects obtainable from the exemplary embodiments of the present invention are not limited to those mentioned above, and other unmentioned effects can be clearly derived and understood by those skilled in the art to which the exemplary embodiments of the present disclosure belong from the following description. That is, unintended effects resulting from the implementation of the exemplary embodiments of the present disclosure can also be derived by those skilled in the art from the exemplary embodiments of the present disclosure. Brief explanation of the drawing

[0010] FIG. 1 is an equivalent circuit diagram showing a cell array of a semiconductor memory device according to exemplary embodiments. FIG. 2a is a plan view for illustrating a semiconductor memory device according to exemplary embodiments. FIG. 2b is a cross-sectional view taken along the cutting line I-I' of FIG. 2a. FIG. 2c is a cross-sectional view taken along the cutting line II-II' of FIG. 2a. FIG. 2d is a cross-sectional view taken along the cutting line III-III' of FIG. 2a. FIG. 3 is a flowchart for explaining a method for manufacturing a semiconductor memory device according to exemplary embodiments. FIGS. 4a to 17b are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to exemplary embodiments. Specific details for implementing the invention

[0011] Hereinafter, exemplary embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings.

[0012] FIG. 1 is a circuit diagram showing a semiconductor memory device (10) according to exemplary embodiments.

[0013] Referring to FIG. 1, a semiconductor memory device (10) may include a plurality of memory cells (MC). Each of the plurality of memory cells (MC) may include a cell transistor (TR) and cell capacitors (CAP). The cell transistor (TR) and the cell capacitors (CAP) may be connected to each other. For example, either the source electrode or the drain electrode of the cell transistor (TR) may be connected to the lower electrode of each of the cell capacitors (CAP).

[0014] A plurality of memory cells (MC) may form a plurality of sub-cell arrays (SCA). According to exemplary embodiments, the plurality of sub-cell arrays (SCA) may be arranged along the X direction. The X direction may be the extension direction of a plurality of word lines (WL).

[0015] A plurality of sub-cell arrays (SCA) may include a plurality of memory cells (MC). The plurality of memory cells (MC) included in the plurality of sub-cell arrays (SCA) may be spaced apart in the Y direction and the Z direction, respectively.

[0016] The Y direction may be the extension direction of multiple bit line straps (BLS). The Z direction may be the extension direction of multiple bit lines (BL). The Y direction may be substantially perpendicular to the X direction. The Z direction may be substantially perpendicular to both the X direction and the Y direction. Alternatively, the X direction may be referred to as the first direction, the Y direction may be referred to as the second direction, and the Z direction may be referred to as the third direction.

[0017] Among the memory cells (MC) included in one of the plurality of the sub cell arrays (SCA), those placed at the same level in the Z direction may share, for example, the upper electrode (PE) of a capacitor (CAP) and may be spaced apart in the Y direction.

[0018] Multiple word lines (WL) can be arranged along the Y direction and the Z direction. Multiple bit lines (BL) can be arranged along the X direction and the Y direction. Multiple bit line straps (BLS) can be arranged along the X direction.

[0019] Multiple bit lines (BL) can be connected to bit line straps (BLS). Each of the multiple bit line straps (BLS) can be connected to multiple bit lines (BL) arranged along the Y direction. For example, two bit lines (BL) connected to one of the multiple sub-cell arrays (SCA) can be connected to a corresponding bit line strap (BLS).

[0020] Multiple cell capacitors (CAP) may share an upper electrode (PE) extending in the X and Z directions. That is, the upper electrode (PE) may be a common electrode of multiple cell capacitors (CAP) arranged along the Z and X directions. For convenience of illustration, the upper electrode (PE) is depicted as extending in the Z direction, and the upper electrodes (PE) depicted as being arranged along the X direction represent a portion of a single upper electrode (PE).

[0021] FIG. 2a is a plan view for illustrating a semiconductor memory device (10) according to exemplary embodiments.

[0022] FIG. 2b is a cross-sectional view taken along the cutting line I-I' of FIG. 2a.

[0023] FIG. 2c is a cross-sectional view taken along the cutting line II-II' of FIG. 2a.

[0024] FIG. 2d is a cross-sectional view taken along the cutting line III-III' of FIG. 2a.

[0025] Referring to FIGS. 2a to 2d, the semiconductor memory device (10) may include a substrate (101), a plurality of cell transistors (CTR) and a plurality of cell capacitors (CAP) disposed on the substrate (101).

[0026] The substrate (101) may include Si, Ge, or SiGe. Alternatively, for example, the substrate (101) may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0027] The substrate (101) may have an upper surface extending in the X direction and the Y direction. The upper surface of the substrate (101) may be perpendicular to the Z direction. The substrate (101) may include a contact area (CNTR) that provides wiring for the aforementioned cell array area (CAR), a plurality of cell transistors (CTR), and a plurality of cell capacitors (CAP).

[0028] A peripheral circuit (not shown) and a wiring layer (not shown) connected to the peripheral circuit may be formed on a substrate (101). For example, the peripheral circuit may include a planar MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that constitutes a subword line driver, a sense amplifier, etc., but is not limited thereto. A lower insulating layer (not shown) disposed to cover the peripheral circuit and the wiring layer may be formed on the substrate (101).

[0029] The substrate (101) may include a cell array region (CAR) and a contact region (CNTR). A plurality of cell transistors (CTR) may be disposed on the cell array region (CAR), and contact electrodes (124, 124U) and conductive contacts (140) may be disposed on the contact region (CNTR).

[0030] A compound semiconductor layer (110) may be disposed on a substrate (101). A lower single-crystal semiconductor pattern (125) may be disposed on the compound semiconductor layer (110). The lower single-crystal semiconductor pattern (125) may be spaced apart from the substrate (101) with the compound semiconductor layer (110) in between. The compound semiconductor layer (110) and the lower single-crystal semiconductor pattern (125) may extend in the cell array region (CAR) and the contact region (CNTR), respectively.

[0031] Each of the plurality of cell transistors (CTR) may include a transistor body (220), word lines (230), a gate insulating layer (240), and a bit line (250), and the plurality of cell capacitors (CAP) may include a first electrode (EL1), a second electrode (EL2), and a capacitor dielectric layer (DL).

[0032] A plurality of transistor bodies (220) may be disposed on a substrate (101). A plurality of transistor bodies (220) may be extended along the Y direction. A plurality of transistor bodies (220) may be spaced apart in the Z direction.

[0033] A plurality of transistor bodies (220) may include an undoped semiconductor material or a doped semiconductor material. For example, a plurality of transistor bodies (220) may include polysilicon.

[0034] The plurality of transistor bodies (220) may include amorphous metal oxide, polycrystalline metal oxide, or a combination of amorphous metal oxide and polycrystalline metal oxide. For example, the plurality of transistor bodies (220) may include at least one of an In-Ga-based oxide (IGO), an In-Zn-based oxide (IZO), or an In-Ga-Zn-based oxide (IGZO).

[0035] Each of the plurality of transistor bodies (220) may include a first source / drain region (222), a single crystal channel layer (224), and a second source / drain region (226). The first source / drain region (222) may be connected to a bit line (250), and the second source / drain region (226) may be connected to a first electrode (EL1) of cell capacitors (CAP).

[0036] A single-crystal channel layer (224) may be interposed between a first source / drain region (222) and a second source / drain region (226). The single-crystal channel layer (224) may be connected to each of the first source / drain region (222) and the second source / drain region (226). The first source / drain region (222) and the second source / drain region (226) may comprise a semiconductor material doped with high concentrations of n-type dopants.

[0037] A plurality of word lines (230) may be arranged adjacent to a plurality of transistor bodies (220). Each of the plurality of word lines (230) may extend in the X direction. According to exemplary embodiments, the semiconductor memory device (10) may include a dual-gate transistor structure. According to exemplary embodiments, each of the plurality of word lines (230) may be arranged on the upper and lower surfaces of the plurality of transistor bodies (220). Each of the plurality of word lines (230) may be spaced apart from the plurality of transistor bodies (220). Each of the plurality of transistor bodies (220) may be interposed between the plurality of word lines (230).

[0038] In exemplary embodiments, a plurality of word lines (230) may include at least one of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0039] A plurality of spacers (232) may be interposed between a plurality of bit lines (250) and a plurality of word lines (230). A plurality of spacers (232) may be placed at the same vertical level (e.g., Z-direction level) as the plurality of word lines (230). A first side wall of a plurality of spacers (232) may be in contact with any one of the plurality of bit lines (250). A second side wall of a plurality of spacers (232) may be in contact with the plurality of word lines (230).

[0040] The spacer closest to the substrate (101) among the plurality of spacers (232) is defined as the lower spacer (232L). The lower spacer (232L) may have the largest thickness (i.e., length in the Z direction) among the plurality of spacers (232). The plurality of spacers (232) and the lower spacer (232L) may include silicon nitride, silicon oxynitride, or silicon oxide.

[0041] A gate insulating layer (240) may be interposed between a plurality of word lines (230) and a transistor body (220). The gate insulating layer (240) may have a uniform thickness and thus may have a conformal structure. The gate insulating layer (240) may cover the top surface, bottom surface, and side surface of each of the plurality of word lines (230).

[0042] In exemplary embodiments, the gate insulating layer (240) may comprise at least one selected from a high-k dielectric material and a ferroelectric material having a dielectric constant higher than that of silicon oxide. For example, the gate insulating layer (240) may comprise at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxide nitride (HfON), hafnium silicon oxide nitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxide nitride (ZrON), zirconium silicon oxide nitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).

[0043] A spacer filling layer (262) may be disposed between a plurality of transistor bodies (220). The spacer filling layer (262) may be disposed at the same vertical level (e.g., Z-direction level) from a plurality of word lines (230) and the substrate (101). A spacer liner (264) may be disposed on the upper surface and the lower surface of the spacer filling layer (262).

[0044] The separation insulation layer (266) may be placed between the spacer filling layer (262) and the spacer filling layer (262) and between two adjacent word lines (230). For example, a gate insulation layer (240) may be interposed between the separation insulation layer (266) and the word lines (230), and a spacer liner (264) may be interposed between the separation insulation layer (266) and the spacer filling layer (262).

[0045] Each of the plurality of bit lines (250) may extend in the Z direction on the substrate (101). The plurality of bit lines (250) may be arranged along the X direction and the Y direction. The plurality of bit lines (250) may include at least one of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0046] A bit line insulating layer (252) extending in the Z direction may be disposed around each of the multiple bit lines (250). The bottom surface of the bit line insulating layer (252) may be in contact with the top surface of the lower spacer (232L).

[0047] Cell capacitors (CAP) may include a first electrode (EL1), a second electrode (EL2), and a capacitor dielectric layer (DL). The first electrode (EL1) may be connected to a second source / drain region (226). The first electrode (EL1) may have a cup shape having a side surface parallel to the Y direction and a bottom surface perpendicular to the Y direction. For example, as shown in FIG. 4, the first electrode (EL1) may have a horizontal cross-section in the shape of a U rotated 90 degrees.

[0048] The capacitor dielectric layer (DL) can cover the surface of the first electrode (EL1). The capacitor dielectric layer (DL) can have a uniform thickness. Accordingly, the capacitor dielectric layer (DL) can have a conformal shape. The second electrode (EL2) can be spaced apart from the first electrode (EL1) with the capacitor dielectric layer (DL) in between.

[0049] In exemplary embodiments, the first electrode (EL1) and the second electrode (EL2) may comprise a doped semiconductor material, a conductive metal nitride such as titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, a metal such as ruthenium, iridium, titanium or tantalum, or a conductive metal oxide such as iridium oxide or niobium oxide.

[0050] A plurality of contact electrodes (124, 124U) may be disposed on a contact region (CNTR). A plurality of contact electrodes (124, 124U) may be disposed on a lower single-crystal semiconductor layer (125). A plurality of contact electrodes (124, 124U) may be stacked along the Z direction.

[0051] The lower single-crystal semiconductor layer (125) may include a semiconductor material. The lower single-crystal semiconductor layer (125) may include a compound semiconductor material such as Si, for example.

[0052] A plurality of contact electrodes (124, 124U) may include a conductive material. The plurality of contact electrodes (124, 124U) may include any one of a doped semiconductor material such as doped silicon and doped germanium, a conductive metal nitride such as titanium nitride and tantalum nitride, a metal such as tungsten, titanium and tantalum, and a metal-semiconductor compound such as tungsten silicide, cobalt silicide, titanium silicide, etc.

[0053] The uppermost contact electrode (124U) may be positioned at the top of the plurality of contact electrodes (124, 124U). The uppermost contact electrode (124U) may be the furthest from the substrate (101) among the plurality of contact electrodes (124, 124U). The contact electrodes (124) may be interposed between the uppermost contact electrode (124U) and the lower single-crystal semiconductor layer (125).

[0054] A dummy electrode (124D) may be further disposed on the uppermost contact electrode (124U). Stopper patterns (133) covering the upper surface of the dummy electrode (124D) may be disposed on the dummy electrode (124D).

[0055] According to exemplary embodiments, a plurality of contact electrodes (124, 124U) may have a predetermined width in the Y direction and extend in the X direction. A plurality of contact electrodes (124, 124U) may extend over a contact region (CNTR) and a cell array region (CAR). Each of the plurality of contact electrodes (124B, 124, 124U) may be connected to a single crystal channel layer (224).

[0056] According to exemplary embodiments, the X direction of each of the plurality of contact electrodes (124, 124U) may differ from one another. For example, each of the plurality of contact electrodes (124, 124U) may protrude further in the X direction than the one positioned above the plurality of contact electrodes (124, 124U).

[0057] Each of the plurality of contact electrodes (124, 124U) can provide a region for landing the conductive contacts (140). For example, each of the contact electrodes (124) can protrude further in the X direction relative to the uppermost contact electrode (124U). Accordingly, the plurality of contact electrodes (124, 124U) can form first and second step structures (ST1, ST2).

[0058] The first and second step structures (ST1, ST2) can be insulated by an interlayer insulating layer (122). The first and second step structures (ST1, ST2) can be spaced apart in the Y direction with the interlayer insulating layer (122) in between. Accordingly, the first and second step structures (ST1, ST2) can provide wiring for different sub-cell arrays (SCA).

[0059] Accordingly, each of the plurality of contact electrodes (124, 124U) may have a variable thickness (i.e., length in the Z direction). For example, the uppermost contact electrode (124U) may include a first connecting portion (124UA) having a first thickness (T1) and a first landing portion (124UB) having a second thickness (T2).

[0060] According to exemplary embodiments, the first thickness (T1) and the second thickness (T2) may be different from each other. According to exemplary embodiments, the second thickness (T2) may be greater than the first thickness (T1). According to exemplary embodiments, the difference between the second thickness (T2) and the first thickness (T1) may be about 30 nm or less, but is not limited thereto.

[0061] According to exemplary embodiments, the first landing portion (124UB) of the top contact electrode (124U) may be spaced further away from the cell array region (CAR) than the first portion (124UA) of the top contact electrode (124U). According to exemplary embodiments, the first landing portion (124UB) of the top contact electrode (124U) may be connected to a corresponding single crystal channel layer (224) through the first portion (124UA) of the top contact electrode (124U).

[0062] According to exemplary embodiments, the first landing portion (124UB) of the top contact electrode (124U) may provide a landing for the conductive contacts (140). According to exemplary embodiments, the first landing portion (124UB) of the top contact electrode (124U) may come into contact with the conductive contacts (140).

[0063] Similarly, each of the contact electrodes (124) may include a second connecting portion (124A) having a first thickness (T1) and a second landing portion (124B) having a second thickness (T2).

[0064] According to exemplary embodiments, the second landing portion (124B) of the contact electrodes (124) may be spaced further away from the cell array region (CAR) than the second connecting portion (124A) of the contact electrodes (124). According to exemplary embodiments, the second landing portion (124B) of the contact electrodes (124) may be connected to the single crystal channel layer (224) through the second connecting portion (124A) of the contact electrodes (124).

[0065] According to exemplary embodiments, a second landing portion (124B) of the contact electrodes (124) may provide a landing for the conductive contacts (140). According to exemplary embodiments, the second landing portion (124B) of the contact electrodes (124) may come into contact with the conductive contacts (140).

[0066] According to exemplary embodiments, the first length (L1), which is the X-direction length of the first landing portion (124UA), may be different from the second length (L2), which is the X-direction length of the second landing portion (124A). According to exemplary embodiments, the first length (L1) may be longer than the second length (L2).

[0067] According to exemplary embodiments, the first landing portion (124UB) may overlap with the second connecting portions (124A) in the Z direction. According to exemplary embodiments, the first landing portion (124UB) may not overlap with the second landing portions (124B) in the Z direction. According to exemplary embodiments, the first landing portion (124UB) may be spaced apart from the second landing portions (124B) in the horizontal direction (e.g., X direction).

[0068] According to exemplary embodiments, the upper insulating layer (135) can cover the first and second step structures (ST1, ST2), the interlayer insulating layer (122), and the conductive contacts (140).

[0069] The interlayer insulating layer (122) and the upper insulating layer (135) may include an insulating material. The interlayer insulating layer (122) and the upper insulating layer (135) may include, for example, silicon oxide. Accordingly, the interlayer insulating layer (122) and the upper insulating layer (135) may be integrated, and a boundary may not be formed between the interlayer insulating layer (122) and the upper insulating layer (135).

[0070] The conductive contacts (140) may include a conductive material. The conductive contacts (140) may include a metallic material, for example, tungsten. Additionally, a conductive barrier, for example, titanium nitride, may be further interposed between the conductive contacts (140) and the upper insulating layer (135).

[0071] FIG. 3 is a flowchart for explaining a method for manufacturing a semiconductor memory device according to exemplary embodiments.

[0072] FIGS. 4a to 17b are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to exemplary embodiments.

[0073] More specifically, FIGS. 4a, FIGS. 8a, FIGS. 9a, FIGS. 10a, FIGS. 11a, FIGS. 12a, FIGS. 13a, FIGS. 14a, FIGS. 15a, FIGS. 16a, and FIGS. 17b represent parts corresponding to FIGS. 2c, and FIGS. 4b, FIGS. 5, FIGS. 6, FIGS. 7, FIGS. 8b, FIGS. 9b, FIGS. 10b, FIGS. 11b, FIGS. 12b, FIGS. 13b, FIGS. 14b, FIGS. 15b, FIGS. 16b, and FIGS. 17b represent parts corresponding to FIGS. 2d.

[0074] Referring to FIGS. 3, FIGS. 4a and FIGS. 4b, in P10, a plurality of compound semiconductor layers (110) and a plurality of single crystal semiconductor layers (120) can be formed on a substrate (101).

[0075] The substrate (101) may include a single-crystal semiconductor material. For example, the substrate (101) may include a semiconductor material such as Si or Ge. Or, for example, the substrate (101) may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GEOI) substrate.

[0076] Each of the plurality of compound semiconductor layers (110) and the plurality of single-crystal semiconductor layers (120) may comprise a single-crystal semiconductor material. Each of the plurality of compound semiconductor layers (110) may comprise a semiconductor material having a predetermined etching selectivity ratio with respect to the plurality of single-crystal semiconductor layers (120). According to some embodiments, the plurality of compound semiconductor layers (110) may have an etching selectivity ratio with respect to the substrate (101). According to some embodiments, the plurality of single-crystal semiconductor layers (120) may comprise a material having the same or similar etching characteristics as the substrate (101).

[0077] According to exemplary embodiments, each of the plurality of compound semiconductor layers (110) may include SiGe. According to exemplary embodiments, each of the plurality of single-crystal semiconductor layers (120) may include Si. For example, each of the plurality of compound semiconductor layers (110) may include single-crystal SiGe, and each of the plurality of single-crystal semiconductor layers (120) may include single-crystal Si.

[0078] According to some other embodiments, each of the plurality of single-crystal semiconductor layers (120) may comprise a single-crystal 2D (2-Dimensional) semiconductor material or a single-crystal oxide semiconductor material. For example, the 2D material semiconductor may comprise MoS2, WSe2, Graphene, Carbon Nanotube, or a combination thereof. For example, the oxide semiconductor material may be In x Ga y Zn z O, Inx Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga y O (where x, y, and z may each be in the range of 0 to 1) or a combination thereof may be included. For example, each of the plurality of single-crystal semiconductor layers (120) may include a single layer or a multilayer of the oxide semiconductor material.

[0079] According to some embodiments, each of the plurality of single-crystal semiconductor layers (120) may comprise a material having a bandgap energy greater than the bandgap energy of silicon. For example, each of the plurality of single-crystal semiconductor layers (120) may comprise a material having a bandgap energy of about 1.5 eV to 5.6 eV.

[0080] A plurality of compound semiconductor layers (110) and a plurality of single-crystal semiconductor layers (120) can be formed by a chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or atomic layer deposition (ALD) process. According to some embodiments, each of the plurality of compound semiconductor layers (110) and the plurality of single-crystal semiconductor layers (120) can be formed through an epitaxial growth process to have a single-crystal nature. According to some embodiments, each of the plurality of compound semiconductor layers (110) and the plurality of single-crystal semiconductor layers (120) can be annealed to have a single-crystal nature after being formed by a deposition process. Each of the plurality of compound semiconductor layers (110) and the plurality of single-crystal semiconductor layers (120) can have a thickness of several tens of nanometers.

[0081] Next, referring to FIGS. 3, 4b and 5, in P20, a plurality of compound semiconductor layers (110) and a plurality of single crystal semiconductor layers (120) can be etched to form a plurality of compound semiconductor patterns (111) and a plurality of single crystal semiconductor patterns (121).

[0082] Each of the plurality of compound semiconductor patterns (111) and the plurality of single crystal semiconductor patterns (121) has a width set in the Y direction and can be extended in the X direction.

[0083] According to exemplary embodiments, among the plurality of compound semiconductor layers (110), two layers adjacent to the substrate (101) and a single crystal semiconductor layer (120) interposed between them (i.e., the lowest single crystal semiconductor layer (120)) may not be etched.

[0084] According to exemplary embodiments, the formation of a plurality of compound semiconductor patterns (111) and a plurality of single-crystal semiconductor patterns (121) may include the step of forming an etching mask using a lithography process and anisotropically etching a plurality of compound semiconductor layers (110) and a plurality of single-crystal semiconductor layers (120) using the etching mask. The plurality of single-crystal semiconductor patterns (121) may constitute a first mold (MLD1) and second molds (MLD2). According to exemplary embodiments, the first mold (MLD1) and the second mold (MLD2) may be spaced apart in the Y direction.

[0085] Next, referring to FIGS. 3 and FIGS. 6, in P30, a stopper layer (131) and buried insulation patterns (132) can be formed.

[0086] A stopper layer (131) can be deposited on a plurality of compound semiconductor patterns (111) and a plurality of single-crystal semiconductor patterns (121). The stopper layer (131) can cover the plurality of compound semiconductor patterns (111) and the plurality of single-crystal semiconductor patterns (121). The stopper layer (131) can have a uniform thickness. Accordingly, the stopper layer (131) can have a conformal shape. The stopper layer (131) may include, for example, SiOCN.

[0087] After forming the stopper layer (131) and providing an insulating material to sufficiently fill the space between the stopper layers (131), embedded insulating patterns (132) can be formed by performing a planarization process such as Chemical Mechanical Polishing (CMP). As a non-limiting example, the planarization process may be CMP with the upper surface of the stopper layer (131) as the end point of the etching.

[0088] According to exemplary embodiments, the buried insulation patterns (132) can fill the space between the stopper layers (131). The upper surface of the buried insulation patterns (132) may be at the same level as the upper surface of the stopper layers (131).

[0089] The buried insulation patterns (132) may include any one of silicon oxide, silicon oxynitride film, carbon-containing silicon oxide film, carbon-containing silicon nitride film and carbon-containing silicon oxynitride film.

[0090] Next, referring to FIGS. 3, 6 and 7, in P40, some of the buried insulation patterns (132) and a portion of the stopper layer (131) can be removed.

[0091] A portion of the stopper layer (131) can be removed by a stripping process. By removing a portion of the stopper layer (131), some of the buried insulating patterns (132) may be exposed. The exposed portions of the buried insulating patterns (132) may be removed by wet etching. By removing some of the buried insulating patterns (132), sides of a plurality of compound semiconductor patterns (111) and a plurality of single crystal semiconductor patterns (121) may be exposed. Accordingly, stopper patterns (133) may be formed, and sides of a plurality of compound semiconductor patterns (111) and a plurality of single crystal semiconductor patterns (121) may be exposed.

[0092] Next, referring to FIGS. 3, FIGS. 7, FIGS. 8a and FIGS. 8b, a plurality of compound semiconductor patterns (111) can be removed in P50.

[0093] According to exemplary embodiments, a plurality of compound semiconductor patterns (111) can be removed by a wet etching process. According to exemplary embodiments, since a plurality of single-crystal semiconductor patterns (121) have a high etching selectivity ratio with respect to a plurality of compound semiconductor patterns (111), the etching amount of each of the plurality of single-crystal semiconductor patterns (121) in the etching of the plurality of compound semiconductor patterns (111) may be relatively small.

[0094] A compound semiconductor layer (110) disposed on a single-crystal semiconductor layer (120) can be etched together with a plurality of compound semiconductor patterns (111). Accordingly, residual compound semiconductor patterns (112) can be formed. A compound semiconductor layer (110) interposed between the single-crystal semiconductor layer (120) and the substrate (101) can be protected by the single-crystal semiconductor layer (120).

[0095] Next, referring to FIGS. 3, FIGS. 8a, FIGS. 8b, FIGS. 9a and FIGS. 9b, each of the plurality of single-crystal semiconductor patterns (121) and the single-crystal semiconductor layer (120) can be partially etched in P60.

[0096] The single-crystal semiconductor patterns (121) can be etched, for example, by wet etching. The single-crystal semiconductor patterns (121) can be etched isotropically. Accordingly, the thickness in the Z direction and the length in the Y direction of each of the plurality of single-crystal semiconductor patterns (121) can be reduced. The bottom and side surfaces of the top single-crystal semiconductor patterns (121) are exposed, while the top surface is covered by stopper patterns (133), so that the top single-crystal semiconductor patterns (121) may have a smaller amount of thickness reduction compared to other single-crystal semiconductor patterns (121). Accordingly, after P60, the thickness of the top single-crystal semiconductor patterns (121) may be greater than the thickness of other single-crystal semiconductor patterns (121). A person skilled in the art will understand, based on the subsequent processes, that the top single-crystal semiconductor patterns (121) correspond to a dummy electrode (124D).

[0097] According to exemplary embodiments, a portion of the single-crystal semiconductor layer (120) not covered by the residual compound semiconductor patterns (112) may be removed. A lower single-crystal semiconductor layer (125) may be formed by partial etching of the single-crystal semiconductor layer (120).

[0098] Next, referring to FIG. 3, FIG. 10a and FIG. 10b, an interlayer insulating layer (122) can be formed in P70.

[0099] According to exemplary embodiments, the interlayer insulating layer (122) can fill the space between each of the single-crystal semiconductor patterns (121) and the lower single-crystal semiconductor layer (125). According to exemplary embodiments, the interlayer insulating layer (122) can cover the single-crystal semiconductor patterns (121) and the lower single-crystal semiconductor layer (125).

[0100] The interlayer insulating layer (122) may include an insulating material with good gap-fill properties. According to exemplary embodiments, the interlayer insulating layer may include silicon oxide.

[0101] Next, referring to FIG. 3 and FIG. 10a through FIG. 11b, in P80, the interlayer insulating layer (122) and the buried insulating patterns (132) can be partially etched. The stopper patterns (133) can be etched together with the interlayer insulating layer (122) and the buried insulating patterns (132). By partially etching the insulating layer (122), the buried insulating patterns (132), and the stopper patterns (133), the upper surface of the top single-crystal semiconductor patterns (121) can be exposed.

[0102] The interlayer insulating layer (122) and the buried insulating patterns (132) can be processed by anisotropic etching. The interlayer insulating layer (122) and the buried insulating patterns (132) can be processed by plasma dry etching. The interlayer insulating layer (122) and the buried insulating patterns (132) can be etched with a high selectivity ratio for a plurality of single-crystal semiconductor patterns (121). Here, the statement that the interlayer insulating layer (122) and the buried insulating patterns (132) are etched with a high selectivity ratio for a plurality of single-crystal semiconductor patterns (121) means that during the etching process, the amount of etching of the interlayer insulating layer (122) and the buried insulating patterns (132) is greater than the amount of etching of the interlayer insulating layer (122) and the buried insulating patterns (132).

[0103] According to exemplary embodiments, in the etching process of P80, the etching selectivity ratio of the interlayer insulating layer (122) and the buried insulating patterns (132) to the plurality of single-crystal semiconductor patterns (121) may be 1:1.1 or greater. According to exemplary embodiments, the etching selectivity ratio of the interlayer insulating layer (122) and the buried insulating patterns (132) to the plurality of single-crystal semiconductor patterns (121) may be 1:20 or less.

[0104] According to exemplary embodiments, plasma etching parameters of the interlayer insulating layer (122) and the buried insulating patterns (132) may be determined such that the etching selectivity ratio of the interlayer insulating layer (122) and the buried insulating patterns (132) with respect to a plurality of single-crystal semiconductor patterns (121) has a high value. The plasma etching parameters may include the type of process gas, the ratio of process gas, chamber pressure, bias power, source power, etc.

[0105] As a non-limiting example, the upper surface of the single-crystal semiconductor pattern (121) may be the end point of the etching process of P80. For example, the etching process of P80 may be terminated when a particle formed by the etching of the single-crystal semiconductor pattern (121) is detected. However, it is not limited thereto, and the etching process of P80 may be terminated after being performed for a set time.

[0106] Next, referring to FIG. 3 and FIG. 11a through FIG. 12b, the best single-crystal semiconductor pattern (121) can be etched in P90. According to exemplary embodiments, the exposed portion of the best single-crystal semiconductor pattern (121) (i.e., the portion not covered by the stopper pattern (133)) can be etched. By etching the best single-crystal semiconductor pattern (121), the upper surface of the interlayer insulating layer (122) can be exposed.

[0107] The best single-crystal semiconductor pattern (121) can be processed by anisotropic etching. The best single-crystal semiconductor pattern (121) can be processed by plasma dry etching. The best single-crystal semiconductor pattern (121) can be etched with high selectivity for the interlayer insulating layer (122) and the buried insulating patterns (132).

[0108] According to exemplary embodiments, the etching process of P90 may have an etching selectivity ratio that is inverted compared to the etching process of P80. According to exemplary embodiments, in the etching process of P90, the etching selectivity ratio of the single crystal semiconductor pattern (121) to the interlayer insulating layer (122) and the buried insulating patterns (132) may be 1:1.1 or greater. According to exemplary embodiments, the etching selectivity ratio of the single crystal semiconductor pattern (121) to the interlayer insulating layer (122) and the buried insulating patterns (132) may be 1:20 or less.

[0109] According to exemplary embodiments, plasma etching parameters of a single-crystal semiconductor pattern (121) may be determined such that the etching selectivity of a plurality of single-crystal semiconductor patterns (121) for an interlayer insulating layer (122) and buried insulating patterns (132) has a high value. According to exemplary embodiments, the type of process gas, the ratio of process gas, the chamber pressure, the bias power, and the source power used in P90 may be different from the type of process gas, the ratio of process gas, the chamber pressure, the bias power, and the source power used in P80.

[0110] Next, referring to FIG. 3 and FIG. 12a through 13b, in P100, the interlayer insulating layer (122) and the buried insulating patterns (132) can be partially etched. The stopper patterns (133) can be etched together with the interlayer insulating layer (122) and the buried insulating patterns (132). The etching of P100 can be performed to expose the upper surface of the second single-crystal semiconductor pattern (121). Since the etching of P100 is similar to the etching of P80, a redundant description thereof is omitted.

[0111] Next, referring to FIG. 3 and FIG. 13a through FIG. 14b, a second single-crystal semiconductor pattern (121) can be etched in P110. An exposed portion of the second single-crystal semiconductor pattern (121) (i.e., a portion not covered by the interlayer insulating layer (122)) can be etched. The etching of P110 can be performed to expose the upper surface of the interlayer insulating layer (122). Since the etching of P110 is similar to the etching of P90, a redundant description thereof is omitted.

[0112] The series of etching processes described with reference to P80 to P110 can be performed repeatedly. Accordingly, first and second step structures (ST1, ST2, see FIG. 1) can be formed in a contact region (CNTR, see FIG. 1).

[0113] The series of etching processes described with reference to P80 to P110 simultaneously etches, for example, a portion in which single-crystal silicon and silicon oxide are alternately arranged and a portion containing only silicon oxide. In the conventional case, single-crystal semiconductor patterns (121), interlayer insulating layers (122), and buried insulating patterns (132) are etched through the repetition of the same etching process, resulting in reduced uniformity of the etching. More specifically, there was a problem in that the etching profile was distorted at the boundary between the portion in which single-crystal silicon and silicon oxide are alternately arranged and the portion containing only silicon oxide.

[0114] According to exemplary embodiments, the reliability of the etching process can be improved by making the parameters of the process that mainly etches the semiconductor patterns (121) and the process that mainly etches the interlayer insulating layer (122) and the buried insulating patterns (132) different.

[0115] Next, referring to FIG. 3 and FIG. 14a through 15b, in P120, the interlayer insulating layer (122) and the embedded insulating patterns (132) can be partially etched. By etching P120, the upper surface of each of the plurality of single-crystal semiconductor patterns (121), excluding the uppermost single-crystal semiconductor pattern (121), can be exposed. Since the etching of P120 is similar to the etching of P80, a redundant description thereof is omitted. By etching P120, the interlayer insulating layer (122) can be recessed in the X direction with respect to the plurality of single-crystal semiconductor patterns (121).

[0116] Next, referring to FIG. 3 and FIG. 16a through FIG. 16b, optional growth patterns (123) can be formed on the upper surface of each of the plurality of single-crystal semiconductor patterns (121) in P130. According to exemplary embodiments, the optional growth patterns (123) may be formed only on the upper surface of each of the plurality of single-crystal semiconductor patterns (121). The optional growth patterns (123) may not be formed, for example, on the interlayer insulating layer (122), the buried insulating patterns (132), and the stopper patterns (133). Accordingly, the optional growth patterns (123) may be spaced apart from the interlayer insulating layer (122), the buried insulating patterns (132), and the stopper patterns (133).

[0117] According to some embodiments, each of the selective growth patterns (123) may be formed by epitaxial growth using a plurality of single-crystal semiconductor patterns (121) as a seed layer. According to other embodiments, each of the selective growth patterns (123) may be formed by a deposition process such as CVD. When each of the selective growth patterns (123) is formed by deposition such as CVD, a mask or the like may be used to limit the deposition location of the selective growth patterns (123). According to exemplary embodiments, when each of the selective growth patterns (123) is formed by deposition such as CVD, an annealing process may be further performed.

[0118] Next, referring to FIG. 3 and FIG. 16a to FIG. 17b, a plurality of contact electrodes (124, 124U) can be formed in P140. A plurality of contact electrodes (124, 124U) can be formed by removing selective growth patterns (123) and a plurality of single-crystal semiconductor patterns (121), and providing a conductive material in the space where the selective growth patterns (123) and a plurality of single-crystal semiconductor patterns (121) have been removed.

[0119] Next, referring to FIGS. 2c, FIGS. 2d and FIGS. 3, an upper insulating layer (135) and conductive contacts (140) can be formed in P150.

[0120] According to exemplary embodiments, the landing portion (124UB) of the best contact electrode (124U) and the landing portion (124B) of the contact electrode (124) have increased thickness, thereby preventing defects caused by excessive etching in the etching process for forming conductive contacts (140).

[0121] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims. Explanation of the symbols

[0122] 10: Semiconductor memory device 124: Contact electrodes 124A: Second connection portion 124B: Second landing portion 124U: Top contact electrode 124UA: First connection portion 124UB: First landing portion 140: Conductive contacts 220: Transistor body 224: Single crystal channel layer CAR: Cell array region CNTR: Contact region

Claims

Claim 1 A substrate comprising a cell array region and a contact region; a plurality of contact electrodes disposed on the contact region and extending in a first direction parallel to the upper surface of the substrate; transistor body portions disposed on the cell array region and extending along a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, wherein each of the transistor body portions comprises a first source-drain region, a single-crystal channel layer, and a second source-drain region disposed sequentially along the second direction; a lower electrode layer disposed on the cell array region and connected to the second source-drain region; and a capacitor dielectric film disposed on the cell array region, covering the lower electrode layer and having a uniform thickness. A semiconductor memory device comprising an upper electrode layer disposed on the cell array region and spaced apart from the lower electrode layer with the capacitor dielectric film in between, wherein the single crystal channel layer of each of the transistor body portions is connected to a corresponding one of a plurality of contact electrodes, and each of the plurality of contact electrodes is longer in the first direction than those disposed above among the plurality of contact electrodes to form a step structure, and each of the plurality of contact electrodes includes a connecting portion having a first thickness and a landing portion having a second thickness, and the landing portion of each of the plurality of contact electrodes has a constant thickness along the first direction. Claim 2 A semiconductor memory device according to claim 1, characterized in that the second thickness is greater than the first thickness. Claim 3 A semiconductor memory device according to claim 1, characterized in that the difference between the second thickness and the first thickness is 30 nm or less. Claim 4 A semiconductor memory device according to claim 1, further comprising conductive contacts disposed on the contact region, extending in a third direction perpendicular to the upper surface of the substrate, and connected to the landing portion of each of the plurality of contact electrodes. Claim 5 A semiconductor memory device according to claim 1, wherein the landing portion of each of the plurality of contact electrodes is connected to the single crystal channel layer through the connection portion. Claim 6 A semiconductor memory device according to claim 1, wherein the landing portion of each of the plurality of contact electrodes overlaps with the connection portion of the lower of the plurality of contact electrodes in a third direction perpendicular to the upper surface of the substrate. Claim 7 A semiconductor memory device according to claim 1, wherein the landing portion of each of the plurality of contact electrodes is spaced apart in the first direction from the landing portion of the lower of the plurality of contact electrodes. Claim 8 A semiconductor memory device according to claim 1, wherein the plurality of contact electrodes includes an uppermost contact electrode positioned furthest from the substrate, and the first directional length of the landing portion of the uppermost contact electrode is different from the first directional length of the landing portion of the plurality of contact electrodes. Claim 9 A semiconductor memory device according to claim 8, characterized in that the first directional length of the landing portion of the uppermost contact electrode is longer than the first directional length of the landing portions of the plurality of contact electrodes. Claim 10 A substrate comprising a cell array region and a contact region; a plurality of memory cells disposed on the cell array region, each comprising a cell transistor and a cell capacitor, wherein the plurality of memory cells are disposed along a third direction perpendicular to the substrate; a first step structure disposed on the contact region and extending in a first direction parallel to the upper surface of the substrate; a second step structure disposed on the contact region and extending in the first direction, and extending in a second direction perpendicular to the first direction and parallel to the upper surface of the substrate; A semiconductor memory device comprising an interlayer insulating layer interposed between the first step structure and the second step structure, wherein each of the first step structure and the second step structure comprises a plurality of contact electrodes stacked along the third direction on the substrate and a top contact electrode disposed on the plurality of contact electrodes, wherein the top contact electrode comprises a first connecting portion having a first thickness and a first landing portion having a second thickness, and each of the plurality of contact electrodes comprises a second connecting portion having the first thickness and a second landing portion having the second thickness, wherein the first direction length of the first landing portion is different from the first direction length of the second landing portion, and the first landing portion of the top contact electrode and the second landing portion of each of the plurality of contact electrodes have a constant thickness along the first direction.

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