Semiconductor device and electronic system

Abstract

A semiconductor device comprises a lower stepped connection portion disposed at a first vertical level on a substrate and having a plurality of lower conductive pad portions, an upper stepped connection portion disposed at a second vertical level higher than the first vertical level on the substrate and having a plurality of upper conductive pad portions, a lower insulating block that contacts each of the plurality of lower conductive pad portions at the first vertical level and covers the lower stepped connection portion, an upper insulating block that contacts each of the plurality of upper conductive pad portions at the second vertical level and includes a portion covering the upper stepped connection portion and a portion covering the lower insulating block, an intermediate insulating film interposed between the lower insulating block and the upper insulating block at a third vertical level between the first vertical level and the second vertical level, and a first plug structure that penetrates the lower stepped connection portion, the intermediate insulating film, and the upper insulating block in the vertical direction at a position spaced horizontally from the upper stepped connection portion, and whose width along the horizontal direction is maximum at the third vertical level.

Description

Technology Field

[0001] The technical concept of the present invention relates to a semiconductor device and an electronic system including the same, and in particular to a semiconductor device equipped with a non-volatile vertical memory element and an electronic system including the same. Background Technology

[0002] In electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing high-capacity data, and accordingly, methods to increase the data storage capacity of semiconductor devices are being studied. For example, as one method to increase the data storage capacity of a semiconductor device, a semiconductor device including a vertical memory element equipped with memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. The problem to be solved

[0003] The technical problem that the technical concept of the present invention aims to solve is to provide a semiconductor device equipped with memory cells arranged in three dimensions that can maintain desired electrical characteristics and reliability even when the number of stacked word lines is increased to improve integration density.

[0004] Another technical problem that the technical concept of the present invention aims to achieve is to provide an electronic system including a semiconductor device that can maintain desired electrical characteristics and reliability even when the number of stacked word lines is increased to improve integration density in a semiconductor device having memory cells arranged in three dimensions. means of solving the problem

[0005] A semiconductor device according to one embodiment of the technical concept of the present invention comprises a substrate, a lower stepped connection portion disposed at a first vertical level on the substrate and having a plurality of lower conductive pad portions, an upper stepped connection portion disposed at a second vertical level higher than the first vertical level on the substrate and having a plurality of upper conductive pad portions, a lower insulating block in contact with each of the plurality of lower conductive pad portions at the first vertical level and covering the lower stepped connection portion, an upper insulating block in contact with each of the plurality of upper conductive pad portions at the second vertical level and including a portion covering the upper stepped connection portion and a portion covering the lower insulating block, an intermediate insulating film interposed between the lower insulating block and the upper insulating block at a third vertical level between the first vertical level and the second vertical level, and a first plug structure penetrating the lower stepped connection portion, the intermediate insulating film, and the upper insulating block in the vertical direction at a position spaced horizontally from the upper stepped connection portion, wherein the width along the horizontal direction is maximum at the third vertical level.

[0006] A semiconductor device according to another embodiment of the technical concept of the present invention comprises a substrate including a memory cell region and a connection region; a first stack including a plurality of lower gate lines that overlap each other along the vertical direction in the memory cell region and a plurality of lower conductive pad portions that are arranged in the connection region and integrally connected to the plurality of lower gate lines; a second stack including a plurality of upper gate lines that overlap each other along the vertical direction in the memory cell region and an upper stepped connection portion that overlaps each other in the vertical direction in the memory cell region and a plurality of upper conductive pad portions that are arranged in the connection region and integrally connected to the plurality of upper gate lines; a lower insulating block covering the lower stepped connection portion at the first vertical level; an upper insulating block covering the upper stepped connection portion and the lower insulating block at the second vertical level; and an intermediate portion interposed between the first stack and the second stack and between the lower insulating block and the upper insulating block at a third vertical level between the first vertical level and the second vertical level. It includes an insulating film and a plug structure that penetrates the lower stepped connection, the intermediate insulating film, and the upper insulating block in the vertical direction at a position spaced horizontally from the first stack in the connection area, and whose width along the horizontal direction is maximum at the third vertical level.

[0007] An electronic system according to one embodiment of the technical concept of the present invention comprises: a main substrate; and a semiconductor device on the main substrate; The semiconductor device comprises a controller electrically connected to the semiconductor device on the main board, wherein the semiconductor device comprises a substrate, a lower stepped connection portion disposed at a first vertical level on the substrate and having a plurality of lower conductive pad portions, an upper stepped connection portion disposed at a second vertical level higher than the first vertical level on the substrate and having a plurality of upper conductive pad portions, a lower insulating block that contacts each of the plurality of lower conductive pad portions at the first vertical level and covers the lower stepped connection portion, an upper insulating block that contacts each of the plurality of upper conductive pad portions at the second vertical level and includes a portion covering the upper stepped connection portion and a portion covering the lower insulating block, an intermediate insulating film interposed between the lower insulating block and the upper insulating block at a third vertical level between the first vertical level and the second vertical level, and a first plug structure that penetrates the lower stepped connection portion, the intermediate insulating film, and the upper insulating block in the vertical direction at a position spaced horizontally from the upper stepped connection portion, and whose width along the horizontal direction is maximum at the third vertical level. Effects of the invention

[0008] A semiconductor device according to the technical concept of the present invention can maintain electrical characteristics and reliability even when the number of stacked word lines is increased to improve integration density in a semiconductor device equipped with memory cells arranged in three dimensions. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram of a semiconductor device according to embodiments of the technical concept of the present invention. FIG. 2 is a schematic perspective view of a semiconductor device according to embodiments of the technical concept of the present invention. FIG. 3 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to embodiments of the technical concept of the present invention. FIG. 4 is a schematic plan view of a portion of a semiconductor device according to embodiments of the technical concept of the present invention. FIG. 5 is a schematic plan view of some components of a memory cell block included in a semiconductor device according to embodiments of the technical concept of the present invention. Figure 6a is a cross-sectional view along the X1 - X1' line of Figure 5. Figure 6b is a cross-sectional view along the X2 - X2' line of Figure 5. Fig. 6c is a cross-sectional view along the Y1-Y1' line of Fig. 5. FIG. 6d is an enlarged cross-sectional view of some components included in the area labeled "EX1" in FIG. 6a. FIG. 6e is an enlarged cross-sectional view of some components included in the area labeled "EX2" in FIG. 6c. FIGS. 7 to 9 are cross-sectional views illustrating semiconductor devices according to different embodiments based on the technical concept of the present invention. FIGS. 10a, FIGS. 10b, and FIGS. 10c are cross-sectional views for illustrating a semiconductor device according to other embodiments of the technical concept of the present invention. FIG. 11 is a schematic plan view of some components of a memory cell block included in a semiconductor device according to other embodiments of the technical concept of the present invention. FIG. 12 is a cross-sectional view showing the configurations of the X3 - X3' line cross-section and the X4 - X4' line cross-section of FIG. 11. FIGS. 13 to 18 are cross-sectional views illustrating semiconductor devices according to other embodiments of the technical concept of the present invention. FIGS. 19a and FIGS. 19b are cross-sectional views for illustrating a semiconductor device according to other embodiments of the technical concept of the present invention. FIGS. 20a to 28 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to embodiments of the technical concept of the present invention, where FIGS. 20a, 21a, 22a, 23a, 24a, 25a, 26a, 27a, and 28 are cross-sectional views according to the process sequence of some components of a portion corresponding to the cross-section along the X1 - X1' line of FIG. 5, FIGS. 20b, 21b, 22b, 23b, 24b, 25b, 26b, and 27b are cross-sectional views according to the process sequence of some components of a portion corresponding to the cross-section along the X2 - X2' line of FIG. 5, and FIGS. 20c, 23c, 26c, and 27c are cross-sectional views according to the process sequence of some components of a portion corresponding to the cross-section along the Y1 - Y1' line of FIG. 5. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0011] FIG. 1 is a block diagram of a semiconductor device (10) according to embodiments of the technical concept of the present invention.

[0012] Referring to FIG. 1, a semiconductor device (10) may include a memory cell array (20) and a peripheral circuit (30). The memory cell array (20) includes a plurality of memory cell blocks (BLK1, BLK2, ..., BLKp). Each of the plurality of memory cell blocks (BLK1, BLK2, ..., BLKp) may include a plurality of memory cells. The memory cell blocks (BLK1, BLK2, ..., BLKp) may be connected to the peripheral circuit (30) through a bit line (BL), a word line (WL), a string select line (SSL), and a ground select line (GSL).

[0013] The peripheral circuit (30) may include a row decoder (32), a page buffer (34), a data input / output circuit (36), control logic (38), and a common source line driver (39). The peripheral circuit (30) may further include various circuits such as a voltage generation circuit that generates various voltages required for the operation of the semiconductor device (10), an error correction circuit for correcting errors in data read from the memory cell array (20), and an input / output interface.

[0014] A memory cell array (20) can be connected to a row decoder (32) via a word line (WL), a string select line (SSL), and a ground select line (GSL), and can be connected to a page buffer (34) via a bit line (BL). In the memory cell array (20), a plurality of memory cells included in a plurality of memory cell blocks (BLK1, BLK2, ..., BLKp) may each be a flash memory cell. The memory cell array (20) may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and a plurality of NAND strings may each include a plurality of memory cells connected to a plurality of vertically stacked word lines (WL).

[0015] The peripheral circuit (30) can receive an address (ADDR), a command (CMD), and a control signal (CTRL) from outside the semiconductor device (10), and can transmit and receive data (DATA) with a device outside the semiconductor device (10).

[0016] The row decoder (32) can select at least one of a plurality of memory cell blocks (BLK1, BLK2, ..., BLKp) in response to an external address (ADDR), and can select the word line (WL), string select line (SSL), and ground select line (GSL) of the selected memory cell block. The row decoder (32) can transmit a voltage for performing memory operations to the word line (WL) of the selected memory cell block.

[0017] The page buffer (34) can be connected to the memory cell array (20) via a bit line (BL). During a program operation, the page buffer (34) can operate as a write driver to apply a voltage to the bit line (BL) according to the data (DATA) to be stored in the memory cell array (20), and during a read operation, it can operate as a detection amplifier to detect the data (DATA) stored in the memory cell array (20). The page buffer (34) can operate according to a control signal (PCTL) provided by the control logic (38).

[0018] The data input / output circuit (36) can be connected to the page buffer (34) through a plurality of data lines (DLs). The data input / output circuit (36) can receive data (DATA) from a memory controller (not shown) during a program operation and provide program data (DATA) to the page buffer (34) based on a column address (C_ADDR) provided by the control logic (38). During a read operation, the data input / output circuit (36) can provide read data (DATA) stored in the page buffer (34) to the memory controller based on a column address (C_ADDR) provided by the control logic (38).

[0019] The data input / output circuit (36) can transmit the input address or command to the control logic (38) or row decoder (32). The peripheral circuit (30) may further include an Electro Static Discharge (ESD) circuit and a pull-up / pull-down driver.

[0020] The control logic (38) can receive a command (CMD) and a control signal (CTRL) from the memory controller. The control logic (38) can provide a row address (R_ADDR) to the row decoder (32) and provide a column address (C_ADDR) to the data input / output circuit (36). The control logic (38) can generate various internal control signals used within the semiconductor device (10) in response to the control signal (CTRL). For example, the control logic (38) can adjust the voltage levels provided to the word line (WL) and bit line (BL) when performing memory operations such as program operation or erase operation.

[0021] The common source line driver (39) can be connected to the memory cell array (20) via the common source line (CSL). The common source line driver (39) can apply a common source voltage (e.g., power supply voltage) or a ground voltage to the common source line (CSL) based on the control signal (CTRL_BIAS) of the control logic (38).

[0022] FIG. 2 is a schematic perspective view of a semiconductor device (10) according to embodiments of the technical concept of the present invention.

[0023] Referring to FIG. 2, a semiconductor device (10) may include a cell array structure (CAS) and a peripheral circuit structure (PCS) that overlap each other in a vertical direction (Z direction). The cell array structure (CAS) may include a memory cell array (20) described with reference to FIG. 1. The peripheral circuit structure (PCS) may include a peripheral circuit (30) described with reference to FIG. 1. FIG. 2 illustrates a structure in which the cell array structure (CAS) and the peripheral circuit structure (PCS) are placed at different vertical levels and overlap each other in a vertical direction (Z direction), but the technical concept of the present invention is not limited thereto. For example, the cell array structure (CAS) and the peripheral circuit structure (PCS) may be placed at the same vertical level.

[0024] The cell array structure (CAS) may include a plurality of tiles (24). Each of the plurality of tiles (24) may include a plurality of memory cell blocks (BLK1, BLK2, ..., BLKp). Each of the plurality of memory cell blocks (BLK1, BLK2, ..., BLKp) may include memory cells arranged in three dimensions.

[0025] In exemplary embodiments, two tiles (24) may form one mat, but are not limited thereto. The memory cell array (20) described with reference to FIG. 1 may include a plurality of mats, for example, four mats, but is not limited thereto.

[0026] FIG. 3 is an equivalent circuit diagram of a memory cell array (MCA) of a semiconductor device according to embodiments of the technical concept of the present invention. FIG. 3 illustrates an equivalent circuit diagram of a vertical NAND flash memory device having a vertical channel structure. A plurality of memory cell blocks (BLK1, BLK2, ..., BLKp) illustrated in FIG. 1 and FIG. 2 may each include a memory cell array (MCA) having a circuit configuration illustrated in FIG. 3.

[0027] Referring to FIG. 3, a memory cell array (MCA) may include a plurality of memory cell strings (MS). The memory cell array (MCA) may include a plurality of bit lines (BL) (BL1, BL2, ..., BLm), a plurality of word lines (WL) (WL1, WL2, ..., WLn-1, WLn), at least one string select line (SSL), at least one ground select line (GSL), and a common source line (CSL). A plurality of memory cell strings (MS) may be formed between the plurality of bit lines (BL) and the common source line (CSL). FIG. 3 illustrates a case where each of the plurality of memory cell strings (MS) includes one ground select line (GSL) and two string select lines (SSL), but the technical concept of the present invention is not limited thereto. For example, each of the plurality of memory cell strings (MS) may include one string select line (SSL).

[0028] Each of the multiple memory cell strings (MS) may include a string select transistor (SST), a ground select transistor (GST), and multiple memory cell transistors (MC1, MC2, ..., MCn-1, MCn). The drain region of the string select transistor (SST) is connected to a bit line (BL), and the source region of the ground select transistor (GST) may be connected to a common source line (CSL). The common source line (CSL) may be a region in which the source regions of the multiple ground select transistors (GST) are connected in common.

[0029] A string select transistor (SST) can be connected to a string select line (SSL), and a ground select transistor (GST) can be connected to a ground select line (GSL). Multiple memory cell transistors (MC1, MC2, ..., MCn-1, MCn) can each be connected to a word line (WL).

[0030] FIG. 4 is a schematic plan view of a portion of a semiconductor device (100) according to embodiments of the technical concept of the present invention.

[0031] Referring to FIG. 4, the cell array structure (CAS) of the semiconductor device (100) may include a substrate (110) and a plurality of memory cell blocks (BLK1, BLK2, ..., BLKp-1, BLKp) disposed on the substrate (110).

[0032] A peripheral circuit (30) described with reference to FIG. 1 may be disposed on the lower part of the substrate (110) or on other areas of the substrate (110). In exemplary embodiments, a plurality of memory cell blocks (BLK1, BLK2, ..., BLKp-1, BLKp) may overlap a peripheral circuit structure (PCS) (see FIG. 2) in a vertical direction (Z direction) with respect to the substrate (110).

[0033] A cell array structure (CAS) may include a memory cell region (MEC) and connection regions (CON) disposed on both sides of the memory cell region (MEC) in a first horizontal direction (X direction). A plurality of memory cell blocks (BLK1, BLK2, ..., BLKp-1, BLKp) may each include a memory stack structure (MST) extending in a first horizontal direction (X direction) across the memory cell region (MEC) and the connection region (CON). The memory stack structure (MST) may include a plurality of gate lines (130) stacked to overlap each other in a vertical direction (Z direction) in the memory cell region (MEC) and the connection region (CON) on the substrate (110). In each of the plurality of memory stack structures (MST), the plurality of gate lines (130) may form a gate stack (GS). In each of the plurality of memory stack structures (MST), the plurality of gate lines (130) may comprise the ground select line (GSL), the plurality of word lines (WL), and the string select line (SSL) as illustrated in FIG. 3. The plurality of memory stack structures (MST) may each include a plurality of memory stacks that are arranged at different vertical levels in the vertical direction (Z direction) and overlap each other along the vertical direction (Z direction). The plurality of memory stacks may each include a plurality of gate lines (130) that overlap each other along the vertical direction (Z direction). In exemplary embodiments, the plurality of memory stacks may each include 48, 64, or 96 gate lines (130) stacked to overlap each other along the vertical direction (Z direction), but are not limited thereto.

[0034] In exemplary embodiments, the area of ​​a plurality of gate lines (130) included in a plurality of memory stack structures (MST) in the XY plane may gradually decrease as the distance from the substrate (110) increases. The central portion of each of the plurality of gate lines (130) that overlap each other in the vertical direction (Z direction) may form a memory cell region (MEC), and the edge portion of each of the plurality of gate lines (130) may form a connection region (CON).

[0035] A plurality of word line cut structures (WLC) that extend in a first horizontal direction (X direction) from a memory cell region (MEC) and a connection region (CON) may be disposed on the substrate (110). The plurality of word line cut structures (WLC) may be disposed spaced apart from each other along a second horizontal direction (Y direction). A plurality of memory cell blocks (BLK1, BLK2, ..., BLKp-1, BLKp) may be disposed one by one between each of the plurality of word line cut structures (WLC).

[0036] FIGS. 5 and FIGS. 6a through 6e are drawings for explaining in more detail a semiconductor device (100) according to embodiments of the technical concept of the present invention. More specifically, FIG. 5 is a schematic plan view of some components of a memory cell block (BLK11, BLK12). FIG. 6a is a cross-sectional view along the X1 - X1' line of FIG. 5. FIG. 6b is a cross-sectional view along the X2 - X2' line of FIG. 5. FIG. 6c is a cross-sectional view along the Y1 - Y1' line of FIG. 5. FIG. 6d is an enlarged cross-sectional view of some components included in the area marked "EX1" in FIG. 6a. FIG. 6e is an enlarged cross-sectional view of some components included in the area marked "EX2" in FIG. 6c. The memory cell blocks (BLK11, BLK12) exemplified in FIG. 5 can each be configured with any one of the plurality of memory cell blocks (BLK1, BLK2, ..., BLKp-1, BLKp) exemplified in FIG. 4.

[0037] Referring to FIG. 5 and FIG. 6a through 6e, a semiconductor device (100) may include a substrate (110) comprising a memory cell region (MEC) and a connection region (CON), a first stack (STA) disposed at a first vertical level on the substrate (110), and a second stack (STB) disposed at a second vertical level higher than the first vertical level on the substrate (110). As used herein, the term “vertical level” means a distance along a vertical direction (Z direction or -Z direction) from the upper surface of the substrate (110).

[0038] The first stack (STA) and the second stack (STB) may each include a plurality of gate lines (130) that overlap each other along the vertical direction (Z direction) in the memory cell region (MEC), and a stepped connection part (STP) having a plurality of conductive pad parts (130A) disposed in the connection region (CON) and integrally connected to the plurality of gate lines (130). The first stack (STA) and the second stack (STB) may form a cell array structure (CAS) as illustrated in FIG. 4. In this specification, the gate line (130) included in the first stack (STA) may be referred to as a "lower gate line," the conductive pad part (130A) included in the first stack (STA) may be referred to as a "lower conductive pad part," and the stepped connection part (STP) included in the first stack (STA) may be referred to as a "lower stepped connection part." Additionally, the gate line (130) included in the second stack (STB) may be referred to as the "upper gate line," the conductive pad portion (130A) included in the second stack (STB) may be referred to as the "upper conductive pad portion," and the stepped connection portion (STP) included in the second stack (STB) may be referred to as the "upper stepped connection portion."

[0039] As illustrated in FIGS. 6a and 6b, an insulating plate (112) and a second conductive plate (118) may be disposed on a substrate (110) in a connection region (CON), and as illustrated in FIG. 6c, a first conductive plate (114) and a second conductive plate (118) may be disposed on a substrate (110) in a memory cell region (MEC). A memory stack structure (MST) including a first stack (STA) and a second stack (STB) may be disposed on the second conductive plate (118) in the memory cell region (MEC) and the connection region (CON).

[0040] In exemplary embodiments, the first conductive plate (114) and the second conductive plate (118) in the memory cell region (MEC) can perform the function of the common source line (CSL) described with reference to FIG. 3. The first conductive plate (114) and the second conductive plate (118) can function as source regions that supply current to vertical memory cells included in the cell array structure (CAS).

[0041] In exemplary embodiments, the substrate (110) may be made of a semiconductor material such as polysilicon. The first conductive plate (114) and the second conductive plate (118) may each be made of a doped polysilicon film, a metal film, or a combination thereof. The metal film may be made of tungsten (W), but is not limited thereto. In the memory stack structure (MST), a plurality of gate lines (130) extending in a horizontal direction parallel to each other and overlapping in a vertical direction (Z direction) may form a gate stack (GS) (see FIG. 4). The plurality of gate lines (130) may each be made of a metal, a metal silicide, an impurity-doped semiconductor, or a combination thereof. For example, each of the multiple gate lines (130) may include a metal such as tungsten, nickel, cobalt, tantalum, etc., a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, etc., doped polysilicon, or a combination thereof.

[0042] An insulating film (132) may be interposed between the second conductive plate (118) and the plurality of gate lines (130), and between each of the plurality of gate lines (130). In each of the first stack (STA) and the second stack (STB), the uppermost gate line (130) among the plurality of gate lines (130) may be covered with an insulating film (132). The insulating film (132) may be made of silicon oxide.

[0043] An intermediate insulating film (135, 136) may be interposed in a third vertical level between a first vertical level in which a first stack (STA) is placed and a second vertical level in which a second stack (STB) is placed. The intermediate insulating film (135, 136) may include a first intermediate insulating film (135) and a second intermediate insulating film (136) stacked sequentially on the first stack (STA). The first intermediate insulating film (135) and the second intermediate insulating film (136) may each be made of silicon oxide.

[0044] As illustrated in FIGS. 5 and 6c, a plurality of word line cut structures (WLC) may be extended along a first horizontal direction (X direction) on a substrate (110) in a memory cell region (MEC) and a connection region (CON). The width of each of the plurality of gate lines (130) included in the memory cell blocks (BLK11, BLK12) in the second horizontal direction (Y direction) may be limited by the plurality of word line cut structures (WLC).

[0045] A plurality of word line cut structures (WLCs) may each be composed of an insulating structure. In exemplary embodiments, the insulating structure may be composed of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric material. For example, the insulating structure may be composed of a silicon oxide film, a silicon nitride film, a SiON film, a SiOCN film, a SiCN film, or a combination thereof. In other exemplary embodiments, at least a portion of the insulating structure may be composed of an air gap. As used herein, the term "air" refers to the atmosphere or other gases that may be present during the manufacturing process.

[0046] A plurality of gate lines (130) may be stacked on a second conductive plate (118) between two adjacent word line cut structures (WLC) so as to overlap each other in a vertical direction (Z direction). The plurality of gate lines (130) may include a ground select line (GSL), a plurality of word lines (WL), and a string select line (SSL) as described with reference to FIG. 3.

[0047] In a plurality of gate lines (130), the upper two gate lines (130) can each be separated in a second horizontal direction (Y direction) with a string select line cut structure (SSLC) in between. The two gate lines (130) separated from each other with a string select line cut structure (SSLC) in between can each form a string select line (SSL) as described with reference to FIG. 3. FIG. 6c illustrates a case in which one string select line cut structure (SSLC) is formed in one gate stack (GS) (see FIG. 4) defined by two adjacent string select line cut structures (SSLC), but the technical concept of the present invention is not limited to what is illustrated in FIG. 6c. For example, at least two string select line cut structures (SSLC) may be formed in one gate stack (GS). The string select line cut structure (SSLC) may be filled with an insulating film. In exemplary embodiments, the string select line cut structure (SSLC) may include an insulating film made of an oxide film, a nitride film, or a combination thereof. In exemplary embodiments, at least a portion of the string select line cut structure (SSLC) may be made of an air gap.

[0048] As illustrated in FIG. 6c, a plurality of channel structures (140) on a substrate (110) in a memory cell region (MEC) may be extended in a vertical direction (Z direction) through a plurality of gate lines (130), a plurality of insulating films (132), a first intermediate insulating film (135), a second intermediate insulating film (136), a second conductive plate (118), and a first conductive plate (114). The plurality of channel structures (140) may be arranged spaced apart from each other along a first horizontal direction (X direction) and a second horizontal direction (Y direction) at a predetermined interval. Each of the plurality of channel structures (140) may include a gate dielectric film (142), a channel region (144), a buried insulating film (146), and a drain region (148).

[0049] As illustrated in FIG. 6e, the gate dielectric film (142) may include a tunneling dielectric film (TD), a charge storage film (CS), and a blocking dielectric film (BD) formed sequentially from the channel region (144) toward the gate line (130). The relative thicknesses of the tunneling dielectric film (TD), the charge storage film (CS), and the blocking dielectric film (BD) are not limited to those illustrated in FIG. 6e and may vary in many ways.

[0050] The tunneling dielectric film (TD) may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage film (CS) is a region in which electrons passing through the tunneling dielectric film (TD) from the channel region (144) can be stored, and may include silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The blocking dielectric film (BD) may be made of silicon oxide, silicon nitride, or a metal oxide with a dielectric constant greater than that of silicon oxide. The metal oxide may be made of hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0051] As illustrated in FIGS. 6c and 6e, the first conductive plate (114) may penetrate a portion of the gate dielectric film (142) in a horizontal direction (X direction and / or Y direction) and come into contact with the channel region (144). The thickness (Z direction size) of the portion of the first conductive plate (114) that overlaps vertically with the gate dielectric film (142) may be greater than the thickness (Z direction size) of the portion of the first conductive plate (114) that overlaps vertically with the second conductive plate (118). The gate dielectric film (142) may include a portion covering the sidewall of the channel region (144) at a level higher than the first conductive plate (114) and a portion covering the bottom surface of the channel region (144) at a level lower than the first conductive plate (114). The channel region (144) may be spaced apart from the substrate (110) with the lowest portion of the gate dielectric film (142) in between. The side wall of the channel area (144) may be configured to be in contact with the first conductive plate (114) and electrically connected to the first conductive plate (114).

[0052] As illustrated in FIGS. 6c and 6e, the channel region (144) may have a cylindrical shape. The channel region (144) may include doped polysilicon or undoped polysilicon.

[0053] The buried insulating film (146) can fill the internal space of the channel region (144). The buried insulating film (146) may be made of an insulating material. For example, the buried insulating film (146) may be made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the buried insulating film (146) may be omitted. In this case, the channel region (144) may have a pillar structure without an internal space.

[0054] The drain region (148) may be made of a doped polysilicon film. Multiple drain regions (148) may be mutually insulated by a first upper insulating film (UL1) covering the second stack (STB). In the memory cell region (MEC), a second upper insulating film (UL2) and a third upper insulating film (UL3) may be formed sequentially on the multiple channel structures (140) and the first upper insulating film (UL1).

[0055] The string select line cut structure (SSLC) can penetrate the first upper insulating film (UL1), the second upper insulating film (UL2), and the third upper insulating film (UL3) in a vertical direction (Z direction). The upper surface of the string select line cut structure (SSLC), the upper surface of the word line cut structure (WLC), and the upper surface of the second upper insulating film (UL2) can extend at approximately the same vertical level. A fourth upper insulating film (UL4) and a fifth upper insulating film (UL5) can be formed sequentially on the string select line cut structure (SSLC), the word line cut structure (WLC), and the third upper insulating film (UL3). The first upper insulating film (UL1), the second upper insulating film (UL2), the third upper insulating film (UL3), the fourth upper insulating film (UL4), and the fifth upper insulating film (UL5) can each be made of an oxide film, a nitride film, or a combination thereof.

[0056] As illustrated in FIGS. 5 and 6c, a plurality of bit lines (BL) may be disposed on a fifth upper insulating film (UL5) in the memory cell region (MEC) of a memory stack structure (MST). The plurality of bit lines (BL) may be extended parallel to each other along a second horizontal direction (Y direction). A plurality of channel structures (140) may be connected to the plurality of bit lines (BL) through a plurality of contact plugs (176) that penetrate the second upper insulating film (UL2), the third upper insulating film (UL3), the fourth upper insulating film (UL4), and the fifth upper insulating film (UL5), respectively.

[0057] As illustrated in FIGS. 6a and 6b, in a connection region (CON), an insulating plate (112) and a second conductive plate (118) may be sequentially stacked on a substrate (110). The insulating plate (112) may have a multilayer structure comprising a first insulating film (112A), a second insulating film (112B), and a third insulating film (112C) sequentially stacked on the substrate (110). In exemplary embodiments, the first insulating film (112A) and the third insulating film (112C) may be made of silicon oxide, and the second insulating film (112B) may be made of silicon nitride.

[0058] In the connection area (CON), a conductive pad portion (130A) having a greater thickness in the vertical direction (Z direction) than other parts of the gate line (130) may be formed at one end of each of the plurality of gate lines (130) included in the first stack (STA) and the second stack (STB). The conductive pad portion (130A) may be integrally connected to the edge portion furthest from the memory cell area (MEC) among the gate lines (130). Although only the conductive pad portion (130A) connected to one end of some of the gate lines (130) among the plurality of gate lines (130) is shown in FIGS. 6a and 6b, other gate lines (130) may also be integrally connected to the conductive pad portion (130A) at other parts not visible in FIGS. 6a and 6b.

[0059] In the connection area (CON), the edge portions of each of the plurality of gate lines (130), plurality of conductive pad portions (130A), and plurality of insulating films (132) included in the first stack (STA) may be covered by a lower insulating block (133). The lower insulating block (133) may be in contact with each of the plurality of gate lines (130), plurality of conductive pad portions (130A), and plurality of insulating films (132) included in the first stack (STA). In the connection area (CON), the edge portions of each of the plurality of gate lines (130), plurality of conductive pad portions (130A), and plurality of insulating films (132) included in the second stack (STB) may be covered by an upper insulating block (137). The upper insulating block (137) may be in contact with each of the plurality of gate lines (130), plurality of conductive pad portions (130A), and plurality of insulating films (132) included in the second stack (STB). The lower insulating block (133) and the upper insulating block (137) may be made of silicon oxide film, but are not limited thereto.

[0060] As illustrated in FIGS. 5 and 6a, a plurality of memory cell contacts (MCC1, MCC2) may be disposed in the connection area (CON). Each of the plurality of memory cell contacts (MCC1, MCC2) may be configured to be electrically connected to one lower conductive pad portion (130A) selected from among a plurality of conductive pad portions (130A) included in the first stack (STA) and the second stack (STB).

[0061] A plurality of memory cell contacts (MCC1, MCC2) may include a plurality of first memory cell contacts (MCC1) and a plurality of second memory cell contacts (MCC2) having different maximum widths in the horizontal direction. In this specification, a plurality of first memory cell contacts (MCC1) may each be referred to as a first plug structure, and a plurality of second memory cell contacts (MCC2) may each be referred to as a second plug structure.

[0062] A plurality of first memory cell contacts (MCC1) may each be positioned at a location spaced apart in the horizontal direction (X direction in FIG. 6a) from the stepped connection portion (STP) included in the second stack (STB). A plurality of first memory cell contacts (MCC1) may each penetrate the stepped connection portion (STP), lower insulation block (133), first intermediate insulation film (135), second intermediate insulation film (136), and upper insulation block (137) included in the first stack (STA) in the vertical direction (Z direction), and may be configured to be electrically connected to one selected conductive pad portion (130A) among a plurality of conductive pad portions (130A) included in the first stack (STA). The width of each of the plurality of first memory cell contacts (MCC1) along the horizontal direction may have a maximum value at the vertical level where the second intermediate insulation film (136) is positioned.

[0063] A plurality of second memory cell contacts (MCC2) can each penetrate a stepped connection portion (STP) included in the second stack (STB) in a vertical direction (Z direction) and be configured to be electrically connected to one selected conductive pad portion (130A) among a plurality of conductive pad portions (130A) included in the second stack (STB).

[0064] As illustrated in FIGS. 5 and 6a, a plurality of first memory cell contacts (MCC1) may be positioned at a horizontally spaced position from a plurality of second memory cell contacts (MCC2). In the horizontal direction (e.g., X direction), the first width (W11) of the uppermost surface of each of the plurality of first memory cell contacts (MCC1) may be larger than the second width (W21) of the uppermost surface of each of the plurality of second memory cell contacts (MCC2).

[0065] As illustrated in FIG. 6a, a plurality of first memory cell contacts (MCC1) may each include a lower plug portion (CA), an upper plug portion (CB), and a plug landing portion (CL) positioned between the lower plug portion (CA) and the upper plug portion (CB). The lower plug portion (CA) is positioned at a first vertical level together with the first stack (STA) and may include a portion penetrating a stepped connection portion (STP) included in the first stack (STA). The upper plug portion (CB) is positioned at a second vertical level together with the second stack (STB) and may be surrounded by an upper insulating block (137) included in the second stack (STB). The plug landing portion (CL) is positioned at a third vertical level between the first vertical level and the second vertical level and may have the largest width among the first memory cell contacts (MCC1) in the horizontal direction. The plug landing portion (CL) may protrude horizontally from the side walls of the lower plug portion (CA) and the upper plug portion (CB), respectively. The side walls and bottom surface of the plug landing portion (CL) may be surrounded by a second intermediate insulating film (136).

[0066] At least some of the plurality of first memory cell contacts (MCC1) may include a portion surrounded by a lower insulating block (133). In each of the plurality of first memory cell contacts (MCC1), the lower plug portion (CA) may have an upper portion adjacent to the bottom surface of the plug landing portion (CL), and the upper plug portion (CB) may have a lower portion adjacent to the top surface of the plug landing portion (CL). As illustrated in FIG. 6d, in the horizontal direction (e.g., X direction), the width (W12) of the lower portion of the upper plug portion (CB) may be greater than the width (W13) of the upper portion of the lower plug portion (CA).

[0067] As illustrated in FIG. 6a, a plurality of first memory cell contacts (MCC1) and a plurality of second memory cell contacts (MCC2) may each penetrate at least a portion of a plurality of gate lines (130) and a plurality of insulating films (132). A plurality of first memory cell contacts (MCC1) and a plurality of second memory cell contacts (MCC2) may each be placed within a hole penetrating at least one of a plurality of gate lines (130). A plurality of first memory cell contacts (MCC1) and a plurality of second memory cell contacts (MCC2) may each be connected to one selected gate line (130) among the plurality of gate lines (130) and may not be connected to any other gate lines (130) other than the selected gate line (130). A plurality of first memory cell contacts (MCC1) and a plurality of second memory cell contacts (MCC2) each contact a conductive pad portion (130A) of one selected gate line (130) among a plurality of gate lines (130), and can be connected to the selected gate line (130) through the conductive pad portion (130A).

[0068] A plurality of first memory cell contacts (MCC1) and a plurality of second memory cell contacts (MCC2) may each be spaced horizontally apart from other gate lines (130) excluding the selected gate line (130). In the first stack (STA), a first insulating ring (152A) may be disposed between each of the plurality of first memory cell contacts (MCC1) and other gate lines (130) not connected thereto. In the second stack (STB), a second insulating ring (152B) may be disposed between each of the plurality of second memory cell contacts (MCC2) and other gate lines (130) not connected thereto. In exemplary embodiments, the first insulating ring (152A) and the second insulating ring (152B) may be made of silicon oxide, but are not limited thereto.

[0069] As illustrated in FIGS. 5 and 6b, a plurality of dummy channel structures (140D1, 140D2) may be disposed in the connection area (CON). The plurality of dummy channel structures (140D1, 140D2) may include a plurality of first dummy channel structures (140D1) that penetrate in a vertical direction (Z direction) the stepped connection portion (STP) included in the first stack (STA), and a plurality of second dummy channel structures (140D2) that penetrate in a vertical direction (Z direction) the stepped connection portion (STP) and the intermediate insulating film (135, 136) included in the first stack (STA) and the second stack (STB), respectively. FIG. 6b illustrates a case where a plurality of first dummy channel structures (140D1) and a plurality of second dummy channel structures (140D2) penetrate a conductive pad portion (130A) included in a stepped connection portion (STP) in a vertical direction (Z direction), but the technical concept of the present invention is not limited to what is illustrated in FIG. 6b. For example, at least some of the plurality of first dummy channel structures (140D1) and a plurality of second dummy channel structures (140D2) may penetrate in a vertical direction (Z direction) a portion of the gate line (130) that is spaced horizontally from the conductive pad portion (130A) in the connection area (CON).

[0070] In the horizontal direction, the width of each of the plurality of first dummy channel structures (140D1) and the width of each of the plurality of second dummy channel structures (140D2) may differ from each other. In this specification, the plurality of first dummy channel structures (140D1) may each be referred to as first plug structures, and the plurality of second dummy channel structures (140D2) may each be referred to as second plug structures.

[0071] As illustrated in FIGS. 5 and 6b, a plurality of first dummy channel structures (140D1) and a plurality of second dummy channel structures (140D2) may be spaced apart in a horizontal direction (e.g., X direction). In the horizontal direction (e.g., X direction), the width (W3) of the top surface of each of the plurality of first dummy channel structures (140D1) may be greater than the width (W4) of the top surface of each of the plurality of second dummy channel structures (140D2).

[0072] A plurality of first dummy channel structures (140D1) may each be positioned at a location spaced apart in the horizontal direction (X direction in FIG. 6b) from the stepped connection (STP) included in the second stack (STB). A plurality of first dummy channel structures (140D1) may each penetrate in the vertical direction (Z direction) the stepped connection (STP), lower insulation block (133), first intermediate insulation film (135), second intermediate insulation film (136), and upper insulation block (137) included in the first stack (STA). A plurality of first dummy channel structures (140D1) may each include a protrusion (PR1) having a maximum width in the horizontal direction. The side walls and bottom surfaces of the protrusion (PR1) of each of the plurality of first dummy channel structures (140D1) may be surrounded by the second intermediate insulation film (136).

[0073] A plurality of first dummy channel structures (140D1) and a plurality of second dummy channel structures (140D2) may be arranged spaced apart from each other along a first horizontal direction (X direction) and a second horizontal direction (Y direction). A plurality of first dummy channel structures (140D1) and a plurality of second dummy channel structures (140D2) may each include a gate dielectric film (142), a channel region (144), a buried insulating film (146), and a drain region (148), similar to a channel structure (140) placed in a memory cell region (MEC). However, the planar size of each of the plurality of first dummy channel structures (140D1) and a plurality of second dummy channel structures (140D2) may be larger than the planar size of the channel structure (140). The number and arrangement shape of the plurality of first dummy channel structures (140D1) and the plurality of second dummy channel structures (140D2) exemplified in FIG. 5 are merely examples, and the technical concept of the present invention is not limited thereto. In the connection area (CON), the plurality of first dummy channel structures (140D1) and the plurality of second dummy channel structures (140D2) can be arranged in various arrangements at various locations selected in the memory stack structure (MST).

[0074] As illustrated in FIGS. 6a and 6b, the upper insulating block (137) in the connection area (CON) may be covered with a first upper insulating film (UL1). The drain area (148) of each of the plurality of first dummy channel structures (140D1) and the plurality of second dummy channel structures (140D2) may be mutually insulated by the first upper insulating film (UL1). In the connection area (CON), the plurality of first dummy channel structures (140D1) and the plurality of second dummy channel structures (140D2) may be covered with a second upper insulating film (UL2).

[0075] As illustrated in FIGS. 5 and 6a, a conductive plate contact (164) may be disposed in the connection area (CON). The conductive plate contact (164) may extend vertically (Z direction) to the substrate (110) through the fourth upper insulating layer (UL4), the third upper insulating layer (UL3), the second upper insulating layer (UL2), the first upper insulating layer (UL1), the upper insulating block (137), the intermediate insulating layers (135, 136), the lower insulating block (133), the second conductive plate (118), and the insulating plate (112). The sidewalls of the conductive plate contact (164) may be covered with an insulating spacer (162). The insulating spacer (162) may be made of a silicon oxide film.

[0076] A plurality of first memory cell contacts (MCC1) and a plurality of second memory cell contacts (MCC2) may each include a portion penetrating the fourth upper insulating film (UL4), the third upper insulating film (UL3), the second upper insulating film (UL2), and the first upper insulating film (UL1).

[0077] A plurality of first memory cell contacts (MCC1), a plurality of second memory cell contacts (MCC2), and a conductive plate contact (164) can each be connected to one of a plurality of upper wiring layers (UML) through a contact plug (172) penetrating a fifth upper insulating film (UL5). A plurality of upper wiring layers (UML) can be placed at the same vertical level as a plurality of bit lines (BL) placed in a memory cell region (MEC). The space between each of the plurality of upper wiring layers (UML) and the plurality of bit lines (BL) can be filled with a sixth upper insulating film (UL6). The sixth upper insulating film (UL6) can be made of an oxide film, a nitride film, or a combination thereof.

[0078] In exemplary embodiments, a plurality of first memory cell contacts (MCC1), a plurality of second memory cell contacts (MCC2), a conductive plate contact (164), a plurality of contact plugs (172), a plurality of contact plugs (176), a plurality of upper wiring layers (UML), and a plurality of bit lines (BL) may each be made of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof, but are not limited thereto.

[0079] According to the semiconductor device (100) described with reference to FIGS. 4 to 6e, in order to improve the integration density of the semiconductor device (100), the number of stacks in the vertical direction (Z direction) of the gate line (130) constituting the memory stack structure (MST) is increased, and accordingly, even when the cell array structure (CAS) includes a plurality of stacks including a first stack (STA) and a second stack (STB), plug structures having various cross-sectional shapes and planar sizes depending on the location in the connection area (CON) of the cell array structure (CAS) include, for example, a plurality of first memory cell contacts (MCC1) and a plurality of second memory cell contacts (MCC2) having different maximum widths in the horizontal direction, and a plurality of first dummy channel structures (140D1) and a plurality of second dummy channel structures (140D2) having different maximum widths in the horizontal direction. Accordingly, when forming holes with a relatively large aspect ratio to form the plug structures, even when various films having different etching characteristics under given etching conditions must be etched, by forming various holes having different cross-sectional shapes and different planar sizes in regions with different etching environments on the substrate (110), the manufacturing process of the semiconductor device (100) can be facilitated and the electrical characteristics and reliability of the semiconductor device (100) can be maintained.

[0080] FIG. 7 is a cross-sectional view for explaining a semiconductor device (200A) according to other embodiments of the technical concept of the present invention. FIG. 7 illustrates some components of the region corresponding to the region indicated as "EX1" in FIG. 6a.

[0081] Referring to FIG. 7, the semiconductor device (200A) may have a configuration generally identical to that of the semiconductor device (100) described with reference to FIGS. 4 through 6e. However, the semiconductor device (200A) may include a first memory cell contact (MCCA) instead of a first memory cell contact (MCC1).

[0082] The first memory cell contact (MCCA) may have a configuration generally identical to that described for the first memory cell contact (MCC1) illustrated in FIG. 5 and 6a. However, the first memory cell contact (MCCA) includes a plug landing portion (L21) positioned between a lower plug portion (CA) and an upper plug portion (CB).

[0083] The horizontal width of the plug landing section (L21) may be variable along the vertical direction (Z direction). For example, the horizontal width of the plug landing section (L21) may have a width that gradually decreases as it approaches the lower plug section (CA), and the cross-section may have an inverted trapezoidal shape.

[0084] FIG. 8 is a cross-sectional view for illustrating a semiconductor device (200B) according to another embodiment of the technical concept of the present invention. FIG. 8 illustrates some components of the region corresponding to the region labeled "EX1" in FIG. 6a.

[0085] Referring to FIG. 8, the semiconductor device (200B) may have a configuration generally identical to that of the semiconductor device (100) described with reference to FIG. 4 through 6e. However, the semiconductor device (200B) may include a first memory cell contact (MCCB) instead of a first memory cell contact (MCC1).

[0086] The first memory cell contact (MCCB) may have a configuration generally identical to that described for the first memory cell contact (MCC1) illustrated in FIG. 5 and 6a. However, the first memory cell contact (MCCB) includes a plug landing portion (L22) positioned between a lower plug portion (CA) and an upper plug portion (CB).

[0087] The horizontal width of the plug landing portion (L22) may be variable along the vertical direction (Z direction). For example, the horizontal width of the plug landing portion (L22) may have a width that gradually decreases as it approaches the lower plug portion (CA), and the cross-section may have a semicircular shape.

[0088] FIG. 9 is a cross-sectional view illustrating a semiconductor device (300) according to another embodiment of the technical concept of the present invention. FIG. 9 illustrates some components of a portion corresponding to the cross-section along line X2 - X2' of FIG. 5.

[0089] Referring to FIG. 9, the semiconductor device (300) may have a configuration generally identical to that of the semiconductor device (100) described with reference to FIGS. 4 to 6e. However, the semiconductor device (300) includes a plurality of first dummy channel structures (340D1) and a plurality of second dummy channel structures (340D2) instead of a plurality of first dummy channel structures (140D1) and a plurality of second dummy channel structures (140D2).

[0090] A plurality of first dummy channel structures (340D1) and a plurality of second dummy channel structures (340D2) may have a configuration generally identical to that described for a plurality of first dummy channel structures (140D1) and a plurality of second dummy channel structures (140D2). However, a plurality of first dummy channel structures (340D1) and a plurality of second dummy channel structures (340D2) may each include a dummy insulating structure (342) instead of the gate dielectric film (142), channel region (144), and buried insulating film (146) illustrated in FIG. 6b. In exemplary embodiments, a drain region (148) may be omitted in each of a plurality of first dummy channel structures (340D1) and a plurality of second dummy channel structures (340D2).

[0091] In the horizontal direction, the width of each of the plurality of first dummy channel structures (340D1) and the width of each of the plurality of second dummy channel structures (340D2) may differ from each other. In this specification, the plurality of first dummy channel structures (340D1) may each be referred to as first plug structures, and the plurality of second dummy channel structures (340D2) may each be referred to as second plug structures. The plurality of first dummy channel structures (340D1) and the plurality of second dummy channel structures (340D2) may be spaced apart in the horizontal direction (e.g., X direction). In the horizontal direction (e.g., X direction), the width (W33) of the top surface of each of the plurality of first dummy channel structures (340D1) may be greater than the width (W34) of the top surface of each of the plurality of second dummy channel structures (340D2).

[0092] A dummy insulation structure (342) included in a plurality of first dummy channel structures (340D1) may include a protrusion (PR31) having a maximum width in the horizontal direction. The side walls and bottom surface of the protrusion (PR31) may be surrounded by a second intermediate insulating film (136). In exemplary embodiments, the dummy insulation structure (342) may be made of silicon oxide, but is not limited thereto.

[0093] FIGS. 10a, FIG. 10b, and FIG. 10c are cross-sectional views for explaining a semiconductor device (400) according to other embodiments of the technical concept of the present invention, FIG. 10a is a cross-sectional view of some components of a portion corresponding to the cross-section along the line X1 - X1' of FIG. 5, FIG. 10b is a cross-sectional view of some components of a portion corresponding to the cross-section along the line X2 - X2' of FIG. 5, and FIG. 10c is a cross-sectional view of some components of a portion corresponding to the cross-section along the line Y1 - Y1' of FIG. 5. In FIG. 10a, FIG. 10b, and FIG. 10c, the same reference numerals as in FIG. 6a to FIG. 6c indicate the same components, and a detailed description thereof is omitted here.

[0094] Referring to FIGS. 10a, 10b, and 10c, the semiconductor device (400) may have a configuration generally identical to that of the semiconductor device (100) described with reference to FIGS. 4 through 6e. However, the semiconductor device (400) may include a cell array structure (CAS) and a peripheral circuit structure (PCS) that overlap each other in the vertical direction (Z direction). The cell array structure (CAS) may include a memory cell array (20) described with reference to FIG. 1. The peripheral circuit structure (PCS) may include a peripheral circuit (30) described with reference to FIG. 1. The cell array structure (CAS) may have a configuration generally identical to that described with reference to FIG. 5 and FIGS. 6a through 6e.

[0095] A peripheral circuit structure (PCS) may include a lower substrate (52), a plurality of peripheral circuits formed on the lower substrate (52), and a multilayer wiring structure (MWS) for interconnecting the plurality of peripheral circuits or connecting the plurality of peripheral circuits to components in a memory cell region (MEC).

[0096] The lower substrate (52) may be made of a semiconductor substrate. For example, the lower substrate (52) may include Si, Ge, or SiGe. An active region (AC) may be defined on the lower substrate (52) by a device isolation film (54). A plurality of transistors (TR) constituting a plurality of peripheral circuits may be formed on the active region (AC). Each of the plurality of transistors (TR) may include a gate (PG) and a plurality of ion implantation regions (PSD) formed within the active region (AC) on both sides of the gate (PG). Each of the plurality of ion implantation regions (PSD) may constitute a source region or a drain region of the transistor (TR).

[0097] A plurality of peripheral circuits included in the peripheral circuit structure (PCS) may include various circuits included in the peripheral circuit (30) described with reference to FIG. 1. In exemplary embodiments, a plurality of peripheral circuits included in the peripheral circuit structure (PCS) may include a row decoder (32), a page buffer (34), a data input / output circuit (36), control logic (38), and a common source line driver (39) as illustrated in FIG. 1.

[0098] A multilayer wiring structure (MWS) included in a peripheral circuit structure (PCS) may include a plurality of peripheral circuit wiring layers (ML60, ML61, ML62) and a plurality of peripheral circuit contacts (MC60, MC61, MC62). At least some of the plurality of peripheral circuit wiring layers (ML60, ML61, ML62) may be configured to be electrically connectable to a transistor (TR). The plurality of peripheral circuit contacts (MC60, MC61, MC62) may be configured to interconnect a selected portion of the plurality of transistors (TR) and the plurality of peripheral circuit wiring layers (ML60, ML61, ML62).

[0099] Although FIGS. 10a, 10b, and 10c illustrate a multilayer wiring structure (MWS) having three wiring layers along the vertical direction (Z direction), the technical concept of the present invention is not limited to what is illustrated in FIGS. 10a, 10b, and 10c. For example, the multilayer wiring structure (MWS) may have two layers or four or more wiring layers.

[0100] A plurality of peripheral circuit wiring layers (ML60, ML61, ML62) and a plurality of peripheral circuit contacts (MC60, MC61, MC62) may each be made of a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, a plurality of peripheral circuit wiring layers (ML60, ML61, ML62) and a plurality of peripheral circuit contacts (MC60, MC61, MC62) may each include a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, or nickel silicide.

[0101] A plurality of transistors (TR) and multilayer wiring structures (MWS) included in the peripheral circuit structure (PCS) can be covered with an interlayer insulating film (70). The interlayer insulating film (70) may include silicon oxide, SiON, SiOCN, etc.

[0102] As illustrated in FIG. 10a and FIG. 10b, a substrate (110) is placed on a peripheral circuit structure (PCS) in a connection area (CON) of a cell array structure (CAS), and an insulating plate (112), a second conductive plate (118), a first stack (STA), and a second stack (STB) can be stacked in sequence on the substrate (110).

[0103] As illustrated in FIG. 10c, a substrate (110) is placed on a peripheral circuit structure (PCS) in the memory cell region (MEC) of a cell array structure (CAS), and a first conductive plate (114), a second conductive plate (118), a first stack (STA), and a second stack (STB) can be stacked in sequence on the substrate (110).

[0104] FIG. 11 is a schematic plan view of some components of memory cell blocks (BLK51, BLK52) included in a semiconductor device (500) according to other embodiments of the technical concept of the present invention. FIG. 12 is a cross-sectional view showing the configurations along the X3 - X3' and X4 - X4' lines of FIG. 11. In FIG. 11 and FIG. 12, the same reference numerals as in FIG. 5 and FIG. 6a through 6c indicate the same components, and a detailed description thereof is omitted here.

[0105] Referring to FIGS. 10 and 11, the semiconductor device (500) may have a configuration generally identical to that of the semiconductor device (100) described with reference to FIGS. 4 to 6e. However, the semiconductor device (500) may further include memory cell blocks (BLK51, BLK52). The memory cell blocks (BLK51, BLK52) may include a plurality of through-electrode regions (TA1, TA2) comprising a plurality of through-electrodes (THV1, THV2) in a connection region (CON).

[0106] A plurality of penetrating electrode regions (TA1, TA2) may include a plurality of first penetrating electrode regions (TA1) and a plurality of second penetrating electrode regions (TA2) that are spaced apart from each other in the horizontal direction. Each of the plurality of first penetrating electrode regions (TA1) may include a plurality of first penetrating electrodes (THV1), and each of the plurality of second penetrating electrode regions (TA2) may include a plurality of second penetrating electrodes (THV2). In the present specification, each of the plurality of first penetrating electrodes (THV1) may be referred to as a first plug structure, and each of the plurality of second penetrating electrodes (THV2) may be referred to as a second plug structure.

[0107] A plurality of first penetrating electrodes (THV1) may each penetrate the stepped connection portion (STP) included in the first stack (STA) in the vertical direction (Z direction) and may not penetrate the stepped connection portion (STP) included in the second stack (STB). A plurality of second penetrating electrodes (THV2) may each penetrate the stepped connection portion (STP) included in the first stack (STA) and the stepped connection portion (STP) included in the second stack (STB) in the vertical direction (Z direction). A plurality of first penetrating electrodes (THV1) and a plurality of second penetrating electrodes (THV2) may each be configured not to be electrically connected to the gate line (130) and the conductive pad portion (130A) included in the first stack (STA) and the second stack (STB), respectively.

[0108] A plurality of first through electrodes (THV1) may each be positioned at a location spaced apart in the horizontal direction (e.g., X direction) from the stepped connection (STP) included in the second stack (STB). The width of each of the plurality of first through electrodes (THV1) along the horizontal direction may have a maximum value at the vertical level where the second intermediate insulating film (136) is positioned.

[0109] A plurality of first penetrating electrodes (THV1) may be positioned at a location spaced apart in the horizontal direction from a plurality of second penetrating electrodes (THV2). In the horizontal direction (e.g., X direction), the first width (W51) of the uppermost surface of each of the plurality of first penetrating electrodes (THV1) may be larger than the second width (W51) of the uppermost surface of each of the plurality of second penetrating electrodes (THV2).

[0110] As illustrated in FIG. 12, a plurality of first through electrodes (THV1) may each include a lower plug portion (TA), an upper plug portion (TB), and a plug landing portion (TL) positioned between the lower plug portion (TA) and the upper plug portion (TB). The lower plug portion (TA) may be positioned at a first vertical level together with the first stack (STA) and may include a portion penetrating a stepped connection portion (STP) included in the first stack (STA). The upper plug portion (TB) may be positioned at a second vertical level together with the second stack (STB) and may be surrounded by an upper insulating block (137) included in the second stack (STB). The plug landing portion (TL) may be positioned at a third vertical level between the first vertical level and the second vertical level and may have the largest width among the first through electrodes (THV1) in the horizontal direction. The plug landing portion (TL) may protrude horizontally from the side walls of the lower plug portion (TA) and the upper plug portion (TB), respectively. The side walls and bottom surface of the plug landing portion (TL) may be surrounded by a second intermediate insulating film (136).

[0111] At least some of the plurality of first through electrodes (THV1) may include a portion surrounded by a lower insulating block (133). In each of the plurality of first through electrodes (THV1), the lower plug portion (TA) may have an upper portion adjacent to the bottom surface of the plug landing portion (TL), and the upper plug portion (TB) may have a lower portion adjacent to the top surface of the plug landing portion (TL). As illustrated in FIG. 12, in the horizontal direction (e.g., X direction), the width (W53) of the lower portion of the upper plug portion (TB) may be greater than the width (W54) of the upper portion of the lower plug portion (TA).

[0112] As illustrated in FIG. 12, a plurality of first through electrodes (THV1) and a plurality of second through electrodes (THV2) may each penetrate at least a portion of a plurality of gate lines (130) and a plurality of insulating films (132). A plurality of first through electrodes (THV1) and a plurality of second through electrodes (THV2) may each be disposed within a hole penetrating at least one of a plurality of gate lines (130). A plurality of first through electrodes (THV1) and a plurality of second through electrodes (THV2) may each not be connected to a gate line (130). A plurality of first through electrodes (THV1) and a plurality of second through electrodes (THV2) may each be spaced apart horizontally from a gate line (130). A plurality of first penetrating electrodes (THV1) and a plurality of second penetrating electrodes (THV2) may each be made of tungsten, titanium, tantalum, copper, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof, but are not limited to these.

[0113] A first insulating ring (152A) may be disposed between a plurality of first through-electrodes (THV1) and an adjacent gate line (130) in the first stack (STA). A second insulating ring (152B) may be disposed between a plurality of second through-electrodes (THV2) and an adjacent gate line (130) in the second stack (STB). The detailed configuration of the first insulating ring (152A) and the second insulating ring (152B) is as described with reference to FIG. 6a.

[0114] FIG. 13 is a cross-sectional view for illustrating a semiconductor device (500A) according to another embodiment of the technical concept of the present invention. FIG. 13 illustrates some components of parts corresponding to the cross-section along the X3 - X3' and X4 - X4' lines of FIG. 11.

[0115] Referring to FIG. 13, the semiconductor device (500A) may have a configuration generally identical to that of the semiconductor device (500) described with reference to FIG. 11 and FIG. 12. However, the semiconductor device (500A) may include a cell array structure (CAS) and a peripheral circuit structure (PCS) that overlap each other in the vertical direction (Z direction). The cell array structure (CAS) may include a memory cell array (20) described with reference to FIG. 1. The peripheral circuit structure (PCS) may include a peripheral circuit (30) described with reference to FIG. 1. The cell array structure (CAS) may have a configuration generally identical to that described with reference to FIG. 5 and FIG. 6a through 6e. The peripheral circuit structure (PCS) may have a configuration generally identical to that described with reference to FIG. 10a through 10c.

[0116] A plurality of through-openings (120H) penetrating the substrate (110), the insulating plate (112), and the second conductive plate (118) may be formed in a portion of the connection area (CON). Each of the plurality of through-openings (120H) may be filled with an insulating plug (120). The plurality of through-openings (120H) may be positioned to overlap in a vertical direction (Z direction) with a portion of the surrounding circuit structure (PCS). The insulating plug (120) may be made of a silicon oxide film, a silicon nitride film, or a combination thereof.

[0117] In the connection area (CON), a plurality of first through-hole electrodes (THV1) and a plurality of second through-hole electrodes (THV2) may each be configured to extend to a peripheral circuit structure (PCS) through a through-hole opening (120H) and be electrically connected to one selected wiring layer among a plurality of peripheral circuit wiring layers (ML60, ML61, ML62). For example, a plurality of first through-hole electrodes (THV1) and a plurality of second through-hole electrodes (THV2) may each be configured to be electrically connected to the uppermost peripheral circuit wiring layer (ML62) among the peripheral circuit wiring layers (ML60, ML61, ML62) closest to the cell array structure (CAS).

[0118] A plurality of first penetrating electrodes (THV1) and a plurality of second penetrating electrodes (THV2) can each be configured to be connected to at least one peripheral circuit selected among a plurality of peripheral circuits through a multilayer wiring structure (MWS) included in a peripheral circuit structure (PCS).

[0119] FIG. 14 is a cross-sectional view illustrating a semiconductor device (500B) according to another embodiment of the technical concept of the present invention. FIG. 14 illustrates some components of parts corresponding to the cross-section along the X3 - X3' line and the cross-section along the X4 - X4' line of FIG. 11.

[0120] Referring to FIG. 14, the semiconductor device (500B) may have a configuration generally identical to that of the semiconductor device (500) described with reference to FIG. 11 and FIG. 12. However, in the stepped connection portion (STP) included in the first stack (STA) of the semiconductor device (500B) and the stepped connection portion (STP) included in the second stack (STB), in some regions corresponding to the first through-electrode region (TA1) and the second through-electrode region (TA2), the structure may have a structure in which some regions of a plurality of gate lines (130) (refer to FIG. 6a to 6c) are replaced with a sacrificial insulating film (134). In the first through-electrode region (TA1) and the second through-electrode region (TA2), the sidewalls of each of the plurality of first through-electrodes (THV1) and the plurality of second through-electrodes (THV2) may have a structure in which they are surrounded by a plurality of insulating films (132) and a plurality of sacrificial insulating films (134). In exemplary embodiments, a plurality of sacrificial insulating films (134) may be made of silicon nitride films.

[0121] In exemplary embodiments, a dam structure (not shown) may be disposed between an insulating structure composed of a plurality of insulating films (132) and a plurality of sacrificial insulating films (134) and a plurality of gate lines (130) (see FIG. 6a to 6c). The constituent material of the dam structure is generally the same as that described for the word line cut structure (WLC) (see FIG. 6c).

[0122] FIG. 15 is a cross-sectional view illustrating a semiconductor device (500C) according to another embodiment of the technical concept of the present invention. FIG. 15 illustrates some components of parts corresponding to the cross-section along the X3 - X3' and X4 - X4' lines of FIG. 11.

[0123] Referring to FIG. 15, the semiconductor device (500C) may have a configuration generally identical to that of the semiconductor device (500B) described with reference to FIG. 14. However, the semiconductor device (500C) may include a cell array structure (CAS) and a peripheral circuit structure (PCS) that overlap each other in the vertical direction (Z direction). The cell array structure (CAS) may include a memory cell array (20) described with reference to FIG. 1. The peripheral circuit structure (PCS) may include a peripheral circuit (30) described with reference to FIG. 1. The cell array structure (CAS) may have a configuration generally identical to that described with reference to FIG. 5, FIG. 6a to 6e, and FIG. 14. The peripheral circuit structure (PCS) may have a configuration generally identical to that described with reference to FIG. 10a to 10c.

[0124] A plurality of through-holes (120H) penetrating the substrate (110), the insulating plate (112), and the second conductive plate (118) may be formed in a portion of the connection area (CON). Each of the plurality of through-holes (120H) may be filled with an insulating plug (120).

[0125] In the connection area (CON), a plurality of first through-hole electrodes (THV1) and a plurality of second through-hole electrodes (THV2) can each be configured to extend to a peripheral circuit structure (PCS) through a through-hole opening (120H) and be electrically connected to one selected wiring layer among a plurality of peripheral circuit wiring layers (ML60, ML61, ML62).

[0126] FIG. 16 is a cross-sectional view for explaining a semiconductor device (600A) according to another embodiment of the technical concept of the present invention. FIG. 16 illustrates an enlarged cross-sectional configuration of a portion corresponding to the area labeled "EX2" in FIG. 6c.

[0127] Referring to FIG. 16, the semiconductor device (600A) may have a configuration generally identical to that of the semiconductor device (100) described with reference to FIGS. 4 through 6e. However, the semiconductor device (600A) may include a gate dielectric film (142A) instead of a gate dielectric film (142). The gate dielectric film (142A) may have a configuration generally identical to that of the gate dielectric film (142) described with reference to FIGS. 6b, 6c, and 6e. However, the gate dielectric film (142A) may include a first blocking dielectric film (BD1) and a second blocking dielectric film (BD2) instead of a blocking dielectric film (BD). The first blocking dielectric film (BD1) may extend parallel to the channel region (144), and the second blocking dielectric film (BD2) may be arranged to surround the gate line (130). The first blocking dielectric film (BD1) and the second blocking dielectric film (BD2) may each be made of silicon oxide, silicon nitride, or a metal oxide. For example, the first blocking dielectric film (BD1) may be made of silicon oxide, and the second blocking dielectric film (BD2) may be made of a metal oxide with a dielectric constant greater than that of the silicon oxide film. The metal oxide may be made of hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0128] FIG. 17 is a cross-sectional view illustrating a semiconductor device (600B) according to another embodiment of the technical concept of the present invention. FIG. 17 illustrates an enlarged cross-sectional configuration of a portion corresponding to the area labeled "EX2" in FIG. 6c.

[0129] Referring to FIG. 17, the semiconductor device (600B) may have a configuration generally identical to that of the semiconductor device (100) described with reference to FIG. 4 through 6e. However, the semiconductor device (600B) may include a gate dielectric film (142A) instead of a gate dielectric film (142). The gate dielectric film (142A) may include a first blocking dielectric film (BD1) and a second blocking dielectric film (BD2). A more detailed configuration of the first blocking dielectric film (BD1) and the second blocking dielectric film (BD2) is described with reference to FIG. 16.

[0130] The semiconductor device (600B) may include a ground select gate line (630) disposed between a substrate (110) and a plurality of gate lines (130). Additionally, the semiconductor device (600B) may include a channel region (644) instead of the channel region (144) of the semiconductor device (100). The channel region (644) may include a lower semiconductor pattern (644A) and an upper semiconductor pattern (644B). The lower semiconductor pattern (644A) may be composed of a semiconductor material layer epitaxially grown from the substrate (110). The lower semiconductor pattern (644A) may have a pillar shape, and the upper surface of the lower semiconductor pattern (644A) may be located above the upper surface of the lowest ground select gate line (630). The upper semiconductor pattern (644B) and the lower semiconductor pattern (644A) may be in contact with each other. The lower semiconductor pattern (644A) may each be made of Si, Ge, or a combination thereof. The upper semiconductor pattern (644B) may have a configuration generally identical to that described for the channel region (144) with reference to FIGS. 6b, 6c, and 6e.

[0131] The ground selection gate line (630) may be surrounded by a second blocking dielectric film (BD2). A gate dielectric film (650) may be interposed between the ground selection gate line (630) and the lower semiconductor pattern (644A), and between the second blocking dielectric film (BD2) and the lower semiconductor pattern (644A).

[0132] FIG. 18 is a cross-sectional view for explaining a semiconductor device (600C) according to another embodiment of the technical concept of the present invention. FIG. 18 illustrates an enlarged cross-sectional configuration of a portion corresponding to the area marked "EX2" in FIG. 6c.

[0133] Referring to FIG. 18, the semiconductor device (600C) may have a configuration largely identical to that described with reference to FIG. 17. However, the semiconductor device (600C) may not include the lower semiconductor pattern (644A) exemplified in FIG. 17. The semiconductor device (600C) may include a channel region (644C) instead of the channel region (144) of the semiconductor device (100). The lower portion of the channel region (644C) may be in contact with the substrate (110). A gate dielectric film (142A) may be interposed between the channel region (644C) and the ground select gate line (630).

[0134] FIGS. 19a and FIGS. 19b are cross-sectional views for explaining a semiconductor device (700) according to other embodiments of the technical concept of the present invention, FIG. 19a is a cross-sectional view of some components of a portion corresponding to the cross-section along the line X1 - X1' of FIG. 5, and FIG. 19b is a cross-sectional view of some components of a portion corresponding to the cross-section along the line X2 - X2' of FIG. 5. In FIGS. 19a and FIG. 19b, the same reference numerals as in FIGS. 6a to 6c indicate the same components, and a detailed description thereof is omitted here.

[0135] Referring to FIGS. 19a and 19b, the semiconductor device (700) may have a configuration generally identical to that of the semiconductor device (100) described with reference to FIGS. 4 through 6e. However, the semiconductor device (700) may include a first stack (STA) disposed on a substrate (110), a second stack (STB) disposed on the first stack (STA), and a third stack (STC) disposed on the second stack (STB). An intermediate insulating film (135, 136) may be interposed between the first stack (STA) and the second stack (STB), and an intermediate insulating film (735, 736) may be interposed between the second stack (STB) and the third stack (STC). The intermediate insulating film (735, 736) may include a first intermediate insulating film (735) and a second intermediate insulating film (736) stacked sequentially on the second stack (STB). The first intermediate insulating layer (735) and the second intermediate insulating layer (736) may each be made of silicon oxide.

[0136] The detailed configuration of the first stack (STA) and the second stack (STB) is as described with reference to FIGS. 6a through 6c. The third stack (STC) may include a plurality of gate lines (130) that overlap each other along the vertical direction (Z direction) in the memory cell region (MEC) (see FIG. 5), and a stepped connection portion (STP) having a plurality of conductive pad portions (130A) disposed in the connection region (CON) and integrally connected to the plurality of gate lines (130). Each edge portion of the plurality of gate lines (130), the plurality of conductive pad portions (130A), and the plurality of insulating films (132) included in the third stack (STC) may be covered by an insulating block (139). The insulating block (139) may contact the plurality of gate lines (130), the plurality of conductive pad portions (130A), and the plurality of insulating films (132) included in the third stack (STC), respectively. The insulating block (139) may be made of silicon oxide, but is not limited thereto. The first stack (STA), the second stack (STB), and the third stack (STC) may form the cell array structure (CAS) illustrated in FIG. 4.

[0137] As illustrated in FIG. 19a, a plurality of memory cell contacts (MCC71, MCC72, MCC73) may be disposed in the connection area (CON). Each of the plurality of memory cell contacts (MCC71, MCC72, MCC73) may be configured to be electrically connected to one lower conductive pad portion (130A) selected from among a plurality of conductive pad portions (130A) included in the first stack (STA), the second stack (STB), and the third stack (STC).

[0138] A plurality of memory cell contacts (MCC71, MCC72, MCC73) may include a plurality of first memory cell contacts (MCC71) that penetrate a stepped connection portion (STP) included in a first stack (STA) in a vertical direction (Z direction) and are spaced horizontally from a second stack (STB) and a third stack (STC); a plurality of second memory cell contacts (MCC72) that penetrate a stepped connection portion (STP) included in a second stack (STB) in a vertical direction (Z direction) and are spaced horizontally from a third stack (STC); and a plurality of third memory cell contacts (MCC73) that penetrate a stepped connection portion (STP) included in a third stack (STC) in a vertical direction (Z direction).

[0139] The width along the horizontal direction of each of the plurality of first memory cell contacts (MCC71) may have a maximum value at the vertical level where the second intermediate insulating film (1366) is placed. The width along the horizontal direction of each of the plurality of second memory cell contacts (MCC72) may have a maximum value at the vertical level where the second intermediate insulating film (736) is placed. In the horizontal direction (e.g., X direction), the width (W71) of the top surface of each of the plurality of first memory cell contacts (MCC71) and the width (W72) of the top surface of each of the plurality of second memory cell contacts (MCC72) may be greater than the width (W73) of the top surface of each of the plurality of third memory cell contacts (MCC73).

[0140] A plurality of first memory cell contacts (MCC71) may each include a lower plug portion (CA), an upper plug portion (CB1), and a plug landing portion (CL1) positioned between the lower plug portion (CA) and the upper plug portion (CB1). The lower plug portion (CA) may be positioned at the same vertical level as the first stack (STA) and may include a portion penetrating the stepped connection portion (STP) included in the first stack (STA). The upper plug portion (CB1) may be positioned at the same vertical level as the second stack (STB) and the third stack (ST3) and may include portions surrounded by the upper insulating block (137) included in the second stack (STB) and the insulating block (139) included in the third stack (ST3). The upper plug portion (CB1) may include a side wall portion that is folded at a portion adjacent to the upper surface of the second intermediate insulating film (736). The plug landing portion (CL1) of the first memory cell contact (MCC71) may have the greatest width in the horizontal direction. The plug landing portion (CL1) may protrude horizontally from the side walls of the lower plug portion (CA) and the upper plug portion (CB1), respectively. The side walls and bottom surface of the plug landing portion (CL1) may be surrounded by the second intermediate insulating film (136).

[0141] In each of the plurality of first memory cell contacts (MCC71), the lower plug portion (CA) may have an upper portion adjacent to the bottom surface of the plug landing portion (CL1), and the upper plug portion (CB1) may have a lower portion adjacent to the top surface of the plug landing portion (CL1). In the horizontal direction (e.g., X direction), the width of the lower portion of the upper plug portion (CB1) may be greater than the width of the upper portion of the lower plug portion (CA).

[0142] Each of the multiple second memory cell contacts (MCC72) may include a lower plug portion (CB2), an upper plug portion (CC), and a plug landing portion (CL2) positioned between the lower plug portion (CB2) and the upper plug portion (CC). The lower plug portion (CB2) may be positioned at the same vertical level as the second stack (STB) and may include a portion penetrating the stepped connection portion (STP) included in the second stack (STB). The upper plug portion (CC) may be positioned at the same vertical level as the third stack (STC) and may be surrounded by an insulating block (139) included in the third stack (STC). Among the second memory cell contacts (MCC72), the plug landing portion (CL2) may have the largest width in the horizontal direction. The plug landing portion (CL2) may protrude horizontally from the side walls of the lower plug portion (CB2) and the upper plug portion (CC), respectively. The side walls and bottom surface of the plug landing section (CL2) can be surrounded by a second intermediate insulating film (736).

[0143] A plurality of first memory cell contacts (MCC71), a plurality of second memory cell contacts (MCC72), and a plurality of third memory cell contacts (MCC73) are each disposed within a hole penetrating at least one of a plurality of gate lines (130) and can be connected to one gate line (130) selected from the plurality of gate lines (130). A plurality of first memory cell contacts (MCC71), a plurality of second memory cell contacts (MCC72), and a plurality of third memory cell contacts (MCC73) may not be connected to any other gate line (130) other than the selected gate line (130). A plurality of first memory cell contacts (MCC71), a plurality of second memory cell contacts (MCC72), and a plurality of third memory cell contacts (MCC73) each contact a conductive pad portion (130A) of one selected gate line (130) among a plurality of gate lines (130), and can be connected to the selected gate line (130) through the conductive pad portion (130A).

[0144] A plurality of first memory cell contacts (MCC71), a plurality of second memory cell contacts (MCC72), and a plurality of third memory cell contacts (MCC73) may each be spaced horizontally apart from other gate lines (130) excluding the selected gate line (130). In the first stack (STA), a first insulating ring (152A) may be placed between a plurality of first memory cell contacts (MCC71) and other gate lines (130) not connected thereto. In the second stack (STB), a second insulating ring (152B) may be placed between a plurality of second memory cell contacts (MCC72) and other gate lines (130) not connected thereto. In the third stack (STC), a third insulating ring (152C) may be placed between a plurality of third memory cell contacts (MCC73) and other gate lines (130) not connected thereto. In exemplary embodiments, the first insulating ring (152A), the second insulating ring (152B), and the third insulating ring (152C) may be made of silicon oxide, but are not limited thereto.

[0145] As illustrated in FIG. 19b, a plurality of dummy channel structures (740D1, 740D2, 740D3) may be arranged in a connection area (CON). The plurality of dummy channel structures (740D1, 740D2, 740D3) may include a plurality of first dummy channel structures (740D1), a plurality of second dummy channel structures (740D2), and a plurality of third dummy channel structures (740D3) spaced apart from each other in the horizontal direction.

[0146] A plurality of first dummy channel structures (740D1) can penetrate in a vertical direction (Z direction) the stepped connection (STP) included in the first stack (STA), the intermediate insulating film (135, 136, 735, 736), the upper insulating block (137) included in the second stack (STB), and the insulating block (139) included in the third stack (STC) at a position spaced horizontally from the second stack (STB) and the third stack (STC).

[0147] A plurality of second dummy channel structures (740D2) can penetrate in the vertical direction (Z direction) the stepped connection (STP), intermediate insulating film (135, 136, 735, 736), and insulating block (139) included in the first stack (STA) and the second stack (STB), respectively, at a position spaced horizontally from the third stack (STC).

[0148] Multiple third dummy channel structures (740D3) can penetrate the stepped connection (STP) and intermediate insulating film (135, 136, 735, 736) included in each of the first stack (STA), second stack (STB), and third stack (STC) in the vertical direction (Z direction).

[0149] FIG. 19b illustrates a case in which a plurality of first dummy channel structures (740D1), a plurality of second dummy channel structures (740D2), and a third dummy channel structure (740D3) penetrate a conductive pad portion (130A) included in a stepped connection portion (STP) in a vertical direction (Z direction), but the technical concept of the present invention is not limited to what is illustrated in FIG. 19b. For example, at least some of the plurality of first dummy channel structures (740D1), a plurality of second dummy channel structures (740D2), and a third dummy channel structure (740D3) may penetrate in a vertical direction (Z direction) a portion of the gate line (130) that is spaced horizontally from the conductive pad portion (130A) in the connection area (CON).

[0150] In the horizontal direction, the widths of each of the plurality of first dummy channel structures (740D1), the plurality of second dummy channel structures (740D2), and the third dummy channel structures (740D3) may differ from each other. In the horizontal direction (e.g., X direction), the width (W74) of the top surface of each of the plurality of first dummy channel structures (740D1) and the width (W75) of the top surface of each of the plurality of second dummy channel structures (740D2) may be greater than the width (W76) of the top surface of each of the plurality of third dummy channel structures (740D3).

[0151] A plurality of first dummy channel structures (740D1) may each include a protrusion (PR71) having a maximum width in the horizontal direction. The side walls and bottom surface of the protrusion (PR71) may be surrounded by a second intermediate insulating film (136). A plurality of second dummy channel structures (740D2) may each include a protrusion (PR72) having a maximum width in the horizontal direction. The side walls and bottom surface of the protrusion (PR72) may be surrounded by a second intermediate insulating film (736).

[0152] As illustrated in FIG. 19a, a conductive plate contact (764) may be disposed in the connection area (CON). The conductive plate contact (764) may have a configuration generally identical to that described for the conductive plate contact (164) with reference to FIG. 6a. However, the conductive plate contact (764) may extend vertically (Z direction) to the substrate (110) through the fourth upper insulating film (UL4), the third upper insulating film (UL3), the second upper insulating film (UL2), the first upper insulating film (UL1), the insulating block (139), the upper insulating block (137), the intermediate insulating films (135, 136, 735, 736), the lower insulating block (133), the second conductive plate (118), and the insulating plate (112). The sidewalls of the conductive plate contact (764) may be covered with insulating spacers (762).

[0153] The constituent materials of the conductive plate contact (764) and the insulating spacer (762), respectively, are as described for the conductive plate contact (164) and the insulating spacer (162) with reference to FIG. 6a.

[0154] Next, a method for manufacturing a semiconductor device according to embodiments based on the technical concept of the present invention will be described in detail.

[0155] FIGS. 20a to 28 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. In particular, FIGS. 20a, 21a, 22a, 23a, 24a, 25a, 26a, 27a, and 28 are cross-sectional views according to the process sequence of some components of a part corresponding to the X1 - X1' line cross-section of FIGS. 5, FIGS. 20b, 21b, 22b, 23b, 24b, 25b, 26b, and 27b are cross-sectional views according to the process sequence of some components of a part corresponding to the X2 - X2' line cross-section of FIGS. 5, and FIGS. 20c, 23c, 26c, and 27c are cross-sectional views according to the process sequence of some components of a part corresponding to the Y1 - Y1' line cross-section of FIGS. 5. An exemplary method of manufacturing a semiconductor device (100) described with reference to FIGS. 20a to 28 and FIGS. 4 to 6e is described.

[0156] Referring to FIGS. 20a, 20b, and 20c, an insulating plate (112) and a second conductive plate (118) can be formed sequentially on a substrate (110) in a memory cell region (MEC) and a connection region (CON). The insulating plate (112) may be made of an insulating film having a multilayer structure including a first insulating film (112A), a second insulating film (112B), and a third insulating film (112C).

[0157] In the memory cell region (MEC) and connection region (CON), a plurality of insulating films (132) and a plurality of sacrificial insulating films (134) can be alternately stacked one by one on the second conductive plate (118). The plurality of insulating films (132) may be made of silicon oxide, and the plurality of sacrificial insulating films (134) may be made of silicon nitride. Each of the plurality of sacrificial insulating films (134) may serve to secure a space for forming a plurality of gate lines (130) in a subsequent process.

[0158] Referring to FIGS. 21a and 21b, after forming an etch stop layer (EST) covering the uppermost insulating layer (132) among the plurality of insulating layers (132) in the results of FIGS. 20a, 20b, and 20c, a portion of each of the plurality of insulating layers (132) and the plurality of sacrificial insulating layers (134) can be removed using a photolithography process in the connection region (CON) so that each end portion of the plurality of insulating layers (132) and the plurality of sacrificial insulating layers (134) can form a step structure (ST) having a gradually smaller width in the horizontal direction as it moves further away from the substrate (110).

[0159] Referring to FIGS. 22a and 22b, in the result of FIGS. 21a and 21b, a sacrificial pad portion (134S) having an increased thickness can be formed at one end of each of the plurality of sacrificial insulating films (134) forming a step structure (ST).

[0160] In exemplary embodiments, to form a sacrificial pad portion (134S) at one end of each of a plurality of sacrificial insulating films (134), a portion of the plurality of insulating films (132) is removed to expose one end of each of the plurality of sacrificial insulating films (134) forming a stepped structure (ST), and then an additional film made of the same material as the constituent material of the plurality of sacrificial insulating films (134) is deposited on the exposed one end of each of the plurality of sacrificial insulating films (134), and the additional film is patterned so that the sacrificial pad portion (134S) remains.

[0161] After that, a lower insulating block (133) covering the step structure (ST) and the second conductive plate (118) can be formed, and the resulting product can be flattened by a CMP process to expose the upper surface of the top insulating film (132). During the flattening process, the etching stop layer (EST) can be removed. After that, a first intermediate insulating film (135) and a second intermediate insulating film (136) covering the upper surfaces of the top insulating film (132) and the lower insulating block (133), respectively, can be formed in sequence.

[0162] Referring to FIGS. 23a, 23b, and 23c, a plurality of lower memory cell contact holes (MCH1), lower plate contact holes (PCH1), and a plurality of lower dummy channel holes (DCH1) disposed in a connection area (CON), and a plurality of lower channel holes (CH1) and a plurality of lower word line cut holes (WCH1) disposed in a memory cell area (MEC) can be formed.

[0163] After that, as illustrated in FIG. 23a, a portion of the sacrificial pad portion (134S) and the sacrificial insulating film (134) exposed inside each of the plurality of lower memory cell contact holes (MCH1) can be etched to expand the horizontal width of each of the plurality of lower memory cell contact holes (MCH1) at the same vertical level as the sacrificial insulating film (134), thereby forming a plurality of indentation spaces in which the side walls of the sacrificial pad portion (134S) and the sacrificial insulating film (134) are exposed. Among the plurality of indentation spaces, the indentation space that exposes the sacrificial insulating film (134) can be filled with a first insulating ring (152A), and the indentation space that exposes the sacrificial pad portion (134S) can be filled again with the sacrificial pad portion (134S). After that, a plurality of first sacrificial films (S1) can be formed to fill a plurality of lower memory cell contact holes (MCH1), a lower plate contact hole (PCH1), a plurality of lower dummy channel holes (DCH1), a plurality of lower channel holes (CH1), and a plurality of lower word line cut holes (WCH1). In exemplary embodiments, the plurality of first sacrificial films (S1) may be made of a silicon oxide film, a polysilicon film, a carbon film, or a tungsten film, but are not limited thereto.

[0164] Referring to FIGS. 24a and 24b, in the connection area (CON), a portion of the second intermediate insulating film (136) can be removed around each of the plurality of lower memory cell contact holes (MCH1) and the plurality of lower dummy channel holes (DCH1) to form a plurality of landing holes (LH) in the second intermediate insulating film (136). The upper sidewalls of each of the plurality of lower memory cell contact holes (MCH1) and the plurality of lower dummy channel holes (DCH1) can be exposed through the plurality of landing holes (LH). The plurality of landing holes (LH) may have an annular ring shape that encloses one of the plurality of lower memory cell contact holes (MCH1) and the plurality of lower dummy channel holes (DCH1) in each plane (e.g., the XY plane).

[0165] Referring to FIGS. 25a and 25b, a plurality of second sacrificial membranes (S2) can be formed to fill a plurality of landing holes (LH) in the result of FIGS. 24a and 24b. The plurality of second sacrificial membranes (S2) may be made of the same material as the plurality of first sacrificial membranes (S1).

[0166] Referring to FIGS. 26a, 26b, and 26c, processes similar to those described with reference to FIGS. 20a to 21b can be performed on the result of FIGS. 25a and 25b to form a structure including a plurality of insulating films (132), a plurality of sacrificial insulating films (134), and a plurality of sacrificial pad portions (134S) necessary for forming a second stack (STC) (see FIGS. 6a to 6c) on a second intermediate insulating film (136), and an upper insulating block (137) covering the structure in a connection area (CON) can be formed.

[0167] After that, a plurality of upper dummy channel holes (DCH2) connected to a plurality of lower dummy channel holes (DCH1) in the connection area (CON) and a plurality of upper channel holes (CH2) connected to a plurality of lower channel holes (CH1) in the memory cell area (MEC) are formed, and a plurality of first sacrificial membranes (S1) exposed through the plurality of upper dummy channel holes (DCH2) and the plurality of upper channel holes (CH2) can be removed.

[0168] After that, a plurality of gate dielectric films (142), a plurality of channel regions (144), and a plurality of buried insulating films (146) can be formed to fill a plurality of lower dummy channel holes (DCH1) and a plurality of upper dummy channel holes (DCH2) in the connection region (CON), and a plurality of lower channel holes (CH1) and a plurality of upper channel holes (CH2) in the memory cell region (MEC). A first upper insulating film (UL1) covering the result of the above process in the connection region (CON) and the memory cell region (MEC), and a plurality of drain regions (148) penetrating the first upper insulating film (UL1) can be formed to form a plurality of first dummy channel structures (140D1) and a plurality of second dummy channel structures (140D2) disposed in the connection region (CON), and a plurality of channel structures (140) disposed in the memory cell region (MEC).

[0169] After that, a plurality of first dummy channel structures (140D1), a plurality of second dummy channel structures (140D2), and a second upper insulating film (UL2) and a third upper insulating film (UL3) covering a plurality of channel structures (140) are formed in the connection area (CON) and the memory cell area (MEC), and a hole is formed by etching a portion of the third upper insulating film (UL3), the second upper insulating film (UL2), the first upper insulating film (UL1), a portion of the plurality of insulating films (132), and a portion of the plurality of sacrificial insulating films (134) in the memory cell area (MEC), and a string selection line cut structure (SSLC) that fills the hole can be formed.

[0170] A plurality of upper word line cut holes (WCH2) connected to a plurality of lower word line cut holes (WCH1) in a memory cell region (MEC) are formed, a plurality of first sacrificial films (S1) exposed through the plurality of upper word line cut holes (WCH2) are removed, and an insulating plate (112) is selectively removed only in the memory cell region (MEC) among the memory cell region (MEC) and the connection region (CON) through the plurality of lower word line cut holes (WCH1) and the plurality of upper word line cut holes (WCH2), and the resulting empty space can be filled with a first conductive plate (114). While removing the insulating plate (112) from the memory cell region (MEC), the portions of the gate dielectric film (182) included in the channel structure (180) in the memory cell region (MEC) that were adjacent to the insulating plate (112) may be removed together with the insulating plate (112), and as a result, the first conductive plate (114) may penetrate a portion of the gate dielectric film (182) in a horizontal direction and come into contact with the channel region (184).

[0171] Through a plurality of lower word line cut holes (WCH1) and a plurality of upper word line cut holes (WCH2), a plurality of sacrificial insulating films (134) and sacrificial pad portions (134S) (see FIG. 25a and FIG. 25b) in the memory cell region (MEC) and connection region (CON) can be replaced with a plurality of gate lines (130) and a plurality of conductive pad portions (130A).

[0172] After the first conductive plate (114) and a plurality of gate lines (130) are formed, a plurality of word line cut holes (WCH) can be filled with a plurality of word line cut structures (WLC).

[0173] Referring to FIGS. 27a, 27b, and 27c, a fourth upper insulating film (UL4) can be formed on the result of FIGS. 26a, 26b, and 26c, and a plurality of upper memory cell contact holes (MCH2) that penetrate the fourth upper insulating film (UL4), the third upper insulating film (UL3), the second upper insulating film (UL2), the first upper insulating film (UL1), and the upper insulating block (137) in the connection area (CON), and an upper plate contact hole (PCH2) connected to the lower plate contact hole (PCH1) can be formed.

[0174] Referring to FIG. 28, a plurality of first sacrificial films (S1) and a plurality of second sacrificial films (S2) exposed through a plurality of upper memory cell contact holes (MCH2) and upper plate contact holes (PCH2) in the results of FIG. 27a, FIG. 27b, and FIG. 27c can be removed, and a plurality of first memory cell contacts (MCC1), a plurality of second memory cell contacts (MCC2), an insulating spacer (162), and a conductive plate contact (164) can be formed.

[0175] Subsequently, in the result of performing the process of FIG. 28, as exemplified in FIG. 6a to 6c, a fifth upper insulating film (UL5) is formed in the memory cell region (MEC) and the connection region (CON); a plurality of contact plugs (172) are formed penetrating the fifth upper insulating film (UL5) in the connection region (CON); a plurality of upper wiring layers (UML) are formed on the fifth upper insulating film (UL5) and the plurality of contact plugs (172) in the connection region (CON); a plurality of contact plugs (176) are formed penetrating the fifth upper insulating film (UL5), the fourth upper insulating film (UL4), the third upper insulating film (UL3), and the second upper insulating film (UL2) in the memory cell region (MEC) and connected to the drain region (148) of a plurality of channel structures (140); a plurality of bit lines (BL) connected to the plurality of contact plugs (176) are formed on the fifth upper insulating film (UL5); and a plurality of upper wiring layers (UML) and a plurality A sixth upper insulating film (UL6) can be formed to fill the space between each bit line (BL).

[0176] Although a method for manufacturing a semiconductor device (100) exemplified in FIGS. 4 to 6e has been described with reference to FIGS. 20a to 28, those skilled in the art will be well aware that, within the scope of the technical concept of the present invention, various modifications and changes can be made to the processes described with reference to FIGS. 20a to 28 to manufacture the semiconductor device (200A, 200B, 300, 400, 500, 500A, 500B, 500C, 600A, 600B, 600C, 700) described with reference to FIGS. 7 to 19b, and semiconductor devices having various structures to which various modifications and changes have been made within the scope of the technical concept of the present invention.

[0177] FIG. 29 is a schematic diagram showing an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.

[0178] Referring to FIG. 29, an electronic system (1000) according to an exemplary embodiment of the present invention may include a semiconductor device (1100) and a controller (1200) electrically connected to the semiconductor device (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device, comprising one or more semiconductor devices (1100). For example, the electronic system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device, comprising at least one semiconductor device (1100).

[0179] The semiconductor device (1100) may be a non-volatile memory device. For example, the semiconductor device (1100) may be a NAND flash memory device comprising at least one of the structures described above for the semiconductor devices (100, 200A, 200B, 300, 400, 500, 500A, 500B, 500C, 600A, 600B, 600C, 700) with reference to FIGS. 4 through 19b. The semiconductor device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F). In exemplary embodiments, the first structure (1100F) may be placed next to the second structure (1100S). The first structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second structure (1100S) may be a memory cell structure including a bit line (BL), a common source line (CSL), a plurality of word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a plurality of memory cell strings (CSTR) located between the bit line (BL) and the common source line (CSL).

[0180] In the second structure (1100S), a plurality of memory cell strings (CSTR) may each include a lower transistor (LT1, LT2) adjacent to a common source line (CSL), an upper transistor (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistor (LT1, LT2) and the upper transistor (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments.

[0181] In exemplary embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. A plurality of gate lower lines (LL1, LL2) may each be gate electrodes of the lower transistors (LT1, LT2). The word line (WL) may be a gate electrode of the memory cell transistor (MCT), and the gate upper lines (UL1, UL2) may be gate electrodes of the upper transistors (UT1, UT2).

[0182] A common source line (CSL), a plurality of gate lower lines (LL1, LL2), a plurality of word lines (WL), and a plurality of gate upper lines (UL1, UL2) can be electrically connected to a decoder circuit (1110) through a plurality of first connecting wires (1115) extending from the first structure (1100F) to the second structure (1100S). A plurality of bit lines (BL) can be electrically connected to a page buffer (1120) through a plurality of second connecting wires (1125) extending from the first structure (1100F) to the second structure (1100S).

[0183] In the first structure (1100F), the decoder circuit (1110) and the page buffer (1120) can perform control operations on at least one of a plurality of memory cell transistors (MCT). The decoder circuit (1110) and the page buffer (1120) can be controlled by a logic circuit (1130).

[0184] The semiconductor device (1100) can communicate with the controller (1200) through an input / output pad (1101) that is electrically connected to the logic circuit (1130). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first structure (1100F) to the second structure (1100S).

[0185] The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). According to embodiments, the electronic system (1000) may include a plurality of semiconductor devices (1100), and in this case, the controller (1200) may control the plurality of semiconductor devices (1100).

[0186] The processor (1210) can control the overall operation of the electronic system (1000), including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can access the semiconductor device (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a NAND interface (1221) that handles communication with the semiconductor device (1100). Through the NAND interface (1221), control commands for controlling the semiconductor device (1100), data to be written to a plurality of memory cell transistors (MCTs) of the semiconductor device (1100), data to be read from a plurality of memory cell transistors (MCTs) of the semiconductor device (1100), etc., can be transmitted. The host interface (1230) can provide communication functions between the electronic system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1210) can control the semiconductor device (1100) in response to the control command.

[0187] FIG. 30 is a schematic perspective view of an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.

[0188] Referring to FIG. 30, an electronic system (2000) according to an exemplary embodiment of the present invention may include a main board (2001), a controller (2002) mounted on the main board (2001), one or more semiconductor packages (2003), and a DRAM (2004). The semiconductor package (2003) and the DRAM (2004) may be connected to the controller (2002) by a plurality of wiring patterns (2005) formed on the main board (2001).

[0189] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the electronic system (2000) and the external host. In exemplary embodiments, the electronic system (2000) may communicate with the external host according to any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In exemplary embodiments, the electronic system (2000) may operate by power supplied from the external host through the connector (2006). The electronic system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2002) and a semiconductor package (2003).

[0190] The controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the electronic system (2000).

[0191] The DRAM (2004) may be a buffer memory to mitigate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the electronic system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (2003). When the DRAM (2004) is included in the electronic system (2000), the controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to the NAND controller for controlling the semiconductor package (2003).

[0192] A semiconductor package (2003) may include first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) may each be a semiconductor package including a plurality of semiconductor chips (2200). Each of the first and second semiconductor packages (2003a, 2003b) may include a package substrate (2100), a plurality of semiconductor chips (2200) on the package substrate (2100), an adhesive layer (2300) disposed on the lower surface of each of the plurality of semiconductor chips (2200), a connecting structure (2400) electrically connecting the plurality of semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the plurality of semiconductor chips (2200) and the connecting structure (2400) on the package substrate (2100).

[0193] The package substrate (2100) may be a printed circuit board including a plurality of package upper pads (2130). Each of the plurality of semiconductor chips (2200) may include an input / output pad (2210). The input / output pad (2210) may correspond to the input / output pad (1101) of FIG. 19. Each of the plurality of semiconductor chips (2200) may include a plurality of gate stacks (3210) and a plurality of channel structures (3220). Each of the plurality of semiconductor chips (2200) may include at least one of semiconductor devices (100, 200A, 200B, 300, 400, 500, 500A, 500B, 500C, 600A, 600B, 600C, 700) with reference to FIG. 4 to FIG. 19b.

[0194] In exemplary embodiments, the connection structure (2400) may be a bonding wire that electrically connects the input / output pad (2210) and the package upper pad (2130). Accordingly, in the first and second semiconductor packages (2003a, 2003b), a plurality of semiconductor chips (2200) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pad (2130) of the package substrate (2100). In exemplary embodiments, in the first and second semiconductor packages (2003a, 2003b), a plurality of semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the bonding wire method connection structure (2400).

[0195] In exemplary embodiments, the controller (2002) and a plurality of semiconductor chips (2200) may be included in a single package. In exemplary embodiments, the controller (2002) and a plurality of semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the controller (2002) and the plurality of semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

[0196] FIG. 31 is a schematic cross-sectional view of semiconductor packages according to an exemplary embodiment of the present invention. FIG. 31 shows in more detail the configuration according to the cross-section along line II-II' of FIG. 30.

[0197] Referring to FIG. 31, in a semiconductor package (2003), the package substrate (2100) may be a printed circuit board. The package substrate (2100) may include a package substrate body portion (2120), a plurality of package upper pads (2130) disposed on the upper surface of the package substrate body portion (2120) (see FIG. 30), a plurality of lower pads (2125) disposed on the lower surface of the package substrate body portion (2120) or exposed through the lower surface, and a plurality of internal wirings (2135) that electrically connect the plurality of upper pads (2130) and the plurality of lower pads (2125) inside the package substrate body portion (2120). The plurality of upper pads (2130) may be electrically connected to a plurality of connection structures (2400). A plurality of lower pads (2125) can be connected to a plurality of wiring patterns (2005) on a main board (2001) of an electronic system (2000) illustrated in FIG. 30 through a plurality of conductive connection parts (2800).

[0198] Each of the plurality of semiconductor chips (2200) may include a semiconductor substrate (3010) and a first structure (3100) and a second structure (3200) that are sequentially stacked on the semiconductor substrate (3010). The first structure (3100) may include a peripheral circuit region including a plurality of peripheral wirings (3110). The second structure (3200) may include a common source line (3205), a gate stack (3210) on the common source line (3205), a channel structure (3220) penetrating the gate stack (3210), and a bit line (3240) electrically connected to the channel structure (3220). In exemplary embodiments, each of the plurality of semiconductor chips (2200) may include a configuration as described for the semiconductor device (100, 200A, 200B, 300, 400, 500, 500A, 500B, 500C, 600A, 600B, 600C, 700) with reference to FIGS. 4 to 19b.

[0199] Each of the plurality of semiconductor chips (2200) may include a through-wire (3245) that is electrically connected to a plurality of peripheral wires (3110) of the first structure (3100) and extends into the second structure (3200). The through-wire (3245) may be positioned outside the gate stack (3210). In other exemplary embodiments, the semiconductor package (2003) may further include a through-wire that penetrates the gate stack (3210). Each of the plurality of semiconductor chips (2200) may further include an input / output pad (2210 of FIG. 30) that is electrically connected to a plurality of peripheral wires (3110) of the first structure (3100).

[0200] Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and changes are possible by those skilled in the art within the technical spirit and scope of the present invention. Explanation of the symbols

[0201] 110: Substrate, 140D1: First dummy channel structure, 140D2: Second dummy channel structure, 340D1: First dummy channel structure, 340D2: Second dummy channel structure, MCC1: First memory cell contact, MCC2: Second memory cell contact, THV1: First through-electrode, THV2: Second through-electrode.

Claims

Claim 1 A substrate; a lower stepped connection portion disposed at a first vertical level on the substrate and having a plurality of lower conductive pad portions; an upper stepped connection portion disposed at a second vertical level higher than the first vertical level on the substrate and having a plurality of upper conductive pad portions; a lower insulating block that contacts each of the plurality of lower conductive pad portions at the first vertical level and covers the lower stepped connection portion; an upper insulating block that contacts each of the plurality of upper conductive pad portions at the second vertical level and includes a portion covering the upper stepped connection portion and a portion covering the lower insulating block; an intermediate insulating film interposed between the lower insulating block and the upper insulating block at a third vertical level between the first vertical level and the second vertical level and having a first thickness in the vertical direction; a first memory cell contact that penetrates the lower stepped connection portion, the intermediate insulating film, and the upper insulating block in the vertical direction at a position spaced horizontally from the upper stepped connection portion, wherein the width along the horizontal direction is maximum at the third vertical level; and a second memory that penetrates the upper stepped connection portion in the vertical direction. It includes cell contacts, wherein the first memory cell contact and the second memory cell contact are spaced apart in the horizontal direction, and in the horizontal direction, the first width of the uppermost surface of the first memory cell contact is greater than the second width of the uppermost surface of the second memory cell contact, and the first memory cell contact is configured to be electrically connected to one selected lower conductive pad among the plurality of lower conductive pad portions, penetrates the selected lower conductive pad portion in the vertical direction, and contacts only the selected lower conductive pad portion among the plurality of lower conductive pad portions, and the second memory cell contact is configured to be electrically connected to one selected upper conductive pad portion among the plurality of upper conductive pad portions.A semiconductor device that penetrates the selected upper conductive pad portion in the vertical direction and contacts only the selected upper conductive pad portion among the plurality of upper conductive pad portions. Claim 2 A semiconductor device according to claim 1, wherein the first memory cell contact comprises a lower plug portion disposed at the first vertical level and including a portion penetrating the lower stepped connection portion, an upper plug portion disposed at the second vertical level and surrounded by the upper insulating block, and a plug landing portion interposed between the lower plug portion and the upper plug portion and protruding in the horizontal direction from the first side wall of the lower plug portion and the second side wall of the upper plug portion at the third vertical level, wherein the plug landing portion has a second thickness smaller than the first thickness in the vertical direction so as to penetrate only a portion of the intermediate insulating film, and the bottom surface of the plug landing portion facing the substrate is in contact with the intermediate insulating film. Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 delete Claim 8 A substrate including a memory cell region and a connection region; a first stack including a plurality of lower gate lines disposed at a first vertical level on the substrate and overlapping each other along the vertical direction in the memory cell region, and a plurality of lower conductive pad portions disposed at the connection region and integrally connected to the plurality of lower gate lines; a second stack including a plurality of upper gate lines disposed at a second vertical level higher than the first vertical level on the substrate and overlapping each other along the vertical direction in the memory cell region, and a plurality of upper conductive pad portions disposed at the connection region and integrally connected to the plurality of upper gate lines; a lower insulating block covering the lower stepped connection portion at the first vertical level; an upper insulating block covering the upper stepped connection portion and the lower insulating block at the second vertical level; an intermediate insulating film having a first thickness in the vertical direction interposed between the first stack and the second stack at a third vertical level between the first vertical level and the second vertical level, and between the lower insulating block and the upper insulating block; and the A first memory cell contact that penetrates the lower stepped connection, the intermediate insulating film, and the upper insulating block in the vertical direction at a position spaced horizontally apart from the first stack, and whose width along the horizontal direction is maximum at the third vertical level, and a second memory cell contact that penetrates the upper stepped connection in the vertical direction, wherein the first memory cell contact and the second memory cell contact are spaced apart in the horizontal direction, and in the horizontal direction, the first width of the uppermost surface of the first memory cell contact is greater than the second width of the uppermost surface of the second memory cell contact.A semiconductor device wherein the first memory cell contact is configured to be electrically connected to one selected lower conductive pad among the plurality of lower conductive pad portions, penetrates the selected lower conductive pad portion in the vertical direction, and contacts only the selected lower conductive pad portion among the plurality of lower conductive pad portions, and the second memory cell contact is configured to be electrically connected to one selected upper conductive pad portion among the plurality of upper conductive pad portions, penetrates the selected upper conductive pad portion in the vertical direction, and contacts only the selected upper conductive pad portion among the plurality of upper conductive pad portions. Claim 9 delete Claim 10 Main board; semiconductor device on the main board; and includes a controller electrically connected to the semiconductor device on the main substrate, wherein the semiconductor device comprises a substrate, a lower stepped connection portion disposed at a first vertical level on the substrate and having a plurality of lower conductive pad portions, an upper stepped connection portion disposed at a second vertical level higher than the first vertical level on the substrate and having a plurality of upper conductive pad portions, a lower insulating block in contact with each of the plurality of lower conductive pad portions at the first vertical level and covering the lower stepped connection portion, an upper insulating block in contact with each of the plurality of upper conductive pad portions at the second vertical level and including a portion covering the upper stepped connection portion and a portion covering the lower insulating block, an intermediate insulating film interposed between the lower insulating block and the upper insulating block at a third vertical level between the first vertical level and the second vertical level and having a first thickness in the vertical direction, and penetrating the lower stepped connection portion, the intermediate insulating film, and the upper insulating block in the vertical direction at a position spaced horizontally from the upper stepped connection portion, and the width along the horizontal direction is at the third vertical level It includes a first memory cell contact that is maximum and a second memory cell contact that penetrates the upper stepped connection portion in the vertical direction, wherein the first memory cell contact and the second memory cell contact are spaced apart in the horizontal direction, and in the horizontal direction, the first width of the uppermost surface of the first memory cell contact is greater than the second width of the uppermost surface of the second memory cell contact, and the first memory cell contact is configured to be electrically connected to one selected lower conductive pad portion among the plurality of lower conductive pad portions, penetrates the selected lower conductive pad portion in the vertical direction, and contacts only the selected lower conductive pad portion among the plurality of lower conductive pad portions.An electronic system wherein the second memory cell contact is configured to be electrically connected to one selected upper conductive pad among the plurality of upper conductive pad portions, penetrates the selected upper conductive pad portion in the vertical direction, and contacts only the selected upper conductive pad portion among the plurality of upper conductive pad portions.

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