Semiconductor Package

Abstract

The technical concept of the present invention provides a semiconductor package comprising: a first semiconductor substrate having opposite active surfaces and inactive surfaces, a first wiring structure disposed on the active surface of the first semiconductor substrate, a plurality of through electrodes penetrating at least a portion of the first semiconductor substrate, and a plurality of first coupling pads connected to each of the plurality of through electrodes; and a second semiconductor chip stacked on the first semiconductor chip and comprising a second semiconductor substrate having opposite active surfaces and inactive surfaces, a second wiring structure disposed on the active surface of the second semiconductor substrate, and a second coupling pad connected to the first coupling pad and disposed on the active surface of the second semiconductor substrate; wherein the first coupling pad extends from an upper surface in contact with the second coupling pad to a lower surface in contact with the through electrode.

Description

Technology Field

[0001] The technical concept of the present invention relates to a semiconductor package. More specifically, it relates to a semiconductor package having stacked semiconductor chips. Background Technology

[0002] As the miniaturization, multifunctionality, and high performance of electronic products are required, there is a demand for high integration and high speed of semiconductor packages. To this end, semiconductor packages containing stacked semiconductor chips are being developed. The problem to be solved

[0003] The problem that the technical concept of the present invention aims to solve is to provide a semiconductor package having a stacked semiconductor chip with improved operational reliability. means of solving the problem

[0004] To solve the above-mentioned problem, the technical concept of the present invention provides a semiconductor package comprising: a first semiconductor substrate having opposite active surfaces and inactive surfaces, a first wiring structure disposed on the active surface of the first semiconductor substrate, a plurality of through electrodes penetrating at least a portion of the first semiconductor substrate, and a plurality of first coupling pads connected to each of the plurality of through electrodes; and a second semiconductor chip stacked on the first semiconductor chip and comprising a second semiconductor substrate having opposite active surfaces and inactive surfaces, a second wiring structure disposed on the active surface of the second semiconductor substrate, and a second coupling pad connected to the first coupling pad and disposed on the active surface of the second semiconductor substrate; wherein the first coupling pad extends from an upper surface in contact with the second coupling pad to a lower surface in contact with the through electrode.

[0005] To solve the above-mentioned problem, the technical concept of the present invention provides a semiconductor package comprising: a first semiconductor substrate having opposite active surfaces and inactive surfaces; a first wiring structure comprising a plurality of metal wirings disposed on the active surface of the first semiconductor substrate and located at different vertical levels; a through electrode penetrating at least a portion of the first semiconductor substrate; a first metal structure disposed on the through electrode; and a first coupling pad connected to the first metal structure; and a second semiconductor chip stacked on the first semiconductor chip and comprising a second semiconductor substrate having opposite active surfaces and inactive surfaces, a second wiring structure disposed on the active surface of the second semiconductor substrate, and a second coupling pad connected to the first coupling pad and disposed on the active surface of the second semiconductor substrate. wherein the first coupling pad extends from an upper surface in contact with the second coupling pad to a lower surface in contact with the first metal structure, and the through electrode protrudes from the first semiconductor substrate and contacts the first metal structure.

[0006] To solve the above-mentioned problem, the technical concept of the present invention comprises: a first semiconductor chip comprising a first semiconductor substrate having opposite active surfaces and inactive surfaces, a first wiring structure disposed on the active surface of the first semiconductor substrate and including a plurality of metal wirings located at different vertical levels and a plurality of vias located at different vertical levels, a through electrode penetrating at least a portion of the first semiconductor substrate, a plurality of second metal structures disposed on the through electrode and in contact with each other, and a first coupling pad connected to the second metal structures; and a second semiconductor chip stacked on the first semiconductor chip and comprising a second semiconductor substrate having opposite active surfaces and inactive surfaces, a second wiring structure disposed on the active surface of the second semiconductor substrate, and a second coupling pad connected to the first coupling pad and disposed on the active surface of the second semiconductor substrate. The first coupling pad extends from an upper surface in contact with the second coupling pad to a lower surface in contact with the second metal structures, and the through electrode protrudes from the first semiconductor substrate and provides a semiconductor package in contact with the second metal structures. Effects of the invention

[0007] According to exemplary embodiments of the present invention, the first coupling pad is directly connected to or connected in close proximity to the through-electrode, so that the voltage drop phenomenon can be improved. Accordingly, the signal integrity (SI) and power integrity (PI) characteristics of the semiconductor package can be improved.

[0008] In addition, according to exemplary embodiments of the present invention, the vertical height of the first bonding pad is relatively high, so that the copper-copper hybrid bonding process can be performed better. Brief explanation of the drawing

[0009] FIG. 1 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. FIGS. 2a and FIGS. 2b are enlarged cross-sectional views showing parts corresponding to part A of FIG. 1. FIG. 3 is a drawing showing a semiconductor package according to one embodiment of the present invention, and is an enlarged cross-sectional view showing a part corresponding to part A of FIG. 1. FIGS. 4a and FIGS. 4b are drawings showing a semiconductor package according to an embodiment of the present invention, and are enlarged cross-sectional views showing a portion corresponding to part A of FIG. 1. FIG. 5 is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention. FIG. 6 is a cross-sectional view showing a semiconductor package according to one embodiment of the present invention. FIG. 7 is a flowchart illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. FIGS. 8a to 8g are cross-sectional views illustrating each step of a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0011] In the following, unless otherwise specifically defined, the direction parallel to the upper surface of the first semiconductor substrate (110) is defined as the horizontal direction, and the length in the direction parallel to the upper surface of the first semiconductor substrate (110) is defined as the horizontal width. Additionally, the direction perpendicular to the upper surface of the first semiconductor substrate (110) is defined as the vertical direction, and the length in the direction perpendicular to the upper surface of the first semiconductor substrate (110) is defined as the vertical height.

[0012] FIG. 1 is a cross-sectional view showing a semiconductor package (1000) according to an exemplary embodiment of the present invention. The center dotted line of FIG. 1 is a line showing the junction (or junction surface) of the first semiconductor chip (100) and the second semiconductor chip (200).

[0013] Referring to FIG. 1, a semiconductor package (1000) may include a first semiconductor chip (100) and a second semiconductor chip (200). The second semiconductor chip (200) may be stacked on the first semiconductor chip (100). In FIG. 1, the horizontal widths of the first semiconductor chip (100) and the second semiconductor chip (200) are shown as being equal to each other, but are not limited thereto; for example, the horizontal width of the first semiconductor chip (100) may be shorter than the horizontal width of the second semiconductor chip (200).

[0014] The first semiconductor chip (100) is electrically connected to the second semiconductor chip (200) through a plurality of first coupling pads (141) and a plurality of second coupling pads (241) to transmit and receive signals and to provide power and ground.

[0015] A first semiconductor chip (100) may include a first semiconductor substrate (110) having opposite active and inactive surfaces, a first wiring structure (120) disposed on the active surface of the first semiconductor substrate (110), a plurality of through electrodes (130) penetrating at least a portion of the first semiconductor substrate (110), a plurality of first coupling pads (141) connected to each of the plurality of through electrodes (130), and a first wiring insulating layer (145). In some embodiments, the first semiconductor chip (100) may further include first dummy structures (143) disposed on the active surface of the first semiconductor substrate (110) and spaced apart from the first coupling pads (141).

[0016] Within the semiconductor package (1000), the active surface of the first semiconductor chip (100) may be positioned so that it faces upward and the inactive surface faces downward. In this case, a redistribution structure (150) may be positioned on the inactive surface of the first semiconductor chip (100). The semiconductor package (1000) may be connected, for example, to a package substrate, through a connection bump (160). Although not shown in FIG. 1, a first rear pad (not shown) connecting the redistribution structure (150) and the connection bump (160) may be interposed.

[0017] The second semiconductor chip (200) may include a second semiconductor substrate (210) having opposite active and inactive surfaces, a second wiring structure (220) disposed on the active surface of the second semiconductor substrate (210), a second coupling pad (241) connected to the first coupling pad (141) and disposed on the active surface of the second semiconductor substrate (210), and a second wiring insulating layer (245). In some embodiments, the second semiconductor chip (200) may further include a second dummy structure (243) spaced apart from the second coupling pad (241) and disposed on the active surface of the second semiconductor substrate (210).

[0018] The first semiconductor substrate (110) and the second semiconductor substrate (210) may include, for example, a group IV semiconductor such as silicon (Si) or germanium (Ge), a group IV-IV compound semiconductor such as silicon-germanium (SiGe) or silicon carbide (SiC), or a group III-V compound semiconductor such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The first semiconductor substrate (110) and the second semiconductor substrate (210) may include a conductive region, for example, an impurity-doped well. The first semiconductor substrate (110) and the second semiconductor substrate (210) may have various device isolation structures, such as a shallow trench isolation (STI) structure.

[0019] Each of the first semiconductor substrate (110) and the second semiconductor substrate (210) may have an active surface and an inactive surface opposite to the active surface. Semiconductor devices comprising a plurality of individual devices of various types may be formed on the active surfaces of each of the first semiconductor substrate (110) and the second semiconductor substrate (210). For example, the plurality of individual devices may include various micro electronic devices, such as a MOSFET (metal-oxide-semiconductor field effect transistor) such as a CMOS transistor (complementary metal-oxide semiconductor transistor), a system LSI (large scale integration), an image sensor such as a CIS (CMOS imaging sensor), a MEMS (micro-electro-mechanical system), an active device, and a passive device. The plurality of individual devices may be electrically connected to the conductive region of the first semiconductor substrate (110) or the second semiconductor substrate (210). Each of the first semiconductor device and the second semiconductor device may further include at least two of the plurality of individual devices, or a conductive wiring or a conductive plug that electrically connects the conductive regions of the first semiconductor substrate (110) and the second semiconductor substrate (210) to the plurality of individual devices. Additionally, each of the plurality of individual devices may be electrically separated from other adjacent individual devices by an insulating film.

[0020] In some embodiments, at least one of the first semiconductor chip (100) and the second semiconductor chip (200) may be a memory chip or a logic chip. The memory chip may be a volatile memory chip, such as, for example, DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or a non-volatile memory chip, such as PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or RRAM (Resistive Random Access Memory). Additionally, the logic chip may be, for example, a microprocessor, an analog device, or a digital signal processor.

[0021] The first wiring structure (120) and the second wiring structure (220) may include a metallic material such as aluminum, copper, or tungsten, for example. In some embodiments, the first wiring structure (120) and the second wiring structure (220) may consist of a wiring barrier film and a wiring metal layer. The wiring barrier film may consist of, for example, a metal, a metal nitride, or an alloy. The wiring metal layer may include at least one metal selected from, for example, W, Al, Ti, Ta, Ru, Mn, or Cu.

[0022] Each of the first wiring structure (120) and the second wiring structure (220) may include a plurality of metal wires and a plurality of vias connecting the plurality of metal wires. In some embodiments, each of the first wiring structure (120) and the second wiring structure (220) may be a multilayer wiring structure having a plurality of metal wires and a plurality of vias located at different vertical levels.

[0023] The first wiring insulation layer (145) and the second wiring insulation layer (245) may each surround the first wiring structure (120) and the second wiring structure (220). In some embodiments, the first wiring insulation layer (145) may surround both sides and the bottom surface of the first dummy structure (143), and the second wiring insulation layer (245) may surround both sides and the top surface of the second dummy structure (143). In some embodiments, when the first wiring structure (120) and the second wiring structure (220) each have a multilayer wiring structure, the first wiring insulation layer (145) and the second wiring insulation layer (245) may each have a multilayer structure in which a plurality of insulation layers are stacked corresponding to the multilayer wiring structure of the first wiring structure (120) and the second wiring structure (220). For example, the first wiring insulation layer (145) and the second wiring insulation layer (245) each have a plurality of insulation layers, and the plurality of insulation layers may be made of silicon oxide, silicon nitride, silicon oxynitride, insulating polymer, or a combination thereof. For example, at least a portion of each of the first wiring insulation layer (145) and the second wiring insulation layer (245) may be made of a polymer formed from PSPI (Photosensitive Polyimide). For example, each of the first wiring insulation layer (145) and the second wiring insulation layer (245) may have a multilayer structure in which a layer made of nitride and a layer formed from PSPI are stacked. Or, for example, each of the first wiring insulation layer (145) and the second wiring insulation layer (245) may have a multilayer structure in which a layer made of nitride and a layer made of TEOS are stacked.

[0024] A plurality of through electrodes (130) may penetrate at least a portion of the first semiconductor substrate (110). Each of the plurality of through electrodes (130) may include a conductive plug penetrating at least a portion of the first semiconductor substrate (110) and a conductive barrier film surrounding the conductive plug. In an exemplary embodiment, one through electrode (130) may be vertically aligned and overlapped with a corresponding first coupling pad (141) and may not be vertically overlapped with a first wiring structure (120). In some embodiments, one through electrode (130) may be vertically aligned and overlapped with a second coupling pad (241) connected to a corresponding first coupling pad (141) and a second wiring structure (220) connected to the second coupling pad (241). In an exemplary embodiment, the upper surface of each of the plurality of through electrodes (130) may be located at the same or similar vertical level as the upper surface of the first semiconductor substrate (110). In an exemplary embodiment, the horizontal width of each of the plurality of penetrating electrodes (130) may be about 2 µm to 3 µm, but is not limited thereto.

[0025] The redistribution structure (150) may include a metallic material such as aluminum, copper, or tungsten, for example. In some embodiments, the redistribution structure (150) may include a plurality of redistribution patterns and a plurality of vias. In some embodiments, the redistribution structure (150) may be a multilayer wiring structure including a plurality of redistribution patterns located at different vertical levels and a plurality of vias located at different vertical levels.

[0026] The connecting bump (160) may be placed on the lower surface of the redistribution structure (150). The connecting bump (160) may include, for example, copper, silver, tin, or an alloy thereof, but is not limited thereto.

[0027] The first coupling pad (141) may be disposed on the active surface of the first semiconductor substrate (110), and the second coupling pad (241) may be disposed on the active surface of the second semiconductor substrate (210). The lower surface of the first coupling pad (141) may be in contact with the upper surface of a through electrode (130) so that the first coupling pad (141) and the through electrode (130) can be electrically connected. The upper surface of the first coupling pad (141) may be in contact with the lower surface of the second coupling pad (241) so that the first coupling pad (141) and the second coupling pad (241) can be electrically connected. That is, the first coupling pad (141) is interposed between the through electrode (130) and the second coupling pad (241), and may extend from the upper surface in contact with the second coupling pad (241) to the lower surface in contact with the through electrode (130). The upper surface of the second coupling pad (241) is in contact with the lower surface of the second wiring structure (220), so that the second coupling pad (241) can be electrically connected to the second wiring structure (220). The first coupling pad (141) and the second coupling pad (241) are connected so that the first semiconductor chip (100) and the second semiconductor chip (200) can be electrically connected. The first coupling pad (141) and the second coupling pad (241) may include, for example, copper. In some embodiments, the horizontal width of the first coupling pad (141) and the horizontal width of the second coupling pad (241) may be the same as each other.

[0028] Each of the first dummy structure (143) and the second dummy structure (243) may be disposed within the first wiring insulation layer (145) and the second wiring insulation layer (245). The first dummy structure (143) and the second dummy structure (243) may be connected and joined to each other. In some embodiments, the horizontal width of each of the first dummy structure (143) and the second dummy structure (243) may be wider than the horizontal width of the first coupling pad (141) and the second coupling pad (241). In some embodiments, the pitch between the first dummy structure (143) and the first coupling pad (141) may be the same as the pitch between the second dummy structure (243) and the second coupling pad (241), but is not limited thereto. In some embodiments, the vertical height of the first dummy structure (143) and the second dummy structure (243) may be shorter than the vertical height of the first coupling pad (141) and the second coupling pad (241).

[0029] FIGS. 2a and 2b are enlarged cross-sectional views showing a portion corresponding to part A of FIG. 1. The center dotted line in FIGS. 2a and 2b is a line representing the junction (or junction surface) between the first semiconductor chip (100) and the second semiconductor chip (200). Since the configuration of the semiconductor packages (1000a, 1000b) shown in FIGS. 2a and 2b is similar to the configuration of the semiconductor package (1000) described with reference to FIG. 1, the following description will focus on the differences.

[0030] Referring to FIGS. 1 and 2a, a semiconductor package (1000a) may include a first semiconductor substrate (110), a first wiring structure (120) including a plurality of metal wirings (120a, 120b, 120c) and a plurality of vias (123a, 123b), a first semiconductor chip (100) including a plurality of through electrodes (130), a plurality of first coupling pads (141), a plurality of first dummy structures (143), and a plurality of first wiring insulating layers (145a, 145b), and a second semiconductor chip (200) including a second semiconductor substrate (210), a second wiring structure (220), a plurality of second coupling pads (241), and a second wiring insulating layer (245).

[0031] Each of the plurality of first coupling pads (141) may be interposed between a corresponding second coupling pad (241) and a through electrode (130). That is, the upper surface of the first coupling pad (141) may be in contact with the lower surface of the second coupling pad (241), and the lower surface of the first coupling pad (141) may be in contact with the upper surface of the through electrode (130). In an exemplary embodiment, the lower surface of the first coupling pad (141) (i.e., the bonding surface between the first coupling pad (141) and the through electrode (130)) may be located at the same vertical level as the lower surface of the first metal wiring (120a). In this case, the lower surface of the first coupling pad (141) and the lower surface of the first metal wiring (120a) may form a co-surface. In an exemplary embodiment, each of the plurality of first coupling pads (141) may include a first portion (S1) that is in contact with the second coupling pad (241) and has a constant horizontal width, and a second portion (S2) that is in contact with the through electrode (130) and has a horizontal width that becomes narrower as it approaches the through electrode (130). That is, the horizontal width of the first portion (S1) may be wider than the horizontal width of the second portion (S2). In an exemplary embodiment, the horizontal width of one through electrode (130) may be wider than the horizontal width of the first portion (S1) and the horizontal width of the second portion (S2) of the first coupling pad (141). In an exemplary embodiment, the vertical length of the first coupling pad (141) may be about 3 µm to about 20 µm, but is not limited thereto.

[0032] The first bonding pad (141) is directly connected to the through electrode (130), so that the SI and PI characteristics of the semiconductor package can be improved. Additionally, the first bonding pad (141) extends from the upper surface in contact with the second bonding pad (241) to the lower surface in contact with the corresponding through electrode (130), thereby securing the process conditions required for the annealing process performed during the bonding process of the first bonding pad (141) and the second bonding pad (241).

[0033] Referring to FIG. 1 and FIG. 2b, a semiconductor package (1000b) may include a first semiconductor substrate (110), a first wiring structure (120) including a plurality of metal wirings (120a, 120b, 120c) and a plurality of vias (123a, 123b), a first semiconductor chip (100) including a plurality of through electrodes (130), a plurality of first coupling pads (141), a plurality of first dummy structures (143), and a plurality of first wiring insulating layers (145a, 145b), and a second semiconductor chip (200) including a second semiconductor substrate (210), a second wiring structure (220), a plurality of second coupling pads (241), and a second wiring insulating layer (245).

[0034] In an exemplary embodiment, the horizontal width of each of the plurality of first coupling pads (141) may become narrower as it approaches the corresponding through electrode (130). For example, the horizontal width of each of the plurality of first coupling pads (141) may have a tapered shape that gradually narrows from the upper surface in contact with the corresponding second coupling pad (241) to the lower surface in contact with the corresponding through electrode (130). That is, the horizontal width of the upper surface of the first coupling pad (141) may be wider than the horizontal width of the lower surface of the first coupling pad (141). In an exemplary embodiment, the vertical length of the first coupling pad (141) may be about 3 µm to about 20 µm, but is not limited thereto.

[0035] FIG. 3 is a drawing showing a semiconductor package according to one embodiment of the present invention, and is an enlarged cross-sectional view showing a part corresponding to part A of FIG. 1.

[0036] Referring to FIGS. 1 and 3, a semiconductor package (1000c) may include a first semiconductor substrate (110), a first wiring structure (120) comprising a plurality of metal wirings (120a, 120b, 120c) located at different vertical levels and a plurality of vias (123a, 123b) located at different vertical levels, a plurality of through electrodes (130), a first metal structure (135) disposed on each of the plurality of through electrodes (130), a plurality of first coupling pads (141), a plurality of first dummy structures (143), a plurality of first wiring insulating layers (145a, 145b), and a second semiconductor chip (200) comprising a second semiconductor substrate (210), a second wiring structure (220), a plurality of second coupling pads (241), and a second wiring insulating layer (245).

[0037] Each of the plurality of first coupling pads (131) may be interposed between the corresponding second coupling pad (241) and the first metal structure (135). That is, the first coupling pad (131) and the second coupling pad (241) may be electrically connected through the first metal structure (135). Each of the plurality of first coupling pads (131) may extend from the upper surface in contact with the second coupling pad (241) to the lower surface in contact with the first metal structure (135), and the through electrode (130) may protrude from the first semiconductor substrate (110) and further extend from the first semiconductor substrate (110) to the lower surface of the first metal structure (135). In an exemplary embodiment, the lower surface of each of the plurality of first coupling pads (131) in contact with the upper surface of the first metal structure (135) may be located at the same vertical level as the upper surface of the second metal wiring (120b). In this case, the upper surface of each through electrode (130) may extend to the same vertical level as the lower surface of the second metal wiring (120b). In an exemplary embodiment, the through electrode (130) may be vertically aligned and overlapped with the corresponding first coupling pad (141) and the first metal structure (135), and may not overlap vertically with the first wiring structure (120). In an exemplary embodiment, the horizontal width of the first coupling pad (141) may become narrower as it approaches the first metal structure (135). The first metal structure (135) may include a metallic material such as, for example, copper, tungsten, or aluminum. For example, the first metal structure (135) is formed through the same metal wiring process as any one of the plurality of metal wirings (120a, 120b, 120c) and may have the same material composition as any one of the plurality of metal wirings (120a, 120b, 120c). In some embodiments, the first metal structure (135) may be in the shape of a rod with a constant horizontal width.In some embodiments, the first metal structure (135) may have a rectangular shape when viewed in cross-section, and may have a circular or square shape when viewed in planar view. In an exemplary embodiment, the horizontal width of the first metal structure (135) may be wider than the horizontal width of the first bonding pad (141). For example, the horizontal width of the first metal structure (135) may be wider than the horizontal width of the lower surface of the first bonding pad (141). In an exemplary embodiment, the horizontal width of the first metal structure may be about 0.5 µm to 10 µm.

[0038] FIGS. 4a and FIGS. 4b are drawings showing a semiconductor package according to an embodiment of the present invention, and are enlarged cross-sectional views showing a portion corresponding to part A of FIG. 1.

[0039] Referring to FIGS. 4a and 4b, a semiconductor package (1000d) may include a first semiconductor substrate (110), a first wiring structure (120) comprising a plurality of metal wirings (120a, 120b, 120c) located at different vertical levels and a plurality of vias (123a, 123b) located at different vertical levels, a plurality of through electrodes (130), a plurality of second metal structures (137), a plurality of first coupling pads (141), a plurality of first dummy structures (143), a plurality of first wiring insulating layers (145a, 145b), a first semiconductor chip (100), and a second semiconductor substrate (210), a second wiring structure (220), a plurality of second coupling pads (241), and a second wiring insulating layer (245).

[0040] A plurality of second metal structures (137) may be disposed on the through electrode (130). Each of the plurality of second metal structures (137) may be in contact with one another. The plurality of second metal structures (137) may include a metallic material such as, for example, copper, tungsten, or aluminum. For example, the second metal structures (137) may be formed through the same metal wiring process as any one of the plurality of vias (123a, 123b), be located at the same level as any one of the plurality of vias (123a, 123b), and have the same material composition as any one of the plurality of vias (123a, 123b).

[0041] Each of the plurality of first coupling pads (131) may extend from an upper surface in contact with the second coupling pad (241) to a lower surface in contact with the second metal structure (137), and the through electrode (130) may protrude from the first semiconductor substrate (130) and further extend from the first semiconductor substrate (130) to the lower surfaces of the second metal structures (137).

[0042] In an exemplary embodiment, the upper surface of a plurality of second metal structures (137) may be located at the same vertical level as the upper surface of the first via (123a). In this case, the upper surface of each through electrode (130) may extend to the same vertical level as the lower surface of the first via (123a). In another embodiment, the upper surface of a plurality of second metal structures (137) may be located at the same vertical level as the upper surface of the second via (123b). In this case, the upper surface of each through electrode (130) may extend to the same vertical level as the lower surface of the first via (123b). In an exemplary embodiment, the through electrode (130) may be aligned perpendicularly with the corresponding first coupling pad (141) and the plurality of second metal structures (137) disposed on the through electrode (130), and may not be overlapped perpendicularly with the first wiring structure (120). In an exemplary embodiment, the horizontal width of a plurality of second metal structures (137) may be wider than the horizontal width of the first coupling pad (141). The horizontal widths of each of the plurality of second metal structures (137) may be equal to each other, but are not limited thereto. For example, some of the horizontal widths of the plurality of second metal structures (137) may be wider than some of the horizontal widths of the remainder of the plurality of second metal structures (137).

[0043] FIG. 5 is a cross-sectional view showing a semiconductor package (1010) according to an embodiment of the present invention. The semiconductor package (1010) may include a first semiconductor chip (100a), a second semiconductor chip (200a), and a molding layer (170). The first semiconductor substrate (110a), first wiring structure (120), first through-electrode (130a), first coupling pad (141), and first dummy structure (143) of the first semiconductor chip (100a) are each similar to the first semiconductor substrate (110), first wiring structure (120), through-electrode (130), first coupling pad (141), and first dummy structure (143) of the first semiconductor chip (100) of FIG. 1, and the second semiconductor substrate (210a), second wiring structure (220), second connection pad (241), and second dummy structure (243) of the second semiconductor chip (200a) of the semiconductor package (1010) are each similar to the second semiconductor substrate (210), second wiring structure (220), second connection pad (241), and second dummy structure of the second semiconductor chip (200) of the semiconductor package (1000) of FIG. 1. It is similar to the structure (243). Therefore, the following will focus on the differences.

[0044] The first semiconductor chip (100a) may include a first semiconductor substrate (110a), a first wiring structure (120), a first through electrode (130a), a first bonding pad (141), and a first dummy structure (143). The horizontal width of the first semiconductor substrate (110a) and the horizontal width of the first wiring structure (110a) may be the same. The vertical height of the first through electrode (130a) may be the same as the vertical height of the first semiconductor substrate (110a).

[0045] In an exemplary embodiment, the horizontal width of the first semiconductor chip (100a) may have a value smaller than the horizontal width of the second semiconductor chip (200a). For example, the horizontal width of the first wiring structure (120) and the horizontal width of the first semiconductor substrate (110a) may each have a value smaller than the horizontal width of the second wiring structure (220) and the horizontal width of the second semiconductor substrate (210a). In an exemplary embodiment, the vertical height of the first semiconductor chip (100a) may have a value larger than the vertical height of the second semiconductor chip (200a), but is not limited thereto.

[0046] The molding layer (170) may surround at least a portion of the first semiconductor chip (100a) and the second semiconductor chip (200a). For example, the sides of the first wiring structure (120) and the sides of the first semiconductor substrate (110a) may be surrounded by the molding layer (170), and a portion of the lower surface of the second wiring structure (220) may be covered by the molding layer (170). The molding layer (170) may be, for example, an epoxy molding compound, but is not limited thereto.

[0047] The second through electrode (130b) can extend vertically through the molding layer (170). The upper surface of the second through electrode (130b) may be in contact with the lower surface of the second wiring structure (220), and the lower surface of the second through electrode (130b) may be in contact with the upper surface of the redistribution structure (150). The vertical height of the second through electrode (130b) may have a value greater than the vertical height of the first through electrode (130a) and the vertical height of the first semiconductor substrate (110a). The horizontal width of the second through electrode (130b) may be equal to the horizontal width of the first through electrode (130a). For example, the horizontal width of the second through electrode (130b) and the horizontal width of the first through electrode (130a) may be about 2 μm to about 3 μm. The second through electrode (130b) can electrically connect the second semiconductor chip (200a) and the redistribution structure (150).

[0048] The redistribution structure (150) may be disposed on the lower surface of the first semiconductor substrate (110a) and the molding layer (170). The horizontal width of the redistribution structure (150) may be greater than the horizontal width of the first semiconductor substrate (110a). A plurality of connection bumps (160) may be disposed on the lower surface of the redistribution structure (150).

[0049] The first wiring structure (120) may surround at least a portion of the first coupling pad (141) and the first dummy structure (143). For example, the first wiring structure (120) may surround the sides of the first coupling pad (141) and the bottom and sides of the first dummy structure (143).

[0050] The second wiring structure (220) may surround at least a portion of the second coupling pad (241) and the second dummy structure (243). For example, the second wiring structure (220) may surround the upper and side surfaces of the second coupling pad (241) and the upper and side surfaces of the second dummy structure (243).

[0051] Although not illustrated in FIG. 5, the first wiring structure (120) may include a lower insulating layer (not illustrated). For example, the first wiring structure (120) may include a lower insulating layer similar to the first wiring insulating layer (145, see FIG. 1), said lower insulating layer may surround at least some of the sides of the first coupling pad (141) and the lower surface and sides of the first dummy structure (143). The second wiring structure (220) may include an upper insulating layer (not illustrated). For example, the second wiring structure (220) may include an upper insulating layer such as the second wiring insulating layer (245, see FIG. 1), said upper insulating layer may surround at least some of the sides of the second coupling pad (241) and the upper surface and sides of the second dummy structure (243). In an exemplary embodiment, the lower insulating layer and the upper insulating layer may be in contact with each other. That is, at the interface where the first semiconductor chip (100a) and the second semiconductor chip (200a) come into contact, the lower insulating layer included in the first semiconductor chip (100a) and the upper insulating layer included in the second semiconductor chip (200a) can come into contact. FIG. 6 is a cross-sectional view showing a semiconductor package (2000) according to an embodiment of the present invention.

[0052] Referring to FIG. 6, the semiconductor package (2000) may include sub-semiconductor packages (1100a, 1100b) comprising a first semiconductor chip (100) and a second semiconductor chip (200), and a main board (400) that mounts the sub-semiconductor packages (1100a, 1100b). In an exemplary embodiment, the sub-semiconductor packages (1100a, 1100b) may be at least one of the semiconductor packages (1000a, 1000b, 1000c, 1000d, 1000e) shown in FIG. 2a through 4b. For example, the first sub-semiconductor package (1100a) may be the semiconductor package (1000a) shown in FIG. 2a, and the second sub-semiconductor package (1100b) may be the semiconductor package (1000c) shown in FIG. 3. In another embodiment, unlike as shown in FIG. 6, at least one of the sub-semiconductor packages (1100a, 1100b) may be the semiconductor package (1010) shown in FIG. 5. For example, the first sub-semiconductor package (1100a) may be the semiconductor package (1000a) shown in FIG. 2a, and the second sub-semiconductor package (1100b) may be the semiconductor package (1010) shown in FIG. 5. The sub-semiconductor packages (1100a, 1100b) will be described below with reference to FIG. 1.

[0053] Sub-semiconductor packages (1100a, 1100b) can be attached to a main board (400) via a plurality of connection bumps (160). The sub-semiconductor packages (1100a, 1100b) can be electrically connected to each other via the main board (400). The plurality of connection bumps (160) can provide at least one of a signal, power, or ground for the sub-semiconductor packages (1100a, 1100b).

[0054] Although FIG. 6 illustrates a semiconductor package (2000) comprising two sub-semiconductor packages (1100a, 1100b), it is not limited thereto, and for example, the semiconductor package (2000) may comprise one sub-semiconductor package or three or more sub-semiconductor packages.

[0055] The main board (400) may include a base board layer (420), a first upper surface pad (410) and a first lower surface pad (440) respectively disposed on the upper and lower surfaces of the base board layer (420), and a first wiring path (430) that electrically connects the first upper surface pad (410) and the first lower surface pad (440) through the base board layer (420).

[0056] In some embodiments, the main board (400) may be a printed circuit board. For example, the main board (400) may be a multi-layer printed circuit board. The base board layer (420) may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide.

[0057] A solder resist layer (not shown) that exposes a plurality of first upper surface pads (410) and a plurality of first lower surface pads (440) may be formed on each of the upper and lower surfaces of the base board layer (420). A plurality of corresponding connection bumps (160) may be connected to each of the plurality of first upper surface pads (410), and a plurality of corresponding external connection terminals (450) may be connected to each of the plurality of first lower surface pads (440). The plurality of connection bumps (160) may electrically connect sub-semiconductor packages (1100a, 1100b) to the first upper surface pads (410). The plurality of external connection terminals (450) may connect the semiconductor package (2000) to the outside.

[0058] The semiconductor package (2000) may further include a molding layer (300) that surrounds both sides and the top surface of sub-semiconductor packages (1100a, 1100b) on the main board (400). The molding layer (300) may include, for example, an epoxy mold compound (EMC).

[0059] In some embodiments, the semiconductor package (2000) does not include a main board (400) but includes, for example, an interposer (not shown), and sub-semiconductor packages (1100a, 1100b) may be mounted on the interposer.

[0060] FIG. 7 is a flowchart illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. FIGS. 8a to 8g are cross-sectional views illustrating each step of a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention.

[0061] Referring to FIGS. 7 and FIGS. 8a to 7c, a plurality of through electrodes (130) can be formed on a first semiconductor substrate (110) (S110). Step S110 may include the steps of forming an opening (O) on the first semiconductor substrate (110), forming an insulating film (133), and filling the opening (O) with a conductive material.

[0062] The opening (O) may be formed, for example, through a dry etching process, but is not limited thereto. The dry etching process may, for example, utilize plasma ions, but is not limited thereto.

[0063] The insulating film (133) may be formed, for example, by a deposition process. The insulating film (133) may cover both side walls and the bottom surface of the opening (O), and the top surface of the first semiconductor substrate (110). The insulating film (133) may include, for example, any one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. In some embodiments, a portion of the insulating film (133) covering the top surface of the first semiconductor substrate (110) may be removed.

[0064] A conductive material can fill the inside of the opening (O). The conductive material may include, for example, a metallic material such as copper. The conductive material can fill the inside of the opening (O) by, for example, electroplating, physical vapor deposition, electroless plating, etc. After the conductive material fills the inside of the opening (O), a through electrode (130) can be formed through a mechanochemical polishing process (S110).

[0065] Referring to FIGS. 7 and FIGS. 8d, a first wiring structure (120) and a first wiring insulation layer (145) may be formed (S120). The first wiring structure (120) may include first to third metal wirings (120a, 120b, 120c). The first to third metal wirings (120a, 120b, 120c) may be formed sequentially. For example, after the first wiring insulation layer (145) is formed on the first semiconductor substrate (110), a portion of the first wiring insulation layer (145) may be etched to form a trench, and the first metal wiring (120a) may be formed within the trench. After that, the same process may be repeated to form the second metal wiring (120b) and the third metal wiring (120c) in sequence. The first wiring structure (120) may be formed only in a portion of the first semiconductor substrate (110). For example, the first wiring structure (120) may not be formed on the through electrode (130).

[0066] Referring to FIGS. 7, 8e, and 8f, a first bonding pad (141) and first dummy structures (143) may be formed (S130). Step S130 may include the steps of etching a portion of the first wiring insulation layer (145), filling with a conductive material (140P), and flattening the conductive material (140P).

[0067] The step of etching a portion of the first wiring insulation layer (145) may be performed, for example, through a dry etching process, but is not limited thereto. The dry etching process may utilize, for example, plasma ions, but is not limited thereto. The etching step may be performed multiple times. For example, the first etching step may be performed in the area where the first dummy structures (143) and the first bonding pad (141) are formed, and the second etching step may be performed in the area where the first bonding pad (141) is formed. Through the second etching step, the upper surface of the through electrode (130) may be exposed.

[0068] A conductive material (140P) can fill the openings formed through the etching step. The conductive material (140P) may include, for example, a metallic material such as copper. The conductive material (140P) can fill the interior of the openings by, for example, electroplating, physical vapor deposition, electroless plating, etc. As the upper surface of the through electrode (130) is exposed by the opening in the area where the first bonding pad (141) is formed, the conductive material (140P) can come into contact with the upper surface of the through electrode (130).

[0069] The conductive material (140P) filling the inside of the opening can be flattened through a mechanochemical polishing process. The flattening process may be, for example, a CMP process, but is not limited thereto.

[0070] Referring to FIGS. 7 and FIGS. 8g, a first semiconductor chip (100) and a second semiconductor chip (200) can be connected (S140). A first bonding pad (141) and a second bonding pad (241) can be brought into contact with each other by a hybrid bonding process, thereby electrically connecting the first semiconductor chip (100) and the second semiconductor chip (200). Step S140 may involve a heat treatment process. For example, Step S140 may involve a low-temperature annealing process. The first bonding pad (141) can be directly connected to the through electrode (130) to improve the SI and PI characteristics of the semiconductor package (1000), and the first bonding pad (141) can be extended from the upper surface in contact with the second bonding pad (241) to the lower surface in contact with the through electrode (130) to secure process conditions for the hybrid bonding process.

[0071] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims. Explanation of the symbols

[0072] 1000: Semiconductor package 100: First semiconductor chip. 110: First semiconductor substrate 120: First wiring structure 130: Through-electrode 141: First coupling pad 143: First dummy structure 145: First wiring insulation layer 150: Rewiring structure 160: Connection bump 200: Second semiconductor chip 2000: Semiconductor package S100: Semiconductor package manufacturing method

Claims

Claim 1 A semiconductor package comprising: a first semiconductor substrate having opposite active and inactive surfaces, a first wiring structure disposed on the active surface of the first semiconductor substrate, a plurality of through electrodes penetrating at least a portion of the first semiconductor substrate, and a plurality of first coupling pads connected to each of the plurality of through electrodes; and a second semiconductor chip stacked on the first semiconductor chip and having opposite active and inactive surfaces, a second wiring structure disposed on the active surface of the second semiconductor substrate, and a second coupling pad connected to the first coupling pad and disposed on the active surface of the second semiconductor substrate; wherein the first coupling pad extends from an upper surface in contact with the second coupling pad to a lower surface in contact with the through electrode, and the vertical level of the upper surface of the first coupling pad is different from the vertical level of the upper surface of the first wiring structure. Claim 2 A semiconductor package according to claim 1, characterized in that the lower surface of the first coupling pad is located at the same vertical level as the lower surface of the first wiring structure. Claim 3 A semiconductor package according to claim 1, wherein the first coupling pad includes a first portion in contact with the second coupling pad and a second portion in contact with the through electrode, wherein the horizontal width of the first portion is constant and the horizontal width of the second portion becomes narrower as it approaches the through electrode. Claim 4 A semiconductor package according to claim 1, characterized in that the horizontal width of the first coupling pad gradually narrows from the upper surface in contact with the second coupling pad to the lower surface in contact with the through electrode. Claim 5 A semiconductor package according to claim 1, characterized in that the vertical height of the first coupling pad is greater than the vertical height of the second coupling pad. Claim 6 A semiconductor package comprising: a first semiconductor substrate having opposite active and inactive surfaces; a first wiring structure comprising a plurality of metal wirings disposed on the active surface of the first semiconductor substrate and located at different vertical levels; a through electrode penetrating at least a portion of the first semiconductor substrate; a first metal structure disposed on the through electrode; and a first coupling pad connected to the first metal structure; and a second semiconductor chip stacked on the first semiconductor chip and comprising a second semiconductor substrate having opposite active and inactive surfaces, a second wiring structure disposed on the active surface of the second semiconductor substrate, and a second coupling pad connected to the first coupling pad and disposed on the active surface of the second semiconductor substrate; wherein the first coupling pad extends from an upper surface in contact with the second coupling pad to a lower surface in contact with the first metal structure, the through electrode protrudes from the first semiconductor substrate and contacts the first metal structure, and the vertical length of the first coupling pad is longer than the vertical length of the first wiring structure. Claim 7 A semiconductor package according to claim 6, characterized in that the horizontal width of the first metal structure is wider than the horizontal width of the first bonding pad. Claim 8 A semiconductor package according to claim 6, characterized in that the horizontal width of the first coupling pad becomes narrower as it approaches the first metal structure. Claim 9 A first semiconductor substrate having opposite active and inactive surfaces; a first wiring structure comprising a plurality of metal wirings positioned at different vertical levels and a plurality of vias positioned at different vertical levels disposed on the active surface of the first semiconductor substrate; a through electrode penetrating at least a portion of the first semiconductor substrate; a plurality of second metal structures disposed on the through electrode and in contact with each other; and a first coupling pad connected to the second metal structures; A semiconductor package comprising: a second semiconductor substrate having an active surface and an inactive surface opposite to each other, stacked on the first semiconductor chip; a second wiring structure disposed on the active surface of the second semiconductor substrate; and a second coupling pad connected to the first coupling pad and disposed on the active surface of the second semiconductor substrate; wherein the first coupling pad extends from an upper surface in contact with the second coupling pad to a lower surface in contact with the second metal structures, and the through electrode protrudes from the first semiconductor substrate and contacts the second metal structures, and the vertical length of the first coupling pad is longer than the vertical length of the first wiring structure. Claim 10 A semiconductor package according to claim 9, wherein the plurality of metal wires includes a first metal wire and a second metal wire located at different vertical levels, the plurality of vias include a first via extended between the first metal wire and the second metal wire, and the upper surface of the second metal structures is located at the same vertical level as the upper surface of the first via.

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