Fabrication of a quantum device

Abstract

In the masking phase, a first segment of the amorphous mask is formed on the lower layer of the substrate. The first segment includes a first set of trenches that expose the lower layer. In the masking phase, a second segment of the amorphous mask is formed on the lower layer. The second segment includes a second set of trenches that expose the lower layer. The segments do not overlap. An open end of one of the first set of trenches faces an open end of one of the second set of trenches, but the ends are separated by a portion of the amorphous mask. In the semiconductor growth phase, the semiconductor material is grown in the first and second sets of trenches by selective region growth to form first and second nanowire sub-networks on the lower layer. The first and second nanowire sub-networks are combined to form a single nanowire network.

Description

Technology Field

[0001] The present application relates to a method for manufacturing a quantum device and a resulting quantum device. Such a quantum device can be used, for example, in a quantum computer. Background Technology

[0002] Quantum computing is a class of computing in which quantum mechanical phenomena, such as quantum state superposition and entanglement, are utilized to perform specific calculations much more rapidly than any conventional computer can. In "topological" quantum computers, calculations are performed by manipulating quasiparticles, referred to as "non-abelian anyons," that arise in specific physical systems. Anyons possess unique physical properties that distinguish them from both fermions and bosons. Non-abelian anyons also possess properties unique to abelian anyons. It is these unique properties that serve as the basis for topological quantum computing, where information is encoded as the topological properties of non-abelian anyons, specifically as the braiding of their spacetime worldlines. This offers specific advantages over other models of quantum computation. One key advantage is stability, because quantum braiding is not affected by perturbations of a scale that can cause error-induced quantum decoherence in other types of quantum computers.

[0003] Broadly speaking, to date, two types of physical systems have been considered as potential hosts for non-Abellian anyons: "5 / 2 fractional quantum Hall" systems in condensed matter physics, and (more recently) semiconductor-superconductor (SE) nanowires. Regarding the latter, a key advance in this field was the recognition that non-Abellian anyons in the form of "Majorana zero modes" (MZMs) can be formed in regions of the semiconductor (SE) coupled to the superconductor (SU). Based on this phenomenon, a network of SE / SU nanowires can be used to generate quantum bits, where each SE / SU nanowire comprises a length of the semiconductor coated with a superconductor.

[0004] A quantum bit, or qubit, is an element that can be measured with two possible outcomes, but can actually be in a quantum superposition of two states corresponding to different outcomes at any given time (when not being measured).

[0005] "Topological" qubits are qubits implemented based on the aforementioned description of non-Abellian anyons in the form of MZMs. Non-Abellian anyons are a type of quasiparticle, meaning they are not particles themselves, but rather excitations in an electronic liquid that behave at least partially like particles. In particular, anyons are quasiparticles occurring in a two-dimensional system (two degrees of freedom in space). The Majorana zero mode is a specific bound state of such quasiparticles. Under certain conditions, these states can be formed near the semiconductor / superconductor interface in SE / SU nanowire networks in a manner that allows them to be manipulated as quantum bits for the purpose of quantum computing. Regions or "segments" of the nanowire network between MZMs are referred to as being in a "topological" regime.

[0006] This summary is provided to introduce a selection of simplified forms of concepts further described in the detailed description below. This summary is not intended to identify the core or essential features of the claimed claims, nor is it intended to be used to limit the scope of the claimed claims. The claimed subject matter is not limited to implementations that address any or all of the disadvantages mentioned herein.

[0007] Although recent advancements in manufacturing technology have brought about significant improvements in the quality of nanowire networks, the approaches to the problem all face challenges regarding scalability and / or quality. This imposes limitations on the size and complexity of nanowire networks that can be fabricated with these approaches.

[0008] Various micro / nano fabrication methods can be used to create high-quality semiconductor (superconductors and also insulating) structures required for quantum devices for potential use in the field of quantum computation. For epitaxial structures (in-plane wire networks) where a mask is used to guide the growth process, there are specific challenges that can be controlled kinetically or / and thermodynamically.

[0009] One challenge concerns defect engineering. In nanowire networks, defect-free regions are limited in size (typically a few microns). Structural defects occur randomly within structures that exceed this critical dimension. This is detrimental to device quality because defective regions can occur within the active area, adversely affecting electron transport.

[0010] Another challenge concerns scalability. In some specific cases, due to fundamental kinetic and / or thermodynamic limitations, the maximum achievable size of the generated structures (e.g., networks) is limited to just tens of microns. This renders some manufacturing methods unscalable, despite the fact that they can produce high-quality structures at smaller levels. It is necessary to make such methods scalable for large-scale applications.

[0011] Embodiments of the present invention provide methods for manufacturing nanowire structures, which can not only produce high-quality structures but also be carried out in a scalable manner to enable the creation of large and potentially complex nanowire networks.

[0012] According to one embodiment disclosed herein, a method for manufacturing a quantum device may be provided, comprising: in a masking phase, forming a first segment of an amorphous mask on a lower layer of a substrate, wherein the first segment comprises a first set of trenches that expose the lower layer; in a masking phase, forming a second segment of an amorphous mask on the lower layer, wherein the second segment comprises a second set of trenches that expose the lower layer, and the first segment and the second segment do not overlap, and the open end of one of the trenches of the first set of trenches faces the open end of one of the trenches of the second set of trenches, but the ends are separated by a portion of the amorphous mask; and in a semiconductor growth phase, growing a semiconductor material in the first set of trenches and the second set of trenches to form a first nanowire sub-network and a second nanowire sub-network on the lower layer by selective-region-growth. and includes the step of combining a first nanowire sub-network and a second nanowire sub-network to form a single nanowire network on the lower layer.

[0013] The first and second segments can be formed simultaneously. That is, the trenches of the first and second sets can be formed simultaneously. Alternatively, the first and second segments can be formed sequentially.

[0014] Therefore, the separated trenches form first and second portions of the entire (i.e., wider or larger) trench (i.e., channel), which define the nanowire but have discontinuities in the entire trench formed by the aforementioned portion of the mask. In other words, the aforementioned portion of the mask effectively acts as a discontinuity in the longer trench formed by the separated trenches. This portion is preferably approximately several nanometers in the direction of the trench. It is a characteristic of some selective region growth techniques that the probability of a trench being filled increases with a decrease in surface area. In cases where the maximum achievable size of the generated structures (e.g., networks) is limited to only tens of microns due to fundamental kinetic and / or thermodynamic limitations, it is advantageous to divide a large mask into smaller segments to increase the chances of a fully grown nanowire network.

[0015] Embodiments of the present invention use a segmentation approach to construct a single (i.e., larger) nanowire network from two or more nanowire sub-networks (i.e., smaller networks). This enables growth methods that cannot produce large structures to be used on a larger scale (e.g., wafer scale). The embodiments also enable effective defect engineering within large nanowire networks because defects are confined to separations between segments of the mask, namely between the open end of one of the first set of trenches and the open end of one of the second set of trenches.

[0016] In the embodiments, the joining step may include merging by lateral growth of the semiconductor material during the semiconductor growth phase.

[0017] Alternatively, the joining step may include, in a subsequent phase for the semiconductor growth phase, connecting the open end of one of the first set of trenches to the open end of one of the second set of trenches through an electrical conductor.

[0018] In the embodiments, the lower layer may be a wafer of the substrate. Alternatively, one or more intermediate layers may be disposed between the mask and the wafer.

[0019] In the embodiments, the open end of the first trench of the first set can be separated from the open end of the first trench of the second set in a non-active region of the nanowire network.

[0020] Not all regions within a nanowire network (e.g., points or regions) serve a role for quantum and / or electrical purposes. While the entire network performs a specific role in quantum computing, the requirements for crystal quality differ for different parts. The parts where quantum effects "occur" have the highest requirements for crystal quality. These are referred to as "active regions." In other words, the quantum or electrical effects required for quantum computing are typically limited to specific regions within the nanowire network, for example, at specific junctions of the network. An active (or operating) region of a nanowire network refers to any region that corresponds to or is expected to occur with said effects. In other words, the operating region is the active or operating region of the quantum device. In contrast, a non-operating region refers to a region that does not correspond to said effects or is not expected to occur with said effects. Accordingly, the portion of the mask separating the first segment and the second segment, that is, separating the open ends of one of the first set of trenches and one of the second set of trenches, can be positioned to coincide with the non-operating region of the mask. The inventors assume that defects in the nanowire structure occur at said separation instead of at random locations (if any). Thus, this allows defects to be confined to non-operating regions instead of occurring randomly across the entire operating region, thereby improving the overall quality of the device.

[0021] In the embodiments, the first and second networks of trenches can be formed by etching an amorphous mask from the underlying layer. Alternatively, the trenches can be formed using nanoimprint or other patterning techniques.

[0022] In the embodiments, the individual patterns of the first and second trenches can be defined by lithography.

[0023] In the embodiments, the amorphous mask may be a dielectric. In the embodiments, the lower layer may be an insulating material.

[0024] In the embodiments, the semiconductor material can be grown by epitaxial techniques. In the embodiments, the semiconductor material can be grown by molecular beam epitaxy.

[0025] In the embodiments, the method may include the step of growing a layer of superconducting material on at least a portion of the nanowire network during the superconducting growth phase.

[0026] In the embodiments, a layer of superconducting material can be applied using a particle beam.

[0027] In the examples, the superconducting material can be grown by epitaxy.

[0028] According to another aspect disclosed herein, a quantum device may be provided, comprising: a substrate and an amorphous mask formed on a lower layer of the substrate—the amorphous mask comprises a first segment comprising a first set of trenches and a second segment comprising a second set of trenches, wherein the first and second segments do not overlap, and the open end of the first trench among the first set of trenches is separated from and faces the open end of the first trench among the second set of trenches—and a nanowire network on the lower layer—the nanowire network is formed from a combination of first and second nanowire sub-networks on the mask, and the first and second nanowire sub-networks comprise a semiconductor material grown in a selective region in the first and second sets of trenches.

[0029] In the embodiments, the device may include an electrical conductor connecting the open ends of the first trenches among the first and second sets of trenches.

[0030] According to another aspect disclosed herein, a method for operating the device may be provided, the method comprising the step of inducing at least one Majora or Zero Mode, MZM, in one or more nanowires of a nanowire network, wherein the at least one MZM is induced by cooling a superconductor to a superconducting temperature and applying a magnetic field to the device. The induction of at least one MZM may further comprise the step of gating at least one of the one or more nanowires to an electrostatic potential. Brief explanation of the drawing

[0031] For a better understanding of the technology and to show how embodiments can be implemented, the following drawings are referenced merely as examples. Figure 1 schematically illustrates an exemplary method for manufacturing a network of nanowires. FIGS. 2A and FIGS. 2B illustrate examples of nanowire networks grown in selective regions. Figure 3 shows an exemplary SEM image of a partial large-scale (>10 µm) nanowire network. Figures 4 and 4a illustrate exemplary SEM images of small-scale (<7 µm) nanowire networks. FIGS. 5 and FIGS. 5a schematically illustrate exemplary nanowire sub-networks that are combined to form a single nanowire network. FIG. 6 illustrates exemplary SEM images showing a segmentation approach on a 30 µm line divided into 10 µm segments, and the inset shows the widening of the gap between the segments. FIGS. 7A and 7B schematically illustrate examples of segmented mask defects occurring at random locations within a nanowire and an uninterrupted mask. Figure 8 illustrates an exemplary cross-sectional TEM of a nanowire having defects occurring at random locations within the nanowire. Specific details for implementing the invention

[0032] Epitaxial semiconductor-superconductor materials are a promising platform for superconducting electronic devices and superconducting quantum computing. In the context of topological quantum computing, superconducting nanowires with strong spin-orbit coupling can support topological excitations that can serve as a basis for fault-tolerant quantum information processing.

[0033] Current approaches for synthesizing semiconductor-superconductor materials for superconducting nanowire electronic devices are based on two-dimensional planar materials (e.g., see Shabani et al. PRB 93, 155402 (2016)) or bottom-up grown nanowire materials (e.g., see Krogstrup et al. Nature Mater. 14, 400-406 (2015)). Both approaches face challenges related to scalability for different reasons.

[0034] In particular, certain mask-guided fabrication methods yield high-quality structures on a small scale but cannot be scaled to larger structures. Figure 3 is a scanning electron microscope (SEM) image of a mask used to guide the growth of a nanowire network. Masks larger than 10 µm were not completely filled with material after growth (see the circular portion of the image). In contrast, Figures 4 and 4a are SEM images illustrating small nanowire networks grown by complete filling of smaller masks. Here, the characteristic size of the mask apertures is less than 7 µm, respectively.

[0035] Furthermore, when it is possible to achieve large-scale networks, a problem of defect formation arises as defects form at random locations within the network. This is exemplified in the schematic image of FIG. 7a, where the nanowire is grown using an uninterrupted mask as in the case of previous methods. Here, defects (702a, 702b) occur at random locations. The cross-sectional image of FIG. 8, which is a transmission electron microscope (TEM) image of the nanowire, shows an actual example of defects occurring in the nanowire.

[0036] To address these and other problems, embodiments of the present invention use a segmentation approach to manufacture quantum devices, thereby breaking down the mask design for large networks into smaller segments. When growth occurs in the smaller segments forming nanowire sub-networks, the sub-networks can be combined (e.g., merged). For example, sub-networks can be combined by lateral extension of the crystal. The resulting structure (network) will be similar to an uninterrupted design, but defects (if present) will be confined to intentional mask break locations. This is schematically illustrated in FIG. 7b, where defects (902a) occur at break locations (904) rather than at random locations throughout the nanowire (906). This resolves the defect problem. Regarding the scalability problem, each sub-network grows independently, ensuring that each is below a critical achievable size for a specific material and growth condition. Any number of fully grown sub-networks can be combined to form a larger network. This ensures the unrestricted scalability of the nanowire networks.

[0037] With reference to FIGS. 1, 5, and 5a, an exemplary three-phase fabrication method will now be described. The fabrication method can be used to create a network of semiconductor (SE) and / or semiconductor / superconductor (SE / SU) nanowires, which can ultimately form the basis of quantum devices or circuits (e.g., in the case of quantum computers) or other mixed semiconductor-superconductor platforms. In particular, this method is particularly suitable for fabricating SE / SU nanowire networks capable of hosting stable MZMs, which can form the basis of defect-free topological quantum computations. Here, SE / SU nanowires refer to semiconductor wires coated with a superconductor.

[0038] An exemplary fabrication method utilizes Selective Area Growth (SAG). SAG is a growth method using crystal growth vacuum chambers, such as Chemical Beam Epitaxy (CBE), Molecular Beam Epitaxy, and MOCVD. For example, G. J Davies Proc. SPIE 2140, Epitaxial Growth Processes, 58 (May 11, 1994); doi: 10.1117 / 12.175795; M Fahed, Doctoral thesis: Selective area growth of in-plane III-V nanostructures using molecular beam epitaxy, 2016. http: / / www.theses.fr / 2016LIL10114; Fukui et al, Appl. Phys. Lett. 58, 2018 (1991); See doi: http: / / dx.doi.org / 10.1063 / 1.105026.

[0039] Since SE / SU nanowire networks are generated using SAG, the entire nanowire network or multiple such networks can be fabricated as a whole on the substrate. The substrate and the nanowire network can be directly integrated into the final product without any need to transfer the nanowires to different surfaces.

[0040] The fabrication of quantum devices involves building a wafer by depositing multiple layers or materials in generally different patterns on a substrate. The entire process involves multiple steps as different layers are built. For the following description, "wafer" will be used herein to refer to the base layer, and "substrate" will refer to the wafer and any other layers already deposited on the wafer at the current stage of the manufacturing process.

[0041] In the first phase (I) (masking phase), an amorphous mask (102) is formed on a lower layer of a substrate (104). The amorphous mask (102) may be formed of a dielectric material. The lower layer of the substrate may be the substrate (104) itself, or an intermediate material layer formed on the substrate. The amorphous mask (102) is composed of a plurality of segments. The following examples will be described in terms of a first segment and a second segment, but it will be recognized that the described methods apply to more than two segments. Each segment includes a set of trenches that expose a lower layer, e.g., a substrate, and the first segment includes a first set of trenches that expose a first pattern of the lower layer, and the second segment includes a second set of trenches that expose a second pattern of the lower layer. The first and second segments may be formed simultaneously, or one segment (e.g., the first segment) may be formed first and then the other segment (e.g., the second segment) may be formed.

[0042] The first and second segments are formed so that they do not overlap, that is, so that their trenches do not overlap in space or cover the same area of ​​the lower layer of the substrate. The first and second segments are also formed such that an open end of one of the first set of trenches (belonging to the first segment of the mask) faces an open end of one of the second set of trenches (belonging to the second segment of the mask). The open ends are separated by a portion of the amorphous mask. That is, a portion of the mask is required as an initial barrier between the open ends of the trenches facing each other. This is schematically illustrated in the examples of FIG. 5 and FIG. 5a. In FIG. 5, trench (502a) of the first set of trenches (belonging to the first segment of the mask) faces trench (502b) of the second set of trenches (belonging to the second segment of the mask). The separation of the trenches is highlighted by a dashed box. In this example, the open end of trench (502b) of the second set of trenches faces the open end of trench (502c) of the third set of trenches (belonging to the third segment of the mask). Similarly, in FIG. 5a, trench (502a) of the first set of trenches (504a) (belonging to the first segment of the mask) faces trench (502b) of the second set of trenches (504b) (belonging to the second segment of the mask).

[0043] Amorphous materials cannot withstand epitaxial growth. That is, they inhibit growth in the regions where they are deposited on the substrate, while growth can proceed on a crystalline substrate with the mask open.

[0044] Generally, the first and second segments may be the same size or different sizes. The first and second segments may be the same shape or different shapes.

[0045] In the example of FIG. 1, a patterned layer of amorphous material (102) (amorphous mask) is formed on the top of the substrate (104). Side and top views of the substrate (104) having the amorphous mask (102) are shown on the left side of FIG. 1. The substrate (104) can be formed of any suitable substrate material, such as InP (Indium Phosphide), and is an insulating substrate in the described examples. In the described examples, the mask material (102) is an oxide, but it can be any amorphous material that facilitates SAG in Phase II (see below) of the manufacturing method.

[0046] An amorphous mask or oxide layer (102) is patterned in such a way that the oxide layer (102) is formed so that trenches (or narrow strips) of the substrate remain exposed in the desired area (106) (i.e., not covered by the mask (102)). In this context, the pattern refers to the structure of the desired area (106) which will ultimately become the structure of the nanowire network, because this is the exposed area (106) where SE nanowires are grown. Thus, the size and structure of the nanowires match the size and structure of the exposed area (106). Although only one exposed area (106) is shown in FIG. 1, nanowires can be grown simultaneously in multiple areas, and all descriptions related to the desired area (106) apply equally to multiple such areas. Thus, the structure of the entire nanowire network can be defined by the structure of the exposed area(s), which itself is defined by the structure of the trenches of each segment of the mask. In this example, the strips and the resulting nanowires have a width of approximately tens or hundreds of nanometers.

[0047] The amorphous mask (102) can be formed in any suitable manner to leave the desired region (106) exposed. For example, a uniform and continuous layer of an amorphous material, such as an oxide, can be deposited on the substrate (104) or other underlying layer, and then the exposed region (106) can be formed by selectively etching the amorphous mask (102) from the desired region (106) (in this case, it is the lithography and subsequent etching that define the ultimate nanowire network structure). As another example, an insulating material (102) can be selectively deposited on the substrate (104) using a mask used to prevent the deposition of the material (e.g., oxide) (102) on the desired regions (106) (in this case, it is the mask that defines the ultimate nanowire network structure). The oxide (102) can be, for example, silicon oxide (SiOx). More generally, other suitable amorphous materials may be used.

[0048] In the second phase (II) (semiconductor growth phase, or SAG phase), semiconductor material (108) is grown in first and second sets of trenches that expose the underlying layer of the substrate. If the underlying layer is the substrate itself, the semiconductor material (108) is grown on the exposed portions of the substrate. Growth of the semiconductor material is initiated in each set of trenches. The selectively region-grown semiconductor material forms first and second nanowire sub-networks in each set of trenches. Each nanowire sub-network may contain one or more nanowires. As illustrated in the example of FIG. 5, each segment contains a single trench, and thus each corresponding sub-network contains a single nanowire. In contrast, in the example of FIG. 5a, each segment contains multiple trenches, and thus each corresponding sub-network contains multiple nanowires.

[0049] Referring again to the example in FIG. 1, the semiconductor material (108) is selectively grown within desired regions (106) on the top of the exposed portion of the substrate (104). An example in which a side view of the substrate (104) is shown is illustrated in the top right of FIG. 1. Due to the patterning of the amorphous mask (102), the selectively grown semiconductor (108) forms nanowires in the plane (i.e., the nanowires are grown as a whole from the opening; the growth proceeds in the z-direction across a whole set of openings defined in the xy plane). The semiconductor material (108) may be, for example, indium arsenide (InAs), indium antimonide (InSb), or any other semiconductor having a relatively large spin orbit and G-factor, or a set of more than one material (heterostructures composed of several materials). The SAG semiconductor (108) can be, for example, a limited 2DEG (two-dimensional electron gas) semiconductor or a single-material semiconductor.

[0050] SAG is a growth method. SAG refers to the localized growth of a semiconductor in exposed regions of a substrate, and the growth conditions are selected to prevent such growth on the amorphous mask itself. This can be based, for example, on chemical beam epitaxy (CBE), molecular beam epitaxy (MBE), or metal-organic chemical vapor deposition (MOCVD). In the context of semiconductors, SAG may refer to a class of epitaxial semiconductor growth (and also referred to as selective region epitaxy), where a patterned amorphous mask is used to define the intended structure (lithographic form) of the semiconductor material to be grown. Epitaxy refers to a technique in which a second crystal is grown on a first crystal using a first crystal as a seed crystal. In SAG, the process is tuned so that semiconductor growth occurs only on regions of the substrate not covered by the amorphous mask (102), and not on the amorphous mask itself, for example, on the amorphous mask. This differs from other film deposition / growth processes, such as uniform deposition (epitaxial or other methods) where a mask is not used, in which the material is deposited uniformly across the surface regardless of its composition (as in Phase III, see below). SAG can be performed in high or ultra-high vacuum and may require careful tuning to achieve the desired selective semiconductor growth.

[0051] To generate desired SE nanowires in the exposed area (106), any suitable SAG process may be used in Phase II. The SAG nanowires are defined along high symmetry in-plane crystal orientations on the substrate, which also provides well-defined faceting of the nanowires. This flattens the SU / SE interface, potentially atomically flattening it, and makes it well-defined.

[0052] SAG is known as such and is therefore not discussed in further detail in this specification. For reference, see Selectivity Map for Molecular Beam Epitaxy of Advanced III-V Quantum Nanowire Networks by Aseev P. et al., DOI: 10.1021 / acs.nanolett.8b03733, https: / / pubs.acs.org / doi / 10.1021 / acs.nanolett.8b03733. For further explanation of SAG, see the cited references by, for example, GJ Davies, M Fahed, and Fukui et al.

[0053] In the semiconductor growth phase (i.e., SAG Phase II), it is sufficient that at the end of the semiconductor growth phase (i.e., SAG Phase II), the semiconductor material (108) fills the desired region (106) (i.e., the regions (106) where the lower layer or substrate (104) is not covered by the mask (102), but does not substantially extend beyond the boundaries of the desired region (106) defined by the mask (102) in the plane of the lower layer or substrate (104) (hereinafter xy-plane). In some cases, it may extend outward in a direction normal (perpendicular) to the plane of the lower layer or substrate (104) (hereinafter z-direction) so as to protrude outward from the mask (102). That is, the semiconductor material (108) extends from the lower layer or substrate (104) in the z-direction to a distance greater than the mask (102). In this way, the semiconductor material (108) forms nanowires (plane-in-plane nanowires) substantially lying on the plane of the lower layer or substrate (102).

[0054] When the first and second nanowire sub-networks are formed, they combine to form a single nanowire network. Thus, the nanowire network, which is the sum of the sub-networks, is larger than each of the individual sub-networks. This allows large-scale networks to be built from smaller sub-networks. The combination of sub-networks can occur naturally. That is, sub-networks can be merged by the lateral growth of the semiconductor during (or at the end of) the semiconductor growth phase. In other words, the previously separated open ends of trenches facing each other are laterally extended and merged. An example of this phenomenon is illustrated in FIG. 6. The top image of FIG. 6 illustrates a 30m trench (602) that is only partially filled during the growth of the nanowires. The bottom image illustrates three distinct 10m trenches (604a, 604b, 604c) that are fully filled during the growth of the nanowires. The images are taken before the merging of the trenches. The enlarged image shows the first and second nanowire sub-networks prior to merging.

[0055] Alternatively, the first and second sub-networks can be combined after the semiconductor growth phase (however, if present, before any superconductor growth phase). The sub-networks can be connected using electrical conductors, for example, metallic leads or materials. That is, the open ends of the separated trenches are connected by an electrically conductive material.

[0056] However, the sub-networks are coupled on an amorphous mask. That is, the lateral extension of the semiconductor allows the semiconductor material to grow over a portion of the mask that acts as a barrier between the open-end trenches. Alternatively, an electrical conductor is placed over that portion to connect the open-end trenches.

[0057] It is a characteristic of the SAG process that the larger the growing structure, the more vulnerable it becomes to the formation of defects in the form of threading dislocations or similar types of faults. By dividing the mask into segments containing intentional breakage, this pulls defect formation near the intentional breakage and prevents unintended defects from forming elsewhere. Therefore, this enables the control of defects and the formation of superstructures of arbitrary size.

[0058] During the semiconductor growth phase, several types of semiconductor materials may be grown to form stacks (heterostructures). In an optional third phase III (superconductor growth phase), one or more layers of superconducting material (112) may be grown over at least a portion of the nanowire network. In some examples, other materials (e.g., dielectrics) may be grown. In the example of FIG. 1, the layer of superconducting material is grown using a particle beam (110). As specified herein, superconducting material means a material that exhibits superconducting properties under at least certain conditions. An example of such a material is aluminum (Al). Alternatively, the superconducting material (112) may be niobium (Nb), titanium nitride (TiN), or any other s-wave superconductor. In the following examples, the superconductor is grown epitaxially in Phase III, and the superconductor growth Phase III may be referred to as the epitaxial growth phase in this context. However, this technique is not limited to this, and it may be possible to achieve the intended results through non-epitaxial superconductor growth in Phase III.

[0059] The superconducting material (112) can be grown in Phase III using, for example, molecular beam epitaxy (MBE) or e-beam evaporation.

[0060] At least a portion of the superconducting layer (112) is formed on the top surface of the SE nanowire (108) so that this portion of the superconducting layer (112) (labeled as 116 in FIG. 1) is in direct contact with the SE (108) of the nanowire. That is, the semiconductor (108) of the nanowire is at least partially covered with a superconducting material.

[0061] This is also a form of epitaxy, but not SAG. In particular, in the epitaxial growth phase III, epitaxial growth occurs not only on the SE (108) of the nanowires but also on the amorphous mask (or dielectric layer) (102).

[0062] In some examples, after the growth of one or more layers during Phase III, one or more layers of the semiconductor material may be grown again.

[0063] In one possible technique, the beam can be substantially angled in the z-direction (a direction perpendicular to the plane of the substrate) so that all exposed surfaces of the amorphous mask (102) and the SE material (108) are essentially covered by the SU layer (112). However, in another example as illustrated, the particle beam (110) is incident on the substrate (104) at a non-zero angle of incidence (film angle) with respect to the z-direction. As a result of this non-zero film angle and the protruding structure of the SE core (108) of the nanowire, the SE of the nanowire is only partially coated by the superconducting layer (112); that is, a portion of the SE nanowire core (indicated as 118) is not coated by the superconducting material. Although the bulk of the amorphous mask (102) is also coated by the superconducting layer (112), due to the angle of the receiving beam (110) and the protruding structure of the SE nanowire cores (108), small areas of the amorphous mask (102) immediately adjacent to the protruding SE nanowires (108) (shadow areas) are left exposed, i.e., not coated by the SU material. One such shadow area is labeled 120 in FIG. 1. The shadow area (120) separates the SE material (108) from a portion of the SU layer (112) in the "side gate" area (122). The portion of the SU layer (112) within the side gate area (122) can be used to form a gate for controlling the nanowires, or (more likely) the SU material can be etched from this area and replaced with a more suitable gate material. In either case, the shadow gap (120) ensures that the gate operates as intended. Forming the gap (120) using such "in-situ" patterning in the SU epitaxy phase IP ensures that the material does not need to be etched too close to the delicate nanowires (108).

[0064] SAG Phase II and superconductor growth Phase III can preferably be performed in a vacuum chamber without moving the substrate (104) between the phases. These phases can be performed under high vacuum or ultra-high vacuum conditions, and such vacuum conditions can be maintained between the phases. Among other things, this ensures a clean SE / SU interface free of unwanted impurities.

[0065] Both the SAG semiconductor growth in Phase II and the superconductor growth in Phase III are placed within individual "growth windows" for these two phases, thereby requiring carefully calibrated conditions to achieve the desired semiconductor and superconductor growth, respectively. Growth conditions, temperatures, and fluxes are selected according to the material type. For example, in the case of MBE (which can be used in both the semiconductor SAG Phase II and the superconductor growth Phase III), the substrate is generally heated to temperatures of about 500°C or higher to clean the surface of the natural oxide. However, in the SE SAG growth Phase II and SU growth Phase III, the individual temperature windows in which the desired growth occurs depend on the composition of the SE material (108) and the SU material (112), respectively. The superconductor can be grown / deposited in-situ without destroying the vacuum. In this way, the surface of the SAG is not oxidized in air and remains clean until the SU is placed, which ensures a clean SE-SU interface.

[0066] The substrate (or lower layer of the substrate) (104) and mask (102) on which the SE / SU nanowire network is grown can be integrated into a final product, such as a quantum circuit or quantum computer, together with the SE / SU nanowire network, without the need to transfer the nanowires from the substrate on which they were originally manufactured.

[0067] In summary, instead of fabricating large structures as a single piece, an array of smaller structures is fabricated and subsequently interconnected into a large structure. This can be achieved by placing mask apertures close together and allowing the nanostructures to merge during the growth process. This enables the fabrication of large networks without the need for additional materials to connect the structures. This is particularly advantageous for structures where maintaining the same set of materials throughout the entire nanowire network is important, for example, in quantum computing.

[0068] The masking step may include: 1. forming an amorphous mask film on a crystalline substrate; 2. lithographically defining the locations of all trenches and thus positioning the trenches close to each other to achieve segmentation; 3. removing the mask material inside the trenches to expose the crystalline material of the substrate to be exposed for epitaxy; 4. growth. The growth phase may include the epitaxial growth of nanowire networks.

[0069] The growth phase can utilize MS SAG (metal-sourced selective area growth). MS SAG is a three-step process. During step (i), indium (In) at an elevated temperature It is formed into a film that collects In only within the mask openings and prevents the accumulation of In on the mask surface. This is possible due to the higher desorption rate of In adatoms from the amorphous mask compared to the surface of a crystalline substrate. During step (ii), the substrate is at a critical temperature for the subsequent conversion of In to InSb, supplying only Sb flux. It is cooled to a temperature below. Note that growth proceeds under a local In-rich regime around the droplet acting as a metal reservoir, even though only Sb flux is externally supplied. During step (iii), the substrate temperature is It rises to this temperature, and at this temperature, selective InSb growth can proceed with both In and Sb fluxes supplied simultaneously.

[0070] In some examples, the initial selective In Tabernacle of step (i) is approximately , , is performed under conditions of t = 10 minutes. These conditions are optionally favorable. During step (ii), the conversion of In to InSb under only Sb flux is approximately , , is performed under conditions of t = 10 min. These conditions are favorable for nucleation. Although not selectively preferred under these conditions, InSb growth proceeds only within the mass because In atoms exist only there and the probability of them migrating to the mask is low. During step (iii), the SAG of InSb, which simultaneously supplies In and Sb fluxes at elevated substrate temperatures, is approximately , , , is performed under conditions of t = 60 min. These conditions are optionally favorable. Here, T is the substrate temperature, and F In and F Sb are the fluxes of In and Sb measured, respectively, in equivalent 2D monolayers grown per second , and t is the duration of each stage.

[0071] Embodiments of the disclosed technology include topologically protected quantum computing circuits comprising networks of nanowires formed using such mixed semiconductor and superconducting regions. In FIG. 2, a wire pattern composed of InAs nanowires grown on an insulating GaAs substrate is shown, for example. In particular, FIG. 2 illustrates the fabrication of a complex network based on a one-dimensional nanowire network.

[0072] As mentioned, selective region growth (SAG) of nanowire networks can be used to generate Majorana-based topological qubits, which utilize the formation of superconducting islands, some of which are topological (T) and some are non-topological (e.g., conventional s-wave (S)). SAG techniques can provide a high level of control over the geometry of the generated devices and are therefore useful for generating components used in scalable topological quantum computation. In exemplary embodiments, one or more Majorana zero modes, MZM, can be induced in at least one nanowire of the nanowire network by cooling the superconductor to a superconducting temperature and applying a magnetic field to the device.

[0073] The examples described herein should be understood as exemplary examples of embodiments of the invention. Additional embodiments and examples are anticipated. Any feature described in connection with any example or embodiment may be used alone or in combination with other features. Additionally, any feature described in connection with any one example or embodiment may also be used in combination with one or more features of any other of the examples or embodiments, or any combination of any other of the examples or embodiments. Furthermore, equivalents and modifications not described herein may also be used within the scope of the invention as defined in the claims.

Claims

Claim 1 In a quantum device, a substrate and an amorphous mask layer formed on the substrate — the amorphous mask layer comprises a first segment defining a first set of trenches extending along the surface of the substrate, and a second segment defining a second set of trenches extending along the surface of the substrate, wherein the first segment and the second segment do not overlap, and the open end of the first trench among the first set of trenches is separated from the open end of the first trench among the second set of trenches and faces the open end of the first trench among the second set of trenches —; A quantum device comprising: a nanowire network in contact with the surface of the substrate — the nanowire network comprises a first nanowire sub-network and a second nanowire sub-network, wherein the first nanowire sub-network and the second nanowire sub-network comprise a semiconductor material in the first set of trenches and the second set of trenches, and wherein the semiconductor material is in contact with the surface of the substrate and extends to the sidewalls of the first set of trenches and the second set of trenches defined by the amorphous mask layer — Claim 2 A quantum device according to claim 1, further comprising an electrical conductor connecting the open end of the first trench among the first set of trenches and the open end of the first trench among the second set of trenches. Claim 3 A quantum device according to claim 1, wherein the substrate comprises a wafer. Claim 4 A quantum device according to claim 1, wherein the amorphous mask is a dielectric. Claim 5 A quantum device according to claim 1, wherein the semiconductor material is indium antimonide. Claim 6 A quantum device according to claim 1, further comprising a layer of superconducting material grown at least partially on the nanowire network. Claim 7 A method for operating a quantum device according to claim 6, comprising the step of inducing at least one Majorana zero mode (MZM) in one or more nanowires of the nanowire network, wherein the at least one MZM is induced by cooling a layer of the superconducting material to a superconducting temperature and applying a magnetic field to the quantum device. Claim 8 A quantum device according to claim 6, wherein the layer of the superconducting material is aluminum, niobium, or titanium nitride or an S-wave superconductor. Claim 9 A quantum device according to claim 1, wherein the semiconductor material is indium arsenide or a limited 2DEG (two-dimensional electron gas) semiconductor. Claim 10 A quantum device according to claim 1, wherein the semiconductor material is a heterostructure. Claim 11 A quantum device according to claim 1, wherein the semiconductor material combines the first nanowire sub-network and the second nanowire sub-network. Claim 12 In a quantum device, an amorphous mask formed on a substrate and an underlying layer of said substrate ― said amorphous mask comprises a first segment comprising a first set of trenches and a second segment comprising a second set of trenches, wherein the first segment and the second segment do not overlap, and the open end of the first trench among the first set of trenches is separated from the first trench among the second set of trenches and faces the first trench among the second set of trenches ―; A quantum device comprising: a nanowire network on the lower layer — the nanowire network is formed from the combination of a first nanowire sub-network and a second nanowire sub-network on the amorphous mask, wherein the first nanowire sub-network and the second nanowire sub-network comprise a semiconductor material grown in the first set of trenches and the second set of trenches, and wherein the semiconductor material comprises a portion on the amorphous mask, wherein the portion combines the first nanowire sub-network and the second nanowire sub-network. Claim 13 A quantum device according to claim 1, further comprising a conductor that combines the first nanowire sub-network and the second nanowire sub-network. Claim 14 A quantum device according to claim 1, wherein a portion of the semiconductor material protrudes from the substrate beyond the amorphous mask. Claim 15 In a quantum device, an amorphous mask formed on a substrate and an underlying layer of the substrate ― said amorphous mask comprises a first segment comprising a first set of trenches and a second segment comprising a second set of trenches, wherein the first segment and the second segment do not overlap, and the open end of the first trench among the first set of trenches is separated from the first trench among the second set of trenches and faces the first trench among the second set of trenches ―; a nanowire network on the underlying layer ― said nanowire network is formed from the combination of a first nanowire sub-network and a second nanowire sub-network on the amorphous mask, said first nanowire sub-network and said second nanowire sub-network comprise a semiconductor material in said first set of trenches and said second set of trenches, and a portion of said semiconductor material protrudes from the substrate beyond the amorphous mask ―; A quantum device comprising a layer of superconducting material grown at least partially on a portion of the semiconductor material protruding from the substrate over the amorphous mask that combines the semiconductor material of the nanowire network and the first nanowire sub-network and the second nanowire sub-network. Claim 16 A quantum device according to claim 15, wherein the first nanowire sub-network and the second nanowire sub-network are coupled by a portion of the semiconductor material protruding from the substrate beyond the amorphous mask, and a layer of the superconducting material on the portion of the semiconductor material couples the first nanowire sub-network and the second nanowire sub-network, and the layer of the superconducting material defines a shadow region not coated by the layer of the superconducting material. Claim 17 In a quantum device, an amorphous mask formed on a substrate and an underlying layer of said substrate ― said amorphous mask comprises a first segment comprising a first set of trenches and a second segment comprising a second set of trenches, wherein the first segment and the second segment do not overlap, and the open end of the first trench among the first set of trenches is separated from the first trench among the second set of trenches and faces the first trench among the second set of trenches ―; A quantum device comprising: a nanowire network on the lower layer — said nanowire network is formed from the combination of a first nanowire sub-network and a second nanowire sub-network on the amorphous mask, said first nanowire sub-network and said second nanowire sub-network comprise semiconductor material in said first set of trenches and said second set of trenches, said semiconductor material grown in said first set of trenches and said second set of trenches protrudes from said amorphous mask — and a layer of said superconducting material on a portion of a shadow region not coated by a layer of said superconducting material. Claim 18 A method for manufacturing a quantum device, comprising the step of forming an amorphous mask on a substrate — said amorphous mask comprises a first segment including a first set of trenches extending along the surface of the substrate to the surface of the substrate, and a second segment including a second set of trenches extending along the surface of the substrate to the surface of the substrate, wherein the first segment and the second segment do not overlap, and the open end of the first trench among the first set of trenches is separated from the open end of the first trench among the second set of trenches and faces the open end of the first trench among the second set of trenches —; A method for manufacturing a quantum device comprising the step of forming a nanowire network on the substrate — wherein the nanowire network is formed from the combination of a first nanowire sub-network and a second nanowire sub-network, and the first nanowire sub-network and the second nanowire sub-network comprise a semiconductor material grown in the first set of trenches and the second set of trenches, and the semiconductor material comprises a portion on the amorphous mask, wherein the portion combines the first nanowire sub-network and the second nanowire sub-network. Claim 19 A method for manufacturing a quantum device, wherein, in claim 18, the step of forming the amorphous mask comprises: in a masking phase: forming the first segment of the amorphous mask on the substrate ― the first set of trenches expose the substrate ―; forming the second segment of the amorphous mask on the substrate ― the second segment comprises the second set of trenches that expose the substrate, and the open end of one of the first set of trenches is separated from the open end of one of the second set of trenches by a portion of the amorphous mask ―; and in a semiconductor growth phase, growing the semiconductor material in the first set of trenches and the second set of trenches to form the first nanowire sub-network and the second nanowire sub-network on the substrate by selective-region-growth.

Images